PHILIPS NE56610-39GW Family of devices designed to generate a reset signal for a variety of microprocessor and logic system Datasheet

NE56610/11/12 Series
System Reset
Rev 0
February, 2001
Preliminary Product Specification
General Description
The NE56610/11/12 series is a family of devices designed to generate a reset signal for a
variety of microprocessor and logic systems. Accurate reset signals are generated during
momentary power interruptions or when ever power supply voltages sag to intolerable levels.
The NE56610/11/12 incorporates an internal timer to provide reset delay and ensure proper
operating voltage has been attained. In addition, a manual reset pin is available. An Open
Collector output topology is incorporated to provide adaptability for a wide variety of logic and
microprocessor systems.
M/R
1
SUB
2
GND
3
5
VCC
4
VOUT
TSSOP5
NE56610/11/12 is available in the TSSOP5 surface mount package.
Features
• 12V DC Maximum Operating Voltage
• Low Operating Voltage (0.65 V)
• Internal Reset Delay Timer
• NE56610 (50 mS Typical)
• NE56611 (100mS Typical)
• NE56612 (200mS Typical)
• Offered in Reset Thresholds of 2.0, 2.7, 2.8, 2.9, 3.0, 3.1, 4.2,
4.3, 4.4, 4.5, 4.7 V DC
• Available in SSOP5 Surface Mount Package
• Manual Reset Input
Applications
• Micro-Computer Systems
• Logic Systems
• Battery Monitoring Systems
• Back-Up Power Supply Circuits
• Voltage Detection Circuits
• Mechanical Reset Circuits
Simplified Device Diagram
VCC
5
NE56610/11/12
4
VOUT
Reset
Delay
+
GND
3
M/R
1
VREF
2
SUB
Ordering Information
Description
Temperature Range
Order Code
DWG#
5-pin SOT23 (TSSOP5) plastic surface mount
-20 - +75 °C
NE56610-xxGW
TSSOP5
System Reset (100mS Typical Internal Reset Delay)
-20 - +75 °C
NE56611-xxGW
TSSOP5
System Reset (200mS Typical Internal Reset Delay)
-20 - +75 °C
NE56612-xxGW
TSSOP5
Note: Each device has 6 (six) detection voltage options, indicated by the -xx on the order code:
XX
Detect Voltage (Typ.)
XX
Detect Voltage (Typ.)
-25
2.5
-39
3.9
-27
2.7
-42
4.2
-29
2.9
-45
4.5
Philips Semiconductors
NE56610/11/12 Series
System Reset
Pin Designation and Description
Pin Designation
Pin No
5
1
2
4
3
Pin Name
Function
1
M/R
Manual Reset input. Connect to ground when not using.
2
SUB
Substrate Pin. Connect to ground.
3
GND
Ground
4
VOUT
Reset High Output pin
5
VCC
Positive Power Supply Input
Maximum Ratings
Parameter
Symbol
Rating
Unit
TSTG
-40 - +125
°C
TA
-20 - +75
°C
Power Supply Voltage
VCC max.
-0.3 - +12
V
Manual Reset Input Voltage
VRES max
-0.3 - +12
V
Pd
150
mW
Symbol
Rating
Unit
TA
-20 - +75
°C
VCC max.
-0.3 - +12
V
Storage Temperature Range
Ambient Operating Temperature Range
Power Dissipation
Recommended Operating Conditions
Parameter
Ambient Operating Temperature Range
Power Supply Voltage
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Philips Semiconductors
NE56610/11/12 Series
System Reset
DC ELECTRICAL CHARACTERISTICS
TA = 25°C, unless otherwise specified.
Note 1: Unless otherwise stated, M/R pin should always be connected to ground.
Symbol
Test
Circuit
Threshold Detection
VCC Falling
RL = 470Ω,
VOL ≤ 0.4V
VS
1
Hysteresis Voltage
VCC = Rising then Falling (∆VS = VSH-VSL)
RL = 470Ω
Threshold Temperature Coefficient
RL = 470Ω, TA = -20°C - +75°C
Low-level Output Voltage
VCC = VS min. -0.05V, RL = 470Ω
Output Leakage Current
VCC = 10V
Circuit ON Current
VCC = VS min. -0.05V, RL = ∞
Circuit OFF Current
VCC = VS typ./0.85V, RL = ∞
Reset Delay Time High (see note 1)
RL = 4.7kΩ
CL = 100pF
∆VS
Parameter
Reset Delay Time Low (see note 2)
RL = 4.7kΩ, CL = 100pF
Operating Supply Voltage
RL = 4.7kΩ, VOL ≤ 0.4V
Output ON Current 1
VCC = VS min. -0.05V, RL = 0
Output On Current 2
VCC = VS min. -0.05V, RL = 0
TA = -20°C - +75°C
M/R Threshold High
M/R Threshold High
VM/RH = 2.0v
M/R Threshold Low
Part#
Min
Typ
Max
Unit
4.3
4.0
3.7
2.75
2.55
2.35
30
4.5
4.2
3.9
2.90
2.70
2.50
50
4.7
4.4
4.1
3.05
2.85
2.65
100
V
1
-45
-42
-39
-29
-27
-25
All
TC / V S
1
All
±0.01
VOL
1
All
0.1
IOH
1
All
ICCL
1
All
ICCH
1
All
TDLH
2
TPHL
2
NE56610
NE56611
NE56612
All
VOPL
1
All
IOL1
1
All
8
mA
IOL2
1
All
6
mA
VM/RH
IM/RH
All
All
2.0
VM/RL
All
-0.3
30
60
120
mV
% / °C
0.4
V
±0.1
µA
300
500
µA
15
25
µA
50
100
200
20
75
150
300
mS
0.65
0.85
10
mS
V
60
V
µA
0.8
V
NOTES:
2. TDLH measured with VCC = (VS typ. -0.4V) and abruptly transitioning to (VS typ. +0.4)V. TDLH is duration from VCC transition high
to output transition high.
3. TDHL measured with VCC ≥ (VS typ. +0.4V) and abruptly transitioning to (VS typ. -0.4)V. TDHL is duration from VCC transition low
to output transition low.
4. Ramp M/R voltage until Output Reset goes low.
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Philips Semiconductors
NE56610/11/12 Series
System Reset
Typical Performance Curves
Figure 1. Normalized Detection versus Temperature
Figure 2. Circuit ON Current versus Temperature
0.05
500
ICCL, CIRCUIT ON CURRENT (µA)
VS, NORMALIZED DETECTION (V)
0.10
Threshold Normalized to 25°C
RL (Pull-Up to VCC) 470Ω
VOL ≤ 0.4V
0.00
-0.05
-0.10
-50
-25
0
25
50
75
100
125
VCC = VS min. -0.05V
RL = ∞
400
300
200
100
-50
TA, TEMPERATURE (°C)
ICCH, CIRCUIT OFF CURRENT (µA)
∆VS, DETECTION HYSTERESIS (mV)
75
100
125
50
-25
0
25
50
75
100
125
VCC = VS typ. +0.85V
RL = ∞
25
20
15
10
-50
-25
0
25
50
75
100
125
TA, TEMPERATURE (°C)
TA, TEMPERATURE (°C)
Figure 5. Low-Level Output Voltage versus Temperature
Figure 6. Operating Supply Voltage versus Temperature
900
120
VCC = VS min. -0.05V
RL (Pull-Up to VCC) 470Ω
VOPL, OPERATING SUPPLY (mV)
VOL, LOW-LEVEL OUTPUT (mV)
50
30
∆VS = VSH - VSL
RL (Pull-Up to VCC) = 470Ω
60
100
80
60
40
-50
25
Figure 4. Circuit OFF Current versus Temperature
70
40
-50
0
TA, TEMPERATURE (°C)
Figure 3.Detection Hysteresis versus Temperature
80
-25
-25
0
25
50
75
100
125
TA, TEMPERATURE (°C)
February 23, 2001
VOL ≤ 0.4V
RL4.7kΩ
800
700
600
500
400
-50
-25
0
25
50
75
100
125
TA, TEMPERATURE (°C)
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NE56610/11/12 Series
System Reset
Typical Performance Curves (continued)
Figure 8. M/R Input High Current versus Temperature
VCC = VS min. -0.05V
RL = 0
60
50
40
30
-50
-25
0
25
50
75
100
125
25
VCC = 5.0V
VM/RH = 2.0V
20
15
10
5.0
-50
-25
TA, TEMPERATURE (°C)
VM/RH, M/R THRESHOLD HIGH (V)
tDLH, RESET DELAY TIME HIGH (mS)
75
100
125
1.6
225
SA56612
200
175
RL4.7kΩ
CL = 100pF
125
SA56611
100
75
SA56610
50
25
-50
-25
0
25
50
75
100
125
VCC = 5.0V
1.4
1.2
1.0
0.8
0.6
-50
Figure 11. Reset Delay Time Low versus Temperature
14
RL4.7kΩ
CL = 100pF
ICC, SUPPLY CURRENT (µA)
11
25
50
75
100
125
50
75
100
125
5.0
VOUT
RL = 470Ω
TA = 25°C
400
4.0
300
3.0
∆VS
ICC
200
2.0
100
1.0
0
0
1.0
2.0
3.0
4.0
5.0
0
VCC, SUPPLY VOLTAGE (V)
TA, TEMPERATURE (°C)
February 23, 2001
25
500
12
0
0
Figure 12. Icc and Vout versus Supply Voltage
13
-25
-25
TA, TEMPERATURE (°C)
TA, TEMPERATURE (°C)
tDHL, RESET DELAY TIME LOW (µS)
50
Figure 10. M/R Threshold High versus Temperature
250
10
-50
25
TA, TEMPERATURE (°C)
Figure 9. Reset Delay Time High versus Temperature
150
0
VOUT, OUTPUT VOLTAGE (V)
IOL, OUTPUT ON CURRENT (µA)
70
IM/RH, M/R INPUT HIGH CURRENT (µA)
Figure 7. Output ON Current versus Temperature
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NE56610/11/12 Series
System Reset
Typical Performance Curves (continued)
IOUT, OUTPUT SINK CURRENT (mA)
Figure 13. Output Sink Current versus Output Voltage
40
VCC = VS min. -0.05V
RL = 0
TA = 25°C
35
30
25
20
15
10
5
0
0
0.2
0.4
0.6
0.8
1.0
VOUT, OUTPUT VOLTAGE (V)
Technical Discussion
Figure 14. Functional Schematic
VCC
5
delay
OSC
T
Q
R
M/R
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4
VOUT Reset
3
GND
2
SUB
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Philips Semiconductors
NE56610/11/12 Series
System Reset
TIMING DIAGRAM
The Timing Diagram shown in Figure 15 depicts the operation
of the device. Letters indicate events on the Time axis.
E-F: Between "E" and "F", VCC recovers and starts
increasing.
A: At start-up, event "A", the VCC and Reset voltages begin to
rise. Also the Reset voltage initially rises but then abruptly
returns to a low state. This is due to VCC reaching the level
(approximately 0.8V) that activates the internal bias circuitry.
F: At "F", VCC reaches the VSH upper threshold. Once again,
the "H" transport delay time (TPLH) is initiated.
B: At event "B", the "H" transport delay time (TPLH) is initiated.
This is caused by and coincident to VCC reaching the threshold
level of VSH. At this level the device is in full operation. The
Reset output remains off as VCC rises above VSH. This is
normal.
C: At event "C" VCC is above the undervoltage detect
threshold and the "H" transport delay time (TPLH) has elapsed.
At this point the device removes the hold on the VOUT reset.
VOUT Reset goes high.
In a microprocessor based system these events remove the
reset from the microprocessor, allowing it to function normally.
D-E: At "D", VCC begins to ramp down causing VOUT to follow
it. VCC continues to sag until the VSL undervoltage threshold is
reached at "E". At that time, reset signal is generated (VOUT
Reset goes low).
G: At "G", VCC is above the undervoltage detect threshold
and the "H" transport delay time (TPLH) has elapsed. At this point
the device removes the hold on the VOUT reset. VOUT Reset
goes high.
H-J: At event "H", VCC is normal, but a manual reset signal
from the logic device is applied at the M/R pin. With the falling
edge of the manual reset signal, the "H" transport delay time
(TPLH) is initiated. At "J", transport delay time (TPLH) has
elapsed and the Vout reset goes high.
K: At event "K" VCC sags to the point where the VSL
undervoltage threshold point is reached and at that level VOUT
reset goes low.
L: At event "L" the VCC voltage has deteriorated to a level
where normal internal circuit bias is no longer able to maintain a
VOUT reset and as a result may exhibit a slight rise to something
less than 0.8V. As VCC decays even further, VOUT reset also
decreases to zero.
Figure 15. Timing Diagram
V
B
C
D
F
H
K
L
∆VS
VSH
VSL
VS
VCC
V
VOUT
TPLH
A
B
TPLH
C
E
TPLH
G
J
K
L
V
M/R
VRES
H
TIME
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NE56610/11/12 Series
System Reset
Application Information
When the manual reset is not needed, the M/R, manual reset
pin is connected to ground as shown in Figure 16 - Typical Hard
Reset Circuit. A capacitor connected from VCC to ground is
recommended when the VCC supply impedance is appreciably
high. This may be the situation with a poor quality or aged
battery.
The second example, shown in Figure 17 - Manual Reset
Circuit, incorporates a manual reset switch from the M/R pin to
VCC. When the manual switch is closed, VOUT reset is logic
high. Conversely, when it is opened, VOUT reset is logic low. As
a precaution a clamp diode is placed from the M/R pin to ground
to insure that the pin does not go below - 0.3V.
Figure 16. Typical Hard Reset Circuit
Figure 17. Manual Reset Circuit
To VCC
RL
RL
Manual
Switch
5
4
VCC
VOUT
2
5
4
VCC
VOUT
M/R SUB GND
M/R SUB GND
1
To CPU
Reset Pin
To VCC
To CPU
Reset Pin
1
3
2
3
Clamp
Diode
Test Circuits
Figure 16. Test Circuit 1
Figure 17. Test Circuit 2
A2
RL
A1
10µF
/ 10V
5
4
VOUT
VCC
VCC
M/R SUB GND
V1
1
2
Input
Pulse
V2
5
4
VCC
VOUT
RL
10µF
/ 10V
5.0 V
M/R SUB GND
1
2
3
3
CRT
VRES
CL = 100pF
CRT = Oscilliscope
A - DC Ammeter
V = DC Voltmeter
Input Pulse
VS typ +0.4V
VS typ -0.4V
0V
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Philips Semiconductors
NE56610/11/12 Series
System Reset
Packing Method
The NE56610/11/12 is packed in reels, as shown here
Guard
Band
Tape Detail
Tape
Cover
Tape
Reel
Assembly
Carrier
Tape
Barcode
Label
Box
LEGAL DISCLAIMER GOES HERE
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