AD ADG406BP Lc2mos 8-/16-channel high performance analog multiplexer Datasheet

a
LC2MOS 8-/16-Channel
High Performance Analog Multiplexers
ADG406/ADG407/ADG426
FEATURES
44 V Supply Maximum Ratings
VSS to VDD Analog Signal Range
Low On Resistance (80 Ω max)
Low Power
Fast Switching
tON < 160 ns
t OFF < 150 ns
Break Before Make Switching Action
Plug-In Upgrade for
DG506A/ADG506A, DG507A/ADG507A,
DG526/ADG526A
ADG406/ADG407 are Plug-In Replacements for
DG406/DG407
FUNCTIONAL BLOCK DIAGRAMS
ADG406
ADG407
S1
S1A
DA
S8A
D
S1B
DB
S16
S8B
1 OF 16
DECODER
1 OF 8
DECODER
A0 A1 A2 A3 EN
A0 A1 A2 EN
ADG426
S1
APPLICATIONS
Audio and Video Routing
Automatic Test Equipment
Data Acquisition Systems
Battery Powered Systems
Sample Hold Systems
Communication Systems
Avionics
D
S16
DECODER/
LATCHES
WR
A0 A1 A2 A3 EN RS
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG406, ADG407 and ADG426 are monolithic CMOS
analog multiplexers. The ADG406 and ADG426 switch one of
sixteen inputs to a common output as determined by the 4-bit
binary address lines A0, A1, A2 and A3. The ADG426 has onchip address and control latches that facilitate microprocessor
interfacing. The ADG407 switches one of eight differential
inputs to a common differential output as determined by the 3bit binary address lines A0, A1 and A2. An EN input on all
devices is used to enable or disable the device. When disabled,
all channels are switched OFF.
1. Extended Signal Range
The ADG406/ADG407/ADG426 are fabricated on an
enhanced LC2MOS process giving an increased signal range
which extends to the supply rails
The ADG406/ADG407/ADG426 are designed on an enhanced
LC2MOS process that provides low power dissipation yet gives
high switching speed and low on resistance. These features
make the parts suitable for high speed data acquisition systems
and audio signal switching. Low power dissipation makes the
parts suitable for battery powered systems. Each channel
conducts equally well in both directions when ON and has an
input signal range which extends to the supplies. In the OFF
condition, signal levels up to the supplies are blocked. All
channels exhibit break before make switching action preventing
momentary shorting when switching channels. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
2. Low Power Dissipation
3. Low RON
4. Single/Dual Supply Operation
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG406/ADG407/ADG426 can be operated from a single
rail power supply. The parts are fully specified with a single
+12 V power supply and will remain functional with single
supplies as low as +5 V.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADG406/ADG407/ADG426–SPECIFICATIONS1
DUAL SUPPLY
(VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted)
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RON Match
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
ADG406, ADG426
ADG407
Channel ON Leakage ID, IS (ON)
ADG406, ADG426
ADG407
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
B Version
–40°C to
+25°C
+85°C
T Version
–55°C to
+25°C
+125°C
VSS to VDD
50
80
4
VSS to VDD
Units
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VD = ± 10 V, IS = –1 mA
VDD = +13.5 V, VSS = –13.5 V
VD = 0 V, IS = –1 mA
125
50
80
4
125
± 0.5
± 20
± 0.5
± 50
nA max
±1
±1
± 20
± 20
±1
±1
± 200
± 100
nA max
nA max
±1
±1
± 20
± 20
±1
±1
± 200
± 100
nA max
nA max
2.4
0.8
V min
V max
±1
µA max
pF typ
VIN = 0 or VDD
f = 1 MHz
RL = 300 Ω, CL = 35 pF;
V1 = ± 10 V, V2 = 710 V;
Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 7
2.4
0.8
±1
8
8
120
150
250
120
150
250
ns typ
ns max
Break Before Make Delay, tOPEN
10
10
10
10
ns min
tON (EN, WR)
120
160
110
150
175
225
130
180
120
160
110
150
175
225
130
180
ns typ
ns max
ns typ
ns max
100
100
10
100
tOFF (EN, RS)
ADG426 Only
tW, Write Pulse Width
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulse Width
Charge Injection
8
8
ns min
ns min
ns min
ns min
pC typ
OFF Isolation
–75
–75
dB typ
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
ADG406, ADG426
ADG407
CD, CS (ON)
ADG406, ADG426
ADG407
85
5
85
5
dB typ
pF typ
50
25
50
25
pF typ
pF typ
60
40
60
40
pF typ
pF typ
100
100
10
100
1
5
1
5
ISS
ISS
VS = VD = ± 10 V;
Test Circuit 4
VS = +5 V
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 10
RL = 1 kΩ, f = 100 kHz;
VEN = 0 V, Test Circuit 11
RL = 1 kΩ, f = 100 kHz, Test Circuit 12
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
IDD
VDD = +16.5 V, VSS = –16.5 V
VD = ± 10 V, VS = 710 V, Test Circuit 2
VD = ± 10 V, VS = 710 V;
Test Circuit 3
100
200
500
1
5
1
5
1
5
100
200
500
1
5
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
VDD = +16.5 V, VSS = –16.5 V
VIN = 0 V, VEN = 0 V
VIN = 0 V, VEN = 2.4 V
NOTES
1
Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
2
–2–
REV. 0
ADG406/ADG407/ADG426
SINGLE SUPPLY (V
DD
= +12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
Parameter
ANALOG SWITCH
Analog Signal Range
RON
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
ADG406, ADG426
ADG407
Channel ON Leakage ID, IS (ON)
ADG406, ADG426
ADG407
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
B Version
–40°C to
+25°C
+85°C
0 to VDD
0 to VDD
Units
Test Conditions/Comments
VD = +3 V, +8.5 V, IS = –1 mA;
VDD = +10.8 V
200
90
125
200
V
Ω typ
Ω max
± 0.5
± 20
± 0.5
± 50
nA max
±1
±1
± 20
± 20
±1
±1
± 200
± 100
nA max
nA max
±1
±1
± 20
± 20
±1
±1
± 200
± 100
nA max
nA max
2.4
0.8
V min
V max
±1
µA max
pF typ
VIN = 0 or VDD
f = 1 MHz
ns typ
ns max
RL = 300 Ω, CL = 35 pF;
V1 = 8 V/0 V, V2 = 0 V/8 V;
Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 7
90
125
2.4
0.8
±1
8
180
220
Break Before Make Delay, tOPEN
10
tON (EN, WR)
180
240
135
180
tOFF (EN, RS)
T Version
–55°C to
+25°C
+125°C
8
350
180
220
350
10
350
220
VS = VD = 8 V/0.1 V, Test Circuit 4
ns typ
180
240
135
180
350
220
ns typ
ns max
ns typ
ns max
ADG426 Only
tW, Write Pulse Width
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulse Width
Charge Injection
5
5
ns min
ns min
ns min
ns min
pC typ
OFF Isolation
–75
–75
dB typ
Channel-to-Channel Crosstalk
85
85
dB typ
CS (OFF)
CD (OFF)
ADG406, ADG426
ADG407
CD, CS (ON)
ADG406, ADG426
ADG407
8
8
pF typ
80
40
80
40
pF typ
pF typ
100
50
100
50
pF typ
pF typ
100
100
10
100
1
5
100
200
500
1
5
100
200
500
NOTES
1
Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
VS = +5 V
VS = 6 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 10
RL = 1 kΩ, f = 100 kHz;
Test Circuit 11
RL = 1 kΩ, f = 100 kHz;
Test Circuit 12
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
IDD
100
100
10
100
VDD = +13.2 V
VD = 8 V/0.1 V, VS = 0.1 V/8 V;
Test Circuit 2
VD = 8 V/0.1 V, VS = 0.1 V/8 V;
Test Circuit 3
–3–
µA typ
µA max
µA typ
µA max
VDD = +13.2 V
VIN = 0 V, VEN = 0 V
VIN = 0 V, VEN = 2.4 V
ADG406/ADG407/ADG426
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
Analog, Digital Inputs2. . . . . . . . . . . . . VSS – 2 V to VDD + 2 V
or 20 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
PLCC Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 80°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SSOP Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 122°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ORDERING GUIDE
Model
Temperature Range
Package Option*
ADG406BN
ADG406BP
ADG407BN
ADG407BP
ADG426BN
ADG426BRS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-28
P-28A
N-28
P-28A
N-28
RS-28
*N = Plastic DIP, P = Plastic Leaded Chip Carrier (PLCC), RS = Shrink Small
Outline Package (SSOP).
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Only
one absolute maximum rating may be applied at any one time.
2
Overvoltages at A, S, D, WR or RS will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
ADG406/ADG407/ADG426
Table I. Truth Table (ADG406)
PIN CONFIGURATIONS
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD
1
28
D
NC
2
27
VSS
NC
3
26 S8
S16
4
25
S7
S15
5
25 S7
S15
5
24
S6
S14
6
24 S6
S14
6
23
S5
S13
7
ADG406
23 S5
S13
7
22
S4
8
8
S3
S11
9
TOP VIEW
(Not to Scale)
22 S4
S12
TOP VIEW
(Not to Scale) 21
S12
S11
9
20
S2
S10 10
20 S2
S10 10
19
S1
S9 11
19 S1
S9 11
18
EN
GND 12
17
A0
NC 13
16
A1
A3
14
15
A2
VDD
1
28 DA
DB
2
27 VSS
NC
3
26 S8A
S8B
4
25 S7A
S7B
5
25 S7A
S7B
5
24 S6A
S6B
6
24 S6A
S6B
6
23 S5A
S5B
7
ADG407
23 S5A
22 S4A
TOP VIEW
21
S3A
(Not to Scale)
S4B
8
22 S4A
S3B
9
TOP VIEW
(Not to Scale)
ADG406
4
3
2
1
28 27 26
S8
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PLCC
DIP
VSS
ON SWITCH
VDD
EN
D
A0
NC
A1
S16
A2
NC
A3
21 S3
A1
A0
EN
DA
VSS
S8A
1
28 27 26
A2
2
A3
DB
VDD
NC
GND
12 13 14 15 16 17 18
NC = NO CONNECT
S5B
7
S4B
8
A3
A2
A1
A0
EN
X
X
X
X
X
X
X
X
X
X
X
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
WR RS
1
ON SWITCH
NC
3
20 S2A
S2B 10
S2B 10
19
S1B 11
19 S1A
S1A
S1B 11
18
EN
GND 12
17
A0
NC 13
16
A1
NC 14
15
A2
Retains Previous
Switch Condition
NONE (Address
and Enable
Latches Cleared)
NONE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
12 13 14 15 16 17 18
NC = NO CONNECT
PIN CONFIGURATION
DIP/SSOP
VDD
1
28
D
NC
2
27
VSS
RS
3
26 S8
S16
4
25
S7
S15
5
24
S6
S14
6
23
S5
S13
7
22
S4
S12
8
TOP VIEW
(Not to Scale) 21
S3
S11
9
20
S2
S10 10
19
S1
S9 11
18
EN
GND 12
17
A0
WR 13
16
A1
A3 14
15
A2
ADG426
–5–
A0
9
NC = NO CONNECT
REV. 0
21 S3A
20 S2A
S3B
Table III. Truth Table (ADG426)
ADG407
4
EN
NONE
1
2
3
4
5
6
7
8
A1
0
1
1
1
1
1
1
1
1
ON SWITCH PAIR
A2
X
0
1
0
1
0
1
0
1
EN
NC
X
0
0
1
1
0
0
1
1
A0
NC
X
0
0
0
0
1
1
1
1
A1
GND
A2
S8B
Table II. Truth Table (ADG407)
ADG406/ADG407/ADG426
TIMING DIAGRAMS (ADG426)
TERMINOLOGY
VDD
VSS
3V
WR
50%
50%
0V
tW
tS
3V
A0, A1, A2, (A3)
EN
0V
GND
RON
RON Match
tH
2V
0.8V
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of WR.
IS (OFF)
ID (OFF)
ID, IS (ON)
VD (VS)
CS (OFF)
CD (OFF)
3V
RS
50%
50%
CD, CS (ON)
CIN
tON (EN)
0V
t RS
t OFF (RS)
V0
0.8V0
SWITCH
OUTPUT
tOFF (EN)
0V
Figure 2.
Figure 2 shows the Reset Pulse Width, tRS, and the Reset Turn
Off Time, tOFF (RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. tR = tF = 20 ns.
tTRANSITION
tOPEN
VINL
VINH
IINL (IINH)
Crosstalk
Off Isolation
Charge
Injection
IDD
ISS
–6–
Most positive power supply potential.
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
Ground (0 V) reference.
Ohmic resistance between D and S.
Difference between the RON of any two
channels.
Source leakage current when the switch is off.
Drain leakage current when the switch is off.
Channel leakage current when the switch
is on.
Analog voltage on terminals D, S.
Channel input capacitance for “OFF”
condition.
Channel output capacitance for “OFF”
condition.
“ON” switch capacitance.
Digital input capacitance.
Delay time between the 50% and 90%
points of the digital input and switch “ON”
condition.
Delay time between the 50% and 90%
points of the digital input and switch “OFF”
condition.
Delay time between the 50% and 90%
points of the digital inputs and the switch
“ON” condition when switching from one
address state to another.
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
Maximum input voltage for logic “0.”
Minimum input voltage for logic “1.”
Input current of the digital input.
A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
A measure of unwanted signal coupling
through an “OFF” channel.
A measure of the glitch impulse
transferred from the digital input to the analog
output during switching.
Positive supply current.
Negative supply current.
REV. 0
ADG406/ADG407/ADG426
Typical Performance Graphs
150
400
TA = +25°C
TA = +25°C
350
VDD = +5V
VSS = 0V
120
VDD = +5V
VSS = –5V
250
VDD = +10V
VSS = –10V
RON – Ω
RON – Ω
90
300
60
30
0
–15
200
VDD = +10V
VSS = 0V
150
–10
100
VDD = +12V
VSS = –12V
VDD = +15V
VSS = –15V
–5
0
5
10
VDD = +12V
VSS = 0V
V DD = +15V
V SS = 0V
50
0
15
0
2.5
5
VD (V S) – Volts
7.5
10
VD (V S) – Volts
12.5
15
Figure 6. RON as a Function of VD (VS): Single Supplies
Figure 3. RON as a Function of VD (VS): Dual Supplies
100
150
VDD = +15V
VSS = –15V
VDD = +12V
VSS = 0V
80
120
+125°C
+125°C
90
RON – Ω
RON – Ω
60
+85°C
40
+25°C
20
0
–15
0
–10
–5
0
5
VD (V S) – Volts
10
15
0
LEAKAGE CURRENT – nA
4
6
8
VD (V S) – Volts
10
12
0.02
VDD = +15V
VSS = –15V
TA = +25°C
V DD = +12V
V SS = 0V
TA = +25°C
LEAKAGE CURRENT – nA
ID(ON)
0.06
0.04
ID(OFF)
0.02
0.00
0.01
IS(OFF)
0.00
ID(OFF)
ID(ON)
–0.01
IS(OFF)
–0.02
–10
–5
0
5
VD (V S) – Volts
10
0
15
2
4
6
VD (V S) – Volts
8
10
12
Figure 8. Leakage Currents as a Function of VD (VS)
Figure 5. Leakage Currents as a Function of VD (VS)
REV. 0
2
Figure 7. RON as a Function of VD (VS) for Different
Temperatures
0.10
–0.02
–15
+25°C
60
30
Figure 4. RON as a Function of VD (VS) for Different
Temperatures
0.08
+85°C
–7–
ADG406/ADG407/ADG426
100
100
VDD = +15V
VSS = –15V
VDD = +15V
VSS = –15V
10
10
EN = 2.4V
ISS – mA
IDD – mA
1
EN = 2.4V
1
0.1
EN = 0V
0.01
0.001
EN = 0V
0.1
2
10
10
3
10
4
5
10
10
6
10
0.0001
2
10
7
10
3
10
FREQUENCY – Hz
4
10
5
6
10
7
Figure 12. Negative Supply Current vs. Switching
Frequency
Figure 9. Positive Supply Current vs. Switching
Frequency
160
220
VDD = +15V
VSS = –15V
tON
VDD = +12V
VSS = 0V
200
140
tON
tTRANSITION
180
tTRANSITION
t – ns
t – ns
120
10
FREQUENCY – Hz
160
140
100
120
80
tOFF
tOFF
100
60
1
3
5
7
9
11
13
80
15
2
VIN – V
4
6
8
10
12
VIN – V
Figure 10. Switching Time vs. VIN (Bipolar Supply)
Figure 13. Switching Time vs. VIN (Single Supply)
300
500
VIN = +5V
VIN = +5V
400
tTRANSITION
tON
200
t – ns
t – ns
300
tON
200
tTRANSITION
100
tOFF
tOFF
100
0
±5
±7
±9
±11
±13
±15
±17
±19
0
±21
5
SUPPLY VOLTAGE – Volts
Figure 11. Switching Time vs. Bipolar Supply
7
9
11
SUPPLY VOLTAGE – Volts
13
15
Figure 14. Switching Time vs. Single Supply
–8–
REV. 0
ADG406/ADG407/ADG426
140
140
VDD = +15V
VSS = –15V
120
CROSSTALK – dB
OFF ISOLATION – dB
VDD = +15V
VSS = –15V
120
100
80
60
100
80
60
40
2
10
10
3
10
4
5
10
10
6
10
40
10 2
7
10 4
10 3
FREQUENCY – Hz
10 5
10 6
10 7
FREQUENCY – Hz
Figure 16. Crosstalk vs. Frequency
Figure 15. OFF Isolation vs. Frequency
Test Circuits
IDS
VDD
VSS
VDD
VSS
V1
S1
ID (OFF)
S2
S
D
A
D
VD
S16
VS
+0.8V
EN
VS
RON = V1/IDS
Test Circuit 3. ID (OFF)
Test Circuit 1. On Resistance
IS (OFF)
A
S1
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
ID (ON)
S2
D
S16
VS
A
VD
S16
EN
+0.8V
EN
VD
VS
Test Circuit 4. ID (ON)
Test Circuit 2. IS (OFF)
REV. 0
D
S1
–9–
2.4V
ADG406/ADG407/ADG426
VIN
50Ω
VDD
VSS
VDD
VSS
A3
S1
A2
S2 THRU S15
A1
S16
ADDRESS
DRIVE – V IN
50%
50%
V2
ADG426*
A0
2.4V
3V
V1
D
EN
RS
GND
VOUT
RL
300Ω
WR
90%
VOUT
CL
35pF
90%
tTRANSITION
tTRANSITION
*SIMILAR CONNECTION FOR ADG406/ADG407
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
VDD
VSS
VDD
VSS
A3
VIN
3V
S1
VS
ADDRESS
DRIVE – V IN
A2 S2 THRU S15
50Ω
A1
ADG426*
A0
S16
RS
2.4V
D
EN
GND
VOUT
RL
300Ω
WR
OUTPUT
CL
35pF
80%
80%
0V
tOPEN
*SIMILAR CONNECTION FOR ADG406/ADG407
Test Circuit 6. Break-Before-Make Delay, tOPEN
VDD
VSS
VDD
VSS
A3
S1
A2
3V
VS
ENABLE
DRIVE–V IN
S2 THRU S16
A1
ADG426*
50%
50%
0V
A0
2.4V
tOFF (EN)
VO
RS
D
EN
GND
VIN
50Ω
WR
VOUT
RL
300Ω
90%
90%
OUTPUT
CL
35pF
0V
tON (EN)
*SIMILAR CONNECTION FOR ADG406/ADG407
Test Circuit 7. Enable Delay, tON (EN), tOFF (EN)
–10–
REV. 0
ADG406/ADG407/ADG426
VDD
VSS
VDD
VSS
A3
S1
3V
VS
A2 S2 THRU S16
A1
A0
ADG426
RL
300Ω
RS
VRS
WR
50%
0V
VOUT
D
EN
2.4V
WR
CL
35pF
V0
tON (WR)
OUTPUT
GND
0.2V0
0V
VWR
Test Circuit 8. Write Turn-On Time, tON (WR)
VDD
VSS
VDD
VSS
A3
3V
S1
A2
A1
VS
50%
RS
S2 THRU S16
0V
ADG426
tOFF (RS)
A0
2.4V
V0
EN
D
RS
GND
VIN
VOUT
RL
300Ω
WR
CL
35pF
0.8V 0
OUTPUT
0V
Test Circuit 9. Reset Turn-Off Time, tOFF (RS)
VDD
VSS
VDD
A3
VSS
RS
2.4V
3V
A2
A1
ADG426*
A0
D
S
VS
RS
EN
VIN
VOUT
CL
1nF
GND
LOGIC
INPUT
(VIN )
∆ VOUT
VOUT
QINJ = C L x ∆VOUT
WR
*SIMILAR CONNECTION FOR ADG406/ADG407
Test Circuit 10. Charge Injection
REV. 0
–11–
ADG406/ADG407/ADG426
VDD
VDD
VDD
S16
VDD
A2
A1
S2
S1
VIN
S16
1kΩ
VIN
1kΩ
ADG426*
A1
RS
EN
GND
VOUT
A0
ADG426*
A0
2.4V
D
S1
WR
A2
VOUT
D
A3
RL
1kΩ
VSS
C1905–18–4/94
A3
EN
2.4V
RS
WR
GND
VSS
VSS
*SIMILAR CONNECTION FOR ADG406/407
VSS
*SIMILAR CONNECTION FOR ADG406/407
Test Circuit 11. OFF Isolation
Test Circuit 12. Crosstalk
OUTLINE DIMENSIONS
Dimensions shown in inches an (mm).
28-Pin Plastic (N-28)
28-Pin PLCC (P-28A)
0.048 (1.21)
0.042 (1.07)
15
0.048 (1.21)
0.042 (1.07)
4
1
14
1.565 (39.70)
1.380 (35.10)
0.060 (1.52)
0.015 (0.38)
0.250
(6.35)
MAX
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
0.050
(1.27)
BSC
0.100
(2.54)
BSC
0.070 (1.77)
MAX
0.625 (15.87)
0.600 (15.24)
0.025 (0.63)
0.015 (0.38)
26
PIN 1
IDENTIFIER
5
0.580 (14.73)
0.485 (12.32)
PIN 1
0.180 (4.57)
0.165 (4.19)
25
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
TOP VIEW
0.032 (0.81)
0.026 (0.66)
0.195 (4.95)
0.125 (3.18)
19
11
0.015 (0.381)
0.008 (0.204)
0.020
(0.50)
R
12
SEATING
PLANE
18
0.040 (1.01)
0.025 (0.64)
0.456 (11.58)
SQ
0.450 (11.43)
0.495 (12.57)
SQ
0.485 (12.32)
0.110 (2.79)
0.085 (2.16)
28-Pin SSOP (RS-28)
28
15
PRINTED IN U.S.A.
28
0.056 (1.42)
0.042 (1.07)
0.212 (5.38)
0.205 (5.207)
0.311 (7.9)
0.301 (7.64)
PIN 1
1
14
0.07 (1.78)
0.066 (1.67)
0.407 (10.34)
0.397 (10.08)
0.008 (0.203)
0.002 (0.050)
0.0256 (0.65)
BSC
0.009 (0.229)
0.005 (0.127)
8°
0°
0.03 (0.762)
0.022 (0.558)
1. LEAD NO. 1 IDENTIFIED BY A DOT.
2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
–12–
REV. 0