ON NTHD5904NT3 Power mosfet 20 v, 4.5 a, dual n−channel, chipfet Datasheet

NTHD5904N
Power MOSFET
20 V, 4.5 A, Dual N−Channel, ChipFETt
Features
• Low RDS(on) and Fast Switching Speed
• Leadless ChipFET Package has 40% Smaller Footprint than TSOP−6.
•
•
Ideal Device for Applications Where Board Space is at a Premium.
ChipFET Package Exhibits Excellent Thermal Capabilities. Ideal for
Applications Where Heat Transfer is Required.
Pb−Free Packages are Available
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V(BR)DSS
RDS(on) TYP
ID MAX
40 mW @ 4.5 V
20 V
4.5 A
55 mW @ 2.5 V
Applications
• DC−DC Buck or Boost Converters
• Low Side Switching
• Optimized for Battery and Low Side Switching Applications in
N−Channel MOSFET
D1, D2
Computing and Portable Equipment
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
Parameter
VDSS
20
V
Gate−to−Source Voltage
VGS
±8.0
V
ID
3.3
A
Continuous Drain
Current (Note 1)
Steady
State
TA=25°C
t≤5s
TA=25°C
Power Dissipation
(Note 1)
Steady
State
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
TA=85°C
TA=25°C
TA=25°C
Steady
State
4.5
PD
1.13
W
ID
2.5
A
W
IDM
10
A
TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode)
IS
2.6
A
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
260
°C
Operating Junction and Storage Temperature
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
Unit
°C/W
Junction−to−Ambient – Steady State (Note 1)
RqJA
110
Junction−to−Ambient – t ≤ 5 s (Note 1)
RqJA
60
Junction−to−Ambient – Steady State (Note 2)
RqJA
195
November, 2005 − Rev. 2
MARKING
DIAGRAM
D1 8
1 S1
1
8
D1 7
2 G1
2
7
D2 6
3 S2
3
D2 5
4 G2
4
6
5
(Top View)
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size
(Cu area = 0.214 in sq).
3. ESD Rating Information: Human Body Model (HBM) Class 0.
© Semiconductor Components Industries, LLC, 2005
PIN
CONNECTIONS
D3 M
G
0.64
tp=10 ms
ChipFET
CASE 1206A
STYLE 2
1.8
PD
Pulsed Drain Current
S1, S2
2.4
TA=85°C
TA=25°C
G1, G2
1
D3 = Specific Device Code
M = Month Code
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
NTHD5904N/D
NTHD5904N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Max
Units
VGS = 0 V, VDS = 16 V
1.0
mA
VGS = 0 V, VDS = 16 V, TJ = 125°C
10
IGSS
VDS = 0 V, VGS = "8.0 V
"100
nA
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250 mA
1.2
V
Drain−to−Source On−Resistance
RDS(on)
VGS = 4.5 V, ID = 3.3 A
40
65
mW
VGS = 2.5 V, ID = 2.3 A
55
105
VDS = 10 V, ID = 3.3 A
6.0
S
465
pF
Parameter
Symbol
Test Conditions
Min
V(BR)DSS
VGS = 0 V
20
IDSS
Typ
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
V
ON CHARACTERISTICS (Note 4)
Forward Transconductance
gFS
0.6
0.75
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
VGS = 0 V, f = 1.0 MHz,
VDS = 16 V
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
30
Total Gate Charge
QG(TOT)
4.0
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
65
nC
0.4
VGS = 2.5 V, VDS = 16 V,
ID = 3.3 A
0.8
QGD
2.0
Total Gate Charge
QG(TOT)
6.0
Threshold Gate Charge
QG(TH)
nC
0.5
VGS = 4.5 V, VDS = 10 V,
ID = 3.3 A
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
0.8
1.7
td(on)
6.0
tr
17
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
td(off)
Fall Time
VGS = 4.5 V, VDS = 16 V,
ID = 3.3 A, RG = 2.5 W
ns
17
tf
5.1
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
Discharge Time
Reverse Recovery Charge
ta
tb
VGS = 0 V, IS = 2.6 A
0.8
19.5
1.15
V
ns
6.0
VGS = 0 V, IS = 2.6 A,
dIS/dt = 100 A/ms
13
QRR
7.0
nC
4. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
Package
Shipping †
NTHD5904NT1
ChipFET
3000 / Tape & Reel
NTHD5904NT1G
ChipFET
(Pb−Free)
3000 / Tape & Reel
NTHD5904NT3
ChipFET
10,000 / Tape & Reel
NTHD5904NT3G
ChipFET
(Pb−Free)
10,000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTHD5904N
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
11
8
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
9
11
TJ = 25°C
VGS = 4 V
VGS = 3 V
2.4 V
2V
5V
10
1.8 V
7
6
1.6 V
5
4
3
1.4 V
2
1.2 V
1
1.5
1
8
7
6
5
4
3
25°C
2
TJ = −55°C
1
1.5
2
2.5
0.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.08
0
ID = 3.3 A
TJ = 25°C
0.07
0.06
0.05
0.04
0.03
0.02
2
1
3
4
5
6
3
0.06
TJ = 25°C
VGS = 2.5 V
0.05
0.04
VGS = 4.5 V
0.03
2
3
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
4
5
6
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.6
10000
ID = 3.3 A
VGS = 2.5 V
VGS = 0 V
TJ = 150°C
1.4
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
125°C
2
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.5
9
1
0
0
0
VDS ≥ 10 V
10
1.2
1.0
1000
100
TJ = 100°C
0.8
0.6
−50
10
−25
0
25
50
75
100
125
150
5
10
15
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
20
NTHD5904N
VDS = 0 V
TJ = 25°C
Ciss
1000
C, CAPACITANCE (pF)
VGS = 0 V
800
600
400
200
Coss
0
10
Crss
5
VGS
0
VDS
5
10
15
20
10
5
QG
4
VDS
6
3
2
QGS
4
QGD
2
1
ID = 3.3 A
TJ = 25°C
0
0
1
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
6
2
3
4
5
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
100
IS, SOURCE CURRENT (AMPS)
6
VDD = 16 V
ID = 3.3 A
VGS = 4.5 V
t, TIME (ns)
8
VGS
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1200
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
tf
td(off)
tr
10
td(on)
1
1
10
VGS = 0 V
TJ = 25°C
5
4
3
2
1
0
0.3
100
0.4
0.5
0.6
0.7
0.8
0.9
RG, GATE RESISTANCE (OHMS)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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4
1.0
NTHD5904N
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
D
8
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
q
6
L
5
HE
5
6
7
8
4
3
2
1
E
1
2
3
e1
4
b
c
e
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
A
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
DIM
A
b
c
D
E
e
e1
L
HE
q
MILLIMETERS
NOM
MAX
1.05
1.10
0.30
0.35
0.15
0.20
3.05
3.10
1.65
1.70
0.65 BSC
0.55 BSC
0.28
0.35
0.42
1.80
1.90
2.00
5° NOM
INCHES
NOM
0.041
0.012
0.006
0.120
0.065
0.025 BSC
0.022 BSC
0.011
0.014
0.071
0.075
5° NOM
MIN
1.00
0.25
0.10
2.95
1.55
MIN
0.039
0.010
0.004
0.116
0.061
MAX
0.043
0.014
0.008
0.122
0.067
0.017
0.079
0.05 (0.002)
SOLDERING FOOTPRINT*
2.032
0.08
2.032
0.08
0.457
0.018
0.635
0.025
1.092
0.043
0.635
0.025
0.178
0.007
0.457
0.018
0.711
0.028
0.66
0.026
SCALE 20:1
mm Ǔ
ǒinches
0.66
0.026
Basic
0.254
0.010
SCALE 20:1
Style 2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
mm Ǔ
ǒinches
NTHD5904N
ChipFET is a trademark of Vishay Siliconix
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTHD5904N/D