ON NCP81147 Precise low voltage synchronous buck controller Datasheet

NCP81147
Precise Low Voltage
Synchronous Buck
Controller with Power
Saving Mode
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MARKING
DIAGRAMS
1
81147
A
L
Y
W
G
Features
•
•
•
(*Note: Microdot may be in either location)
ROSC/EN
16
15
14
CSP
VCC
PIN CONNECTIONS
13
12
CSN/VO
LG
2
11
FBG
LX
3
10
VSEN
BOOT
4
9
FB
5
6
7
8
COMP
1
SYNC
VCCP
PGOOD
High Performance Operational Error Amplifier
Internal Soft−Start/Stop
±0.5% Internal Voltage Accuracy, 0.8 V voltage reference
OCP accuracy, Four Re−entry Times Before Latch
“Lossless” Differential Inductor Current Sensing
Internal High Precision Current Sensing Amplifier
Oscillator Frequency Range of 100 kHz − 1000 kHz
20 ns Adaptive FET Non−overlap Time of Internal Gate Driver
5.0 V to 12 V Operation
Support 1.5 V to 19 V Vin
Vout from 0.8 V to 3.3 V (5 V with 12 VCC)
Chip Enable through OSC pin
Latched Over Voltage Protection (OVP)
Internally Fixed OCP Threshold
Guaranteed Startup Into Pre−Charged Loads
Thermally Compensated Current Monitoring
Thermal Shutdown Protection
Integrated MOSFET Drivers
Integrated BOOST Diode with internal Rbst = 2.2 W
Automatic Power Saving Mode to Maximize Efficiency During Light
Load Operation
Sync Function
Remote Ground Sensing
This is a Pb−Free Device*
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
UG
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
81147
ALYWG
G
QFN16
CASE 485G
GND
The NCP81147 is a simple single phase solution with differential
phase current sensing, power saving operation, and gate drivers to
provide accurately regulated power.
The adaptive non overlap gate drive and power saving operation
circuit provide a low switching loss and high efficiency solution for
server, notebook, and desktop systems. A high performance
operational error amplifier is provided to simplify compensation of the
system. The NCP81147 features also include soft−start sequence,
accurate overvoltage and over current protection, UVLO for VCC and
VCCP, and thermal shutdown.
(Top View)
ORDERING INFORMATION
Device
Package
Shipping
Applications
NCP81147MNTXG
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Desktop and Server Systems
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 0
1
QFN16 3000 / Tape & Reel
(Pb−Free)
Publication Order Number:
NCP81147/D
VCC
PGOOD
NCP81147
15
6
2.2 W
Over Current
Detector
CSP 13
4
BOOT
5
UG
3
LX
1
VCCP
2
LG
CDIFF
+
−
Current Sense
Amplifier
CSN/VO 12
−
COMP 8
FBG 11
VREF*75%
UVP
Control Logic,
Protection,
RAMP
Generator and
PWM Logic
+
+
0.8V
−
Error Amplifier
FB 9
+
VREF*125%
1.24V
SYNC 7
Programmable
VREF*50%
UVLO
Control
OVP
−
−
VSEN 10
ROSC/EN 14
OSC
OVP,
UNLATCHED
+
OSC
16 GND
Figure 1. NCP81147 BLOCK DIAGRAM
PIN DESCRIPTIONS
Pin No.
Symbol
Description
1
VCCP
2
LG
Bottom gate MOSFET driver pin
3
LX
Switch node
4
BOOT
5
UG
6
PGOOD
7
SYNC
Synchronization Pin. The controller synchronizes on the falling edge of a square wave provided to
this pin. Short to GND if not used.
8
COMP
Output of the error amplifier
Power supply for bottom gate MOSFET drivers
Supply rail for the floating top gate driver
Top gate MOSFET driver pin
Power Good. It is an open−drain output, set free after SS (with 3x clock delay) as long as the output
voltage monitored through VSEN is within specifications.
9
FB
10
VSEN
Inverting input to the error amplifier
Output Voltage Sense
11
FBG
Remote Ground Sense
12
CSN/VO
13
CSP
14
ROSC/EN
Inductor differential sense inverting input
Inductor differential sense non−inverting input
Programs the switching frequency; EN: Pull−low to disable the device
15
VCC
Supply rail for the controller internal circuitry
16
GND
Ground reference
THERMAL PAD
Connects with the silicon substrate for good thermal contact with the PCB. Connect to GND plane.
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2
NCP81147
VCC
PGOOD
VCCP
VIN
15
3
SYNC
RFB2
CFB2
9
8
FB
LX
COMP
CH1
CF1
10
RVFB1
UG
FBG
VSEN
RF1
RFB3
2
CBOOT1
CSP
NCP81147
CSN/VO
LOUT1
5
3
Q4
2
1
VOUT
3
11
1
4
+ COUT1
LG
2
12
BOOT
1
ROSC1
13
SYNC
ROSC/EN
RNTC1
VCCP
GND
RS2
Q3
VCC
7
CSEN1
PGOOD
14
6
RS1
16
RSEN1
ENABLE
JP3
2
R2
1
ETCH
R1
Figure 2. Typical Application Circuit
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
VMAX
VMIN
Unit
VCC, VCCP
15
−0.3
V
BOOT
35V wrt/GND
40 V <100 ns
wrt/GND
15 wrt/LX
−0.3
V
High−Side Driver Output
(Top Gate)
UG
35
40 V ≤ 50 ns
wrt/GND
15 wrt/LX
−0.3 wrt/LX
−5 V < 200 ns
V
Switching Node
(Bootstrap Supply Return)
LX
35
40 < 100 ns
−5
−10 V < 200 ns
V
Low−Side Driver Output
(Bottom Gate)
LG
15
−0.3
−5 V < 200 ns
V
Controller Power Supply Voltages to GND
Boost Supply Voltage Input
6
−0.3, −1 V < 1 ms
V
PGOOD
7
−0.3, −1 V < 1 ms
V
SYNC
7
−0.3, −1 V < 1 ms
V
CSP, CSN/VO with
VCC = 12 V
10
−0.3, −1 V < 1 ms
V
All Other Pins
PGOOD
SYNC
Current Sense Amplifier
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*All signals referenced to GND unless noted otherwise.
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NCP81147
THERMAL INFORMATION
Symbol
Typ
Unit
Thermal Resistance, Junction−to−Ambient
Rating
RqJA
60
°C/W
Thermal Resistance, Junction−to−Case
RqJC
18
°C/W
Operating Junction Temperature Range
TJ
0 to 125
°C
Operating Ambient Temperature Range
TA
−40 to 85
°C
Maximum Storage Temperature Range
TSTG
−55 to +150
°C
Moisture Sensitivity Level
MSL
1
−
QFN Package
ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < TA < 85°C; 4.5 V < VCC < 13.2 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
SUPPLY OPERATING CONDITIONS
VCC Voltage Range
4.5
13.2
V
VCCP Voltage Range
4.5
13.2
V
dV/dt on VCC (Note 1)
−10
10
V/ms
dV/dt on VCCP (Note 1)
−10
10
V/ms
VCC AND BOOT INPUT SUPPLY CURRENT
VCC Operating Current
VCC = 5 V, EN = High
VCC = 12 V, EN = High
5.0
mA
VCC Supply Current
VCC = 5 V, EN = Low
VCC = 12 V, EN = Low
400
uA
VCCP INPUT SUPPLY CURRENT
VCCP Operating Current
UG and LG Open
VCCP = 5 V, EN = High
VCCP = 12 V, EN = High
mA
VCCP Supply Current
VCCP = 5 V, EN = Low
VCCP = 12 V, EN = Low
200
mA
VCC Rising
4.50
V
3.5
5.0
VCC SUPPLY VOLTAGE
VCC UVLO Start Threshold
VCC UVLO Hysteresis
VCC Rising or Falling
300
mV
VCCP SUPPLY VOLTAGE
4.2
VCCP UVLO Start Threshold
VCCP UVLO Hysteresis
V
200
mV
120
dB
18
MHz
8.0
V/ms
0.800
V
ERROR AMPLIFIER COMP
Open Loop DC Gain (Note 1)
Open Loop Unity Gain Bandwidth (Note 1)
Slew Rate (Note 1)
15
COMP pin to GND with 100 pF load
VREF
Internal Reference Voltage
Output Voltage Accuracy
Vout to FBG excluding external resistor divider
tolerance
−1.5
1.5
%
Common Mode Input Voltage Range
(Note 1, GNG, output within 10mV)
VCC ≤ 7.5 V
−0.3
3.5
V
Common Mode Input Voltage Range
(Note 1, GNG, output within 10 mV)
VCC > 7.5 V
−0.3
5.5
V
CURRENT SENSE AMPLIFIERS
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
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NCP81147
ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < TA < 85°C; 4.5 V < VCC < 13.2 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
15
%
OSCILLATOR (with no ROSC Resistor Defaults to 200 kHz)
Switching Frequency Accuracy
ROSC open
−15
OSC Gain (Note 1)
Disable threshold
10
ROSC/EN pin, Vdis_th
kHz /
mA
0.75
V
MODULATORS (PWM Comparators)
Minimum Pulse Width
Fsw = 200 kHz, OSC open
Minimum Turn Off Time (LG on)
Fsw = 200 kHz, OSC open
90
250
Magnitude of the PWM Ramp
VIN = 5 V or 12 V
Maximum Duty Cycle
OSC/EN = OPEN
80
In light load, maximum time for LG to turn on
after HG turns off
30
Minimum Skip mode frequency
350
ns
450
ns
95
%
1.50
V
kHz
SOFT−START
Soft Start Time @ 200 kHz
1024 clock cycles, OSC/EN open
5.12
ms
Rdis
120
W
SOFT−OFF
Soft OFF bleeding resistor
OVER CURRENT PROTECTION
First Over Current Threshold
Second Over Current Threshold
CSP−CSN, 4xMasking
17
CSP−CSN, Immediate action
20
23
30
mV
mV
SYNC PIN
Synchronization Input
VIL, square wave
Synchronization Input
VIH, square wave
1.0
2.5
V
V
PROTECTION AND PGOOD
Output Voltage
Logic Low, Sinking 4 mA
0.4
V
OVP Threshold
VSEN rising above 1.25 * Vref
110
125
140
%
UVP Threshold
VSEN falling below 0.75 * Vref
70
75
80
%
Vth_disoff with respect to 0.5 Vref
40
50
60
%
Power Good High Delay (Note 1)
50
ms
Power Good Low Delay (Note 1)
1
ms
40
ns
20
ns
Unlatched Overvoltage Threshold
ZERO CURRENT DETECTION (LX Pin)
Blanking Time before Zero Current
Detection (Note 1)
Capture Time for LX Voltage (Note 1)
Blanking Time after LG is < 1.0 V
Time to capture LX voltage once LG is < 1.0 V
(must be within dead time limits)
Negative LX detection voltage
Vbdls
150
300
450
mV
Positive LX detection voltage
Vbdhs
0.2
0.5
1.0
V
300 kHz
3.0
3.7
ms
Time for Vth adjustment and settling time
(Note 1)
Initial Negative Current Detection
Threshold Voltage Set Point (Note 1)
LX−GND, Includes ± 2 mV Offset Range
Vth adjustable Range (Note 1)
1.0
−16
0
mV
15
mV
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
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NCP81147
ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < TA < 85°C; 4.5 V < VCC < 13.2 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
VBOOT − VLX = 12 V, Cload = 3 nF, VCC =12 V
2.5
5
W
VBOOT − VLX = 12V, VCC =12 V
2.0
2.5
W
TrDRVH Transition Time
CLOAD = 2 nF, VCC =12 V
16
ns
TfDRVH Transition Time
CLOAD = 2 nF, VCC =12 V
11
ns
Driving High, CLOAD = 3 nF,
VCC = 12 V, VCCP =12 V
15
Unbiased, BOOT − LX = 0
45
VLX = GND, Cload = 3 nF, VCC =12 V
2.0
3.0
W
VLX = VCC, VCC =12 V
1.0
1.5
W
TrDRVL Transition Time
CLOAD = 3 nF, VCC =12 V
16
ns
TfDRVL Transition Time
CLOAD = 3 nF, VCC =12 V
11
ns
HIGH SIDE DRIVER UG
RH_TG Output Resistance, Sourcing
RH_TG Output Resistance, Sinking
TpdhDRVH Propagation Delay (Notes 1, 2)
UG Internal Resistor to LX
30
ns
kW
LOW SIDE DRIVER LG
RH_BG Output Resistance, Sourcing
RL_BG Output Resistance, Sinking
TpdhDRVL Propagation Delay (Notes 1, 2)
Driving High, CLOAD = 3 nF, VCCP = 12 V,
VCCP = 12 V
10
LX Internal Resistor to GND
20
35
ns
45
kW
180
°C
50
°C
THERMAL SHUTDOWN
Tsd Thermal Shutdown (Note 1)
150
Tsdhys Thermal Shutdown Hysteresis
(Note 1)
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
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6
NCP81147
1V
1V
Figure 3. Gate Timing Diagram
Switching Frequency
of an internal ramp signal correspondingly with a fixed
delay time. The external signal has to sit within a 0-40%
frequency window above the local frequency configured by
the Rosc resistor to allow the synchronization function
working properly.
Connecting a resistor from ROSC/EN to an external
voltage source Vpu will configure the switching frequency.
Normal range would be 100 kHz to 1 MHz. With no resistor
connected to the pin, the oscillator frequency is 200 kHz.
The switching frequency will follow the relationship:
V pu * 1.240
Power Good
kHz
mA
When Rosc = infinity (no resistor connected), Fsw =
200 kHz; when Vpu = ground, the frequency programmed
will be higher than 200 kHz. Pulling Rosc/EN pin to ground
solidly with a less than 10 kW resistor will result in the part
being disabled.
The PGOOD pin is an open drain connection with no
internal pullup resistor. An active high output signals the
normal operation of the converter. PGOOD is pulled low
during soft-start cycle, and if there is an overvoltage or
undervoltage fault. If the voltage on the VSEN pin is within
±10% of Vref (0.8 V) then the PGOOD pin will not be pulled
low.
Soft−Start
Overvoltage Protection (OV)
Soft−Start will begin if VCC, VCCP are both above their
UVLO thresholds and EN pin is set free. IC initially waits
a fixed delay time and then ramps the reference in 5.12 ms
(1024 clock cycles when Rosc open) in closed−loop
regulation. After soft−start, PGOOD signal will be released
with 3 clock cycles delay.
Protection active during soft−start:
• Overvoltage Protection always enabled;
• Undervoltage Protection is enabled after reference
voltage ramps up to 80% of the final value. During
soft−start, a UVP fault will initiate a complete soft
restart.
If the voltage on the VSEN pin exceeds the overvoltage
threshold (1000 mV or 125% Vref), the NCP81147 will latch
an overvoltage fault. During an overvoltage fault event the
UG pin will be pulled low, and the LG pin will stay high until
the voltage on the VSEN pin goes below 400 mV or 50%
Vref, then a soft-bleeding resistor will be connected from
switch node to ground to continuously discharge the output
voltage softly. To clear the overvoltage fault, toggling VCC
or EN is needed.
F SW + 200 kHz *
R OSC
@ 10
(eq. 1)
Undervoltage Protection (UV)
If the voltage on the FB pin falls below the undervoltage
threshold after the softstart cycle completes, the NCP81147
will latch an undervoltage fault. During an undervoltage
fault, both the UG and LG pins will be pulled low. Toggling
VCC power or EN will reset the undervoltage protection.
Synchronization Function
Synchronize through the SYNC pin. Synchronization
function allows different converters to share the same input
filter reducing the resulting RMS current and reducing the
need for total caps to sustain the load. Synchronized systems
also exhibit higher EMI noise immunity and better
regulation.
The device synchronizes to the Falling edge of the SYNC
pin external input signal (eg. high side gate signal, switch
node signal, distribution clock signal), and locks the phase
PreOVP Protection
If the NCP81147 is powered on but not enabled, the VSEN
pin will be monitored for preOVP condition. If the VSEN
exceeds the preset threshold, the device will force LG pin
high to protect the load. The PreOVP function will be
disabled when the device is enabled and the normal OV
function will operate instead.
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NCP81147
VPU
LG
BUFFER
VSEN
VTH
Figure 4. PreOVP circuit
Vin Detection
OCP2 will be tripped, the UG and LG will be pulled low and
latched immediately. Toggling VCC power or EN will reset
the Overcurrent protection.
The current sensing R/C network should be selected to
match the inductor time constant as below,
During the soft start after the VSEN pin exceeds 80% Vref,
UV protection will be enabled; If a UV fault is triggered in
the softstart, it will restart SS after a fixed delay. The UV
protection is to avoid IC to startup without Vin or with
insufficient Vin voltage.
(RCS1ńńRCS2) @ C +
Overcurrent Protection
L
DCR
(Notes: the actual RC network time constant may be
slightly higher)
Thus, OCP1 and OCP2 levels can be configured as,
NCP81147 measures the differential current sensing
signal through CSP and CSN/VO pin. There are two current
protection levels: OCP1 and OCP2. If the differential
voltage across pin CSP and CSN/VO is over 20 mV (but
below 30 mV) for four consecutive cycles, OCP1 will be
tripped. Both UG and LG will be forced to low to turn off the
high side and low side FETs, it is a latched condition; If the
differential voltage across pin CSP and CSN is over 30 mV,
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OCP1 +
20 mV RCS1 ) RCS2
@
DCR
RCS2
OCP2 +
30 mV RCS1 ) RCS2
@
DCR
RCS2
NCP81147
L
DCR
RS1
RS2
CS
CSP
CSN/VO
Figure 5. Differential Current Sense Network
Light Load Operation
this way, the ripple variation during transition between the
discontinuous and continuous current mode can be
minimized.
In the light load condition, NCP81147 will work in a diode
emulation mode with bottom gate turning off if the inductor
current is below zero. The system therefore works in
discontinuous conduction mode (DCM). The zero current
detection is done by sensing switch node and automatically
adjusted to minimize the low side FET body diode
conduction time (right after LG turns off) in diode emulation
mode.
If the load reduces further, COMP signal will be close or
below the internal ramp bottom triggering minimum on time
operation, the system will start skipping pulses, working in
a reduced frequency range. NCP81147 has an internal
ultrasonic timer to keep the device from working in an audio
frequency and below. This timer initiates after high side gate
off signal and expires after ~30 ms.
Normally high side gate signal will reset this ultrasonic
timer repeatedly before it expires. In a very light load or load
release, if there is no high side gate pulses until the timer
expires, the low side MOSFET(s) will be forced to turn on
to discharge the output. Through properly compensated
network the comp signal will climb up to generate next burst
of switching pulses and the converter will regulate the
output voltage to its target level. This can last a few cycles
or continuously depending on the system load level.
In light load operation, if synchronization is enabled,
NCP81147 will also check the SYNC pin input signal cycle
by cycle. If the external sync signal is within the
synchronization frequency range, the NCP81147 will
interleave its switching pulses with it after a proper delay. In
Voltage Feedback
The NCP81147 allow the output voltage to be adjusted
from 0.8 V to 5 V via an external resistor divider network
(R1, R2). The controller will regulate the output voltage to
maintain the FB pin voltage to 0.8 V reference voltage. The
relation between the resistor divider network and the output
voltage is as below;
R2 + R1 @
ǒV
0.8 V
out * 0.8 V
Ǔ
VOUT
R1
VFB
R2
Figure 6. Feedback Voltage
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NCP81147
Vin
POR_VCC
UVLO_VCC
VCC
1.24V
OSC/EN
0.75V
LG (Stays Low
until first PWM
pulse except in
case of a Fault)
UG
OVP
(125%Vref)
Vref = 0.8 V
80% Vrer
OCP/
Normal
shutdown
Vout.
FB
Vth_disoff
(50%Vref)
v
v
Softstop
UV monitor
SoftStart
Normal
1024cycle
~5ms@200kHzz
Pre-OVP valid
Figure 7. Start Up and Shutdown Timing Diagram
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10
NCP81147
PWR
ON
EN>Vdis_th
No
VCC> POR &
VCCDR > UVLO _VCCDR (16−
pin )
Yes
PreOVP detection
BG on
VSEN >OV Vth
VCC > POR &
VCCDR > UVLO
_
VCCDR
BOOT >UVLO_BOOT
No
Yes
Fosc detection
Soft Start ,
Normal Operation
OCP, OVP, UVP detection
UV (after Vout reaches UV
threshold in softstart )
OC
OV
UVP
OVP
TG OFF, BG
OFF
PGOOD=0
TG OFF, BG ON
PGOOD=0
OCP
After 4 times reentry for
1st threshod
or immediately over 2nd
threshold
No
Vout < Vth_disoff
TG OFF, BG
OFF
Yes
Vo discharge
mode
Yes
4 times
reentry
OVP
Vcc<UVLO_Vcc, Or
EN<Vdis_th Or
Boot<UVLO_Boot
No
No
Figure 8. State Diagram
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11
NCP81147
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE F
D
A
B
ÇÇÇ
ÇÇÇ
ÇÇÇ
PIN 1
LOCATION
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
0.10 C
2X
ÉÉ
ÉÉ
EXPOSED Cu
0.10 C
2X
TOP VIEW
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
(A3)
A3
ÇÇ
ÉÉ
MOLD CMPD
A1
DETAIL B
A
0.05 C
ALTERNATE
CONSTRUCTIONS
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
16X
L
MILLIMETERS
MIN
NOM MAX
0.80
0.90
1.00
0.00
0.03
0.05
0.20 REF
0.18
0.24
0.30
3.00 BSC
1.65
1.75
1.85
3.00 BSC
1.65
1.75
1.85
0.50 BSC
0.18 TYP
0.30
0.40
0.50
0.00
0.08
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
0.10 C A B
DETAIL A
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
16X
0.58
D2
PACKAGE
OUTLINE
8
4
9
1
E2
16X
2X
2X
1.84 3.30
K
1
16X
16
e
e/2
BOTTOM VIEW
16X
0.30
b
0.10 C A B
0.05 C
0.50
PITCH
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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