BSI BH616UV8010TC Ultra low power/high speed cmos sram 512k x 16 bit Datasheet

Ultra Low Power/High Speed CMOS SRAM
512K X 16 bit
BSI
BH616UV8010
n FEATURES
n DESCRIPTION
Ÿ Wide VCC low operation voltage : 1.65V ~ 3.6V
Ÿ Ultra low power consumption :
VCC = 3.0V
Operation current : 5.0mA at 70ns at 25OC
1.5mA at 1MHz at 25OC
Standby current : 2.5uA at 25OC
VCC = 2.0V
Data retention current : 2.5uA at 25OC
Ÿ High speed access time :
-70
70ns at 1.8V at 85OC
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation, no clock, no refreash
Ÿ Data retention supply voltage as low as 1.0V
The BH616UV8010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 by 16 bits and operates
in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.6V/25OC and maximum access time of 70ns at 1.8V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH616UV8010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH616UV8010 is available in DICE form, JEDEC standard 48-pin
TSOP-I and 48-ball BGA package.
n PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
VCC
RANGE
POWER CONSUMPTION
SPEED
(ns)
VCC=1.8~3.6V
BH616UV8010DI
+0OC to +70OC
(ICC, Max)
PKG TYPE
13uA
10uA
10mA
7mA
1.65V ~ 3.6V
O
70
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BH616UV8010TC
BH616UV8010TI
1
2
3
15uA
12uA
10mA
7mA
BGA-48-0608
n BLOCK DIAGRAM
n PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DICE
TSOP1-48
O
-25 C to +85 C
BH616UV8010AI
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
Operating
(ICCSB1, Max)
VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V
70
BH616UV8010TI
STANDBY
4
5
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE1
A0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
Address
Row
Buffer
Decoder
.
.
.
.
.
.
16
.
.
.
.
16
.
OE
A0
A1
A2
CE2
B
DQ8
UB
A3
A4
CE1
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
A17
A7
DQ3
VCC
E
VCC
DQ12
VSS
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
NC
A12
A13
WE
DQ7
H
A18
A8
A9
A10
A11
NC
1024 x 8192
CE2
CE1
WE
OE
UB
LB
VCC
VSS
16
Data
Input
Buffer
Data
Output
Buffer
Column I/O
Write Driver
Sense Amp
16
512
Column Decoder
DQ15
LB
Memory Array
8192
DQ0
.
6
A
1024
10
Input
9
Address Input Buffer
Control
A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH616UV8010
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Revision 1.0
Jul.
2005
BSI
BH616UV8010
n PIN DESCRIPTIONS
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 16 bit in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0-DQ15 Data Input/Output
Ports
VCC
16 bi-directional ports are used to read data from or write data into the RAM.
VSS
Ground
Power Supply
n TRUTH TABLE
MODE
Chip De-selected
(Power Down)
Output Disabled
Read
Write
CE1
CE2
WE
OE
LB
UB
H
X
X
X
X
X
High Z
High Z
ICCSB, ICCSB1
X
L
X
X
X
X
High Z
High Z
ICCSB, ICCSB1
X
X
X
X
H
H
High Z
High Z
ICCSB, ICCSB1
L
H
H
H
X
X
High Z
High Z
ICC
L
L
DOUT
DOUT
ICC
H
L
High Z
DOUT
ICC
L
H
DOUT
High Z
ICC
L
L
DIN
DIN
ICC
H
L
X
DIN
ICC
L
H
DIN
X
ICC
L
L
H
H
H
L
L
X
DQ0~DQ7 DQ8~DQ15 VCC CURRENT
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
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2005
BSI
BH616UV8010
(1)
n ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
VTERM
TBIAS
TSTG
Storage Temperature
n OPERATING RANGE
RATING
(2)
-0.5
to 4.6V
UNITS
V
-40 to +125
O
C
-60 to +150
O
C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
AMBIENT
TEMPERATURE
RANG
O
VCC
O
Commercial
0 C to + 70 C
1.65V ~ 3.6V
Industrial
-25OC to + 85OC
1.65V ~ 3.6V
n CAPACITANCE
(1)
O
(TA = 25 C, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
2. –2.0V in case of AC pulse width less than 30 ns
MAX.
Input
VIN = 0V
6
Capacitance
Input/Output
CIO
VI/O = 0V
8
Capacitance
1. This parameter is guaranteed and not 100% tested.
CIN
O
UNITS
pF
pF
O
n DC ELECTRICAL CHARACTERISTICS (TA = -25 C to +85 C)
PARAMETER
NAME
PARAMETER
VCC
Power Supply
VIL
Input Low Voltage
TEST CONDITIONS
VCC=1.8V
MIN.
TYP.(1)
MAX.
UNITS
1.65
--
3.6
V
-0.3(2)
--
Input High Voltage
IIL
Input Leakage Current
ILO
Output Leakage Current
VOL
Output Low Voltage
VCC=1.8V
1.4
VCC=3.6V
2.0
VIN = 0V to VCC,
CE1 = VIH or CE2 = VIL
V
0.8
VCC=3.6V
VIH
0.4
--
VCC+0.3(3)
V
--
--
1
uA
--
--
1
uA
--
--
VI/O = 0V to V CC,
VOH
Output High Voltage
ICC
ICC1
ICCSB
ICCSB1
(5)
CE1 = VIH or CE2 = VIL or OE = VIH or
UB = LB = VIH
V CC = Max, IOL = 0.2mA
VCC=1.8V
V CC = Max, IOL = 2.0mA
VCC=3.6V
V CC = Min, IOH = -0.1mA
VCC=1.8V
VCC-0.2
V CC = Min, IOH = -1.0mA
VCC=3.6V
2.4
Operating Power Supply
Current
CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = FMAX(4)
Operating Power Supply
Current
CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = 1MHz
Standby Current – TTL
CE1 = VIH, or CE2 = VIL,
IDQ = 0mA
Standby Current – CMOS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧V CC-0.2V or VIN≦0.2V
VCC=1.8V
--
--
VCC=3.6V
VCC=1.8V
--
--
VCC=3.6V
--
4.5
7
5.0
10
1.0
1.5
1.5
2.0
--
0.5
V
mA
mA
mA
1.0
VCC=3.6V
VCC=1.8V
V
0.4
VCC=3.6V
VCC=1.8V
0.2
--
2.5
12
2.5
15
uA
1. Typical characteristics are at TA=25OC.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICCSB1(MAX.) is 10uA/13uA at VCC=1.8V/3.6V and TA=0OC ~ 70OC.
R0201-BH616UV8010
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2005
BSI
BH616UV8010
O
O
n DATA RETENTION CHARACTERISTICS (TA = -25 C to +85 C)
SYMBOL
VDR
(3)
ICCDR
PARAMETER
TEST CONDITIONS
VCC for Data Retention
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
Data Retention Current
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
Chip Deselect to Data
Retention Time
tCDR
tR
MIN.
TYP. (1)
MAX.
UNITS
1.0
--
--
V
0.5
3.0
2.5
12
0
--
--
ns
tRC (2)
--
--
ns
VCC=1.0V
--
VCC=2.0V
uA
See Retention Waveform
Operation Recovery Time
1. TA=25OC.
2. tRC = Read Cycle Time.
3. ICCDR(MAX.) is 2.5uA /10uA at VCC=1.0V/2.0V and TA=0OC ~ 70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
VCC
VDR≧1.0V
VCC
tCDR
tR
CE1≧VCC - 0.2V
VIH
CE1
VCC
VIH
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
VDR≧1.0V
VCC
VCC
tCDR
VCC
tR
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
VCC / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1,
tCHZ2, tBDO, tOHZ, tWHZ, tOW
Output Load
Others
WAVEFORM
0.5Vcc
CL = 5pF+1TTL
Output
CL(1)
VCC
GND
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
WILL BE CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
CL = 30pF+1TTL
ALL INPUT PULSES
1 TTL
INPUTS
90%
10%
→ ←
Rise Time:
1V/ns
90%
10%
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BH616UV8010
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Jul.
2005
BSI
BH616UV8010
O
O
n AC ELECTRICAL CHARACTERISTICS (TA = -25 C to +85 C)
READ CYCLE
JEDEC
PARAMETER
NAME
PARANETER
NAME
tAVAX
tRC
tAVQX
tAA
tE1LQV
tACS1
Chip Select Access Time
tE2LQV
tACS2
Chip Select Access Time
CYCLE TIME : 70ns
DESCRIPTION
UNITS
MIN.
TYP.
MAX.
Read Cycle Time
70
--
--
ns
Address Access Time
--
--
70
ns
(CE1)
--
--
70
ns
(CE2)
--
--
70
ns
(LB, UB)
--
--
70
ns
--
--
30
ns
tBLQV
tBA
Data Byte Control Access Time
tGLQV
tOE
Output Enable to Output Valid
tE1LQX
tCLZ1
Chip Select to Output Low Z
(CE1)
10
--
--
ns
tE2LQX
tCLZ2
Chip Select to Output Low Z
(CE2)
10
--
--
ns
tBLQX
tBE
Data Byte Control to Output Low Z
(LB, UB)
10
--
--
ns
tGLQX
tOLZ
Output Enable to Output Low Z
5
--
--
ns
tE1HQZ
tCHZ1
Chip Select to Output High Z
(CE1)
--
--
25
ns
tE2HQZ
tCHZ2
Chip Select to Output High Z
(CE2)
--
--
25
ns
tBHQZ
tBDO
Data Byte Control to Output High Z
(LB, UB)
--
--
25
ns
tGHQZ
tOHZ
Output Enable to Output High Z
--
--
25
ns
tAVQX
tOH
Data Hold from Address Change
10
--
--
ns
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
tRC
ADDRESS
tOH
tAA
tOH
DOUT
R0201-BH616UV8010
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Revision 1.0
Jul.
2005
BSI
READ CYCLE 2
BH616UV8010
(1,3,4)
CE1
tACS1
CE2
(6)
tACS2
tCLZ
tCHZ
(5,6)
(5, 6)
DOUT
READ CYCLE 3
(1, 4)
tRC
ADDRESS
tAA
OE
tOH
tOE
tOLZ
CE1
(5)
tACS1
tCLZ1
CE2
(5)
tOHZ
tCHZ
(5)
(1,5)
tACS2
tCLZ2
tCHZ2
(2,5)
tBA
LB, UB
tBE
tBDO
DOUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BH616UV8010
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Revision 1.0
Jul.
2005
BSI
BH616UV8010
O
O
n AC ELECTRICAL CHARACTERISTICS (TA = -25 C to +85 C)
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARANETER
NAME
tAVAX
tWC
tAVWL
CYCLE TIME : 70ns
DESCRIPTION
UNITS
MIN.
TYP.
MAX.
Write Cycle Time
70
--
--
ns
tAS
Address Set up Time
0
--
--
ns
tAVWH
tAW
Address Valid to End of Write
50
--
--
ns
tELWH
tCW
Chip Select to End of Write
50
--
--
ns
tBLWH
tBW
Data Byte Control to End of Write
50
--
--
ns
tWLWH
tWP
Write Pulse Width
35
--
--
ns
tWHAX
tWR1
Write Recovery Time
(CE1, WE)
0
--
--
ns
tE2LAX
tWR2
Write Recovery Time
(CE2)
0
--
--
ns
tWLQZ
tWHZ
Write to Output High Z
--
--
20
ns
tDVWH
tDW
Data to Write Time Overlap
30
--
--
ns
tWHDX
tDH
Data Hold from Write Time
0
--
--
ns
tGHQZ
tOHZ
Output Disable to Output in High Z
--
--
25
ns
tWHQX
tOW
End of Write to Output Active
5
--
--
ns
(LB, UB)
n SWITCHING WAVEFORMS (WRITE CYCLE)
(1)
WRITE CYCLE 1
tWC
ADDRESS
OE
tCW
CE1
(5)
CE2
(5)
tCW
tWR1
(11)
(3)
(11)
tWR2
tBW
(3)
LB, UB
tAW
WE
tWP
tAS
tOHZ
(2)
(4,10)
DOUT
tDH
tDW
DIN
R0201-BH616UV8010
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Revision 1.0
Jul.
2005
BSI
WRITE CYCLE 2
BH616UV8010
(1,6)
tWC
ADDRESS
(5)
CE1
CE2
tCW
(11)
tCW
(11)
(5)
(12)
LB, UB
tAW
tWP
WE
tAS
tWHZ
tWR
tBW
(3)
(2)
(4,10)
tOW
(7)
(8)
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of the signal
that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BH616UV8010
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Revision 1.0
Jul.
2005
BSI
BH616UV8010
n ORDERING INFORMATION
BH616UV8010
X
X
Z
YY
SPEED
70: 70ns
PKG MATERIAL
-: Normal
G: Green
GRADE
I: -25oC ~ +85oC
PACKAGE
T: TSOP 1-48
A: BGA-48-0608
D:DICE
Note:
Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not
authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in
significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
n
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
1.4 Max.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
E1
e
D1
VIEW A
48 mini-BGA (6 x 8)
R0201-BH616UV8010
9
Revision 1.0
Jul.
2005
BSI
BH616UV8010
PACKAGE DIMENSIONS
TSOP1-48 Pin (12mm x 20mm)
R0201-BH616UV8010
10
Revision 1.0
Jul.
2005
BSI
BH616UV8010
n Revision History
Revision No.
History
Draft Date
Remark
1.0
Initial Production Version
July 15,2005
Initial
R0201-BH616UV8010
11
Revision 1.0
Jul.
2005
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