Renesas H2371 Renesas 16-bit single-chip microcomputer h8s family/h8s/2300 sery Datasheet

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Notice
1.
2.
3.
4.
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All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
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Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
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You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
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characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
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User’s Manual
16
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and
additions. Details should always be checked by referring to the
relevant text.
H8S/2378,
H8S/2378R Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2300 Series
H8S/2378
H8S/2377
H8S/2375
H8S/2374
H8S/2373
H8S/2372
H8S/2371
H8S/2370
HD64F2378B
HD64F2377
HD6432375
HD64F2374
HD6412373
HD64F2372
HD64F2371
HD64F2370
H8S/2378R
H8S/2377R
H8S/2375R
H8S/2374R
H8S/2373R
H8S/2372R
H8S/2371R
H8S/2370R
HD64F2378R
HD64F2377R
HD6432375R
HD64F2374R
HD6412373R
HD64F2372R
HD64F2371R
HD64F2370R
Rev.7.00 2009.03
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
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Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
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products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
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8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
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12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev.7.00 Mar. 18, 2009 page ii of lxvi
REJ09B0109-0700
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in
the manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In
operation with an unused pin in the open-circuit state, extra electromagnetic noise is
induced in the vicinity of LSI, an associated shoot-through current flows internally, and
malfunctions may occur due to the false recognition of the pin state as an input signal.
Unused pins should be handled as described under Handling of Unused Pins in the
manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the
states of pins are not guaranteed from the moment when power is supplied until the
reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on
reset function are not guaranteed from the moment when power is supplied until the
power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has
become stable. When switching the clock signal during program execution, wait until the
target clock signal has stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization
of the clock signal. Moreover, when switching to a clock signal produced with an
external resonator (or by an external oscillator) while program execution is in progress,
wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number,
confirm that the change will not lead to problems.
⎯ The characteristics of MPU/MCU in the same group but having different type numbers
may differ because of the differences in internal memory capacity and layout pattern.
When changing to products of different type numbers, implement a system-evaluation
test for each of the products.
Rev.7.00 Mar. 18, 2009 page iii of lxvi
REJ09B0109-0700
Configuration of This Manual
This manual comprises the following items:
1. General Precautions in the Handling of MPU/MCU Products
2. Configuration of This Manual
3. Preface
4. Main Revisions for This Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
5. Contents
6. Overview
7. Description of Functional Modules
•
CPU and System-Control Modules
•
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
8. List of Registers
9. Electrical Characteristics
10. Appendix
11. Index
Rev.7.00 Mar. 18, 2009 page iv of lxvi
REJ09B0109-0700
Preface
The H8S/2378 Group and H8S/2378R Group microcomputers (MCU) made up of the H8S/2000
CPU employing Renesas Technology original architecture as their cores, and the peripheral
functions required to configure a system.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space.
This LSI is equipped with direct memory access controller (DMAC and EXDMAC) and data
transfer controller (DTC) bus masters, ROM and RAM, a 16-bit timer pulse unit (TPU), a
programmable pulse generator (PPG), an 8-bit timer (TMR), a watchdog timer (WDT), a serial
communication interface (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O
ports as on-chip peripheral modules required for system configuration. I2C bus interface 2 (IIC2)
can also be included as an optional interface.
A high functionality bus controller is also provided, enabling fast and easy connection of DRAM
and other kinds of memory.
A single-power flash memory (F-ZTATTM*) version is available for this LSI’s ROM. The
F-ZTAT version provides flexibility as it can be reprogrammed in no time to cope with all
situations from the early stages of mass production to full-scale mass production. This is
particularly applicable to application devices with specifications that will most probably change.
This manual describes this LSI’s hardware.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using this LSI in the design of
application systems. Target users are expected to understand the fundamentals of
electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed
description of the instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
Rev.7.00 Mar. 18, 2009 page v of lxvi
REJ09B0109-0700
In order to understand the details of the CPU’s functions
Read the H8S/2600 Series, H8S/2000 Series Software Manual.
For the execution state of each instruction in this LSI, see Appendix D, Bus State during
Execution of Instructions.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 25,
List of Registers.
Examples:
Related Manuals:
Register name:
The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Number notation:
Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation:
An overbar is added to a low-active signal: xxxx
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
H8S/2378 Group and H8S/2378R Group Manuals:
Document Title
Document No.
H8S/2378 Group,H8S/2378R Group Hardware Manual
This manual
H8S/2600 Series, H8S/2000 Series Software Manual
REJ09B0139
User’s Manuals for Development Tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage
Editor Compiler Package V.6.01 User’s Manual
REJ10B0161
H8S, H8/300 Series Simulator/Debugger User’s Manual
REJ10B0211
H8S, H8/300 Series High-performance Embedded Workshop,
High-performance Debugging Interface V.3 Tutorial
REJ10B0024
High-performance Embedded Workshop V.4.04 User’s Manual
REJ10J1737
Rev.7.00 Mar. 18, 2009 page vi of lxvi
REJ09B0109-0700
Main Revisions for This Edition
Item
Page
Revision (See Manual for Details)
3.4 Memory Map in
Each Operating Mode
79
Figure amended
ROM: 512 kbytes
RAM: 32 kbytes
Mode 5
(User boot mode)
ROM: 512 kbytes
RAM: 32 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
Figure 3.2 Memory
Map for H8S/2378 and
H8S/2378R (2)
H'000000
H'000000
On-chip ROM
84
H'000000
On-chip ROM
H'080000
Figure 3.7 Memory
Map for H8S/2374 and
H8S/2374R (1)
ROM: 512 kbytes
RAM: 32 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
On-chip ROM
H'080000
H'080000
Figure amended
H'FF4000
H'FF4000
On-chip RAM/
external address
space*1
H'FFC000
Figure 3.15 Memory
Map for H8S/2370 and
H8S/2370R (2)
92
230
H'FF4000
Reserved area*4
H'FF4000
H'FF8000
On-chip RAM/
external address
space*1
H'FF8000
268
Table 6.12 Pin States
in Idle Cycle
7.3.7 DMA Terminal
Control Register
(DMATCR)
306
Reserved area*4
On-chip
H'FF4000
Reserved area*4
H'FF8000
On-chip RAM/
external address
space*3
RAM *5
H'FFC000
H'FFC000
Figure amended
64-Mbit synchronous DRAM
1 Mword × 16 bits × 4-bank configuration
8-bit column address
This LSI
(Address shift size set to 8 bits)
Figure 6.51 Example
of DQMU and DQML
Byte Control
6.9.2 Pin States in
Idle Cycle
H'FFC000
Figure amended
H'FFC000
6.7.11 Byte Access
Control
On-chip RAM*3
CS2 (RAS)
RAS
CS3 (CAS)
CAS
Table amended
Pins
Pin State
EDACKn (n = 3, 2)
High
Description amended
… The TEND pin is available only for channel B in short
address mode.
Rev.7.00 Mar. 18, 2009 page vii of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
Section 8 EXDMA
Controller (EXDMAC)
359
Description amended
8.3.5 EXDMA
Address Control
Register (EDACR)
370
… The EXDMAC can carry out high-speed data transfer, in
place of the CPU, to and from external devices and external
memory with a DACK (DMA transfer notification) facility.
Table amended
Bit
Bit Name
Initial Value
R/W
Description
15
14
SAT1
SAT0
0
0
R/W
R/W
Source Address Update Mode
These bits specify incrementing/decrementing of
the transfer source address (EDSAR). When an
external device with DACK is designated as the
transfer source in single address mode, the
specification by these bits is ignored.
0×: Fixed
10: Incremented (+1 in byte transfer, +2 in word
transfer)
11: Decremented (–1 in byte transfer, –2 in word
transfer)
372
Table amended
Bit
Bit Name
Initial Value
R/W
Description
7
6
DAT1
DAT0
0
0
R/W
R/W
Destination Address Update Mode
These bits specify incrementing/decrementing of
the transfer destination address (EDDAR). When
an external device with DACK is designated as the
transfer destination in single address mode, the
specification by these bits is ignored.
0×: Fixed
10: Incremented (+1 in byte transfer, +2 in word
transfer)
11: Decremented (–1 in byte transfer, –2 in word
transfer)
8.4.2 Address Modes
Single Address Mode:
376
Description amended
… In the example of transfer between external memory and an
external device with DACK shown in figure 8.3, data is output to
the data bus by the external device and written to external
memory in the same bus cycle.
The transfer direction, that is whether the external device with
DACK is the transfer source or transfer destination, can be
specified with the SDIR bit in EDMDR. Transfer is performed
from the external memory (EDSAR) to the external device with
DACK when SDIR = 0, and from the external device with DACK
to the external memory (EDDAR) when SDIR = 1.
Rev.7.00 Mar. 18, 2009 page viii of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
8.4.2 Address Modes
377
Figure amended
Figure 8.3 Data Flow in
Single Address Mode
External
memory
External device
with DACK
Figure 8.4 Example of 378
Timing in Single Address
Mode
Figure amended
Transfer from external memory to external device with DACK
EXDMA cycle
φ
Address bus
EDSAR
RD
Address to external memory space
RD signal to external memory space
WR
EDACK
Data output from external memory
Data bus
ETEND
Transfer from external device with DACK to external memory
EXDMA cycle
φ
Address bus
EDDAR
Address to external memory space
RD
WR
WR signal to external memory space
EDACK
Data bus
Data output from external device
with DACK
ETEND
Rev.7.00 Mar. 18, 2009 page ix of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
9.8.5 Chain Transfer
453
Description amended
… SCI and
A/D converter interrupt/activation sources, on
the other hand, are cleared when the DTC reads or writes to the
prescribed register.
10.1.4 Pin Functions
471
• P10/PO8/TIOCA0
Table amended
TPU channel 0
settings
(1) in table
below
Pin function
(2) in table below
TIOCA0 output
P10 input
P10 output
PO8 output
TIOCA0 input *1
10.9.7 Pin Functions
511
• PA7/A23/IRQ7,
PA6/A22/IRQ6,
PA5/A21/IRQ5
• PA4/A20/IRQ4
Table amended
Pin
function
PAn
input
PAn
output
PAn
input
Address
output
PAn
input
PAn
output
input
PAn
output
PAn
input
Address
output
IRQn interrupt input*
511
Table amended
Operating
mode
Pin
function
1, 2
4
Address
output
PA4
input
PA4
output
7
PA4
input
Address
output
PA4
input
PA4
output
PA4
input
PA4
output
PA4
input
Address
output
PAn
input
PAn
output
PAn
input
Address
output
IRQ4 interrupt input*
• PA3/A19, PA2/A18,
PA1/A17, PA20/A16
512
Table amended
Pin
function
10.10.5 Pin Functions
515
Address
output
PAn
input
PAn
output
PAn
input
Address
output
PAn
input
PAn
output
Table amended
PBnDDR
Pin function
—
0
1
0
1
0
1
Address
output
PBn
input
Address
output
PBn
input
PBn
output
PBn
input
Address
output
Legend added
Legend: n = 7 to 0
10.11.5 Pin Functions
519
Table amended
PCnDDR
Pin function
Rev.7.00 Mar. 18, 2009 page x of lxvi
REJ09B0109-0700
—
0
1
0
1
0
1
Address
output
PCn
input
Address
output
PCn
input
PCn
output
PCn
input
Address
output
Item
Page
Revision (See Manual for Details)
10.12.5 Pin Functions
523
Table amended
PDnDDR
Pin function
—
0
1
—
Data I/O
PDn input
PDn output
Data I/O
Legend added
Legend: n = 7 to 0
10.13.5 Pin Functions
527
Table amended
PEnDDR
Pin function
0
1
—
0
1
0
1
—
PEn
input
PEn
output
Data I/O
PEn
input
PEn
output
PEn
input
PEn
output
Data I/O
Legend added
Legend: n = 7 to 0
10.14.4 Pin Functions
531
• PF7/φ
10.16.1 Port H Data
Direction Register
(PHDDR)
Table amended
PF7DDR
541
0
1
Table amended
Bit
Bit Name
Initial Value
R/W
Description
3
PH3DDR
0
W
• Mode 7 (when EXPE = 0)
2
PH2DDR
0
W
1
PH1DDR
0
W
0
PH0DDR
0
W
Pins PH3 to PH0 are I/O ports, and their functions can be switched with
PHDDR.
1
Pin PH1 functions as the SDRAMφ* output pin when the input level of the
2
2
DCTL pin * is high. When the input level of the DCTL pin* is low, pin
PH1 is an I/O port and its function can be switched with PHDDR.
15.3.7 Serial Status
Register (SSR)
705
Note: * Only 0 can be written, to clear the flag. Alternately,
use the bit clear instruction to clear the flag.
Normal Serial
Communication
Interface Mode (When
SMIF in SCMR is 0)
Smart Card Interface
Mode (When SMIF in
SCMR is 1)
Note amended
709
Note amended
Note: 1. Only 0 can be written, to clear the flag. Alternately,
use the bit clear instruction to clear the flag.
2. Elementary time unit (etu): Transfer duration for one
bit
Rev.7.00 Mar. 18, 2009 page xi of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
15.3.9 Bit Rate
Register (BRR)
712
Table amended
Operating Frequency φ (MHz)
Table 15.3 BRR
Settings for Various Bit
Rates (Asynchronous
Mode)
8
Bit Rate
(bit/s)
n
9.8304
Error
(%)
N
n
10
Error
(%)
N
n
12
Error
(%)
N
n
N
Error
(%)
9600
0
25
0.16
0
31
0.00
0
32
–1.36
0
38
0.16
19200
0
12
0.16
0
15
0.00
0
15
1.73
0
19
–2.34
31250
0
7
0.00
0
9
–1.70
0
9
0.00
0
11
0.00
38400
—
—
—
0
7
0.00
0
7
1.73
0
9
–2.34
Operating Frequency φ (MHz)
12.288
Bit Rate
(bit/s)
713
n
14
Error
(%)
N
n
14.7456
Error
(%)
N
n
Error
(%)
N
16
n
Error
(%)
N
9600
0
39
0.00
0
45
–0.93
0
47
0.00
0
51
0.16
19200
0
19
0.00
0
22
–0.93
0
23
0.00
0
25
0.16
31250
0
11
2.40
0
13
0.00
0
14
–1.70
0
15
0.00
38400
0
9
0.00
—
—
—
0
11
0.00
0
12
0.16
Table amended
Operating Frequency φ (MHz)
17.2032
Bit Rate
(bit/s)
713
n
N
18
Error
(%)
n
19.6608
N
Error
(%)
n
N
Error
(%)
20
n
N
Error
(%)
19200
0
27
0.00
0
28
1.02
0
31
0.00
0
32
–1.36
31250
0
16
1.20
0
17
0.00
0
19
–1.70
0
19
0.00
38400
0
13
0.00
0
14
–2.34
0
15
0.00
0
15
1.73
Table amended
Operating Frequency φ (MHz)
25
714
30
Bit Rate
(bit/s)
n
N
Error
(%)
34*
1
33
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
19200
0
40
–0.76
0
48
–0.35
0
53
–0.54
0
54
0.62
31250
0
24
0.00
0
29
0.00
0
32
0.00
0
33
0.00
38400
0
19
1.73
0
23
1.73
0
26
–0.54
0
27
–1.18
Table amended
Operating
Frequency φ (MHz)
35*
2
Rev.7.00 Mar. 18, 2009 page xii of lxvi
REJ09B0109-0700
Bit Rate
(bit/s)
n
N
Error
(%)
38400
0
27
1.73
Item
Page
Revision (See Manual for Details)
15.4.4 SCI
Initialization
(Asynchronous Mode)
727
Description added
15.6.2 SCI
Initialization (Clocked
Synchronous Mode)
741
2
Section 16 I C Bus
Interface 2 (IIC2)
(Option)
2
Before transmitting and receiving data, you should first clear the
TE and RE bits in SCR to 0, then initialize the SCI as shown in
figure 15.5. Do not write to SMR, SCMR, IrCR, or SEMR while
the SCI is operating. This also applies to writing the same data
as the current register contents. …
Description added
Before transmitting and receiving data, you should first clear the
TE and RE bits in SCR to 0, then initialize the SCI as described
in a sample flowchart in figure 15.15. Do not write to SMR,
SCMR, IrCR, or SEMR while the SCI is operating. This also
applies to writing the same data as the current register contents.
…
771
Description amended
2
The I C bus interface conforms to and provides a subset of the
2
NXP Semiconductors I C bus (inter-IC bus) interface (Rev. 3)
standard and fast mode functions. The register configuration
2
that controls the I C bus differs partly from the NXP
Semiconductors configuration, however.
16.3.1 I C Bus Control 776
Register A (ICCRA)
Table amended
Table 16.2 Transfer
Rate
φ=
CKS3 CKS2 CKS1 CKS0 Clock 8 MHz
φ=
10 MHz
φ=
20 MHz
φ=
25 MHz
φ=
33 MHz
0*4
357 kHz
714 kHz*3
893 kHz*3
1179 kHz*3 1214 kHz*3 1250 kHz*3
Bit 3
Bit 2
0*4
Bit 1
0
1
Transfer Rate
Bit 0
φ=
1
34 MHz*
φ=
2
35 MHz*
0
φ/28
1
φ/40
200 kHz
250 kHz
500 kHz*
3
625 kHz*3
825 kHz*3
850 kHz*3
875 kHz*3
0
φ/48
167 kHz
208 kHz
417 kHz*3
521 kHz*3
688 kHz*3
708 kHz*3
729 kHz*3
1
φ/64
125 kHz
156 kHz
313 kHz
391 kHz
516 kHz*
3
531 kHz*3
547 kHz*3
286 kHz
Notes 3 and 4 added
2
3. I C bus interface specification (standard mode: max. 100
kHz, fast mode: max. 400 kHz).
4. Due to load conditions, etc., it may not be possible to attain
the specified transfer rate when CKS3 and CKS2 are both
cleared to 0 (bit period: 7.5 tcyc) and the operating
frequency is 20 MHz or higher. Use a bit period other than
7.5 tcyc when the operating frequency exceeds 20 MHz.
Rev.7.00 Mar. 18, 2009 page xiii of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
16.3.5 I2C Bus Status
Register (ICSR)
782
Table amended
Bit
Bit Name
Initial Value
R/W
Description
7
TDRE
0
R/W
Transmit Data Register Empty
[Setting condition]
•
When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty
•
When TRS has been set
•
When a transition from the receive mode to the
transmit mode has been made in the slave mode
[Clearing conditions]
783
•
When 0 is written in TDRE after reading TDRE = 1
•
When data is written in ICDRT
Table amended
Bit
Bit Name
Initial Value
R/W
2
AL
0
R/W
Description
Arbitration Lost Flag
This flag indicates that arbitration was lost in master
mode.
When two or more master devices attempt to seize
2
the bus at nearly the same time, if the I C bus
interface detects data differing from the data it sent, it
sets AL to 1 to indicate that the bus has been taken
by another master.
[Setting conditions]
•
If the internal SDA and SDA pin disagree at the
rise of SCL in master transmit mode
•
When the internal SDA high in master mode while
a start condition is detected
[Clearing condition]
•
16.4.7 Example of
Use
797
When 0 is written in AL/OVE after reading
AL/OVE=1
Figure amended
Start
Figure 16.14 Sample
Flowchart for Master
Transmit Mode
Initialize
Read BBSY in ICCRB
[1]
Test the status of the SCL and SDA lines.*
[2]
Select master transmit mode.*
[1]
No
BBSY=0 ?
Yes
Set MST = 1 and TRS
= 1 in ICCRA.
Write BBSY = 1
and SCP = 0.
[2]
[3]
[3]
Start condition issuance.*
[4]
Select transmit data for the first byte (slave address + R/W),
and clear TDRE to 0.
Note: * Ensure that no interrupts occur between when BBSY
is cleared to 0 and start condition [3].
Rev.7.00 Mar. 18, 2009 page xiv of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
16.4.7 Example of
Use
798
Figure amended
[14] Clear RCVD to 0.
Figure 16.15 Sample
Flowchart for Master
Receive Mode
Read RDRF in ICSR
No
[9]
RDRF=1 ?
[15] Clear ACKBT.
[16] Set slave receive mode.
Yes
Clear STOP of ICSR
[10]
Write BBSY = 0
and SCP = 0
[11]
Read STOP of ICSR
No
[12]
STOP=1 ?
Yes
Read ICDRR
[13]
Set RCVD = 0 (ICCRA)
[14]
Clear ACKBT in ICIER
[15]
Set MST = 0 (ICCRA)
[16]
End
Figure 16.17 Sample
Flowchart for Slave
Receive Mode
800
Figure amended
[2] Set the acknowledge for the transmit device.
Set ACKBT=0 in ICIER
TDRE=0 ?
[2]
No
[3] Dummy read ICDRR.
Slave transmit mode
Yes
No
[4] Wait the reception end of 1 byte.
RDRF=1 ?
[5] Judge the (last receive - 1).
Yes
Dummy read ICDRR
16.7 Usage Notes
803
[3]
[6] Read the received data, and clear RDRF to 0.
Usage note added
2
(3) I C bus interface 2
(IIC2) master receive
mode
(4) Limitations on
transfer rate setting
2
values when using I C
bus interface 2 (IIC2) in
multi-master mode
(5) Limitations on use
of bit manipulation
instructions to set MST
2
and TRS when using I C
bus interface 2 (IIC2) in
multi-master mode
Rev.7.00 Mar. 18, 2009 page xv of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
17.1 Features
806
Figure amended
Figure 17.1 Block
Diagram of A/D
Converter
AVCC
Vref
10-bit D/A
AVSS
21.1 Features
862
Description amended
• Programming/erase protection
There are three types of flash memory programming/erase
protection that may be selected: hardware protection,
software protection, and error protection.
21.1.1 Operating
Mode
864
21.3.1 Programming/
Erasing Interface
Register
872
21.3.2 Programming/
Erasing Interface
Parameter
879
21.3.3 Flash Vector
Address Control
Register (FVACR)
889
Description amended
When the mode pins are set in the reset state and a reset start
is performed, the MCU transitions to an operating mode as
shown in figure 21.2.
Description amended
• Flash Code Control and Status Register (FCCS)
FCCS is used to request monitoring of flash memory
programming/erase errors or downloading of on-chip
programs.
Description amended
When download, initialization, or on-chip program is executed,
registers of the CPU except for ER0 and ER1 are stored. The
return value of the processing result is written in ER0, ER1.
Since the stack area is used for storing the registers except for
ER0, ER1, the stack area must be saved at the processing start.
(A maximum size of a stack area to be used is 128 bytes.)
Description amended
FVACR modifies the space from which the vector table data of
the NMI interrupts is read. Normally the vector table data is read
from the address spaces from H'00001C to H'00001F.
Rev.7.00 Mar. 18, 2009 page xvi of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
21.4.2 User Program
Mode
889
Description amended
…For details on the frequency setting, see the description in
21.3.2 (2) (a), Flash programming/erasing frequency parameter
(FPEFEQ: general register ER0 of CPU).
(2) Programming
Procedure in User
Program Mode
…For details, see the descriptions in 21.3.2 (2) (a), Flash
programming/erasing frequency parameter (FPEFEQ: general
register ER0 of CPU), and 21.3.2 (2) (b), Flash user branch
address setting parameter (FUBRA: general register ER1 of
CPU).
6. The FPEFEQ and
FUBRA parameters are
set for initialization.
21.8 Serial
Communication
Interface Specification
for Boot Mode
930
Description amended
•
Size (one byte): Amount of device-code data
This is fixed at 4
(4) Inquiry and
Selection States
(b) Device Selection
Figure 21.21
Programming
Sequence
942
Figure amended
Host
Boot program
Programming selection (H'42, H'43
(9) Programming/
Erasing State
943
)
Transfer of the
programming
program
Description amended
• Programming Address (four bytes): Start address for
programming
(b) 128-byte
programming
Multiple of the size specified in response to the programming
unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'00010000)
24.2.1 Clock Division
Mode
972
25.2 Register Bits
1004
Description amended
…In clock division mode, the CPU, bus masters, and on-chip
peripheral functions all operate on the operating clock (1/2,
1/4 ) specified by bits SCK2 to SCK0.
Table amended
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
FCCS*8
—
—
FLER
—
—
—
SCO
FLASH
—
Rev.7.00 Mar. 18, 2009 page xvii of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
26.1.2 DC
Characteristics
1020
Table amended
Symbol
Min.
Typ.
Max.
Test
Unit Conditions
VIH
VCC × 0.9
—
VCC +0.3
V
RES, NMI, EMLE
VCC × 0.9
—
VCC +0.3
V
EXTAL
VCC × 0.7
—
VCC +0.3
V
Port 3,
3
P50 to P53* ,
3
3
ports 6* and 8* ,
3
ports A to H*
2.2
—
VCC +0.3
V
2.2
—
AVCC +0.3
V
–0.3
—
VCC × 0.1
V
Item
Table 26.2 DC
Characteristics (1)
Input high
voltage
STBY,
MD2 to MD0
Port 4, Port 9
Input low
voltage
RES, STBY,
MD2 to MD0,
EMLE
VIL
NMI, EXTAL
3
Ports 3 to 6* ,
3
Port 8* ,
3
ports A to H* ,
port 9
Output high All output pins
voltage
VOH
Output low
voltage
VOL
All output pins
4
P32 to P35*
–0.3
—
VCC × 0.2
V
–0.3
—
VCC × 0.2
V
VCC –0.5
—
—
V
IOH = –200 μA
VCC –1.0
—
—
V
IOH = –1 mA
—
—
0.4
V
IOL = 1.6 mA
—
—
0.5
V
IOL = 8.0 mA
Notes 4 added
4. When used as SCL0 to SCL1, SDA0 to SDA1.
Table 26.4
Permissible Output
Currents
26.1.6 Flash Memory
Characteristics
1022
Table amended
Item
Permissible output low
current (per pin)
1033
Table 26.13 Flash
Memory Characteristics
(0.35-μm F-ZTAT
Version)
1034
SCL0, 1, SDA0, 1
Symbol
Min.
Typ.
Max.
Unit
IOL
—
—
8.0
mA
—
—
2.0
Output pins other
than the above
Table amended
Item
Symbol
Min.
Typ.
Programming time*1 *2 *4
Max.
tP
—
10
200
ms/
128 bytes
Erase time*1 *3 *6
tE
—
50
1000
ms/blocks
Rewrites
NWEC
Times
tDRP
100*7
10*9
10000*8 —
Data retention time
—
Years
—
Unit
Test
Conditions
Notes 7 to 9 added
7. The minimum number of rewrites after which all
characteristics are guaranteed. (Characteristics are
guaranteed over a range of one rewrite to the minimum
number of rewrites.)
8. Reference value for 25°C. (Rewrites usually function up to
this standard value.)
9. The data retention characteristics within the specification
range, including the minimum number of rewrites.
Rev.7.00 Mar. 18, 2009 page xviii of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
26.2.2 DC
Characteristics
1036
Table amended
Symbol
Min.
Typ.
Max.
Test
Unit Conditions
VIH
VCC × 0.9
—
VCC +0.3
V
RES, NMI, EMLE
VCC × 0.9
—
VCC +0.3
V
EXTAL
VCC × 0.7
—
VCC +0.3
V
Port 3,
3
P50 to P53* ,
3
3
ports 6* and 8* ,
3
ports A to H*
2.2
—
VCC +0.3
V
2.2
—
AVCC +0.3
V
–0.3
—
VCC × 0.1
V
Item
Table 26.15 DC
Characteristics
Input high
voltage
STBY,
MD2 to MD0
Port 4, Port 9
Input low
voltage
RES, STBY,
MD2 to MD0,
EMLE
VIL
NMI, EXTAL
3
Ports 3 to 6* ,
3
Port 8* ,
3
ports A to H* ,
port 9
Table 26.17
Permissible Output
Currents
26.2.3 AC
Characteristics
Table 26.21 Bus
Timing (2)
1038
Output high All output pins
voltage
VOH
Output low
voltage
VOL
All output pins
4
P32 to P35*
–0.3
—
VCC × 0.2
V
–0.3
—
VCC × 0.2
V
VCC –0.5
—
—
V
IOH = –200 μA
VCC –1.0
—
—
V
IOH = –1 mA
—
—
0.4
V
IOL = 1.6 mA
—
—
0.5
V
IOL = 8.0 mA
Table amended
Item
<ermissible output low
current (per pin)
1044
SCL0, 1, SDA0, 1
Output pins other
than the above
Symbol
Min.
Typ.
Max.
Unit
IOL
—
—
8.0
mA
—
—
2.0
Table amended
Item
Symbol
Min.
WAIT hold time
tWTH
5
Rev.7.00 Mar. 18, 2009 page xix of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
26.3.2 DC
Characteristics
1051
Table amended
Symbol
Min.
Typ.
Max.
Test
Unit Conditions
VIH
VCC × 0.9
—
VCC +0.3
V
RES, NMI, EMLE
VCC × 0.9
—
VCC +0.3
V
EXTAL
VCC × 0.7
—
VCC +0.3
V
Port 3,
3
P50 to P53* ,
3
3
ports 6* and 8* ,
3
ports A to H*
2.2
—
VCC +0.3
V
2.2
—
AVCC +0.3
V
–0.3
—
VCC × 0.1
V
Item
Table 26.28 DC
Characteristics
Input high
voltage
STBY,
MD2 to MD0
Port 4, Port 9
Input low
voltage
RES, STBY,
MD2 to MD0,
EMLE
VIL
NMI, EXTAL
3
Ports 3 to 6* ,
3
Port 8* ,
3
ports A to H* ,
port 9
Table 26.30
Permissible Output
Currents
26.3.3 AC
Characteristics
1053
Output low
voltage
VOL
All output pins
4
P32 to P35*
VCC × 0.2
V
VCC × 0.2
V
VCC –0.5
—
—
V
IOH = –200 μA
VCC –1.0
—
—
V
IOH = –1 mA
—
—
0.4
V
IOL = 1.6 mA
—
—
0.5
V
IOL = 8.0 mA
Table amended
<ermissible output low
current (per pin)
1059
1070
Figure 26.7 Basic Bus
Timing: Two-State
Access
Figure 26.8 Basic Bus
Timing: Three-State
Access
VOH
—
—
Item
Table 26.34 Bus
Timing (2)
26.4.3 Bus Timing
Output high All output pins
voltage
–0.3
–0.3
SCL0, 1, SDA0, 1
Symbol
Min.
Typ.
Max.
Unit
IOL
—
—
8.0
mA
—
—
2.0
Output pins other
than the above
Table amended
Item
Symbol
Min.
WAIT hold time
tWTH
5
Figure amended
tEDACD1
tEDACD2
EDACK2, EDACK3
1071
Figure amended
tEDACD1
tEDACD2
EDACK2, EDACK3
Figure 26.10 Basic
Bus Timing: Two-State
Access (CS Assertion
Period Extended)
1073
Figure amended
tEDACD1
EDACK2, EDACK3
Rev.7.00 Mar. 18, 2009 page xx of lxvi
REJ09B0109-0700
tEDACD2
Item
Page
Revision (See Manual for Details)
26.4.3 Bus Timing
1074
Figure amended
Figure 26.11 Basic
Bus Timing: ThreeState Access (CS
Assertion Period
Extended)
Figure 26.14 DRAM
Access Timing: TwoState Access
tEDACD2
tEDACD1
EDACK2, EDACK3
1077
Figure amended
tEDACD2
tEDACD1
EDACK2, EDACK3
Figure 26.15 DRAM
Access Timing: TwoState Access, One
Wait
1078
Figure 26.16 DRAM
Access Timing: TwoState Burst Access
1079
Figure amended
EDACK2, EDACK3
Figure amended
tEDACD1
tEDACD2
EDACK2, EDACK3
Figure 26.17 DRAM
Access Timing: ThreeState Access (RAST =
1)
1080
Figure 26.18 DRAM
Access Timing: ThreeState Burst Access
1081
26.4.4 DMAC and
EXDMAC Timing
1088
tEDACD2
tEDACD1
EDACK2, EDACK3
Figure amended
EDACK2, EDACK3
Figure amended
tEDACD1
Figure 26.28 DMAC
and EXDMAC Single
Address Transfer
Timing: Two-State
Access
Figure 26.29 DMAC
and EXDMAC Single
Address Transfer
Timing: Three-State
Access
Figure amended
tEDACD2
EDACK2, EDACK3
1089
Figure amended
tEDACD1
tEDACD2
EDACK2, EDACK3
Rev.7.00 Mar. 18, 2009 page xxi of lxvi
REJ09B0109-0700
Item
Page
Revision (See Manual for Details)
26.4.4 DMAC and
EXDMAC Timing
1090
Figure amended
tETED
Figure 26.30 DMAC
and EXDMAC
TEND/ETEND Output
Timing
Figure 26.31 DMAC
and EXDMAC
DREQ/EDREQ Input
Timing
tETED
ETEND2, ETEND3
1090
Figure amended
tEDRQS tDERQH
EDREQ2, EDREQ3
Figure 26.32
EXDMAC EDRAK
Output Timing
1090
Figure amended
tEDRKD
EDRAK2, EDRAK3
C. Package
Dimensions
1107
Figure replaced
Figure C.2 Package
Dimensions (TLP145V)
All trademarks and registered trademarks are the property of their respective owners.
Rev.7.00 Mar. 18, 2009 page xxii of lxvi
REJ09B0109-0700
tEDRKD
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
Features .................................................................................................................................. 1
Block Diagram ....................................................................................................................... 3
Pin Description....................................................................................................................... 7
1.3.1 Pin Arrangement ....................................................................................................... 7
1.3.2 Pin Arrangement in Each Operating Mode ............................................................. 12
1.3.3 Pin Functions .......................................................................................................... 18
Section 2 CPU......................................................................................................35
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Features ................................................................................................................................ 35
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 36
2.1.2 Differences from H8/300 CPU ............................................................................... 37
2.1.3 Differences from H8/300H CPU............................................................................. 37
CPU Operating Modes ......................................................................................................... 38
2.2.1 Normal Mode.......................................................................................................... 38
2.2.2 Advanced Mode ...................................................................................................... 40
Address Space ...................................................................................................................... 42
Register Configuration ......................................................................................................... 43
2.4.1 General Registers .................................................................................................... 44
2.4.2 Program Counter (PC) ............................................................................................ 45
2.4.3 Extended Control Register (EXR) .......................................................................... 45
2.4.4 Condition-Code Register (CCR) ............................................................................. 46
2.4.5 Initial Register Values............................................................................................. 47
Data Formats ........................................................................................................................ 47
2.5.1 General Register Data Formats ............................................................................... 48
2.5.2 Memory Data Formats ............................................................................................ 50
Instruction Set ...................................................................................................................... 51
2.6.1 Table of Instructions Classified by Function .......................................................... 52
2.6.2 Basic Instruction Formats ....................................................................................... 61
Addressing Modes and Effective Address Calculation ........................................................ 62
2.7.1 Register Direct—Rn................................................................................................ 63
2.7.2 Register Indirect—@ERn ....................................................................................... 63
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)................. 63
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn ..... 63
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32....................................... 64
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 .................................................................... 64
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................... 65
2.7.8 Memory Indirect—@@aa:8 ................................................................................... 65
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2.8
2.9
2.7.9 Effective Address Calculation ................................................................................ 66
Processing States.................................................................................................................. 68
Usage Note........................................................................................................................... 69
2.9.1 Note on Bit Manipulation Instructions.................................................................... 69
Section 3 MCU Operating Modes ....................................................................... 71
3.1
3.2
3.3
3.4
Operating Mode Selection.................................................................................................... 71
Register Descriptions ........................................................................................................... 72
3.2.1 Mode Control Register (MDCR) ............................................................................ 72
3.2.2 System Control Register (SYSCR) ......................................................................... 72
Operating Mode Descriptions .............................................................................................. 75
3.3.1 Mode 1 .................................................................................................................... 75
3.3.2 Mode 2 .................................................................................................................... 75
3.3.3 Mode 3 .................................................................................................................... 75
3.3.4 Mode 4 .................................................................................................................... 75
3.3.5 Mode 5 .................................................................................................................... 76
3.3.6 Mode 7 .................................................................................................................... 76
3.3.7 Pin Functions .......................................................................................................... 77
Memory Map in Each Operating Mode ............................................................................... 78
Section 4 Exception Handling ............................................................................. 93
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Exception Handling Types and Priority ............................................................................... 93
Exception Sources and Exception Vector Table .................................................................. 93
Reset..................................................................................................................................... 95
4.3.1 Reset Exception Handling....................................................................................... 95
4.3.2 Interrupts after Reset............................................................................................... 97
4.3.3 On-Chip Peripheral Functions after Reset Release ................................................. 97
Trace Exception Handling.................................................................................................... 98
Interrupt Exception Handling............................................................................................... 98
Trap Instruction Exception Handling................................................................................... 99
Stack Status after Exception Handling............................................................................... 100
Usage Note......................................................................................................................... 101
Section 5 Interrupt Controller............................................................................ 103
5.1
5.2
5.3
Features .............................................................................................................................. 103
Input/Output Pins ............................................................................................................... 105
Register Descriptions ......................................................................................................... 105
5.3.1 Interrupt Control Register (INTCR)...................................................................... 106
5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................. 106
5.3.3 IRQ Enable Register (IER) ................................................................................... 108
5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 110
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5.4
5.5
5.6
5.7
5.3.5 IRQ Status Register (ISR)..................................................................................... 116
5.3.6 IRQ Pin Select Register (ITSR) ............................................................................ 117
5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 119
Interrupt Sources ................................................................................................................ 120
5.4.1 External Interrupts ................................................................................................ 120
5.4.2 Internal Interrupts.................................................................................................. 121
Interrupt Exception Handling Vector Table....................................................................... 121
Interrupt Control Modes and Interrupt Operation .............................................................. 127
5.6.1 Interrupt Control Mode 0 ...................................................................................... 127
5.6.2 Interrupt Control Mode 2 ...................................................................................... 129
5.6.3 Interrupt Exception Handling Sequence ............................................................... 130
5.6.4 Interrupt Response Times ..................................................................................... 132
5.6.5 DTC and DMAC Activation by Interrupt ............................................................. 133
Usage Notes ....................................................................................................................... 134
5.7.1 Conflict between Interrupt Generation and Disabling .......................................... 134
5.7.2 Instructions that Disable Interrupts ....................................................................... 135
5.7.3 Times when Interrupts Are Disabled .................................................................... 135
5.7.4 Interrupts during Execution of EEPMOV Instruction........................................... 135
5.7.5 Change of IRQ Pin Select Register (ITSR) Setting .............................................. 135
5.7.6 IRQ Status Register (ISR)..................................................................................... 136
Section 6 Bus Controller (BSC).........................................................................137
6.1
6.2
6.3
6.4
Features .............................................................................................................................. 137
Input/Output Pins ............................................................................................................... 139
Register Descriptions ......................................................................................................... 142
6.3.1 Bus Width Control Register (ABWCR)................................................................ 143
6.3.2 Access State Control Register (ASTCR) .............................................................. 143
6.3.3 Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)............................................ 144
6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................. 150
6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL).................... 151
6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL)............................... 153
6.3.7 Bus Control Register (BCR) ................................................................................. 154
6.3.8 DRAM Control Register (DRAMCR) .................................................................. 156
6.3.9 DRAM Access Control Register (DRACCR) ....................................................... 164
6.3.10 Refresh Control Register (REFCR) ...................................................................... 167
6.3.11 Refresh Timer Counter (RTCNT)......................................................................... 170
6.3.12 Refresh Time Constant Register (RTCOR) .......................................................... 170
Bus Control ........................................................................................................................ 171
6.4.1 Area Division ........................................................................................................ 171
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6.6
6.7
6.4.2 Bus Specifications................................................................................................. 172
6.4.3 Memory Interfaces ................................................................................................ 174
6.4.4 Chip Select Signals ............................................................................................... 175
Basic Bus Interface ............................................................................................................ 176
6.5.1 Data Size and Data Alignment.............................................................................. 176
6.5.2 Valid Strobes......................................................................................................... 178
6.5.3 Basic Timing......................................................................................................... 178
6.5.4 Wait Control ......................................................................................................... 187
6.5.5 Read Strobe (RD) Timing ..................................................................................... 188
6.5.6 Extension of Chip Select (CS) Assertion Period................................................... 189
DRAM Interface ................................................................................................................ 191
6.6.1 Setting DRAM Space............................................................................................ 191
6.6.2 Address Multiplexing............................................................................................ 191
6.6.3 Data Bus................................................................................................................ 192
6.6.4 Pins Used for DRAM Interface............................................................................. 193
6.6.5 Basic Timing......................................................................................................... 194
6.6.6 Column Address Output Cycle Control ................................................................ 195
6.6.7 Row Address Output State Control....................................................................... 196
6.6.8 Precharge State Control ........................................................................................ 198
6.6.9 Wait Control ......................................................................................................... 199
6.6.10 Byte Access Control ............................................................................................. 202
6.6.11 Burst Operation..................................................................................................... 203
6.6.12 Refresh Control..................................................................................................... 208
6.6.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface ..... 213
Synchronous DRAM Interface........................................................................................... 216
6.7.1 Setting Continuous Synchronous DRAM Space................................................... 216
6.7.2 Address Multiplexing............................................................................................ 217
6.7.3 Data Bus................................................................................................................ 218
6.7.4 Pins Used for Synchronous DRAM Interface ....................................................... 218
6.7.5 Synchronous DRAM Clock .................................................................................. 220
6.7.6 Basic Timing......................................................................................................... 220
6.7.7 CAS Latency Control............................................................................................ 222
6.7.8 Row Address Output State Control....................................................................... 224
6.7.9 Precharge State Count........................................................................................... 225
6.7.10 Bus Cycle Control in Write Cycle ........................................................................ 227
6.7.11 Byte Access Control ............................................................................................. 228
6.7.12 Burst Operation..................................................................................................... 231
6.7.13 Refresh Control..................................................................................................... 234
6.7.14 Mode Register Setting of Synchronous DRAM.................................................... 240
6.7.15 DMAC and EXDMAC Single Address Transfer Mode
and Synchronous DRAM Interface....................................................................... 241
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6.8
6.9
6.10
6.11
6.12
6.13
6.14
Burst ROM Interface.......................................................................................................... 246
6.8.1 Basic Timing......................................................................................................... 246
6.8.2 Wait Control ......................................................................................................... 248
6.8.3 Write Access ......................................................................................................... 248
Idle Cycle ........................................................................................................................... 249
6.9.1 Operation .............................................................................................................. 249
6.9.2 Pin States in Idle Cycle ......................................................................................... 268
Write Data Buffer Function ............................................................................................... 268
Bus Release........................................................................................................................ 269
6.11.1 Operation .............................................................................................................. 270
6.11.2 Pin States in External Bus Released State............................................................. 271
6.11.3 Transition Timing ................................................................................................. 272
Bus Arbitration................................................................................................................... 274
6.12.1 Operation .............................................................................................................. 274
6.12.2 Bus Transfer Timing ............................................................................................. 275
Bus Controller Operation in Reset ..................................................................................... 276
Usage Notes ....................................................................................................................... 277
6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 277
6.14.2 External Bus Release Function and Software Standby ......................................... 277
6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 277
6.14.4 BREQO Output Timing ........................................................................................ 278
6.14.5 Notes on Usage of the Synchronous DRAM ........................................................ 278
Section 7 DMA Controller (DMAC) .................................................................279
7.1
7.2
7.3
7.4
7.5
Features .............................................................................................................................. 279
Input/Output Pins ............................................................................................................... 281
Register Descriptions ......................................................................................................... 281
7.3.1 Memory Address Registers (MARA and MARB) ................................................ 283
7.3.2 I/O Address Registers (IOARA and IOARB) ....................................................... 283
7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ................................... 284
7.3.4 DMA Control Registers (DMACRA and DMACRB) .......................................... 285
7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 293
7.3.6 DMA Write Enable Register (DMAWER) ........................................................... 304
7.3.7 DMA Terminal Control Register (DMATCR)...................................................... 306
Activation Sources ............................................................................................................. 307
7.4.1 Activation by Internal Interrupt Request............................................................... 308
7.4.2 Activation by External Request ............................................................................ 309
7.4.3 Activation by Auto-Request.................................................................................. 309
Operation............................................................................................................................ 309
7.5.1 Transfer Modes ..................................................................................................... 309
7.5.2 Sequential Mode ................................................................................................... 312
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7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
7.5.11
7.5.12
7.5.13
7.6
7.7
Idle Mode.............................................................................................................. 314
Repeat Mode ......................................................................................................... 316
Single Address Mode............................................................................................ 320
Normal Mode........................................................................................................ 323
Block Transfer Mode ............................................................................................ 326
Basic Bus Cycles................................................................................................... 331
DMA Transfer (Dual Address Mode) Bus Cycles ................................................ 332
DMA Transfer (Single Address Mode) Bus Cycles.............................................. 340
Write Data Buffer Function .................................................................................. 346
Multi-Channel Operation ...................................................................................... 347
Relation between DMAC and External Bus Requests, Refresh Cycles,
and EXDMAC ...................................................................................................... 349
7.5.14 DMAC and NMI Interrupts................................................................................... 350
7.5.15 Forced Termination of DMAC Operation............................................................. 351
7.5.16 Clearing Full Address Mode ................................................................................. 352
Interrupt Sources ................................................................................................................ 353
Usage Notes ....................................................................................................................... 354
7.7.1 DMAC Register Access during Operation............................................................ 354
7.7.2 Module Stop.......................................................................................................... 355
7.7.3 Write Data Buffer Function .................................................................................. 356
7.7.4 TEND Output........................................................................................................ 356
7.7.5 Activation by Falling Edge on DREQ Pin ............................................................ 357
7.7.6 Activation Source Acceptance .............................................................................. 358
7.7.7 Internal Interrupt after End of Transfer................................................................. 358
7.7.8 Channel Re-Setting ............................................................................................... 358
Section 8 EXDMA Controller (EXDMAC) ...................................................... 359
8.1
8.2
8.3
8.4
Features .............................................................................................................................. 359
Input/Output Pins ............................................................................................................... 361
Register Descriptions ......................................................................................................... 362
8.3.1 EXDMA Source Address Register (EDSAR) ....................................................... 362
8.3.2 EXDMA Destination Address Register (EDDAR) ............................................... 362
8.3.3 EXDMA Transfer Count Register (EDTCR)........................................................ 363
8.3.4 EXDMA Mode Control Register (EDMDR) ........................................................ 365
8.3.5 EXDMA Address Control Register (EDACR) ..................................................... 370
Operation............................................................................................................................ 374
8.4.1 Transfer Modes ..................................................................................................... 374
8.4.2 Address Modes ..................................................................................................... 375
8.4.3 DMA Transfer Requests ....................................................................................... 379
8.4.4 Bus Modes ............................................................................................................ 379
8.4.5 Transfer Modes ..................................................................................................... 381
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8.5
8.6
8.4.6 Repeat Area Function ........................................................................................... 383
8.4.7 Registers during DMA Transfer Operation........................................................... 385
8.4.8 Channel Priority Order.......................................................................................... 390
8.4.9 EXDMAC Bus Cycles (Dual Address Mode)....................................................... 393
8.4.10 EXDMAC Bus Cycles (Single Address Mode) .................................................... 400
8.4.11 Examples of Operation Timing in Each Mode...................................................... 405
8.4.12 Ending DMA Transfer .......................................................................................... 418
8.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 419
Interrupt Sources ................................................................................................................ 420
Usage Notes ....................................................................................................................... 422
8.6.1 EXDMAC Register Access during Operation ...................................................... 422
8.6.2 Module Stop State................................................................................................. 422
8.6.3 EDREQ Pin Falling Edge Activation.................................................................... 422
8.6.4 Activation Source Acceptance .............................................................................. 423
8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR ....................................... 423
8.6.6 ETEND Pin and CBR Refresh Cycle.................................................................... 423
Section 9 Data Transfer Controller (DTC) ........................................................425
9.1
9.2
9.3
9.4
9.5
9.6
Features .............................................................................................................................. 425
Register Descriptions ......................................................................................................... 427
9.2.1 DTC Mode Register A (MRA) ............................................................................. 427
9.2.2 DTC Mode Register B (MRB).............................................................................. 429
9.2.3 DTC Source Address Register (SAR)................................................................... 429
9.2.4 DTC Destination Address Register (DAR)........................................................... 429
9.2.5 DTC Transfer Count Register A (CRA) ............................................................... 430
9.2.6 DTC Transfer Count Register B (CRB)................................................................ 430
9.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) ...................................... 430
9.2.8 DTC Vector Register (DTVECR)......................................................................... 431
Activation Sources ............................................................................................................. 432
Location of Register Information and DTC Vector Table ................................................. 433
Operation............................................................................................................................ 437
9.5.1 Normal Mode........................................................................................................ 440
9.5.2 Repeat Mode ......................................................................................................... 441
9.5.3 Block Transfer Mode ............................................................................................ 442
9.5.4 Chain Transfer ...................................................................................................... 443
9.5.5 Interrupt Sources................................................................................................... 444
9.5.6 Operation Timing.................................................................................................. 444
9.5.7 Number of DTC Execution States ........................................................................ 445
Procedures for Using DTC................................................................................................. 447
9.6.1 Activation by Interrupt.......................................................................................... 447
9.6.2 Activation by Software ......................................................................................... 447
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9.8
Examples of Use of the DTC ............................................................................................. 448
9.7.1 Normal Mode........................................................................................................ 448
9.7.2 Chain Transfer ...................................................................................................... 449
9.7.3 Chain Transfer when Counter = 0......................................................................... 450
9.7.4 Software Activation .............................................................................................. 452
Usage Notes ....................................................................................................................... 452
9.8.1 Module Stop Mode Setting ................................................................................... 452
9.8.2 On-Chip RAM ...................................................................................................... 452
9.8.3 DTCE Bit Setting.................................................................................................. 453
9.8.4 DMAC Transfer End Interrupt.............................................................................. 453
9.8.5 Chain Transfer ...................................................................................................... 453
Section 10 I/O Ports........................................................................................... 455
10.1 Port 1.................................................................................................................................. 460
10.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 460
10.1.2 Port 1 Data Register (P1DR)................................................................................. 461
10.1.3 Port 1 Register (PORT1)....................................................................................... 461
10.1.4 Pin Functions ........................................................................................................ 462
10.2 Port 2.................................................................................................................................. 472
10.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 472
10.2.2 Port 2 Data Register (P2DR)................................................................................. 473
10.2.3 Port 2 Register (PORT2)....................................................................................... 473
10.2.4 Pin Functions ........................................................................................................ 474
10.3 Port 3.................................................................................................................................. 482
10.3.1 Port 3 Data Direction Register (P3DDR).............................................................. 482
10.3.2 Port 3 Data Register (P3DR)................................................................................. 483
10.3.3 Port 3 Register (PORT3)....................................................................................... 483
10.3.4 Port 3 Open Drain Control Register (P3ODR)...................................................... 484
10.3.5 Port Function Control Register 2 (PFCR2) ........................................................... 485
10.3.6 Pin Functions ........................................................................................................ 486
10.4 Port 4.................................................................................................................................. 489
10.4.1 Port 4 Register (PORT4)....................................................................................... 489
10.4.2 Pin Functions ........................................................................................................ 490
10.5 Port 5.................................................................................................................................. 491
10.5.1 Port 5 Data Direction Register (P5DDR).............................................................. 491
10.5.2 Port 5 Data Register (P5DR)................................................................................. 491
10.5.3 Port 5 Register (PORT5)....................................................................................... 492
10.5.4 Pin Functions ........................................................................................................ 492
10.6 Port 6.................................................................................................................................. 494
10.6.1 Port 6 Data Direction Register (P6DDR).............................................................. 494
10.6.2 Port 6 Data Register (P6DR)................................................................................. 495
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10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.6.3 Port 6 Register (PORT6)....................................................................................... 495
10.6.4 Pin Functions ........................................................................................................ 496
Port 8.................................................................................................................................. 499
10.7.1 Port 8 Data Direction Register (P8DDR).............................................................. 499
10.7.2 Port 8 Data Register (P8DR)................................................................................. 500
10.7.3 Port 8 Register (PORT8)....................................................................................... 500
10.7.4 Pin Functions ........................................................................................................ 501
Port 9.................................................................................................................................. 505
10.8.1 Port 9 Register (PORT9)....................................................................................... 505
10.8.2 Pin Functions ........................................................................................................ 506
Port A................................................................................................................................. 507
10.9.1 Port A Data Direction Register (PADDR) ............................................................ 507
10.9.2 Port A Data Register (PADR) ............................................................................... 508
10.9.3 Port A Register (PORTA) ..................................................................................... 508
10.9.4 Port A Pull-Up MOS Control Register (PAPCR) ................................................. 509
10.9.5 Port A Open Drain Control Register (PAODR).................................................... 509
10.9.6 Port Function Control Register 1 (PFCR1) ........................................................... 509
10.9.7 Pin Functions ........................................................................................................ 511
10.9.8 Port A Input Pull-Up MOS States......................................................................... 512
Port B ................................................................................................................................. 513
10.10.1 Port B Data Direction Register (PBDDR) ............................................................ 513
10.10.2 Port B Data Register (PBDR) ............................................................................... 514
10.10.3 Port B Register (PORTB) ..................................................................................... 514
10.10.4 Port B Pull-Up MOS Control Register (PBPCR).................................................. 515
10.10.5 Pin Functions ........................................................................................................ 515
10.10.6 Port B Input Pull-Up MOS States ......................................................................... 516
Port C ................................................................................................................................. 517
10.11.1 Port C Data Direction Register (PCDDR) ............................................................ 517
10.11.2 Port C Data Register (PCDR) ............................................................................... 518
10.11.3 Port C Register (PORTC) ..................................................................................... 518
10.11.4 Port C Pull-Up MOS Control Register (PCPCR).................................................. 519
10.11.5 Pin Functions ........................................................................................................ 519
10.11.6 Port C Input Pull-Up MOS States ......................................................................... 520
Port D................................................................................................................................. 521
10.12.1 Port D Data Direction Register (PDDDR) ............................................................ 521
10.12.2 Port D Data Register (PDDR) ............................................................................... 522
10.12.3 Port D Register (PORTD) ..................................................................................... 522
10.12.4 Port D Pull-up Control Register (PDPCR)............................................................ 523
10.12.5 Pin Functions ........................................................................................................ 523
10.12.6 Port D Input Pull-Up MOS States......................................................................... 524
Port E ................................................................................................................................. 525
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10.13.1 Port E Data Direction Register (PEDDR) ............................................................. 525
10.13.2 Port E Data Register (PEDR)................................................................................ 526
10.13.3 Port E Register (PORTE)...................................................................................... 526
10.13.4 Port E Pull-up Control Register (PEPCR) ............................................................ 527
10.13.5 Pin Functions ........................................................................................................ 527
10.13.6 Port E Input Pull-Up MOS States ......................................................................... 528
10.14 Port F.................................................................................................................................. 528
10.14.1 Port F Data Direction Register (PFDDR) ............................................................. 529
10.14.2 Port F Data Register (PFDR) ................................................................................ 530
10.14.3 Port F Register (PORTF) ...................................................................................... 530
10.14.4 Pin Functions ........................................................................................................ 531
10.15 Port G................................................................................................................................. 535
10.15.1 Port G Data Direction Register (PGDDR) ............................................................ 535
10.15.2 Port G Data Register (PGDR) ............................................................................... 536
10.15.3 Port G Register (PORTG) ..................................................................................... 536
10.15.4 Port Function Control Register 0 (PFCR0) ........................................................... 537
10.15.5 Pin Functions ........................................................................................................ 537
10.16 Port H................................................................................................................................. 540
10.16.1 Port H Data Direction Register (PHDDR) ............................................................ 540
10.16.2 Port H Data Register (PHDR) ............................................................................... 542
10.16.3 Port H Register (PORTH) ..................................................................................... 542
10.16.4 Pin Functions ........................................................................................................ 543
Section 11 16-Bit Timer Pulse Unit (TPU) ....................................................... 545
11.1 Features .............................................................................................................................. 545
11.2 Input/Output Pins ............................................................................................................... 549
11.3 Register Descriptions ......................................................................................................... 550
11.3.1 Timer Control Register (TCR) .............................................................................. 552
11.3.2 Timer Mode Register (TMDR) ............................................................................. 557
11.3.3 Timer I/O Control Register (TIOR) ...................................................................... 558
11.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 576
11.3.5 Timer Status Register (TSR)................................................................................. 578
11.3.6 Timer Counter (TCNT)......................................................................................... 581
11.3.7 Timer General Register (TGR) ............................................................................. 581
11.3.8 Timer Start Register (TSTR)................................................................................. 581
11.3.9 Timer Synchronous Register (TSYR)................................................................... 582
11.4 Operation............................................................................................................................ 583
11.4.1 Basic Functions..................................................................................................... 583
11.4.2 Synchronous Operation......................................................................................... 589
11.4.3 Buffer Operation ................................................................................................... 591
11.4.4 Cascaded Operation .............................................................................................. 596
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11.5
11.6
11.7
11.8
11.9
11.10
11.4.5 PWM Modes ......................................................................................................... 598
11.4.6 Phase Counting Mode ........................................................................................... 603
Interrupt Sources ................................................................................................................ 609
DTC Activation.................................................................................................................. 611
DMAC Activation.............................................................................................................. 611
A/D Converter Activation .................................................................................................. 611
Operation Timing............................................................................................................... 612
11.9.1 Input/Output Timing ............................................................................................. 612
11.9.2 Interrupt Signal Timing......................................................................................... 615
Usage Notes ....................................................................................................................... 619
11.10.1 Module Stop Mode Setting ................................................................................... 619
11.10.2 Input Clock Restrictions ....................................................................................... 619
11.10.3 Caution on Cycle Setting ...................................................................................... 620
11.10.4 Contention between TCNT Write and Clear Operations ...................................... 620
11.10.5 Contention between TCNT Write and Increment Operations............................... 621
11.10.6 Contention between TGR Write and Compare Match .......................................... 622
11.10.7 Contention between Buffer Register Write and Compare Match ......................... 623
11.10.8 Contention between TGR Read and Input Capture............................................... 624
11.10.9 Contention between TGR Write and Input Capture.............................................. 625
11.10.10 Contention between Buffer Register Write and Input Capture .......................... 626
11.10.11 Contention between Overflow/Underflow and Counter Clearing...................... 627
11.10.12 Contention between TCNT Write and Overflow/Underflow............................. 628
11.10.13 Multiplexing of I/O Pins .................................................................................... 629
11.10.14 Interrupts and Module Stop Mode ..................................................................... 629
Section 12 Programmable Pulse Generator (PPG) ............................................631
12.1 Features .............................................................................................................................. 631
12.2 Input/Output Pins ............................................................................................................... 633
12.3 Register Descriptions ......................................................................................................... 633
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL).......................................... 634
12.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 635
12.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 635
12.3.4 PPG Output Control Register (PCR)..................................................................... 638
12.3.5 PPG Output Mode Register (PMR)....................................................................... 639
12.4 Operation............................................................................................................................ 641
12.4.1 Output Timing....................................................................................................... 642
12.4.2 Sample Setup Procedure for Normal Pulse Output ............................................... 643
12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) ........... 644
12.4.4 Non-Overlapping Pulse Output............................................................................. 645
12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ............................... 647
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12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase
Complementary Non-Overlapping Output) .......................................................... 648
12.4.7 Inverted Pulse Output ........................................................................................... 650
12.4.8 Pulse Output Triggered by Input Capture ............................................................. 651
12.5 Usage Notes ....................................................................................................................... 651
12.5.1 Module Stop Mode Setting ................................................................................... 651
12.5.2 Operation of Pulse Output Pins............................................................................. 651
Section 13 8-Bit Timers (TMR) ........................................................................ 653
13.1 Features .............................................................................................................................. 653
13.2 Input/Output Pins ............................................................................................................... 655
13.3 Register Descriptions ......................................................................................................... 655
13.3.1 Timer Counter (TCNT)......................................................................................... 656
13.3.2 Time Constant Register A (TCORA).................................................................... 656
13.3.3 Time Constant Register B (TCORB) .................................................................... 656
13.3.4 Timer Control Register (TCR) .............................................................................. 657
13.3.5 Timer Control/Status Register (TCSR) ................................................................. 659
13.4 Operation............................................................................................................................ 663
13.4.1 Pulse Output.......................................................................................................... 663
13.5 Operation Timing............................................................................................................... 664
13.5.1 TCNT Incrementation Timing .............................................................................. 664
13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 665
13.5.3 Timing of Timer Output when Compare-Match Occurs....................................... 666
13.5.4 Timing of Compare Match Clear .......................................................................... 666
13.5.5 Timing of TCNT External Reset........................................................................... 667
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 667
13.6 Operation with Cascaded Connection ................................................................................ 668
13.6.1 16-Bit Counter Mode ............................................................................................ 668
13.6.2 Compare Match Count Mode................................................................................ 668
13.7 Interrupt Sources ................................................................................................................ 669
13.7.1 Interrupt Sources and DTC Activation ................................................................. 669
13.7.2 A/D Converter Activation..................................................................................... 669
13.8 Usage Notes ....................................................................................................................... 670
13.8.1 Contention between TCNT Write and Clear......................................................... 670
13.8.2 Contention between TCNT Write and Increment ................................................. 671
13.8.3 Contention between TCOR Write and Compare Match ....................................... 672
13.8.4 Contention between Compare Matches A and B .................................................. 673
13.8.5 Switching of Internal Clocks and TCNT Operation.............................................. 673
13.8.6 Mode Setting with Cascaded Connection ............................................................. 675
13.8.7 Interrupts in Module Stop Mode........................................................................... 675
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Section 14 Watchdog Timer (WDT)..................................................................677
14.1 Features .............................................................................................................................. 677
14.2 Input/Output Pin................................................................................................................. 678
14.3 Register Descriptions ......................................................................................................... 679
14.3.1 Timer Counter (TCNT)......................................................................................... 679
14.3.2 Timer Control/Status Register (TCSR) ................................................................. 679
14.3.3 Reset Control/Status Register (RSTCSR) ............................................................. 681
14.4 Operation............................................................................................................................ 682
14.4.1 Watchdog Timer Mode ......................................................................................... 682
14.4.2 Interval Timer Mode ............................................................................................. 683
14.5 Interrupt Source ................................................................................................................. 684
14.6 Usage Notes ....................................................................................................................... 684
14.6.1 Notes on Register Access...................................................................................... 684
14.6.2 Contention between Timer Counter (TCNT) Write and Increment ...................... 686
14.6.3 Changing Value of CKS2 to CKS0....................................................................... 686
14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 686
14.6.5 Internal Reset in Watchdog Timer Mode.............................................................. 687
14.6.6 System Reset by WDTOVF Signal....................................................................... 687
Section 15 Serial Communication Interface (SCI, IrDA)..................................689
15.1 Features .............................................................................................................................. 689
15.2 Input/Output Pins ............................................................................................................... 692
15.3 Register Descriptions ......................................................................................................... 693
15.3.1 Receive Shift Register (RSR) ............................................................................... 694
15.3.2 Receive Data Register (RDR) ............................................................................... 694
15.3.3 Transmit Data Register (TDR).............................................................................. 694
15.3.4 Transmit Shift Register (TSR) .............................................................................. 695
15.3.5 Serial Mode Register (SMR)................................................................................. 695
15.3.6 Serial Control Register (SCR)............................................................................... 698
15.3.7 Serial Status Register (SSR) ................................................................................. 703
15.3.8 Smart Card Mode Register (SCMR) ..................................................................... 710
15.3.9 Bit Rate Register (BRR) ....................................................................................... 711
15.3.10 IrDA Control Register (IrCR) ............................................................................... 720
15.3.11 Serial Extension Mode Register (SEMR) ............................................................. 721
15.4 Operation in Asynchronous Mode ..................................................................................... 723
15.4.1 Data Transfer Format ............................................................................................ 723
15.4.2 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode ......................................................................................... 725
15.4.3 Clock..................................................................................................................... 726
15.4.4 SCI Initialization (Asynchronous Mode) .............................................................. 727
15.4.5 Data Transmission (Asynchronous Mode)............................................................ 728
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15.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 730
15.5 Multiprocessor Communication Function.......................................................................... 734
15.5.1 Multiprocessor Serial Data Transmission ............................................................. 735
15.5.2 Multiprocessor Serial Data Reception .................................................................. 737
15.6 Operation in Clocked Synchronous Mode ......................................................................... 740
15.6.1 Clock..................................................................................................................... 740
15.6.2 SCI Initialization (Clocked Synchronous Mode) .................................................. 741
15.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 741
15.6.4 Serial Data Reception (Clocked Synchronous Mode)........................................... 744
15.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) .............................................................................. 746
15.7 Operation in Smart Card Interface Mode........................................................................... 748
15.7.1 Pin Connection Example....................................................................................... 748
15.7.2 Data Format (Except for Block Transfer Mode) ................................................... 749
15.7.3 Block Transfer Mode ............................................................................................ 750
15.7.4 Receive Data Sampling Timing and Reception Margin........................................ 750
15.7.5 Initialization .......................................................................................................... 752
15.7.6 Data Transmission (Except for Block Transfer Mode) ......................................... 753
15.7.7 Serial Data Reception (Except for Block Transfer Mode) .................................... 755
15.7.8 Clock Output Control............................................................................................ 757
15.8 IrDA Operation .................................................................................................................. 759
15.9 Interrupt Sources ................................................................................................................ 762
15.9.1 Interrupts in Normal Serial Communication Interface Mode................................ 762
15.9.2 Interrupts in Smart Card Interface Mode .............................................................. 764
15.10 Usage Notes ....................................................................................................................... 765
15.10.1 Module Stop Mode Setting ................................................................................... 765
15.10.2 Break Detection and Processing ........................................................................... 765
15.10.3 Mark State and Break Sending.............................................................................. 765
15.10.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only)...................................................................... 766
15.10.5 Relation between Writes to TDR and the TDRE Flag .......................................... 766
15.10.6 Restrictions on Use of DMAC or DTC................................................................. 766
15.10.7 Operation in Case of Mode Transition.................................................................. 767
Section 16 I2C Bus Interface 2 (IIC2) (Option)................................................. 771
16.1 Features .............................................................................................................................. 771
16.2 Input/Output Pins ............................................................................................................... 773
16.3 Register Descriptions ......................................................................................................... 774
16.3.1 I2C Bus Control Register A (ICCRA) ................................................................... 775
16.3.2 I2C Bus Control Register B (ICCRB) ................................................................... 777
16.3.3 I2C Bus Mode Register (ICMR)............................................................................ 778
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16.4
16.5
16.6
16.7
16.3.4 I2C Bus Interrupt Enable Register (ICIER)........................................................... 780
16.3.5 I2C Bus Status Register (ICSR) ............................................................................ 782
16.3.6 Slave address register (SAR) ................................................................................ 784
16.3.7 I2C Bus Transmit Data Register (ICDRT) ............................................................ 785
16.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 785
16.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 785
Operation............................................................................................................................ 786
16.4.1 I2C Bus Format ..................................................................................................... 786
16.4.2 Master Transmit Operation ................................................................................... 787
16.4.3 Master Receive Operation..................................................................................... 789
16.4.4 Slave Transmit Operation ..................................................................................... 791
16.4.5 Slave Receive Operation....................................................................................... 794
16.4.6 Noise Canceler ...................................................................................................... 796
16.4.7 Example of Use..................................................................................................... 796
Interrupt Request................................................................................................................ 801
Bit Synchronous Circuit..................................................................................................... 802
Usage Notes ....................................................................................................................... 803
Section 17 A/D Converter..................................................................................805
17.1 Features .............................................................................................................................. 805
17.2 Input/Output Pins ............................................................................................................... 807
17.3 Register Description........................................................................................................... 808
17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 808
17.3.2 A/D Control/Status Register (ADCSR) ................................................................ 809
17.3.3 A/D Control Register (ADCR) ............................................................................. 811
17.4 Operation............................................................................................................................ 812
17.4.1 Single Mode.......................................................................................................... 812
17.4.2 Scan Mode ............................................................................................................ 812
17.4.3 Input Sampling and A/D Conversion Time........................................................... 813
17.4.4 External Trigger Input Timing .............................................................................. 815
17.5 Interrupt Source ................................................................................................................. 816
17.6 A/D Conversion Accuracy Definitions .............................................................................. 816
17.7 Usage Notes ....................................................................................................................... 818
17.7.1 Module Stop Mode Setting ................................................................................... 818
17.7.2 Permissible Signal Source Impedance .................................................................. 818
17.7.3 Influences on Absolute Precision.......................................................................... 819
17.7.4 Setting Range of Analog Power Supply and Other Pins ....................................... 819
17.7.5 Notes on Board Design ......................................................................................... 819
17.7.6 Notes on Noise Countermeasures ......................................................................... 819
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Section 18 D/A Converter ................................................................................. 821
18.1 Features .............................................................................................................................. 821
18.2 Input/Output Pins ............................................................................................................... 824
18.3 Register Descriptions ......................................................................................................... 825
18.3.1 D/A Data Registers 0 to 5 (DADR0 to DADR5) .................................................. 825
18.3.2 D/A Control Registers 01, 23, and 45 (DACR01, DACR23, DACR45) .............. 825
18.4 Operation............................................................................................................................ 829
18.5 Usage Notes ....................................................................................................................... 830
18.5.1 Setting for Module Stop Mode.............................................................................. 830
18.5.2 D/A Output Hold Function in Software Standby Mode........................................ 830
Section 19 RAM ................................................................................................ 831
Section 20 Flash Memory (0.35-μm F-ZTAT Version).................................... 833
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
20.9
20.10
20.11
Features .............................................................................................................................. 833
Mode Transitions ............................................................................................................... 834
Block Configuration........................................................................................................... 838
Input/Output Pins ............................................................................................................... 840
Register Descriptions ......................................................................................................... 840
20.5.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 840
20.5.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 842
20.5.3 Erase Block Register 1 (EBR1) ............................................................................ 843
20.5.4 Erase Block Register 2 (EBR2) ............................................................................ 844
On-Board Programming Modes......................................................................................... 846
20.6.1 Boot Mode ............................................................................................................ 846
20.6.2 User Program Mode.............................................................................................. 849
Flash Memory Programming/Erasing ................................................................................ 850
20.7.1 Program/Program-Verify ...................................................................................... 850
20.7.2 Erase/Erase-Verify................................................................................................ 852
20.7.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 852
Program/Erase Protection .................................................................................................. 854
20.8.1 Hardware Protection ............................................................................................. 854
20.8.2 Software Protection............................................................................................... 854
20.8.3 Error Protection..................................................................................................... 854
Programmer Mode ............................................................................................................. 855
Power-Down States for Flash Memory.............................................................................. 855
Usage Notes ....................................................................................................................... 856
Section 21 Flash Memory (0.18-μm F-ZTAT Version).................................... 861
21.1 Features .............................................................................................................................. 861
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21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.1.1 Operating Mode .................................................................................................... 864
21.1.2 Mode Comparison................................................................................................. 865
21.1.3 Flash MAT Configuration..................................................................................... 866
21.1.4 Block Division ...................................................................................................... 867
21.1.5 Programming/Erasing Interface ............................................................................ 868
Input/Output Pins ............................................................................................................... 870
Register Descriptions ......................................................................................................... 871
21.3.1 Programming/Erasing Interface Register .............................................................. 872
21.3.2 Programming/Erasing Interface Parameter ........................................................... 879
21.3.3 Flash Vector Address Control Register (FVACR)................................................ 889
On-Board Programming Mode .......................................................................................... 891
21.4.1 Boot Mode ............................................................................................................ 891
21.4.2 User Program Mode.............................................................................................. 895
21.4.3 User Boot Mode.................................................................................................... 906
21.4.4 Procedure Program and Storable Area for Programming Data ............................. 910
Protection ........................................................................................................................... 920
21.5.1 Hardware Protection ............................................................................................. 920
21.5.2 Software Protection............................................................................................... 921
21.5.3 Error Protection..................................................................................................... 921
Switching between User MAT and User Boot MAT ......................................................... 923
Programmer Mode ............................................................................................................. 924
Serial Communication Interface Specification for Boot Mode .......................................... 924
Usage Notes ....................................................................................................................... 952
Section 22 Masked ROM...................................................................................953
Section 23 Clock Pulse Generator .....................................................................955
23.1 Register Descriptions ......................................................................................................... 955
23.1.1 System Clock Control Register (SCKCR) ............................................................ 955
23.1.2 PLL Control Register (PLLCR) ............................................................................ 957
23.2 Oscillator............................................................................................................................ 958
23.2.1 Connecting a Crystal Resonator............................................................................ 958
23.2.2 External Clock Input ............................................................................................. 959
23.3 PLL Circuit ........................................................................................................................ 961
23.4 Frequency Divider.............................................................................................................. 961
23.5 Usage Notes ....................................................................................................................... 962
23.5.1 Notes on Clock Pulse Generator ........................................................................... 962
23.5.2 Notes on Resonator ............................................................................................... 962
23.5.3 Notes on Board Design ......................................................................................... 963
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Section 24 Power-Down Modes ........................................................................ 965
24.1 Register Descriptions ......................................................................................................... 968
24.1.1 Standby Control Register (SBYCR) ..................................................................... 968
24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)..................... 970
24.1.3 Extension Module Stop Control Registers H and L
(EXMSTPCRH, EXMSTPCRL) .......................................................................... 971
24.2 Operation............................................................................................................................ 972
24.2.1 Clock Division Mode............................................................................................ 972
24.2.2 Sleep Mode ........................................................................................................... 973
24.2.3 Software Standby Mode........................................................................................ 973
24.2.4 Hardware Standby Mode ...................................................................................... 976
24.2.5 Module Stop Mode ............................................................................................... 978
24.2.6 All-Module-Clocks-Stop Mode ............................................................................ 978
24.3 φ Clock Output Control...................................................................................................... 979
24.4 Usage Notes ....................................................................................................................... 979
24.4.1 I/O Port Status....................................................................................................... 979
24.4.2 Current Dissipation during Oscillation Stabilization Standby Period ................... 979
24.4.3 EXDMAC, DMAC, and DTC Module Stop ......................................................... 980
24.4.4 On-Chip Peripheral Module Interrupts ................................................................. 980
24.4.5 Writing to MSTPCR, EXMSTPCR ...................................................................... 980
24.4.6 Notes on Clock Division Mode............................................................................. 980
Section 25 List of Registers............................................................................... 981
25.1 Register Addresses (Address Order) .................................................................................. 981
25.2 Register Bits....................................................................................................................... 993
25.3 Register States in Each Operating Mode.......................................................................... 1007
Section 26 Electrical Characteristics ............................................................... 1019
26.1 Electrical Characteristics for H8S/2377, H8S/2375, H8S/2373, H8S/2377R,
H8S/2375R, and H8S/2373R ........................................................................................... 1019
26.1.1 Absolute Maximum Ratings ............................................................................... 1019
26.1.2 DC Characteristics .............................................................................................. 1020
26.1.3 AC Characteristics .............................................................................................. 1023
26.1.4 A/D Conversion Characteristics.......................................................................... 1032
26.1.5 D/A Conversion Characteristics.......................................................................... 1032
26.1.6 Flash Memory Characteristics ............................................................................ 1033
26.1.7 Usage Note.......................................................................................................... 1034
26.2 Electrical Characteristics for H8S/2378........................................................................... 1035
26.2.1 Absolute Maximum Ratings ............................................................................... 1035
26.2.2 DC Characteristics .............................................................................................. 1036
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26.2.3 AC Characteristics .............................................................................................. 1039
26.2.4 A/D Conversion Characteristics.......................................................................... 1048
26.2.5 D/A Conversion Characteristics.......................................................................... 1048
26.2.6 Flash Memory Characteristics ............................................................................ 1049
26.3 Electrical Characteristics for H8S/2374, H8S/2372, H8S/2371, H8S/2370,
H8S/2378R, H8S/2374R, H8S/2372R, H8S/2371R, H8S/2370R.................................... 1050
26.3.1 Absolute Maximum Ratings ............................................................................... 1050
26.3.2 DC Characteristics .............................................................................................. 1051
26.3.3 AC Characteristics .............................................................................................. 1054
26.3.4 A/D Conversion Characteristics.......................................................................... 1063
26.3.5 D/A Conversion Characteristics.......................................................................... 1063
26.3.6 Flash Memory Characteristics ............................................................................ 1064
26.4 Timing Charts .................................................................................................................. 1067
26.4.1 Clock Timing ...................................................................................................... 1067
26.4.2 Control Signal Timing ........................................................................................ 1069
26.4.3 Bus Timing ......................................................................................................... 1070
26.4.4 DMAC and EXDMAC Timing........................................................................... 1088
26.4.5 Timing of On-Chip Peripheral Modules ............................................................. 1091
Appendix
A.
B.
C.
D.
........................................................................................................1095
I/O Port States in Each Pin State...................................................................................... 1095
Product Lineup................................................................................................................. 1105
Package Dimensions ........................................................................................................ 1106
Bus State during Execution of Instructions...................................................................... 1108
Index
........................................................................................................1131
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Figures
Section 1 Overview................................................................................................1
Figure 1.1
Figure 1.2
Figure 1.3
Figure 1.4
Figure 1.5
Figure 1.6
Figure 1.7
Figure 1.8
Figure 1.9
Internal Block Diagram for H8S/2378 0.18μm F-ZTAT Group
and H8S/2378R 0.18μm F-ZTAT Group .................................................................... 3
Internal Block Diagram for H8S/2377 and H8S/2377R.............................................. 4
Internal Block Diagram for H8S/2375 and H8S/2375R.............................................. 5
Internal Block Diagram for H8S/2373 and H8S/2373R.............................................. 6
Pin Arrangement for H8S/2378 0.18μm F-ZTAT Group
and H8S/2378R 0.18μm F-ZTAT Group .................................................................... 7
Pin Arrangement for H8S/2377 and H8S/2377R ........................................................ 8
Pin Arrangement for H8S/2375 and H8S/2375R ........................................................ 9
Pin Arrangement for H8S/2373 and H8S/2373R ...................................................... 10
Pin Arrangement (TLP-145V: Top View)................................................................. 11
Section 2 CPU......................................................................................................35
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8
Figure 2.9
Figure 2.9
Figure 2.10
Figure 2.11
Figure 2.12
Figure 2.13
Exception Vector Table (Normal Mode)................................................................... 39
Stack Structure in Normal Mode............................................................................... 39
Exception Vector Table (Advanced Mode)............................................................... 40
Stack Structure in Advanced Mode........................................................................... 41
Memory Map............................................................................................................. 42
CPU Internal Registers.............................................................................................. 43
Usage of General Registers ....................................................................................... 44
Stack.......................................................................................................................... 45
General Register Data Formats (1)............................................................................ 48
General Register Data Formats (2)............................................................................ 49
Memory Data Formats............................................................................................... 50
Instruction Formats (Examples) ................................................................................ 62
Branch Address Specification in Memory Indirect Addressing Mode...................... 65
State Transitions ........................................................................................................ 69
Section 3 MCU Operating Modes........................................................................71
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3.8
Memory Map for H8S/2378 and H8S/2378R (1) ...................................................... 78
Memory Map for H8S/2378 and H8S/2378R (2) ...................................................... 79
Memory Map for H8S/2377 and H8S/2377R (1) ...................................................... 80
Memory Map for H8S/2377 and H8S/2377R (2) ...................................................... 81
Memory Map for H8S/2375 and H8S/2375R (1) ...................................................... 82
Memory Map for H8S/2375 and H8S/2375R (2) ...................................................... 83
Memory Map for H8S/2374 and H8S/2374R (1) ...................................................... 84
Memory Map for H8S/2374 and H8S/2374R (2) ...................................................... 85
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Figure 3.9
Figure 3.10
Figure 3.11
Figure 3.12
Figure 3.13
Figure 3.14
Figure 3.15
Memory Map for H8S/2373 and H8S/2373R............................................................ 86
Memory Map for H8S/2372 and H8S/2372R (1) ...................................................... 87
Memory Map for H8S/2372 and H8S/2372R (2) ...................................................... 88
Memory Map for H8S/2371 and H8S/2371R (1) ...................................................... 89
Memory Map for H8S/2371 and H8S/2371R (2) ...................................................... 90
Memory Map for H8S/2370 and H8S/2370R (1) ...................................................... 91
Memory Map for H8S/2370 and H8S/2370R (2) ...................................................... 92
Section 4 Exception Handling ............................................................................. 93
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Reset Sequence (Advanced Mode with On-chip ROM Enabled).............................. 96
Reset Sequence (Advanced Mode with On-chip ROM Disabled) ............................ 97
Stack Status after Exception Handling .................................................................... 100
Operation when SP Value Is Odd............................................................................ 101
Section 5 Interrupt Controller............................................................................ 103
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Block Diagram of Interrupt Controller.................................................................... 104
Block Diagram of Interrupts IRQ15 to IRQ0 .......................................................... 121
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0. 128
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2. 130
Interrupt Exception Handling .................................................................................. 131
Conflict between Interrupt Generation and Disabling............................................. 134
Section 6 Bus Controller (BSC) ........................................................................ 137
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10
Figure 6.11
Figure 6.12
Figure 6.13
Figure 6.14
Figure 6.15
Block Diagram of Bus Controller............................................................................ 138
Read Strobe Negation Timing (Example of 3-State Access Space) ........................ 150
CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0) ................................................ 152
RAS Signal Assertion Timing (2-State Column Address Output Cycle,
Full Access)............................................................................................................. 163
CAS Latency Control Cycle Disable Timing during Continuous Synchronous
DRAM Space Write Access (for CAS Latency 2) .................................................. 166
Area Divisions......................................................................................................... 171
CSn Signal Output Timing (n = 0 to 7) ................................................................... 176
Access Sizes and Data Alignment Control (8-Bit Access Space) ........................... 177
Access Sizes and Data Alignment Control (16-Bit Access Space) ......................... 177
Bus Timing for 8-Bit, 2-State Access Space ........................................................... 179
Bus Timing for 8-Bit, 3-State Access Space ........................................................... 180
Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)........... 181
Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) ............ 182
Bus Timing for 16-Bit, 2-State Access Space (Word Access) ................................ 183
Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)........... 184
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Figure 6.16
Figure 6.17
Figure 6.18
Figure 6.19
Figure 6.20
Figure 6.21
Figure 6.22
Figure 6.23
Figure 6.24
Figure 6.25
Figure 6.26
Figure 6.27
Figure 6.28
Figure 6.29
Figure 6.30
Figure 6.31
Figure 6.32
Figure 6.33
Figure 6.34
Figure 6.35
Figure 6.36
Figure 6.37
Figure 6.38
Figure 6.39
Figure 6.40
Figure 6.41
Figure 6.42
Figure 6.43
Figure 6.44
Figure 6.45
Figure 6.46
Figure 6.47
Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) ............ 185
Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................ 186
Example of Wait State Insertion Timing................................................................. 188
Example of Read Strobe Timing ............................................................................. 189
Example of Timing when Chip Select Assertion Period Is Extended ..................... 190
DRAM Basic Access Timing (RAST = 0, CAST = 0)............................................ 194
Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0).............................................................................................................. 195
Example of Access Timing when RAS Signal Goes Low from Beginning
of Tr State (CAST = 0) ............................................................................................ 196
Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0) ........................................................................................... 197
Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0)....... 198
Example of Wait State Insertion Timing (2-State Column Address Output) .......... 200
Example of Wait State Insertion Timing (3-State Column Address Output) .......... 201
2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0).......... 202
Example of 2-CAS DRAM Connection .................................................................. 203
Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) ............................... 204
Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) ............................... 205
Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0)......... 206
Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0).............. 207
RTCNT Operation................................................................................................... 208
Compare Match Timing .......................................................................................... 209
CBR Refresh Timing............................................................................................... 209
CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)................. 210
Example of CBR Refresh Timing (CBRM = 1) ...................................................... 211
Self-Refresh Timing ................................................................................................ 212
Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States ............................................................................................................... 213
Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1
(RAST = 0, CAST = 0) ........................................................................................... 214
Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1) ........................................................................................... 215
Relationship between φ and SDRAMφ (when PLL Frequency Multiplication
Factor Is ×1 or ×2)................................................................................................... 220
Basic Access Timing of Synchronous DRAM (CAS Latency 1) ............................ 221
CAS Latency Control Timing (SDWCD = 0, CAS Latency 3)............................... 223
Example of Access Timing when Row Address Output Hold State Is 1 State
(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) .......................................... 224
Example of Timing with Two-State Precharge Cycle
(TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2) ............................................ 226
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Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled
(SDWCD = 1) ......................................................................................................... 227
Figure 6.49 DQMU and DQML Control Timing (Upper Byte Write Access:
SDWCD = 0, CAS Latency 2) ................................................................................ 228
Figure 6.50 DQMU and DQML Control Timing (Lower Byte Read Access:
CAS Latency 2) ....................................................................................................... 229
Figure 6.51 Example of DQMU and DQML Byte Control ........................................................ 230
Figure 6.52 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) ......... 232
Figure 6.53 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2)..... 234
Figure 6.54 Auto Refresh Timing............................................................................................... 235
Figure 6.55 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1)..................... 236
Figure 6.56 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) ..................... 237
Figure 6.57 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0,
RLW1 = 0, RLW0 = 0) ........................................................................................... 238
Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2) ........ 239
Figure 6.59 Synchronous DRAM Mode Setting Timing............................................................ 240
Figure 6.60 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 ............ 242
Figure 6.61 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 ............ 244
Figure 6.62 Example of Timing when the Read Data Is Extended by Two States
(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2) .................... 245
Figure 6.63 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) ............. 247
Figure 6.64 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) ............. 248
Figure 6.65 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) ............ 249
Figure 6.66 Example of Idle Cycle Operation (Write after Read) .............................................. 250
Figure 6.67 Example of Idle Cycle Operation (Read after Write) .............................................. 251
Figure 6.68 Relationship between Chip Select (CS) and Read (RD) ......................................... 252
Figure 6.69 Example of DRAM Full Access after External Read (CAST = 0).......................... 253
Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) .......... 254
Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)
(IDLC = 0, RAST = 0, CAST = 0).......................................................................... 254
Figure 6.72 Example of Synchronous DRAM Full Access after External Read
(CAS Latency 2)...................................................................................................... 255
Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode
(Read in Different Area) (IDLC = 0, CAS Latency 2) ............................................ 256
Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode
(Read in Different Area) (IDLC = 1, CAS Latency 2) ............................................ 257
Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, CAS Latency 2) ...................................................... 258
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Figure 6.76 Example of Idle Cycle Operation after DRAM Access
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) .......... 259
Figure 6.77 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)............................................ 260
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) ........................................................ 261
Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2) ............ 262
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)...................... 263
Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to DRAM Space in RAS Down Mode ........................................... 266
Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to Continuous Synchronous DRAM Space in RAS Down
Mode (SDWCD = 1, CAS Latency 2)..................................................................... 267
Figure 6.83 Example of Timing when Write Data Buffer Function Is Used .............................. 269
Figure 6.84 Bus Released State Transition Timing .................................................................... 272
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface ........... 273
Section 7 DMA Controller (DMAC) .................................................................279
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Figure 7.5
Figure 7.6
Figure 7.7
Figure 7.8
Figure 7.9
Figure 7.10
Figure 7.11
Figure 7.12
Figure 7.13
Figure 7.14
Figure 7.15
Figure 7.16
Figure 7.17
Figure 7.18
Figure 7.19
Figure 7.20
Block Diagram of DMAC ....................................................................................... 280
Areas for Register Re-Setting by DTC (Channel 0A) ............................................. 305
Operation in Sequential Mode................................................................................. 313
Example of Sequential Mode Setting Procedure ..................................................... 314
Operation in Idle Mode ........................................................................................... 315
Example of Idle Mode Setting Procedure................................................................ 316
Operation in Repeat mode ....................................................................................... 318
Example of Repeat Mode Setting Procedure........................................................... 319
Operation in Single Address Mode (When Sequential Mode Is Specified) ............ 321
Example of Single Address Mode Setting Procedure
(When Sequential Mode Is Specified)..................................................................... 322
Operation in Normal Mode ..................................................................................... 324
Example of Normal Mode Setting Procedure.......................................................... 325
Operation in Block Transfer Mode (BLKDIR = 0) ................................................. 327
Operation in Block Transfer Mode (BLKDIR = 1) ................................................. 328
Operation Flow in Block Transfer Mode ................................................................ 329
Example of Block Transfer Mode Setting Procedure.............................................. 330
Example of DMA Transfer Bus Timing.................................................................. 331
Example of Short Address Mode Transfer .............................................................. 332
Example of Full Address Mode Transfer (Cycle Steal) .......................................... 333
Example of Full Address Mode Transfer (Burst Mode).......................................... 334
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Figure 7.21
Figure 7.22
Figure 7.23
Figure 7.24
Figure 7.25
Figure 7.26
Figure 7.27
Figure 7.28
Figure 7.29
Figure 7.30
Figure 7.31
Figure 7.32
Figure 7.33
Figure 7.34
Figure 7.35
Figure 7.36
Figure 7.37
Figure 7.38
Figure 7.39
Figure 7.40
Figure 7.41
Example of Full Address Mode Transfer (Block Transfer Mode) .......................... 335
Example of DREQ Pin Falling Edge Activated Normal Mode Transfer................. 336
Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer..... 337
Example of DREQ Pin Low Level Activated Normal Mode Transfer.................... 338
Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer ........ 339
Example of Single Address Mode Transfer (Byte Read) ........................................ 340
Example of Single Address Mode (Word Read) Transfer....................................... 341
Example of Single Address Mode Transfer (Byte Write) ....................................... 342
Example of Single Address Mode Transfer (Word Write)...................................... 343
Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer..... 344
Example of DREQ Pin Low Level Activated Single Address Mode Transfer........ 345
Example of Dual Address Transfer Using Write Data Buffer Function.................. 346
Example of Single Address Transfer Using Write Data Buffer Function ............... 347
Example of Multi-Channel Transfer ....................................................................... 348
Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt ..................................................................................................... 350
Example of Procedure for Forcibly Terminating DMAC Operation....................... 351
Example of Procedure for Clearing Full Address Mode ......................................... 352
Block Diagram of Transfer End/Transfer Break Interrupt ...................................... 353
DMAC Register Update Timing ............................................................................. 354
Contention between DMAC Register Update and CPU Read................................. 355
Example in which Low Level Is Not Output at TEND Pin ..................................... 357
Section 8 EXDMA Controller (EXDMAC) ...................................................... 359
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10
Figure 8.11
Figure 8.12
Figure 8.13
Figure 8.14
Figure 8.15
Figure 8.16
Block Diagram of EXDMAC.................................................................................. 360
Example of Timing in Dual Address Mode............................................................. 376
Data Flow in Single Address Mode......................................................................... 377
Example of Timing in Single Address Mode .......................................................... 378
Example of Timing in Cycle Steal Mode ................................................................ 380
Examples of Timing in Burst Mode ........................................................................ 381
Examples of Timing in Normal Transfer Mode ...................................................... 382
Example of Timing in Block Transfer Mode .......................................................... 383
Example of Repeat Area Function Operation.......................................................... 384
Example of Repeat Area Function Operation in Block Transfer Mode .................. 385
EDTCR Update Operations in Normal Transfer Mode and
Block Transfer Mode............................................................................................... 388
Procedure for Changing Register Settings in Operating Channel ........................... 389
Example of Channel Priority Timing ...................................................................... 391
Examples of Channel Priority Timing..................................................................... 392
Example of Normal Transfer Mode (Cycle Steal Mode) Transfer .......................... 393
Example of Normal Transfer Mode (Burst Mode) Transfer.................................... 394
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Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer............................. 395
Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge ......... 396
Figure 8.19 Example of Block Transfer Mode Transfer Activated
by EDREQ Pin Falling Edge................................................................................... 397
Figure 8.20 Example of Normal Mode Transfer Activated
by EDREQ Pin Low Level ...................................................................................... 398
Figure 8.21 Example of Block Transfer Mode Transfer Activated by
EDREQ Pin Low Level........................................................................................... 399
Figure 8.22 Example of Single Address Mode (Byte Read) Transfer ........................................ 400
Figure 8.23 Example of Single Address Mode (Word Read) Transfer....................................... 400
Figure 8.24 Example of Single Address Mode (Byte Write) Transfer ....................................... 401
Figure 8.25 Example of Single Address Mode (Word Write) Transfer...................................... 402
Figure 8.26 Example of Single Address Mode Transfer Activated by
EDREQ Pin Falling Edge........................................................................................ 403
Figure 8.27 Example of Single Address Mode Transfer Activated by
EDREQ Pin Low Level........................................................................................... 404
Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Dual Address Mode) ..................................................................... 405
Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode) ....................................................................... 406
Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(Contention with Another Channel/Single Address Mode)..................................... 406
Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Dual Address Mode/BGUP = 0)........................................................ 407
Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Dual Address Mode/BGUP = 1)........................................................ 407
Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode/BGUP = 1) ..................................................... 408
Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode
(Contention with Another Channel/Single Address Mode)..................................... 408
Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Dual Address Mode/Low Level Sensing)...................................... 409
Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing) ....................................... 410
Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing) ................................ 410
Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention
with Another Channel/Dual Address Mode/Low Level Sensing ............................ 411
Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0).................... 412
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Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) .............. 413
Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0) ..................... 414
Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1)........................ 415
Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1) ..................... 416
Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode
(Contention with Another Channel/Dual Address Mode/Low Level Sensing) ....... 417
Figure 8.45 Transfer End Interrupt Logic................................................................................... 420
Figure 8.46 Example of Procedure for Restarting Transfer on Channel
in which Transfer End Interrupt Occurred .............................................................. 421
Section 9 Data Transfer Controller (DTC) ........................................................ 425
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Figure 9.10
Figure 9.11
Block Diagram of DTC ........................................................................................... 426
Block Diagram of DTC Activation Source Control ................................................ 433
Correspondence between DTC Vector Address and Register Information ............. 434
Correspondence between DTC Vector Address and Register Information ............. 434
Flowchart of DTC Operation .................................................................................. 438
Memory Mapping in Normal Mode ........................................................................ 440
Memory Mapping in Repeat Mode ......................................................................... 441
Memory Mapping in Block Transfer Mode ............................................................ 442
Operation of Chain Transfer.................................................................................... 443
DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................... 444
DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)............................................................................................... 445
Figure 9.12 DTC Operation Timing (Example of Chain Transfer) ............................................ 445
Figure 9.13 Chain Transfer when Counter = 0 ........................................................................... 451
Section 11 16-Bit Timer Pulse Unit (TPU) ....................................................... 545
Figure 11.1 Block Diagram of TPU............................................................................................ 548
Figure 11.2 Example of Counter Operation Setting Procedure .................................................. 583
Figure 11.3 Free-Running Counter Operation ............................................................................ 584
Figure 11.4 Periodic Counter Operation..................................................................................... 585
Figure 11.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 586
Figure 11.6 Example of 0 Output/1 Output Operation ............................................................... 587
Figure 11.7 Example of Toggle Output Operation ..................................................................... 587
Figure 11.8 Example of Setting Procedure for Input Capture Operation.................................... 588
Figure 11.9 Example of Input Capture Operation ...................................................................... 589
Figure 11.10 Example of Synchronous Operation Setting Procedure .......................................... 590
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Figure 11.11 Example of Synchronous Operation........................................................................ 591
Figure 11.12 Compare Match Buffer Operation........................................................................... 592
Figure 11.13 Input Capture Buffer Operation............................................................................... 592
Figure 11.14 Example of Buffer Operation Setting Procedure..................................................... 593
Figure 11.15 Example of Buffer Operation (1) ............................................................................ 594
Figure 11.16 Example of Buffer Operation (2) ............................................................................ 595
Figure 11.17 Cascaded Operation Setting Procedure ................................................................... 596
Figure 11.18 Example of Cascaded Operation (1)........................................................................ 597
Figure 11.19 Example of Cascaded Operation (2)........................................................................ 597
Figure 11.20 Example of PWM Mode Setting Procedure ............................................................ 600
Figure 11.21 Example of PWM Mode Operation (1) ................................................................... 601
Figure 11.22 Example of PWM Mode Operation (2) ................................................................... 601
Figure 11.23 Example of PWM Mode Operation (3) ................................................................... 602
Figure 11.24 Example of Phase Counting Mode Setting Procedure............................................. 603
Figure 11.25 Example of Phase Counting Mode 1 Operation ...................................................... 604
Figure 11.26 Example of Phase Counting Mode 2 Operation ...................................................... 605
Figure 11.27 Example of Phase Counting Mode 3 Operation ...................................................... 606
Figure 11.28 Example of Phase Counting Mode 4 Operation ...................................................... 607
Figure 11.29 Phase Counting Mode Application Example........................................................... 609
Figure 11.30 Count Timing in Internal Clock Operation.............................................................. 612
Figure 11.31 Count Timing in External Clock Operation ............................................................ 612
Figure 11.32 Output Compare Output Timing ............................................................................. 613
Figure 11.33 Input Capture Input Signal Timing.......................................................................... 613
Figure 11.34 Counter Clear Timing (Compare Match) ................................................................ 614
Figure 11.35 Counter Clear Timing (Input Capture) .................................................................... 614
Figure 11.36 Buffer Operation Timing (Compare Match) ........................................................... 615
Figure 11.37 Buffer Operation Timing (Input Capture) ............................................................... 615
Figure 11.38 TGI Interrupt Timing (Compare Match) ................................................................. 616
Figure 11.39 TGI Interrupt Timing (Input Capture) ..................................................................... 616
Figure 11.40 TCIV Interrupt Setting Timing................................................................................ 617
Figure 11.41 TCIU Interrupt Setting Timing................................................................................ 617
Figure 11.42 Timing for Status Flag Clearing by CPU ................................................................ 618
Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation ................................. 618
Figure 11.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .................. 619
Figure 11.45 Contention between TCNT Write and Clear Operations......................................... 620
Figure 11.46 Contention between TCNT Write and Increment Operations ................................. 621
Figure 11.47 Contention between TGR Write and Compare Match ............................................ 622
Figure 11.48 Contention between Buffer Register Write and Compare Match............................ 623
Figure 11.49 Contention between TGR Read and Input Capture ................................................. 624
Figure 11.50 Contention between TGR Write and Input Capture ................................................ 625
Figure 11.51 Contention between Buffer Register Write and Input Capture................................ 626
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Figure 11.52 Contention between Overflow and Counter Clearing ............................................. 627
Figure 11.53 Contention between TCNT Write and Overflow..................................................... 628
Section 12 Programmable Pulse Generator (PPG) ............................................ 631
Figure 12.1 Block Diagram of PPG............................................................................................ 632
Figure 12.2 Overview Diagram of PPG...................................................................................... 641
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) ................................. 642
Figure 12.4 Setup Procedure for Normal Pulse Output (Example) ............................................ 643
Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) ..................................... 644
Figure 12.6 Non-Overlapping Pulse Output ............................................................................... 645
Figure 12.7 Non-Overlapping Operation and NDR Write Timing ............................................. 646
Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)............................. 647
Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)................ 648
Figure 12.10 Inverted Pulse Output (Example) ............................................................................ 650
Figure 12.11 Pulse Output Triggered by Input Capture (Example).............................................. 651
Section 13 8-Bit Timers (TMR) ........................................................................ 653
Figure 13.1 Block Diagram of 8-Bit Timer Module................................................................... 654
Figure 13.2 Example of Pulse Output......................................................................................... 663
Figure 13.3 Count Timing for Internal Clock Input.................................................................... 664
Figure 13.4 Count Timing for External Clock Input .................................................................. 664
Figure 13.5 Timing of CMF Setting ........................................................................................... 665
Figure 13.6 Timing of Timer Output .......................................................................................... 666
Figure 13.7 Timing of Compare Match Clear ............................................................................ 666
Figure 13.8 Timing of Clearance by External Reset................................................................... 667
Figure 13.9 Timing of OVF Setting............................................................................................ 667
Figure 13.10 Contention between TCNT Write and Clear ........................................................... 670
Figure 13.11 Contention between TCNT Write and Increment.................................................... 671
Figure 13.12 Contention between TCOR Write and Compare Match.......................................... 672
Section 14 Watchdog Timer (WDT) ................................................................. 677
Figure 14.1
Figure 14.2
Figure 14.3
Figure 14.4
Figure 14.5
Figure 14.6
Block Diagram of WDT .......................................................................................... 678
Operation in Watchdog Timer Mode ...................................................................... 683
Operation in Interval Timer Mode .......................................................................... 684
Writing to TCNT, TCSR, and RSTCSR.................................................................. 685
Contention between TCNT Write and Increment.................................................... 686
Circuit for System Reset by WDTOVF Signal (Example)...................................... 687
Section 15 Serial Communication Interface (SCI, IrDA).................................. 689
Figure 15.1 Block Diagram of SCI............................................................................................. 691
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Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 723
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 725
Figure 15.4 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode). 726
Figure 15.5 Sample SCI Initialization Flowchart ....................................................................... 727
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 728
Figure 15.7 Sample Serial Transmission Flowchart ................................................................... 729
Figure 15.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 730
Figure 15.9 Sample Serial Reception Data Flowchart (1) .......................................................... 732
Figure 15.9 Sample Serial Reception Data Flowchart (2) .......................................................... 733
Figure 15.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ............................................ 735
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart .......................................... 736
Figure 15.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)................................ 737
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1).......................................... 738
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2).......................................... 739
Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First) ................ 740
Figure 15.15 Sample SCI Initialization Flowchart ....................................................................... 741
Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode .................... 742
Figure 15.17 Sample Serial Transmission Flowchart ................................................................... 743
Figure 15.18 Example of SCI Operation in Reception ................................................................. 744
Figure 15.19 Sample Serial Reception Flowchart ........................................................................ 745
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ........ 747
Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections................................ 748
Figure 15.22 Normal Smart Card Interface Data Format ............................................................. 749
Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0) ........................................................ 749
Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1)....................................................... 750
Figure 15.25 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Bit Rate) ................................................................ 751
Figure 15.26 Retransfer Operation in SCI Transmit Mode .......................................................... 754
Figure 15.27 TEND Flag Generation Timing in Transmission Operation ................................... 754
Figure 15.28 Example of Transmission Processing Flow............................................................. 755
Figure 15.29 Retransfer Operation in SCI Receive Mode ............................................................ 756
Figure 15.30 Example of Reception Processing Flow.................................................................. 757
Figure 15.31 Timing for Fixing Clock Output Level.................................................................... 757
Figure 15.32 Clock Halt and Restart Procedure ........................................................................... 758
Figure 15.33 Block Diagram of IrDA........................................................................................... 759
Figure 15.34 IrDA Transmit/Receive Operations......................................................................... 760
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Figure 15.35 Example of Synchronous Transmission Using DTC............................................... 766
Figure 15.36 Sample Flowchart for Mode Transition during Transmission................................. 768
Figure 15.37 Port Pin States during Mode Transition
(Internal Clock, Asynchronous Transmission) ........................................................ 769
Figure 15.38 Port Pin States during Mode Transition
(Internal Clock, Synchronous Transmission) .......................................................... 769
Figure 15.39 Sample Flowchart for Mode Transition during Reception ...................................... 770
Section 16 I2C Bus Interface 2 (IIC2) (Option)................................................. 771
Figure 16.1 Block Diagram of I2C Bus Interface 2..................................................................... 772
Figure 16.2 External Circuit Connections of I/O Pins ................................................................ 773
Figure 16.3 I2C Bus Formats ...................................................................................................... 786
Figure 16.4 I2C Bus Timing........................................................................................................ 786
Figure 16.5 Master Transmit Mode Operation Timing 1............................................................ 788
Figure 16.6 Master Transmit Mode Operation Timing 2............................................................ 788
Figure 16.7 Master Receive Mode Operation Timing 1 ............................................................. 790
Figure 16.8 Master Receive Mode Operation Timing 2 ............................................................. 791
Figure 16.9 Slave Transmit Mode Operation Timing 1.............................................................. 792
Figure 16.10 Slave Transmit Mode Operation Timing 2.............................................................. 793
Figure 16.11 Slave Receive Mode Operation Timing 1 ............................................................... 795
Figure 16.12 Slave Receive Mode Operation Timing 2 ............................................................... 795
Figure 16.13 Block Diagram of Noise Canceler........................................................................... 796
Figure 16.14 Sample Flowchart for Master Transmit Mode ........................................................ 797
Figure 16.15 Sample Flowchart for Master Receive Mode .......................................................... 798
Figure 16.16 Sample Flowchart for Slave Transmit Mode........................................................... 799
Figure 16.17 Sample Flowchart for Slave Receive Mode ............................................................ 800
Figure 16.18 Timing of the Bit Synchronous Circuit ................................................................... 802
Section 17 A/D Converter ................................................................................. 805
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Figure 17.5
Figure 17.6
Figure 17.7
Block Diagram of A/D Converter ........................................................................... 806
A/D Conversion Timing.......................................................................................... 814
External Trigger Input Timing ................................................................................ 815
A/D Conversion Accuracy Definitions ................................................................... 817
A/D Conversion Accuracy Definitions ................................................................... 817
Example of Analog Input Circuit ............................................................................ 818
Example of Analog Input Protection Circuit ........................................................... 820
Section 18 D/A Converter ................................................................................. 821
Figure 18.1 Block Diagram of D/A Converter for H8S/2378 0.18μm F-ZTAT Group,
H8S/2378R 0.18μm F-ZTAT Group, H8S/2377, and H8S/2377R ......................... 822
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Figure 18.2 Block Diagram of D/A Converter for H8S/2375, H8S/2375R, H8S/2373,
and H8S/2373R ....................................................................................................... 823
Figure 18.3 Example of D/A Converter Operation..................................................................... 830
Section 20 Flash Memory (0.35-μm F-ZTAT Version) ....................................833
Figure 20.1 Block Diagram of Flash Memory........................................................................... 834
Figure 20.2 Flash Memory State Transitions.............................................................................. 835
Figure 20.3 Boot Mode............................................................................................................... 836
Figure 20.4 User Program Mode ................................................................................................ 837
Figure 20.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)....................... 839
Figure 20.6 Programming/Erasing Flowchart Example in User Program Mode ........................ 849
Figure 20.7 Program/Program-Verify Flowchart ....................................................................... 851
Figure 20.8 Erase/Erase-Verify Flowchart ................................................................................. 853
Figure 20.9 Power-On/Off Timing ............................................................................................. 858
Figure 20.10 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode).............................. 859
Section 21 Flash Memory (0.18-μm F-ZTAT Version) ....................................861
Figure 21.1 Block Diagram of Flash Memory............................................................................ 863
Figure 21.2 Mode Transition of Flash Memory.......................................................................... 864
Figure 21.3 Flash Memory Configuration .................................................................................. 866
Figure 21.4 Block Division of User MAT .................................................................................. 867
Figure 21.5 Overview of User Procedure Program .................................................................... 868
Figure 21.6 System Configuration in Boot Mode....................................................................... 892
Figure 21.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 892
Figure 21.8 Overview of Boot Mode State Transition Diagram................................................. 894
Figure 21.9 Programming/Erasing Overview Flow.................................................................... 895
Figure 21.10 RAM Map when Programming/Erasing Is Executed .............................................. 896
Figure 21.11 Programming Procedure.......................................................................................... 897
Figure 21.12 Erasing Procedure ................................................................................................... 904
Figure 21.13 Procedure for Programming User MAT in User Boot Mode .................................. 907
Figure 21.14 Procedure for Erasing User MAT in User Boot Mode ............................................ 909
Figure 21.15 Transitions to Error-Protection State....................................................................... 922
Figure 21.16 Switching between the User MAT and User Boot MAT ........................................ 923
Figure 21.17 Boot Program States................................................................................................ 925
Figure 21.18 Bit-Rate-Adjustment Sequence ............................................................................... 926
Figure 21.19 Communication Protocol Format ............................................................................ 927
Figure 21.20 New Bit-Rate Selection Sequence........................................................................... 938
Figure 21.21 Programming Sequence........................................................................................... 942
Figure 21.22 Erasure Sequence .................................................................................................... 945
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Section 22 Masked ROM .................................................................................. 953
Figure 22.1 Block Diagram of 256-kbyte Masked ROM (HD6432375) .................................... 953
Section 23 Clock Pulse Generator ..................................................................... 955
Figure 23.1
Figure 23.2
Figure 23.3
Figure 23.4
Figure 23.5
Figure 23.6
Figure 23.7
Block Diagram of Clock Pulse Generator ............................................................... 955
Connection of Crystal Resonator (Example)........................................................... 958
Crystal Resonator Equivalent Circuit ...................................................................... 958
External Clock Input (Examples) ............................................................................ 959
External Clock Input Timing................................................................................... 960
Note on Board Design for Oscillation Circuit ......................................................... 963
Recommended External Circuitry for PLL Circuit ................................................. 963
Section 24 Power-Down Modes ........................................................................ 965
Figure 24.1
Figure 24.2
Figure 24.3
Figure 24.4
Mode Transitions..................................................................................................... 967
Software Standby Mode Application Example ....................................................... 976
Hardware Standby Mode Timing ............................................................................ 977
Hardware Standby Mode Timing when Power Is Supplied .................................... 978
Section 26 Electrical Characteristics ............................................................... 1019
Figure 26.1 Output Load Circuit .............................................................................................. 1023
Figure 26.2 System Clock Timing............................................................................................ 1067
Figure 26.3 SDRAMφ Timing.................................................................................................. 1067
Figure 26.4 (1) Oscillation Settling Timing................................................................................ 1068
Figure 26.4 (2) Oscillation Settling Timing................................................................................ 1068
Figure 26.5 Reset Input Timing................................................................................................ 1069
Figure 26.6 Interrupt Input Timing........................................................................................... 1069
Figure 26.7 Basic Bus Timing: Two-State Access ................................................................... 1070
Figure 26.8 Basic Bus Timing: Three-State Access ................................................................. 1071
Figure 26.9 Basic Bus Timing: Three-State Access, One Wait................................................ 1072
Figure 26.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) ............... 1073
Figure 26.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) ............. 1074
Figure 26.12 Burst ROM Access Timing: One-State Burst Access ........................................... 1075
Figure 26.13 Burst ROM Access Timing: Two-State Burst Access........................................... 1076
Figure 26.14 DRAM Access Timing: Two-State Access ........................................................... 1077
Figure 26.15 DRAM Access Timing: Two-State Access, One Wait.......................................... 1078
Figure 26.16 DRAM Access Timing: Two-State Burst Access ................................................. 1079
Figure 26.17 DRAM Access Timing: Three-State Access (RAST = 1) ..................................... 1080
Figure 26.18 DRAM Access Timing: Three-State Burst Access ............................................... 1081
Figure 26.19 CAS-Before-RAS Refresh Timing........................................................................ 1082
Figure 26.20 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) ........................... 1082
Figure 26.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0)............. 1083
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Figure 26.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1)............. 1083
Figure 26.23 External Bus Release Timing ................................................................................ 1084
Figure 26.24 External Bus Request Output Timing.................................................................... 1084
Figure 26.25 Synchronous DRAM Basic Access Timing (CAS Latency 2) .............................. 1085
Figure 26.26 Synchronous DRAM Self-Refresh Timing ........................................................... 1086
Figure 26.27 Read Data: Two-State Expansion (CAS Latency 2).............................................. 1087
Figure 26.28 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access....... 1088
Figure 26.29 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access..... 1089
Figure 26.30 DMAC and EXDMAC TEND/ETEND Output Timing ....................................... 1090
Figure 26.31 DMAC and EXDMAC DREQ/EDREQ Input Timing.......................................... 1090
Figure 26.32 EXDMAC EDRAK Output Timing ...................................................................... 1090
Figure 26.33 I/O Port Input/Output Timing................................................................................ 1091
Figure 26.34 PPG Output Timing............................................................................................... 1091
Figure 26.35 TPU Input/Output Timing ..................................................................................... 1091
Figure 26.36 TPU Clock Input Timing....................................................................................... 1092
Figure 26.37 8-Bit Timer Output Timing ................................................................................... 1092
Figure 26.38 8-Bit Timer Clock Input Timing ........................................................................... 1092
Figure 26.39 8-Bit Timer Reset Input Timing ............................................................................ 1092
Figure 26.40 WDT Output Timing ............................................................................................. 1093
Figure 26.41 SCK Clock Input Timing ...................................................................................... 1093
Figure 26.42 SCI Input/Output Timing: Synchronous Mode ..................................................... 1093
Figure 26.43 A/D Converter External Trigger Input Timing...................................................... 1093
Figure 26.44 I2C Bus Interface 2 Input/Output Timing (Option) ............................................... 1094
Appendix
Figure C.1
Figure C.2
Figure D.1
........................................................................................................1095
Package Dimensions (FP-144H) ........................................................................... 1106
Package Dimensions (TLP-145V)......................................................................... 1107
Timing of Address Bus, RD, HWR, and LWR
(8-Bit Bus, 3-State Access, No Wait).................................................................... 1109
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Tables
Section 1 Overview................................................................................................1
Table 1.1
Table 1.2
Pin Arrangement in Each Operating Mode ............................................................... 12
Pin Functions............................................................................................................. 18
Section 2 CPU......................................................................................................35
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 2.13
Instruction Classification........................................................................................... 51
Operation Notation .................................................................................................... 52
Data Transfer Instructions ......................................................................................... 53
Arithmetic Operations Instructions ........................................................................... 54
Logic Operations Instructions ................................................................................... 56
Shift Instructions ....................................................................................................... 56
Bit Manipulation Instructions.................................................................................... 57
Branch Instructions ................................................................................................... 59
System Control Instructions ...................................................................................... 60
Block Data Transfer Instructions............................................................................... 61
Addressing Modes..................................................................................................... 63
Absolute Address Access Ranges ............................................................................. 64
Effective Address Calculation................................................................................... 66
Section 3 MCU Operating Modes........................................................................71
Table 3.1
Table 3.2
MCU Operating Mode Selection............................................................................... 71
Pin Functions in Each Operating Mode..................................................................... 77
Section 4 Exception Handling .............................................................................93
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Exception Types and Priority .................................................................................... 93
Exception Handling Vector Table ............................................................................. 94
Status of CCR and EXR after Trace Exception Handling ......................................... 98
Status of CCR and EXR after Trap Instruction Exception Handling ........................ 99
Section 5 Interrupt Controller ............................................................................103
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Pin Configuration .................................................................................................... 105
Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................. 122
Interrupt Control Modes.......................................................................................... 127
Interrupt Response Times........................................................................................ 132
Number of States in Interrupt Handling Routine Execution Statuses...................... 133
Section 6 Bus Controller (BSC).........................................................................137
Table 6.1
Pin Configuration .................................................................................................... 139
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Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Table 6.8
Table 6.9
Table 6.10
Table 6.11
Table 6.12
Table 6.13
Bus Specifications for Each Area (Basic Bus Interface) ......................................... 173
Data Buses Used and Valid Strobes ........................................................................ 178
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space.............. 191
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing ..... 192
DRAM Interface Pins.............................................................................................. 193
Relation between Settings of Bits RMTS2 to RMTS0
and Synchronous DRAM Space.............................................................................. 216
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing ..... 217
Synchronous DRAM Interface Pins ........................................................................ 219
Setting CAS Latency ............................................................................................... 222
Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space..................................................................................... 264
Pin States in Idle Cycle ........................................................................................... 268
Pin States in Bus Released State ............................................................................. 271
Section 7 DMA Controller (DMAC)................................................................. 279
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Table 7.10
Table 7.11
Table 7.12
Pin Configuration .................................................................................................... 281
Short Address Mode and Full Address Mode (Channel 0)...................................... 282
DMAC Activation Sources ..................................................................................... 307
DMAC Transfer Modes........................................................................................... 310
Register Functions in Sequential Mode................................................................... 312
Register Functions in Idle Mode ............................................................................. 315
Register Functions in Repeat Mode ........................................................................ 317
Register Functions in Single Address Mode ........................................................... 320
Register Functions in Normal Mode ....................................................................... 323
Register Functions in Block Transfer Mode............................................................ 326
DMAC Channel Priority Order ............................................................................... 347
Interrupt Sources and Priority Order ....................................................................... 353
Section 8 EXDMA Controller (EXDMAC) ...................................................... 359
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Pin Configuration .................................................................................................... 361
EXDMAC Transfer Modes ..................................................................................... 374
EXDMAC Channel Priority Order.......................................................................... 390
Interrupt Sources and Priority Order ....................................................................... 420
Section 9 Data Transfer Controller (DTC) ........................................................ 425
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Relationship between Activation Sources and DTCER Clearing............................ 432
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................. 435
Chain Transfer Conditions ...................................................................................... 439
Register Function in Normal Mode......................................................................... 440
Register Function in Repeat Mode .......................................................................... 441
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Table 9.6
Table 9.7
Table 9.8
Register Function in Block Transfer Mode ............................................................. 442
DTC Execution Status ............................................................................................. 446
Number of States Required for Each Execution Status ........................................... 446
Section 10 I/O Ports ...........................................................................................455
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Port Functions ......................................................................................................... 456
Input Pull-Up MOS States (Port A)......................................................................... 512
Input Pull-Up MOS States (Port B)......................................................................... 516
Input Pull-Up MOS States (Port C)........................................................................ 520
Input Pull-Up MOS States (Port D)......................................................................... 524
Input Pull-Up MOS States (Port E) ......................................................................... 528
Section 11 16-Bit Timer Pulse Unit (TPU)........................................................545
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 11.7
Table 11.8
Table 11.9
Table 11.10
Table 11.11
Table 11.12
Table 11.13
Table 11.14
Table 11.15
Table 11.16
Table 11.17
Table 11.18
Table 11.19
Table 11.20
Table 11.21
Table 11.22
Table 11.23
Table 11.24
Table 11.25
Table 11.26
Table 11.27
Table 11.28
TPU Functions......................................................................................................... 546
Pin Configuration .................................................................................................... 549
CCLR2 to CCLR0 (Channels 0 and 3).................................................................... 553
CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)........................................................... 553
TPSC2 to TPSC0 (Channel 0)................................................................................. 554
TPSC2 to TPSC0 (Channel 1)................................................................................. 554
TPSC2 to TPSC0 (Channel 2)................................................................................. 555
TPSC2 to TPSC0 (Channel 3)................................................................................. 555
TPSC2 to TPSC0 (Channel 4)................................................................................. 556
TPSC2 to TPSC0 (Channel 5)................................................................................. 556
MD3 to MD0........................................................................................................... 558
TIORH_0................................................................................................................. 560
TIORL_0 ................................................................................................................. 561
TIOR_1 ................................................................................................................... 562
TIOR_2 ................................................................................................................... 563
TIORH_3................................................................................................................. 564
TIORL_3 ................................................................................................................. 565
TIOR_4 ................................................................................................................... 566
TIOR_5 ................................................................................................................... 567
TIORH_0................................................................................................................. 568
TIORL_0 ................................................................................................................. 569
TIOR_1 ................................................................................................................... 570
TIOR_2 ................................................................................................................... 571
TIORH_3................................................................................................................. 572
TIORL_3 ................................................................................................................. 573
TIOR_4 ................................................................................................................... 574
TIOR_5 ................................................................................................................... 575
Register Combinations in Buffer Operation............................................................ 592
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Table 11.29
Table 11.30
Table 11.31
Table 11.32
Table 11.33
Table 11.34
Table 11.35
Table 11.36
Cascaded Combinations .......................................................................................... 596
PWM Output Registers and Output Pins................................................................. 599
Clock Input Pins in Phase Counting Mode.............................................................. 603
Up/Down-Count Conditions in Phase Counting Mode 1 ........................................ 604
Up/Down-Count Conditions in Phase Counting Mode 2 ........................................ 605
Up/Down-Count Conditions in Phase Counting Mode 3 ........................................ 606
Up/Down-Count Conditions in Phase Counting Mode 4 ........................................ 607
TPU Interrupts......................................................................................................... 610
Section 12 Programmable Pulse Generator (PPG) ............................................ 631
Table 12.1
Pin Configuration .................................................................................................... 633
Section 13 8-Bit Timers (TMR) ........................................................................ 653
Table 13.1
Table 13.2
Table 13.3
Table 13.4
Table 13.5
Pin Configuration .................................................................................................... 655
Clock Input to TCNT and Count Condition ............................................................ 658
8-Bit Timer Interrupt Sources ................................................................................. 669
Timer Output Priorities ........................................................................................... 673
Switching of Internal Clock and TCNT Operation.................................................. 674
Section 14 Watchdog Timer (WDT) ................................................................. 677
Table 14.1
Table 14.2
Pin Configuration .................................................................................................... 678
WDT Interrupt Source............................................................................................. 684
Section 15 Serial Communication Interface (SCI, IrDA).................................. 689
Table 15.1
Table 15.2
Table 15.3
Table 15.4
Table 15.5
Table 15.6
Table 15.7
Table 15.8
Table 15.9
Table 15.10
Table 15.11
Table 15.12
Table 15.13
Table 15.14
Pin Configuration .................................................................................................... 692
Relationships between N Setting in BRR and Bit Rate B ....................................... 711
BRR Settings for Various Bit Rates (Asynchronous Mode) ................................... 712
Maximum Bit Rate for Each Frequency (Asynchronous Mode) ............................. 715
Maximum Bit Rate with External Clock Input (Asynchronous Mode)................... 716
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ....................... 717
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)....... 718
Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(when n = 0 and S = 372) ........................................................................................ 718
Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372) ........................................................................................................ 719
Serial Transfer Formats (Asynchronous Mode) ...................................................... 724
SSR Status Flags and Receive Data Handling......................................................... 731
Settings of Bits IrCKS2 to IrCKS0 ......................................................................... 761
SCI Interrupt Sources .............................................................................................. 763
Interrupt Sources ..................................................................................................... 764
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Section 16 I2C Bus Interface 2 (IIC2) (Option) .................................................771
Table 16.1
Table 16.2
Table 16.3
Table 16.4
Pin Configuration .................................................................................................... 773
Transfer Rate ........................................................................................................... 776
Interrupt Requests ................................................................................................... 801
Time for monitoring SCL........................................................................................ 802
Section 17 A/D Converter..................................................................................805
Table 17.1
Table 17.2
Table 17.3
Table 17.4
Table 17.5
Table 17.6
Pin Configuration .................................................................................................... 807
Analog Input Channels and Corresponding ADDR Registers................................. 808
A/D Conversion Time (Single Mode) ..................................................................... 814
A/D Conversion Time (Scan Mode)........................................................................ 815
A/D Converter Interrupt Source .............................................................................. 816
Analog Pin Specifications ....................................................................................... 820
Section 18 D/A Converter..................................................................................821
Table 18.1
Table 18.2
Table 18.3
Table 18.4
Pin Configuration .................................................................................................... 824
Control of D/A Conversion ..................................................................................... 826
Control of D/A Conversion ..................................................................................... 827
Control of D/A Conversion ..................................................................................... 828
Section 19 RAM ................................................................................................831
Section 20 Flash Memory (0.35-μm F-ZTAT Version) ....................................833
Table 20.1
Table 20.2
Table 20.3
Table 20.4
Table 20.5
Table 20.6
Table 20.7
Differences between Boot Mode and User Program Mode..................................... 835
Pin Configuration .................................................................................................... 840
Erase Blocks............................................................................................................ 845
Setting On-Board Programming Mode ................................................................... 846
Boot Mode Operation.............................................................................................. 848
System Clock Frequencies for which Automatic Adjustment
of LSI Bit Rate Is Possible ...................................................................................... 849
Flash Memory Operating States .............................................................................. 855
Section 21 Flash Memory (0.18-μm F-ZTAT Version) ....................................861
Table 21.1 Comparison of Programming Modes ...................................................................... 865
Table 21.2 Pin Configuration .................................................................................................... 870
Table 21.3 Register/Parameter and Target Mode...................................................................... 872
Table 21.4 Parameters and Target Modes ................................................................................. 880
Table 21.5 Setting On-Board Programming Mode ................................................................... 891
Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI ........... 893
Table 21.7 Executable MAT ..................................................................................................... 911
Table 21.8 (1) Useable Area for Programming in User Program Mode ....................................... 912
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Table 21.8 (2) Useable Area for Erasure in User Program Mode................................................. 914
Table 21.8 (3) Useable Area for Programming in User Boot Mode ............................................. 916
Table 21.8 (4) Useable Area for Erasure in User Boot Mode....................................................... 918
Table 21.9 Hardware Protection................................................................................................ 920
Table 21.10 Software Protection ................................................................................................. 921
Table 21.11 Inquiry and Selection Commands ........................................................................... 928
Table 21.12 Programming/Erasing Command ............................................................................ 941
Table 21.13 Status Code.............................................................................................................. 950
Table 21.14 Error Code............................................................................................................... 951
Table 21.15 User Branch Processing Start Intervals ................................................................... 952
Section 23 Clock Pulse Generator ..................................................................... 955
Table 23.1
Table 23.2
Table 23.3
Damping Resistance Value ..................................................................................... 958
Crystal Resonator Characteristics............................................................................ 959
External Clock Input Conditions ............................................................................. 960
Section 24 Power-Down Modes ........................................................................ 965
Table 24.1
Table 24.2
Table 24.3
Operating Modes and Internal states of the LSI ...................................................... 966
Oscillation Stabilization Time Settings ................................................................... 975
φ Pin State in Each Processing State ....................................................................... 979
Section 26 Electrical Characteristics ............................................................... 1019
Table 26.1
Table 26.2
Table 26.3
Table 26.4
Table 26.5
Table 26.6
Table 26.7
Table 26.8
Table 26.9
Table 26.10
Table 26.11
Table 26.12
Table 26.13
Table 26.14
Table 26.15
Table 26.16
Table 26.17
Table 26.18
Table 26.19
Absolute Maximum Ratings.................................................................................. 1019
DC Characteristics (1) ........................................................................................... 1020
DC Characteristics (2) ........................................................................................... 1021
Permissible Output Currents ................................................................................. 1022
Clock Timing......................................................................................................... 1024
Control Signal Timing........................................................................................... 1025
Bus Timing (1) ...................................................................................................... 1026
Bus Timing (2) ...................................................................................................... 1027
DMAC and EXDMAC Timing ............................................................................. 1029
Timing of On-Chip Peripheral Modules................................................................ 1030
A/D Conversion Characteristics ............................................................................ 1032
D/A Conversion Characteristics ............................................................................ 1032
Flash Memory Characteristics (0.35-μm F-ZTAT Version) ................................. 1033
Absolute Maximum Ratings.................................................................................. 1035
DC Characteristics................................................................................................. 1036
DC Characteristics................................................................................................. 1037
Permissible Output Currents ................................................................................. 1038
Clock Timing......................................................................................................... 1039
Control Signal Timing........................................................................................... 1040
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Table 26.20
Table 26.21
Table 26.22
Table 26.23
Table 26.24
Table 26.25
Table 26.26
Table 26.27
Table 26.28
Table 26.29
Table 26.30
Table 26.31
Table 26.32
Table 26.33
Table 26.34
Table 26.35
Table 26.36
Table 26.37
Table 26.38
Table 26.39
Table 26.40
Table 26.41
Appendix
Table D.1
Bus Timing (1) ...................................................................................................... 1041
Bus Timing (2) ...................................................................................................... 1043
DMAC and EXDMAC Timing ............................................................................. 1045
Timing of On-Chip Peripheral Modules................................................................ 1046
A/D Conversion Characteristics ............................................................................ 1048
D/A Conversion Characteristics ............................................................................ 1048
Flash Memory Characteristics (0.18-μm F-ZTAT Version) ................................. 1049
Absolute Maximum Ratings.................................................................................. 1050
DC Characteristics................................................................................................. 1051
DC Characteristics................................................................................................. 1052
Permissible Output Currents ................................................................................. 1053
Clock Timing......................................................................................................... 1054
Control Signal Timing........................................................................................... 1055
Bus Timing (1) ...................................................................................................... 1056
Bus Timing (2) ...................................................................................................... 1058
DMAC and EXDMAC Timing ............................................................................. 1060
Timing of On-Chip Peripheral Modules................................................................ 1061
A/D Conversion Characteristics ............................................................................ 1063
D/A Conversion Characteristics ............................................................................ 1063
Flash Memory Characteristics (0.18-μm F-ZTAT Version) (512 kbytes) ............ 1064
Flash Memory Characteristics (0.18-μm F-ZTAT Version) (384 kbytes) ............ 1065
Flash Memory Characteristics (0.18-μm F-ZTAT Version) (256 kbytes) ............ 1066
........................................................................................................1095
Execution State of Instructions.............................................................................. 1110
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Section 1 Overview
Section 1 Overview
1.1
Features
• High-speed H8S/2000 CPU with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions
• Various peripheral functions
DMA controller (DMAC)
EXDMA controller (EXDMAC)*
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
Programmable pulse generator (PPG)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
I2C bus interface 2 (IIC2)
10-bit A/D converter
8-bit D/A converter
Clock pulse generator
Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
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Section 1 Overview
• On-chip memory
ROM Type
Model
ROM
RAM
Remarks
Flash memory version
HD64F2378B
512 kbytes
32 kbytes
H8S/2378 0.18μm F-ZTAT Group
H8S/2378R 0.18μm F-ZTAT Group
Masked ROM version
ROMless version
HD64F2378R
512 kbytes
32 kbytes
HD64F2377
384 kbytes
24 kbytes
HD64F2377R
384 kbytes
24 kbytes
HD64F2374
384 kbytes
32 kbytes
H8S/2378 0.18μm F-ZTAT Group
HD64F2374R
384 kbytes
32 kbytes
H8S/2378R 0.18μm F-ZTAT Group
HD64F2372
256 kbytes
32 kbytes
H8S/2378 0.18μm F-ZTAT Group
HD64F2372R
256 kbytes
32 kbytes
H8S/2378R 0.18μm F-ZTAT Group
HD64F2371
256 kbytes
24 kbytes
H8S/2378 0.18μm F-ZTAT Group
HD64F2371R
256 kbytes
24 kbytes
H8S/2378R 0.18μm F-ZTAT Group
HD64F2370
256 kbytes
16 kbytes
H8S/2378 0.18μm F-ZTAT Group
HD64F2370R
256 kbytes
16 kbytes
H8S/2378R 0.18μm F-ZTAT Group
HD6432375
256 kbytes
16 kbytes
HD6432375R
256 kbytes
16 kbytes
HD6412373
⎯
16 kbytes
HD6412373R
⎯
16 kbytes
• General I/O ports
I/O pins: 96
Input-only pins: 17
• Supports various power-down states
• Compact package
Package
(Code)
Body Size
Pin Pitch
FP-144
FP-144H (FP-144HV*)
22.0 × 22.0 mm
0.5 mm
LGA-145
TLP-145V*
9.0 × 9.0 mm
0.65 mm
Note: * Pb-free version
Rev.7.00 Mar. 18, 2009 page 2 of 1136
REJ09B0109-0700
Section 1 Overview
Port A
Port B
Periheral adree bus
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
Port C
DMAC
ROM*
(Flash memory)
PA7/A23/IRQ7
PA6/A22/IRQ6
PA5/A21/IRQ5
PA4/A20/IRQ4
PA3/A19
PA2/A18
PA1/A17
PA0/A16
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
Port 3
DTC
Peripheral data bus
Port F
Port G
Interrupt controller
Bus controller
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
Internal data bus
H8S/2000 CPU
Clock
pulse
generator
PG6/BREQ
PG5/BACK
PG4/BREQO
PG3/CS3/RAS3/CAS*
PG2/CS2/RAS2/RAS
PG1/CS1
PG0/CS0
P35/SCK1/SCL0/(OE)/(CKE)*
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
EXDMAC
RAM
WDT
Port 6
SCI x 5 channels
IIC bus interface(option)
TPU x 8 channels
Port 5
8-bit D/A converter
x 6 channels
PPG
10-bit A/D converter
Port 8
P53/ADTRG/IRQ3
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
Port 4
Port 9
Port H
P47/AN7/DA1
P46/AN6/DA0
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
P97/AN15/DA5
P96/AN14/DA4
P95/AN13/DA3
P94/AN12/DA2
P93/AN11
P92/AN10
P91/AN9
P90/AN8
PH3/CS7/OE/(IRQ7)/CKE*
PH2/CS6/(IRQ6)
PH1/CS5/RAS5/SDRAMφ*
PH0/CS4/RAS4/WE*
Port 2
Vref
AVcc
AVss
Port 1
P20/PO0/TIOCA3/(IRQ8)
P21/PO1/TIOCB3/(IRQ9)
P22/PO2/TIOCC3/(IRQ10)
P23/PO3/TIOCD3/TxD4/(IRQ11)
P24/PO4/TIOCA4/RxD4/(IRQ12)
P25/PO5/TIOCB4/(IRQ13)
P26/PO6/TIOCA5/(IRQ14)
P27/PO7/TIOCB5/(IRQ15)
TMR x 2 channels
P10/PO8/TIOCA0
P11/PO9/TIOCB0
P12/PO10/TIOCC0/TCLKA
P13/PO11/TIOCD0/TCLKB
P14/PO12/TIOCA1
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2/EDRAK2
P17/PO15/TIOCB2/TCLKD/EDRAK3
P85/(IRQ5)/SCK3/EDACK3
P84/(IRQ4)/EDACK2
P83/(IRQ3)/RxD3/ETEND3
P82/(IRQ2)/ETEND2
P81/(IRQ1)/TxD3/EDREQ3
P80/(IRQ0)/EDREQ2
Port E
PLL
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/LCAS/IRQ15/DQML*
PF1/UCAS/IRQ14/DQMU*
PF0/WAIT
P65/TMO1/DACK1/IRQ13
P64/TMO0/DACK0/IRQ12
P63/TMCI1/TEND1/IRQ11
P62/TMCI0/TEND0/IRQ10
P61/TMRI1/DREQ1/IRQ9
P60/TMRI0/DREQ0/IRQ8
Port D
Internal adree bus
MD2
MD1
MD0
DCTL
EXTAL
XTAL
EMLE
STBY
RES
WDTOVF
NMI
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Block Diagram
Vcc
Vcc
Vcc
Vcc
PLLVcc
PLLVss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
VCL
1.2
Note: * Not available for the H8S/2378 0.18µm
F-ZTAT Group.
Figure 1.1 Internal Block Diagram for H8S/2378 0.18μm F-ZTAT Group
and H8S/2378R 0.18μm F-ZTAT Group
Rev.7.00 Mar. 18, 2009 page 3 of 1136
REJ09B0109-0700
Port A
PA7/A23/IRQ7
PA6/A22/IRQ6
PA5/A21/IRQ5
PA4/A20/IRQ4
PA3/A19
PA2/A18
PA1/A17
PA0/A16
Port B
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
Port C
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
Port 3
DMAC
ROM*
(Flash memory)
Periheral adree bus
DTC
Peripheral data bus
Port F
Port G
Interrupt controller
Bus controller
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
Internal data bus
H8S/2000 CPU
Clock
pulse
generator
PG6/BREQ
PG5/BACK
PG4/BREQO
PG3/CS3/RAS3/CAS*
PG2/CS2/RAS2/RAS
PG1/CS1
PG0/CS0
P35/SCK1/SCL0/(OE)/(CKE)*
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
EXDMAC
RAM
WDT
Port 6
SCI x 5 channels
I2 C bus interface 2 (option)
TPU x 6 channels
Port 5
8-bit D/A converter
x 6 channels
PPG
10-bit A/D converter
Port 8
P53/ADTRG/IRQ3
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
Port 4
Port 9
Port H
P47/AN7/DA1
P46/AN6/DA0
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
P97/AN15/DA5
P96/AN14/DA4
P95/AN13/DA3
P94/AN12/DA2
P93/AN11
P92/AN10
P91/AN9
P90/AN8
PH3/CS7/OE/(IRQ7)/CKE*
PH2/CS6/(IRQ6)
PH1/CS5/RAS5/SDRAMφ*
PH0/CS4/RAS4/WE*
Port 2
Vref
AVcc
AVss
Port 1
P20/PO0/TIOCA3/(IRQ8)
P21/PO1/TIOCB3/(IRQ9)
P22/PO2/TIOCC3/(IRQ10)
P23/PO3/TIOCD3/TxD4/(IRQ11)
P24/PO4/TIOCA4/RxD4/(IRQ12)
P25/PO5/TIOCB4/(IRQ13)
P26/PO6/TIOCA5/(IRQ14)
P27/PO7/TIOCB5/(IRQ15)
TMR x 2 channels
P10/PO8/TIOCA0
P11/PO9/TIOCB0
P12/PO10/TIOCC0/TCLKA
P13/PO11/TIOCD0/TCLKB
P14/PO12/TIOCA1
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2/EDRAK2
P17/PO15/TIOCB2/TCLKD/EDRAK3
P85/(IRQ5)/SCK3/EDACK3
P84/(IRQ4)/EDACK2
P83/(IRQ3)/RxD3/ETEND3
P82/(IRQ2)/ETEND2
P81/(IRQ1)/TxD3/EDREQ3
P80/(IRQ0)/EDREQ2
Port E
PLL
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/LCAS/IRQ15/DQML*
PF1/UCAS/IRQ14/DQMU*
PF0/WAIT
P65/TMO1/DACK1/IRQ13
P64/TMO0/DACK0/IRQ12
P63/TMCI1/TEND1/IRQ11
P62/TMCI0/TEND0/IRQ10
P61/TMRI1/DREQ1/IRQ9
P60/TMRI0/DREQ0/IRQ8
Port D
Internal adree bus
MD2
MD1
MD0
DCTL
EXTAL
XTAL
EMLE
STBY
RES
WDTOVF
NMI
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Vcc
Vcc
Vcc
Vcc
Vcc
PLLVcc
PLLVss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Section 1 Overview
Note: * Not available for the H8S/2377.
Figure 1.2 Internal Block Diagram for H8S/2377 and H8S/2377R
Rev.7.00 Mar. 18, 2009 page 4 of 1136
REJ09B0109-0700
Port A
Port B
Port 6
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P35/SCK1/SCL0/(OE)/(CKE)*
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
WDT
SCI x 5 channels
2
I C bus interface 2 (option)
TPU x 6 channels
Port 5
8-bit D/A converter
x 2 channels
PPG
10-bit A/D converter
Port 8
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
Port C
RAM
PA7/A23/IRQ7
PA6/A22/IRQ6
PA5/A21/IRQ5
PA4/A20/IRQ4
PA3/A19
PA2/A18
PA1/A17
PA0/A16
Port 3
DMAC
ROM*
(Masked ROM)
Periheral adree bus
DTC
Peripheral data bus
Port F
Port G
Interrupt controller
Bus controller
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
Internal data bus
H8S/2000 CPU
Clock
pulse
generator
PG6/BREQ
PG5/BACK
PG4/BREQO
PG3/CS3/RAS3/CAS*
PG2/CS2/RAS2/RAS
PG1/CS1
PG0/CS0
P53/ADTRG/IRQ3
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
Port 4
Port 9
Port H
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
P97/AN15
P96/AN14
P95/AN13/DA3
P94/AN12/DA2
P93/AN11
P92/AN10
P91/AN9
P90/AN8
PH3/CS7/OE/(IRQ7)/CKE*
PH2/CS6/(IRQ6)
PH1/CS5/RAS5/SDRAMφ*
PH0/CS4/RAS4/WE*
Port 2
Vref
AVcc
AVss
Port 1
P20/PO0/TIOCA3/(IRQ8)
P21/PO1/TIOCB3/(IRQ9)
P22/PO2/TIOCC3/(IRQ10)
P23/PO3/TIOCD3/TxD4/(IRQ11)
P24/PO4/TIOCA4/RxD4/(IRQ12)
P25/PO5/TIOCB4/(IRQ13)
P26/PO6/TIOCA5/(IRQ14)
P27/PO7/TIOCB5/(IRQ15)
TMR x 2 channels
P10/PO8/TIOCA0
P11/PO9/TIOCB0
P12/PO10/TIOCC0/TCLKA
P13/PO11/TIOCD0/TCLKB
P14/PO12/TIOCA1
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2
P17/PO15/TIOCB2/TCLKD
P85/(IRQ5)/SCK3
P84/(IRQ4)
P83/(IRQ3)/RxD3
P82/(IRQ2)
P81/(IRQ1)/TxD3
P80/(IRQ0)
Port E
PLL
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/LCAS/IRQ15/DQML*
PF1/UCAS/IRQ14/DQMU*
PF0/WAIT
P65/TMO1/DACK1/IRQ13
P64/TMO0/DACK0/IRQ12
P63/TMCI1/TEND1/IRQ11
P62/TMCI0/TEND0/IRQ10
P61/TMRI1/DREQ1/IRQ9
P60/TMRI0/DREQ0/IRQ8
Port D
Internal adree bus
MD2
MD1
MD0
DCTL
EXTAL
XTAL
EMLE
STBY
RES
WDTOVF
NMI
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Vcc
Vcc
Vcc
Vcc
Vcc
PLLVcc
PLLVss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Section 1 Overview
Note: * Not available for the H8S/2375.
Figure 1.3 Internal Block Diagram for H8S/2375 and H8S/2375R
Rev.7.00 Mar. 18, 2009 page 5 of 1136
REJ09B0109-0700
Port A
Port B
Port 6
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P35/SCK1/SCL0/(OE)/(CKE)*
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
WDT
SCI x 5 channels
I2 C bus interface (option)
TPU x 6 channels
Port 5
8-bit D/A converter
x 2 channels
PPG
10-bit A/D converter
Port 8
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
Port C
RAM
PA7/A23/IRQ7
PA6/A22/IRQ6
PA5/A21/IRQ5
PA4/A20/IRQ4
PA3/A19
PA2/A18
PA1/A17
PA0/A16
Port 3
DMAC
Periheral adree bus
DTC
Peripheral data bus
Port F
Port G
Interrupt controller
Bus controller
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
Internal data bus
H8S/2000 CPU
Clock
pulse
generator
PG6/BREQ
PG5/BACK
PG4/BREQO
PG3/CS3/RAS3/CAS*
PG2/CS2/RAS2/RAS
PG1/CS1
PG0/CS0
P53/ADTRG/IRQ3
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
Note: * Not available for the H8S/2373.
Port 4
Port 9
Port H
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
P97/AN15
P96/AN14
P95/AN13/DA3
P94/AN12/DA2
P93/AN11
P92/AN10
P91/AN9
P90/AN8
PH3/CS7/OE/(IRQ7)/CKE*
PH2/CS6/(IRQ6)
PH1/CS5/RAS5/SDRAMφ*
PH0/CS4/RAS4/WE*
Port 2
Vref
AVcc
AVss
Port 1
P20/PO0/TIOCA3/(IRQ8)
P21/PO1/TIOCB3/(IRQ9)
P22/PO2/TIOCC3/(IRQ10)
P23/PO3/TIOCD3/TxD4/(IRQ11)
P24/PO4/TIOCA4/RxD4/(IRQ12)
P25/PO5/TIOCB4/(IRQ13)
P26/PO6/TIOCA5/(IRQ14)
P27/PO7/TIOCB5/(IRQ15)
TMR x 2 channels
P10/PO8/TIOCA0
P11/PO9/TIOCB0
P12/PO10/TIOCC0/TCLKA
P13/PO11/TIOCD0/TCLKB
P14/PO12/TIOCA1
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2
P17/PO15/TIOCB2/TCLKD
P85/(IRQ5)/SCK3
P84/(IRQ4)
P83/(IRQ3)/RxD3
P82/(IRQ2)
P81/(IRQ1)/TxD3
P80/(IRQ0)
Port E
PLL
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/LCAS/IRQ15/DQML*
PF1/UCAS/IRQ14/DQMU*
PF0/WAIT
P65/TMO1/DACK1/IRQ13
P64/TMO0/DACK0/IRQ12
P63/TMCI1/TEND1/IRQ11
P62/TMCI0/TEND0/IRQ10
P61/TMRI1/DREQ1/IRQ9
P60/TMRI0/DREQ0/IRQ8
Port D
Internal adree bus
MD2
MD1
MD0
DCTL
EXTAL
XTAL
EMLE
STBY
RES
WDTOVF
NMI
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Vcc
Vcc
Vcc
Vcc
Vcc
PLLVcc
PLLVss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Section 1 Overview
Figure 1.4 Internal Block Diagram for H8S/2373 and H8S/2373R
Rev.7.00 Mar. 18, 2009 page 6 of 1136
REJ09B0109-0700
Section 1 Overview
Pin Description
1.3.1
Pin Arrangement
LQFP-144
(Top view)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
MD2
VSS
P80/(IRQ0)/EDREQ2
Vcc
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
Vss
PC5/A5
PC6/A6
PC7/A7
PB0/A8
PB1/A9
PB2/A10
PB3/A11
Vss
PB4/A12
PB5/A13
PB6/A14
PB7/A15
PA0/A16
PA1/A17
Vss
PA2/A18
PA3/A19
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/IRQ7
EMLE*3
P81/(IRQ1)/TxD3/EDREQ3
P82/(IRQ2)/ETEND2
PH0/CS4/RAS4/WE*1
PH1/CS5/RAS5/SDRAMφ*1
PG2/CS2/RAS2/RAS
PG3/CS3/RAS3/CAS*1
AVcc
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6/DA0
P47/AN7/DA1
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12/DA2
P95/AN13/DA3
P96/AN14/DA4
P97/AN15/DA5
AVss
PG4/BREQO
PG5/BACK
PG6/BREQ
P50/TxD2/IRQ0
P51/RxD2/IRQ1
P52/SCK2/IRQ2
P53/ADTRG/IRQ3
P35/SCK1/SCL0/(OE)/(CKE)*1
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
MD0
MD1
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PG1/CS1
PG0/CS0
P65/TMO1/IDACK1/RQ13
P64/TMO0/DACK0/IRQ12
P63/TMCI1/TEND1/IRQ11
STBY
Vss
NC*2
NC*2
VCC
VCC
EXTAL
XTAL
Vss
PF7/φ
PLLVss
RES
PLLVcc
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/IRQ15/LCAS/DQML*1
PF1/IRQ14/UCAS/DQMU*1
PF0/WAIT
P62/TMCI0/TEND0/IRQ10
P61/TMRI1/DREQ1/IRQ9
P60/TMRI0/DREQ0/IRQ8
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
1.3
Vcc
PE7/D7
Vss
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
DCTL
P85/(IRQ5)/SCK3/EDACK3
P84/(IRQ4)/EDACK2
P83/(IRQ3)/RxD3/ETEND3
P27/PO7/TIOCB5/(IRQ15)
P26/PO6/TIOCA5/(IRQ14)
P25/PO5/TIOCB4/(IRQ13)
P24/PO4/TIOCA4/RxD4/(IRQ12)
P23/PO3/TIOCD3/TxD4/(IRQ11)
P22/PO2/TIOCC3/(IRQ10)
P21/PO1/TIOCB3/(IRQ9)
P20/PO0/TIOCA3/(IRQ8)
Vss
P17/PO15/TIOCB2/TCLKD/EDRAK3
P16/PO14/TIOCA2/EDRAK2
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1
P13/PO11/TIOCD0/TCLKB
P12/PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0
P10/PO8/TIOCA0
VCL*4
NMI
WDTOVF
PH3/CS7/(IRQ7)/OE/CKE*1
PH2/CS6/(IRQ6)
41
0.1μF
(recommended
value)
Notes: 1. Not available for the H8S/2378 0.18µm F-ZTAT Group.
2. These NC pins should be open.
3. On-chip emulator enable. In normal operating mode, this pin should be fixed low. Driving this pin high enables the on-chip emulation function.
When the on-chip emulation function is in use, pins P53, PG4, PG5, PG6, and WDTOVF are exclusively for the on-chip emulator pins.
For details of an example of connection to E10A, please refer to E10A Emulator User's Manual.
4. The VCL pin should be connected to an external capacitor.
Figure 1.5 Pin Arrangement for H8S/2378 0.18μm F-ZTAT Group
and H8S/2378R 0.18μm F-ZTAT Group
Rev.7.00 Mar. 18, 2009 page 7 of 1136
REJ09B0109-0700
LQFP-144
(Top view)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Vcc
PE7/D7
Vss
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
DCTL
P85/(IRQ5)/SCK3/EDACK3
P84/(IRQ4)/EDACK2
P83/(IRQ3)/RxD3/ETEND3
P27/PO7/TIOCB5/(IRQ15)
P26/PO6/TIOCA5/(IRQ14)
P25/PO5/TIOCB4/(IRQ13)
P24/PO4/TIOCA4/RxD4/(IRQ12)
P23/PO3/TIOCD3/TxD4/(IRQ11)
P22/PO2/TIOCC3/(IRQ10)
P21/PO1/TIOCB3/(IRQ9)
P20/PO0/TIOCA3/(IRQ8)
Vss
P17/PO15/TIOCB2/TCLKD/EDRAK3
P16/PO14/TIOCA2/EDRAK2
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1
P13/PO11/TIOCD0/TCLKB
P12/PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0
P10/PO8/TIOCA0
Vcc
NMI
WDTOVF
PH3/CS7/(IRQ7)/OE/CKE*1
PH2/CS6/(IRQ6)
MD2
VSS
P80/(IRQ0)/EDREQ2
Vcc
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
Vss
PC5/A5
PC6/A6
PC7/A7
PB0/A8
PB1/A9
PB2/A10
PB3/A11
Vss
PB4/A12
PB5/A13
PB6/A14
PB7/A15
PA0/A16
PA1/A17
Vss
PA2/A18
PA3/A19
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/IRQ7
EMLE*3
P81/(IRQ1)/TxD3/EDREQ3
P82/(IRQ2)/ETEND2
PH0/CS4/RAS4/WE*1
PH1/CS5/RAS5/SDRAMφ*1
PG2/CS2/RAS2/RAS
PG3/CS3/RAS3/CAS*1
AVcc
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6/DA0
P47/AN7/DA1
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12/DA2
P95/AN13/DA3
P96/AN14/DA4
P97/AN15/DA5
AVss
PG4/BREQO
PG5/BACK
PG6/BREQ
P50/TxD2/IRQ0
P51/RxD2/IRQ1
P52/SCK2/IRQ2
P53/ADTRG/IRQ3
P35/SCK1/SCL0/(OE)/(CKE)*1
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
MD0
MD1
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PG1/CS1
PG0/CS0
P65/TMO1/DACK1/IRQ13
P64/TMO0/DACK0/IRQ12
P63/TMCI1/TEND1/IRQ11
STBY
Vss
NC*2
NC*2
VCC
VCC
EXTAL
XTAL
Vss
PF7/φ
PLLVss
RES
PLLVcc
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/IRQ15/LCAS/DQML*1
PF1/IRQ14/UCAS/DQMU*1
PF0/WAIT
P62/TMCI0/TEND0/IRQ10
P61/TMRI1/DREQ1/IRQ9
P60/TMRI0/DREQ0/IRQ8
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Section 1 Overview
Notes: 1. Not available for the H8S/2377.
2. These NC pins should be open.
3. On-chip emulator enable. In normal operating mode, this pin should be fixed low. Driving this pin high enables the on-chip emulation function.
When the on-chip emulation function is in use, pins P54, PG4, PG5, PG6, and WDTOVF are exclusively for the on-chip emulator pins.
For details on an example of connection to E10A, please refer to E10A Emulator User's Manual.
Figure 1.6 Pin Arrangement for H8S/2377 and H8S/2377R
Rev.7.00 Mar. 18, 2009 page 8 of 1136
REJ09B0109-0700
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
LQFP-144
(Top view)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
Vcc
PE7/D7
Vss
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
DCTL
P85/(IRQ5)/SCK3
P84/(IRQ4)
P83/(IRQ3)/RxD3
P27/PO7/TIOCB5/(IRQ15)
P26/PO6/TIOCA5/(IRQ14)
P25/PO5/TIOCB4/(IRQ13)
P24/PO4/TIOCA4/RxD4/(IRQ12)
P23/PO3/TIOCD3/TxD4/(IRQ11)
P22/PO2/TIOCC3/(IRQ10)
P21/PO1/TIOCB3/(IRQ9)
P20/PO0/TIOCA3/(IRQ8)
Vss
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1
P13/PO11/TIOCD0/TCLKB
P12/PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0
P10/PO8/TIOCA0
Vcc
NMI
WDTOVF
PH3/CS7/(IRQ7)/OE/CKE*1
PH2/CS6/(IRQ6)
MD2
VSS
P80/(IRQ0)
Vcc
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
Vss
PC5/A5
PC6/A6
PC7/A7
PB0/A8
PB1/A9
PB2/A10
PB3/A11
Vss
PB4/A12
PB5/A13
PB6/A14
PB7/A15
PA0/A16
PA1/A17
Vss
PA2/A18
PA3/A19
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/IRQ7
EMLE*3
P81/(IRQ1)/TxD3
P82/(IRQ2)
PH0/CS4/RAS4/WE*1
PH1/CS5/RAS5/SDRAMφ*1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PG2/CS2/RAS2/RAS
PG3/CS3/RAS3/CAS*1
AVcc
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12/DA2
P95/AN13/DA3
P96/AN14
P97/AN15
AVss
PG4/BREQO
PG5/BACK
PG6/BREQ
P50/TxD2/IRQ0
P51/RxD2/IRQ1
P52/SCK2/IRQ2
P53/ADTRG/IRQ3
P35/SCK1/SCL0/(OE)/(CKE)*1
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
MD0
MD1
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PG1/CS1
PG0/CS0
P65/TMO1/DACK1/IRQ13
P64/TMO0/DACK0/IRQ12
P63/TMCI1/TEND1/IRQ11
STBY
Vss
NC*2
NC*2
VCC
VCC
EXTAL
XTAL
Vss
PF7/φ
PLLVss
RES
PLLVcc
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/IRQ15/LCAS/DQML*1
PF1/IRQ14/UCAS/DQMU*1
PF0/WAIT
P62/TMCI0/TEND0/IRQ10
P61/TMRI1/DREQ1/IRQ9
P60/TMRI0/DREQ0/IRQ8
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Section 1 Overview
Notes: 1. Not available for the H8S/2375.
2. These NC pins should be open.
3. This pin should be fixed low.
Figure 1.7 Pin Arrangement for H8S/2375 and H8S/2375R
Rev.7.00 Mar. 18, 2009 page 9 of 1136
REJ09B0109-0700
LQFP-144
(Top view)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Vcc
PE7/D7
Vss
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
DCTL*4
P85/(IRQ5)/SCK3
P84/(IRQ4)
P83/(IRQ3)/RxD3
P27/PO7/TIOCB5/(IRQ15)
P26/PO6/TIOCA5/(IRQ14)
P25/PO5/TIOCB4/(IRQ13)
P24/PO4/TIOCA4/RxD4/(IRQ12)
P23/PO3/TIOCD3/TxD4/(IRQ11)
P22/PO2/TIOCC3/(IRQ10)
P21/PO1/TIOCB3/(IRQ9)
P20/PO0/TIOCA3/(IRQ8)
Vss
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1
P13/PO11/TIOCD0/TCLKB
P12/PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0
P10/PO8/TIOCA0
Vcc
NMI
WDTOVF
PH3/CS7/(IRQ7)/OE/CKE*1
PH2/CS6/(IRQ6)
MD2
VSS
P80/(IRQ0)
Vcc
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
Vss
PC5/A5
PC6/A6
PC7/A7
PB0/A8
PB1/A9
PB2/A10
PB3/A11
Vss
PB4/A12
PB5/A13
PB6/A14
PB7/A15
PA0/A16
PA1/A17
Vss
PA2/A18
PA3/A19
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/IRQ7
EMLE*3
P81/(IRQ1)/TxD3
P82/(IRQ2)
PH0/CS4/RAS4/WE*1
PH1/CS5/RAS5/SDRAMφ*1
PG2/CS2/RAS2/RAS
PG3/CS3/RAS3/CAS*1
AVcc
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12/DA2
P95/AN13/DA3
P96/AN14
P97/AN15
AVss
PG4/BREQO
PG5/BACK
PG6/BREQ
P50/TxD2/IRQ0
P51/RxD2/IRQ1
P52/SCK2/IRQ2
P53/ADTRG/IRQ3
P35/SCK1/SCL0/(OE)/(CKE)*1
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
MD0
MD1
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PG1/CS1
PG0/CS0
P65/TMO1/DACK1/IRQ13
P64/TMO0/DACK0/IRQ12
P63/TMCI1/TEND1/IRQ11
STBY
Vss
NC*2
NC*2
VCC
VCC
EXTAL
XTAL
Vss
PF7/φ
PLLVss
RES
PLLVcc
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/IRQ15/LCAS/DQML*1
PF1/IRQ14/UCAS/DQMU*1
PF0/WAIT
P62/TMCI0/TEND0/IRQ10
P61/TMRI1/DREQ1/IRQ9
P60/TMRI0/DREQ0/IRQ8
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Section 1 Overview
Notes: 1.
2.
3.
4.
Not available for the H8S/2373.
These NC pins should be open.
This pin should be fixed low.
On the H8S/2378R, driving this pin is high causes the SDRAMφ dedicated clock for the synchronous DRAM to be output.
Figure 1.8 Pin Arrangement for H8S/2373 and H8S/2373R
Rev.7.00 Mar. 18, 2009 page 10 of 1136
REJ09B0109-0700
Section 1 Overview
1
2
3
4
5
A
VSS
MD1
MD0
P32
P35
B
MD2 VCC
P31
P34
P51
C
PC0
P80
PC1
P30
D
PC4
PC2
PC3
E
PC7
VSS
F
PB3
G
9
10
11
12
13
P50 AVSS P94
P90
P44
P40
PG2
PG3
PG4
P93
P47
P45
P42 AVCC VREF PG1
P33
P52
PG5
P92
P46
P43
P41
P64
P53
PG6
P97
P96
P95
P91
P63
PG0
VCC STBY
PC5
PB0
NC
VSS
VSS
NC EXTAL
PC6
PB1
VSS
PF7
VCC
RES XTAL
PB6
PB2
PA0
PB4
PF6
NC
PF5 PLLVSS
H
VSS
PB7
PA3
PB5
PF2
PF4
PF1 PLLVCC
J
PA5
PA2
PA7
PA1
P62
PF0
P60
PF3
EMLE PA6
P82
PA4
VSS
P23
P24
P25
P84
PE1
PD7
PD6
P61
P10
PE4
VSS
PD4
PD2
PD5
DCTL PE3
PE6
PD3
PD0
PE5
PE7
VCC
PD1
K
6
7
8
HD64F2378B, HD64F2374,
HD64F2372, HD64F2371,
HD64F2370, HD64F2378R,
HD64F2374R, HD64F2372R,
HD64F2371R, HD64F2370R
(145-pin)
Pin Arrangement
(Top View)
L
PH0
P81
P12
P15
P20
P83
PE0
M
PH1
PH3 WDTOVF P11
P14
P16
P21
P27
N
NMI
PH2
P17
P22
P26
P85
VCL
P13
PE2
P65
Note: Connect NC to VSS or leave it open.
The VCL pin must be connected to an external capacitor (recommended value: 0.1 µF).
Figure 1.9 Pin Arrangement (TLP-145V: Top View)
Rev.7.00 Mar. 18, 2009 page 11 of 1136
REJ09B0109-0700
Section 1 Overview
1.3.2
Pin Arrangement in Each Operating Mode
Table 1.1
Pin Arrangement in Each Operating Mode
Pin No.
Pin Name
LQFP- LGA144
145
Mode 1
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
1
B1
MD2
MD2
MD2
MD2
MD2
Vss
2
A1
Vss
Vss
Vss
Vss
Vss
Vss
3
C2
P80/(IRQ0)/
3
EDREQ2*
P80/(IRQ0)/
3
EDREQ2*
P80/(IRQ0)/
3
EDREQ2*
P80/(IRQ0)/
3
EDREQ2*
P80/(IRQ0)/
3
EDREQ2*
NC
Mode 7
*4
Mode 2
*4
4
B2
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
5
C1
A0
A0
PC0/A0
PC0/A0
PC0
A0
6
C3
A1
A1
PC1/A1
PC1/A1
PC1
A1
7
D2
A2
A2
PC2/A2
PC2/A2
PC2
A2
8
D3
A3
A3
PC3/A3
PC3/A3
PC3
A3
9
D1
A4
A4
PC4/A4
PC4/A4
PC4
A4
10
E2
Vss
Vss
Vss
Vss
Vss
Vss
11
E3
A5
A5
PC5/A5
PC5/A5
PC5
A5
12
F2
A6
A6
PC6/A6
PC6/A6
PC6
A6
13
E1
A7
A7
PC7/A7
PC7/A7
PC7
A7
14
E4
A8
A8
PB0/A8
PB0/A8
PB0
A8
15
F3
A9
A9
PB1/A9
PB1/A9
PB1
A9
16
G2
A10
A10
PB2/A10
PB2/A10
PB2
A10
17
F1
A11
A11
PB3/A11
PB3/A11
PB3
A11
18
F4
Vss
Vss
Vss
Vss
Vss
Vss
19
G4
A12
A12
PB4/A12
PB4/A12
PB4
A12
20
H4
A13
A13
PB5/A13
PB5/A13
PB5
A13
21
G1
A14
A14
PB6/A14
PB6/A14
PB6
A14
22
H2
A15
A15
PB7/A15
PB7/A15
PB7
A15
23
G3
A16
A16
PA0/A16
PA0/A16
PA0
A16
24
J4
A17
A17
PA1/A17
PA1/A17
PA1
A17
25
H1
Vss
Vss
Vss
Vss
Vss
Vss
26
J2
A18
A18
PA2/A18
PA2/A18
PA2
A18
27
H3
A19
A19
PA3/A19
PA3/A19
PA3
NC
Rev.7.00 Mar. 18, 2009 page 12 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Pin Name
LQFP- LGA144
145
Mode 1*4
Mode 2*
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
28
K4
5
A20/IRQ4*
A20/IRQ4*
PA4/A20/IRQ4
PA4/A20/IRQ4
PA4/IRQ4
NC
29
J1
PA5/A21/IRQ5
PA5/A21/IRQ5
PA5/A21/IRQ5
PA5/A21/IRQ5
PA5/IRQ5
NC
30
K2
PA6/A22/IRQ6
PA6/A22/IRQ6
PA6/A22/IRQ6
PA6/A22/IRQ6
PA6/IRQ6
NC
31
J3
PA7/A23/IRQ7
PA7/A23/IRQ7
PA7/A23/IRQ7
PA7/A23/IRQ7
PA7/IRQ7
NC
32
K1
EMLE
EMLE
EMLE
EMLE
EMLE
33
L2
P81/(IRQ1)/
TXD3/
EDREQ3*3
P81/(IRQ1)/
TXD3/
3
EDREQ3*
P81/(IRQ1)/
TXD3/
3
EDREQ3*
P81/(IRQ1)/
TXD3/
3
EDREQ3*
P81/(IRQ1)/
TXD3/
3
EDREQ3*
NC
34
K3
P82/(IRQ2)/
3
ETEND2*
P82/(IRQ2)/
3
ETEND2*
P82/(IRQ2)/
3
ETEND2*
P82/(IRQ2)/
3
ETEND2*
P82/(IRQ2)
NC
35
L1
PH0/CS4/
1
RAS4/WE*
PH0/CS4/
RAS4/WE*1
PH0/CS4/
RAS4/WE*1
PH0/CS4/
RAS4/WE*1
PH0
NC
36
M1
PH1/CS5/RAS5/
1
SDRAMφ*
PH1/CS5/RAS5/
1
SDRAMφ*
PH1/CS5/RAS5/
1
SDRAMφ*
PH1/CS5/RAS5/
1
SDRAMφ*
PH1/SDRAMφ
NC
37
N2
PH2/CS6/(IRQ6) PH2/CS6/(IRQ6)
PH2/CS6/(IRQ6)
PH2/CS6/(IRQ6) PH2/(IRQ6)
NC
38
M2
PH3/CS7/(IRQ7)/ PH3/CS7/(IRQ7)/ PH3/CS7/(IRQ7)/ PH3/CS7/(IRQ7)/ PH3/(IRQ7)
1
1
1
1
OE/CKE*
OE/CKE*
OE/CKE*
OE/CKE*
NC
39
M3
WDTOVF
WDTOVF
WDTOVF
WDTOVF
WDTOVF
NC
40
N1
NMI
NMI
NMI
NMI
NMI
Vcc
Mode 7
*2
4
5
VCL
*2
VCL
*2
VCL
*2
VCL
*2
VCL*2
41
N3
VCL
42
L3
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
NC
43
M4
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
NC
44
L4
P12/PO10/
TIOCC0/TCLKA
P12/PO10/
TIOCC0/TCLKA
P12/PO10/
TIOCC0/TCLKA
P12/PO10/
TIOCC0/TCLKA
P12/PO10/
TIOCC0/TCLKA
NC
45
N4
P13/PO11/
TIOCD0/TCLKB
P13/PO11/
TIOCD0/TCLKB
P13/PO11/
TIOCD0/TCLKB
P13/PO11/
TIOCD0/TCLKB
P13/PO11/
TIOCD0/TCLKB
NC
46
M5
P14/PO12/
TIOCA1
P14/PO12/
TIOCA1
P14/PO12/
TIOCA1
P14/PO12/
TIOCA1
P14/PO12/
TIOCA1
NC
47
L5
P15/PO13/
TIOCB1/TCLKC
P15/PO13
TIOCB1/TCLKC
P15/PO13/
TIOCB1/TCLKC
P15/PO13/
TIOCB1/TCLKC
P15/PO13/
TIOCB1/TCLKC
NC
48
M6
P16/PO14/
TIOCA2/
EDRAK2*3
P16/PO14/
TIOCA2/
EDRAK2*3
P16/PO14/
TIOCA2/
EDRAK2*3
P16/PO14/
TIOCA2/
EDRAK2*3
P16/PO14/
TIOCA2/
NC
Rev.7.00 Mar. 18, 2009 page 13 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Pin Name
LQFP- LGA144
145
49
N5
Mode 7
Mode 1*4
Mode 2*
4
P17/PO15/
P17/PO15/
TIOCB2/TCLKD/ TIOCB2/TCLKD/
EDRAK3*3
EDRAK3*3
Mode 4
EXPE = 1
P17/PO15/
TIOCB2/TCLKD/
EDRAK3*3
P17/PO15/
P17/PO15/
TIOCB2/TCLKD/ TIOCB2/TCLKD
EDRAK3*3
EXPE = 0
Flash Memory
Programmer
Mode
NC
50
K5
Vss
Vss
Vss
Vss
Vss
Vss
51
L6
P20/PO0/
TIOCA3/(IRQ8)
P20/PO0/
TIOCA3/(IRQ8)
P20/PO0/
TIOCA3/(IRQ8)
P20/PO0/
TIOCA3/(IRQ8)
P20/PO0/
TIOCA3/(IRQ8)
NC
52
M7
P21/PO1/
TIOCB3/(IRQ9)
P21/PO1/
TIOCB3/(IRQ9)
P21/PO1/
TIOCB3/(IRQ9)
P21/PO1/
TIOCB3/(IRQ9)
P21/PO1/
TIOCB3/(IRQ9)
NC
53
N6
P22/PO2/
P22/PO2/
P22/PO2/
P22/PO2/
P22/PO2/
OE
TIOCC3/(IRQ10) TIOCC3/(IRQ10) TIOCC3/(IRQ10) TIOCC3/(IRQ10) TIOCC3/(IRQ10)
54
K6
P23/PO3/
TIOCD3/TxD4/
(IRQ11)
P23/PO3/
TIOCD3/TxD4/
(IRQ11)
P23/PO3/
TIOCD3/TxD4/
(IRQ11)
P23/PO3/
TIOCD3/TxD4/
(IRQ11)
P23/PO3/
TIOCD3/TxD4/
(IRQ11)
CE
55
K7
P24/PO4/
TIOCA4/RxD4/
(IRQ12)
P24/PO4/
TIOCA4/RxD4/
(IRQ12)
P24/PO4/
TIOCA4/RxD4/
(IRQ12)
P24/PO4/
TIOCA4/RxD4/
(IRQ12)
P24/PO4/
TIOCA4/RxD4/
(IRQ12)
WE
56
K8
P25/PO5/
TIOCB4/
(IRQ13)
P25/PO5/
TIOCB4/
(IRQ13)
P25/PO5/
TIOCB4/
(IRQ13)
P25/PO5/
TIOCB4/
(IRQ13)
P25/PO5/
TIOCB4/
(IRQ13)
Vss
57
N7
P26/PO6/
P26/PO6/
TIOCA5/(IRQ14) TIOCA5/(IRQ14)
P26/PO6/
TIOCA5/(IRQ14)
P26/PO6/
P26/PO6/
TIOCA5/(IRQ14) TIOCA5/(IRQ14)
NC
58
M8
P27/PO7/
P27/PO7/
TIOCB5/(IRQ15) TIOCB5/(IRQ15)
P27/PO7/
TIOCB5/(IRQ15)
P27/PO7/
P27/PO7/
TIOCB5/(IRQ15) TIOCB5/(IRQ15)
NC
59
L7
P83/(IRQ3)/
RxD3/
3
ETEND3*
P83/(IRQ3)/
RxD3/
3
ETEND3*
P83/(IRQ3)/
RxD3/
3
ETEND3*
P83/(IRQ3)/
RxD3/
3
ETEND3*
P83/(IRQ3)/
RxD3
NC
60
K9
P84/(IRQ4)/
EDACK2
P84/(IRQ4)/
EDACK2
P84/(IRQ4)/
EDACK2
P84/(IRQ4)/
EDACK2
P84/(IRQ4)
NC
61
N8
P85/(IRQ5)/
SCK3/
EDACK3*3
P85/(IRQ5)/
SCK3/
EDACK3*3
P85/(IRQ5)/
SCK3/
EDACK3*3
P85/(IRQ5)/
SCK3/
EDACK3*3
P85/(IRQ5)/
SCK3
NC
62
M9
DCTL
DCTL
DCTL
DCTL
DCTL
NC
63
L8
D0
PE0/D0
PE0/D0
PE0/D0
PE0
NC
64
K10
D1
PE1/D1
PE1/D1
PE1/D1
PE1
NC
65
N9
D2
PE2/D2
PE2/D2
PE2/D2
PE2
NC
66
M10
D3
PE3/D3
PE3/D3
PE3/D3
PE3
NC
67
L9
D4
PE4/D4
PE4/D4
PE4/D4
PE4
NC
68
N10
D5
PE5/D5
PE5/D5
PE5/D5
PE5
NC
Rev.7.00 Mar. 18, 2009 page 14 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Pin Name
LQFP- LGA144
145
Mode 1*4
Mode 2*
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
69
D6
PE6/D6
PE6/D6
PE6/D6
PE6
NC
M11
Mode 7
4
70
L10
Vss
Vss
Vss
Vss
Vss
Vss
71
N11
D7
PE7/D7
PE7/D7
PE7/D7
PE7
NC
72
N12
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
73
M13
D8
D8
D8
D8
PD0
I/O0
74
N13
D9
D9
D9
D9
PD1
I/O1
75
L12
D10
D10
D10
D10
PD2
I/O2
76
M12
D11
D11
D11
D11
PD3
I/O3
77
L11
D12
D12
D12
D12
PD4
I/O4
78
L13
D13
D13
D13
D13
PD5
I/O5
79
K12
D14
D14
D14
D14
PD6
I/O6
80
K11
D15
D15
D15
D15
PD7
I/O7
81
J12
P60/TMRI0/
DREQ0/IRQ8
P60/TMRI0/
DREQ0/IRQ8
P60/TMRI0/
DREQ0/IRQ8
P60/TMRI0/
DREQ0/IRQ8
P60/TMRI0/
DREQ0/IRQ8
NC
82
K13
P61/TMRI1/
DREQ1/IRQ9
P61/TMRI1/
DREQ1/IRQ9
P61/TMRI1/
DREQ1/IRQ9
P61/TMRI1/
DREQ1/IRQ9
P61/TMRI1/
DREQ1/IRQ9
NC
83
J10
P62/TMCI0/
TEND0/IRQ10
P62/TMCI0/
TEND0/IRQ10
P62/TMCI0/
TEND0/IRQ10
P62/TMCI0/
TEND0/IRQ10
P62/TMCI0/
TEND0/IRQ10
NC
84
J11
PF0/WAIT
PF0/WAIT
PF0/WAIT
PF0/WAIT
PF0
NC
85
H12
PF1/UCAS/
IRQ14/DQMU*1
PF1/UCAS/
IRQ14/DQMU*1
PF1/UCAS/
IRQ14/DQMU*1
PF1/UCAS/
IRQ14/DQMU*1
PF1/IRQ14
NC
86
H10
PF2/LCAS/
1
IRQ15/DQML*
PF2/LCAS/
1
IRQ15/DQML*
PF2/LCAS/
1
IRQ15/DQML *
PF2/LCAS/
1
IRQ15/DQML*
PF2/IRQ15
NC
87
J13
PF3/LWR
PF3/LWR
PF3/LWR
PF3/LWR
PF3
NC
88
H11
HWR
HWR
HWR
HWR
PF4
NC
89
G12
RD
RD
RD
RD
PF5
NC
90
G10
PF6/AS
PF6/AS
PF6/AS
PF6/AS
PF6
NC
91
H13
PLLVcc
PLLVcc
PLLVcc
PLLVcc
PLLVcc
Vcc
92
F12
RES
RES
RES
RES
RES
RES
93
G13
PLLVss
PLLVss
PLLVss
PLLVss
PLLVss
Vss
94
F10
PF7/φ
PF7/φ
PF7/φ
PF7/φ
PF7/φ
NC
95
E10
Vss
Vss
Vss
Vss
Vss
Vss
96
F13
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
Rev.7.00 Mar. 18, 2009 page 15 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Pin Name
LQFP- LGA144
145
Mode 1*4
Mode 2*
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
97
E13
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
98
F11
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
99
D12
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
100
G11
NC
NC
NC
NC
NC
NC
101
E12
NC
NC
NC
NC
NC
NC
102
E11
Vss
Vss
Vss
Vss
Vss
Vss
103
D13
STBY
STBY
STBY
STBY
STBY
Vcc
104
D10
P63/TMCI1/
TEND1/IRQ11
P63/TMCI1/
TEND1/IRQ11
P63/TMCI1/
TEND1/IRQ11
P63/TMCI1/
TEND1/IRQ11
P63/TMCI1/
TEND1/IRQ11
NC
105
C12
P64/TMO0/
DACK0/IRQ12
P64/TMO0/
DACK0/IRQ12
P64/TMO0/
DACK0/IRQ12
P64/TMO0/
DACK0/IRQ12
P64/TMO0/
DACK0/IRQ12
NC
106
C13
P65/TMO1/
DACK1/IRQ13
P65/TMO1/
DACK1/IRQ13
P65/TMO1/
DACK1/IRQ13
P65/TMO1/
DACK1/IRQ13
P65/TMO1/
DACK1/IRQ13
NC
107
D11
PG0/CS0
PG0/CS0
PG0/CS0
PG0/CS0
PG0
NC
108
B13
PG1/CS1
PG1/CS1
PG1/CS1
PG1/CS1
PG1
NC
109
A12
PG2/CS2/
RAS2/RAS
PG2/CS2/
RAS2/RAS
PG2/CS2/
RAS2/RAS
PG2/CS2/
RAS2/RAS
PG2
NC
110
A13
PG3/CS3/
RAS3/CAS*1
PG3/CS3/
RAS3/CAS*1
PG3/CS3/
RAS3/CAS*1
PG3/CS3/
RAS3/CAS*1
PG3
NC
111
B11
AVcc
AVcc
AVcc
AVcc
AVcc
Vcc
Mode 7
4
112
B12
Vref
Vref
Vref
Vref
Vref
NC
113
A11
P40/AN0
P40/AN0
P40/AN0
P40/AN0
P40/AN0
NC
114
C11
P41/AN1
P41/AN1
P41/AN1
P41/AN1
P41/AN1
NC
115
B10
P42/AN2
P42/AN2
P42/AN2
P42/AN2
P42/AN2
NC
116
C10
P43/AN3
P43/AN3
P43/AN3
P43/AN3
P43/AN3
NC
117
A10
P44/AN4
P44/AN4
P44/AN4
P44/AN4
P44/AN4
NC
118
B9
P45/AN5
P45/AN5
P45/AN5
P45/AN5
P45/AN5
NC
119
C9
P46/AN6/DA0*3
P46/AN6/DA0*3
P46/AN6/DA0*3
P46/AN6/DA0*3
P46/AN6/DA0*3
NC
120
B8
P47/AN7/DA1*3
P47/AN7/DA1*3
P47/AN7/DA1*3
P47/AN7/DA1*3
P47/AN7/DA1*3
NC
121
A9
P90/AN8
P90/AN8
P90/AN8
P90/AN8
P90/AN8
NC
122
D9
P91/AN9
P91/AN9
P91/AN9
P91/AN9
P91/AN9
NC
123
C8
P92/AN10
P92/AN10
P92/AN10
P92/AN10
P92/AN10
NC
124
B7
P93/AN11
P93/AN11
P93/AN11
P93/AN11
P93/AN11
NC
Rev.7.00 Mar. 18, 2009 page 16 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Pin Name
LQFP- LGA144
145
Mode 1*4
Mode 2*
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
125
P94/AN12/DA2
P94/AN12/DA2
P94/AN12/DA2
P94/AN12/DA2
P94/AN12/DA2
NC
A8
Mode 7
4
126
D8
P95/AN13/DA3
P95/AN13/DA3
P95/AN13/DA3
P95/AN13/DA3
P95/AN13/DA3
NC
127
D7
P96/AN14/
3
DA4*
P96/AN14/
3
DA4*
P96/AN14/
3
DA4*
P96/AN14/
3
DA4*
P96/AN14/
3
DA4*
NC
128
D6
P97/AN15/
3
DA5*
P97/AN15/
DA5*3
P97/AN15/
DA5*3
P97/AN15/
DA5*3
P97/AN15/
DA5*3
NC
129
A7
AVss
AVss
AVss
AVss
AVss
Vss
130
B6
PG4/BREQO
PG4/BREQO
PG4/BREQO
PG4/BREQO
PG4
NC
131
C7
PG5/BACK
PG5/BACK
PG5/BACK
PG5/BACK
PG5
NC
132
D5
PG6/BREQ
PG6/BREQ
PG6/BREQ
PG6/BREQ
PG6
NC
133
A6
P50/TxD2/IRQ0
P50/TxD2/IRQ0
P50/TxD2/IRQ0
P50/TxD2/IRQ0
P50/TxD2/IRQ0
Vss
134
B5
P51/RxD2/IRQ1
P51/RxD2/IRQ1
P51/RxD2/IRQ1
P51/RxD2/IRQ1
P51/RxD2/IRQ1
Vss
135
C6
P52/SCK2/IRQ2
P52/SCK2/IRQ2
P52/SCK2/IRQ2
P52/SCK2/IRQ2
P52/SCK2/IRQ2
Vcc
136
D4
P53/ADTRG/
IRQ3
P53/ADTRG/
IRQ3
P53/ADTRG/
IRQ3
P53/ADTRG/
IRQ3
P53/ADTRG/
IRQ3
NC
137
A5
P35/SCK1/SCL0/ P35/SCK1/SCL0/ P35/SCK1/SCL0/ P35/SCK1/SCL0/ P35/SCK1/SCL0
1
1
1
1
(OE)/(CKE)*
(OE)/(CKE)*
(OE)/(CKE)*
(OE)/(CKE)*
NC
138
B4
P34/SCK0/
SCK4/SDA0
P34/SCK0/
SCK4/SDA0
P34/SCK0/
SCK4/SDA0
P34/SCK0/
SCK4/SDA0
P34/SCK0/
SCK4/SDA0
NC
139
C5
P33/RxD1/SCL1
P33/RxD1/SCL1
P33/RxD1/SCL1
P33/RxD1/SCL1
P33/RxD1/SCL1
NC
140
A4
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
Vcc
141
B3
P31/TxD1
P31/TxD1
P31/TxD1
P31/TxD1
P31/TxD1
NC
142
C4
P30/TxD0/IrTxD
P30/TxD0/IrTxD
P30/TxD0/IrTxD
P30/TxD0/IrTxD
P30/TxD0/IrTxD
NC
143
A3
MD0
MD0
MD0
MD0
MD0
Vss
144
A2
MD1
MD1
MD1
MD1
MD1
Vss
145
E5
NC
NC
NC
NC
NC
NC
Notes: 1. Not available for the H8S/2378 Group.
2. These pins are Vcc pins in the H8S/2377, H8S/2377R, H8S/2376, H8S/2375,
H8S/2375R, H8S/2373, and H8S/2373R.
3. Not available for the H8S/2375 and H8S/2375R.
4. Only modes 1 and 2 may be used on ROM-less version.
5. This port is assigned as A20 in modes 1 and 2.
Rev.7.00 Mar. 18, 2009 page 17 of 1136
REJ09B0109-0700
Section 1 Overview
1.3.3
Table 1.2
Pin Functions
Pin Functions
Pin No.
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
H8S/2375
0.18μm
H8S/2373
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
Type
Symbol
Power
supply
VCC
4, 41, 72,
98, 99
B2, N12,
F11, D12
4, 41, 72,
98, 99
VSS
2, 10, 18,
25, 50, 70,
95, 102
A1, E2,
F4, H1,
K5, L10,
E10, E11
PLLVCC
91
PLLVSS
VCL*3
Input
For connection to
the power supply.
VCC pins should be
connected to the
system power
supply.
2, 10, 18, 2, 10, 18,
25, 50, 70, 25, 50, 70,
95, 102
95, 102
Input
For connection to
ground. VSS pins
should be
connected to the
system power
supply (0 V).
H13
91
91
Input
Power supply pin
for the on-chip PLL
oscillator.
93
G13
93
93
Input
Ground pin for the
on-chip PLL
oscillator.
41
N3
⎯
⎯
Output This pin must not
be connected to the
system power
supply and should
be connected VSS
pin via 0.1-μF
(recommended
value) capacitor
(place it close to
pin).
Rev.7.00 Mar. 18, 2009 page 18 of 1136
REJ09B0109-0700
4, 41, 72,
98, 99
Function
Section 1 Overview
Pin No.
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
Type
Symbol
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
Clock
XTAL
96
F13
96
96
Input
For connection to a
crystal oscillator.
See section 23,
Clock Pulse
Generator, for
typical connection
diagrams for a
crystal resonator
and external clock
input.
EXTAL
97
E13
97
97
Input
For connection to a
crystal oscillator.
The EXTAL pin can
also input an
external clock. See
section 23, Clock
Pulse Generator,
for typical
connection
diagrams for a
crystal resonator
and external clock
input.
φ
94
F10
94
94
Output Supplies the system
clock to external
devices.
M1
36
36
Output When a synchronous DRAM is
connected, this pin
is connected to the
CLK pin of the
synchronous
DRAM. For details,
refer to section 6,
Bus Controller
(BSC).
SDRAMφ*1 36
Function
Rev.7.00 Mar. 18, 2009 page 19 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Type
Symbol
Operating MD2
mode
MD1
control
MD0
DCTL*1
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
1, 144,
143
B1, A2,
A3
1, 144,
143
1, 144,
143
Input
These pins set the
operating mode.
These pins should
not be changed
while the MCU is
operating.
62
M9
62
62
Input
When this pin is
driven high for the
H8S/2378R Group,
SDRAMφ dedicated
to the synchronous
DRAM is output.
Function
When not using the
synchronous DRAM
interface or for the
H8S/2378 Group,
drive this pin low.
The level of this pin
must not be
changed during
operation.
System
control
RES
92
F12
92
92
Input
Reset pin. When
this pin is driven
low, the chip is
reset.
STBY
103
D13
103
103
Input
When this pin is
driven low, a
transition is made to
hardware standby
mode.
Rev.7.00 Mar. 18, 2009 page 20 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Type
Symbol
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
System
control
EMLE
32
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
K1
32
32
Input
Function
On-chip Emulator
Enable Pin
When the on-chip
emulator in the
H8S/2378 0.18μm
F-ZTAT Group,
H8S/2377,
H8S/2377R, or
H8S/2378R 0.18μm
F-ZTAT Group is
used, this pin
should be fixed
high. At this time,
pins P53, PG4 to
PG6, and WDTOVF
are exclusively for
the on-chip
emulator, therefore,
the corresponding
pin functions of
those pins are not
available.
When the on-chip
emulator is not
used or the
H8S/2375,
H8S/2375R,
H8S/2373, or
H8S/2373R is used,
this pin should be
fixed low.
For details, refer to
E10A Emulator
User’s Manual.
Rev.7.00 Mar. 18, 2009 page 21 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
Function
Type
Symbol
Address
bus
A23 to A0 31 to 26,
24 to 19,
17 to 11,
9 to 5
J3, K2, J1,
K4, H3, J2,
J4, G3, H2,
G1, H4, G4,
F1, G2, F3,
E4, E1, F2,
E3, D1, D3,
D2, C3, C1
31 to 26,
24 to 19,
17 to 11,
9 to 5
31 to 26,
24 to 19,
17 to 11,
9 to 5
Output These pins output
an address.
Data bus
D15 to D0 80 to 73, 71,
69 to 63
K11, K12,
L13, L11,
M12, L12,
N13, M13,
N11, M11,
N10, L9, M10,
N9, K10, L8
80 to 73,
71,
69 to 63
80 to 73,
71,
69 to 63
Input/ These pins
output constitute a
bidirectional data
bus.
Bus
control
CS7 to
CS0
38 to 35,
110 to 107
M2, N2, M1,
L1, A13, A12,
B13, D11
38 to 35, 38 to 35,
110 to 107 110 to 107
Output Signals that select
division areas 7 to 0
in the external
address space
AS
90
G10
90
90
Output When this pin is
low, it indicates that
address output on
the address bus is
valid.
RD
89
G12
89
89
Output When this pin is
low, it indicates that
the external
address space is
being read.
Rev.7.00 Mar. 18, 2009 page 22 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Type
Symbol
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
Bus
control
HWR
88
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
H11
88
88
Function
Output Strobe signal
indicating that
external address
space is to be
written, and the
upper half (D15 to
D8) of the data bus
is enabled.
Write enable signal
for accessing the
DRAM space.
LWR
87
J13
87
87
Output Strobe signal
indicating that
external address
space is to be
written, and the
lower half (D7 to
D0) of the data bus
is enabled.
BREQ
132
D5
132
132
Input
BREQO
130
B6
130
130
Output External bus
request signal when
the internal bus
master accesses
the external space
in external bus
release state.
BACK
131
C7
131
131
Output Indicates the bus is
released to the
external bus
master.
The external bus
master requests the
bus to this LSI.
Rev.7.00 Mar. 18, 2009 page 23 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Type
Symbol
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
Bus
control
UCAS
85
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
H12
85
85
Function
Output Upper column
address strobe
signal for accessing
the 16-bit DRAM
space.
Column address
strobe signal for
accessing the 8-bit
DRAM space.
LCAS
86
H10
86
86
Output Lower column
address strobe
signal for accessing
the 16-bit DRAM
space.
DQMU*1
85
H12
85
85
Output Upper data mask
enable signal for
16-bit synchronous
DRAM for
accessing the 16-bit
synchronous DRAM
space.
Data mask enable
signal for accessing
the 8-bit synchronous DRAM space.
DQML*1
86
H10
Rev.7.00 Mar. 18, 2009 page 24 of 1136
REJ09B0109-0700
86
86
Output Lower-data mask
enable signal for
accessing the 16-bit
synchronous DRAM
interface space.
Section 1 Overview
Pin No.
Type
Symbol
Bus
control
RAS/
RAS2
RAS3 to
RAS5
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
109, 110,
35, 36
A12,
A13,
L1,
M1
109, 110,
35, 36
109, 110,
35, 36
Function
Output Row address strobe
signal for the
synchronous DRAM
interface.
RAS signal is a row
address strobe
signal when areas 2
to 5 are set to the
continuous DRAM
space.
RAS*1
109
A12
109
109
Output Row address strobe
signal for the
synchronous DRAM
of the synchronous
DRAM interface.
CAS*1
110
A13
110
110
Output Column address
strobe signal for the
synchronous DRAM
of the synchronous
DRAM interface.
WE*1
35
L1
35
35
Output Write enable signal
for the synchronous
DRAM of the
synchronous DRAM
interface.
WAIT
84
J11
84
84
Input
Requests insertion
of a wait state in the
bus cycle when
accessing external
3-state address
space.
Rev.7.00 Mar. 18, 2009 page 25 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Type
Symbol
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
Bus
control
OE
(OE)
38,
137
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
M2,
A5
38,
137
38,
137
Function
Output Output enable
signal for DRAM
interface space.
The output pins of
OE and (OE) are
selected by the port
function control
register 2 (PFCR2)
of port 3.
CKE*1
(CKE)*1
38,
137
M2,
A5
38,
137
38,
137
Output Clock enable signal
of the synchronous
DRAM interface
space.
The output pins of
CKE and (CKE) are
selected by the port
function control
register 2 (PFCR2)
of port 3.
Interrupt
signals
NMI
40
N1
40
40
IRQ15 to
IRQ0
86, 85,
106 to 104,
83 to 81,
31 to 28,
136 to 133
H10, H12,
C13, C12,
D10, J10,
K13, J12,
J3, K2, J1,
K4, D4, C6,
B5, A6
86, 85,
106 to 104,
83 to 81,
31 to 28,
136 to 133
Input
86, 85,
106 to 104,
83 to 81,
31 to 28,
136 to 133
M8, N7, K8,
K7, K6, N6,
M7, L6, M2,
N2, N8, K9,
L7, K3, L2, C2
58 to 51,
38, 37,
61 to 59,
34, 33, 3
58 to 51,
38, 37,
61 to 59,
34, 33, 3
(IRQ15) to 58 to 51,
(IRQ0)
38, 37,
61 to 59,
34, 33, 3
Rev.7.00 Mar. 18, 2009 page 26 of 1136
REJ09B0109-0700
Input
Nonmaskable
interrupt request
pin. Fix high when
not used.
These pins request
a maskable
interrupt.
The input pins of
IRQn and (IRQn)
are selected by the
IRQ pin select
register (ITSR) of
the interrupt
controller.
(n = 0 to 15)
Section 1 Overview
Pin No.
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
Type
Symbol
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
DMA
controller
(DMAC)
DREQ1
DREQ0
82,
81
K13,
J12
82,
81
82,
81
Input
TEND1
TEND0
104,
83
D10,
J10
104,
83
104,
83
Output These signals
indicate the end of
DMAC data
transfer.
DACK1
DACK0
106,
105
C13,
C12
106,
105
106,
105
Output DMAC single
address transfer
acknowledge
signals.
EXDMA
EDREQ3, 33,
controller EDREQ2 3
(EXDMAC)
*2
ETEND3, 59,
ETEND2 34
L2,
C2
33,
3
⎯
Input
L7,
K3
59,
34
⎯
Output These signals
indicate the end of
EXDMAC data
transfer.
EDACK3, 61,
EDACK2 60
N8,
K9
61,
60
⎯
Output EXDMAC single
address transfer
acknowledge
signals.
EDRAK3, 49,
EDRAK2 48
N5,
M6
49,
48
⎯
Output These signals notify
an external device
of acceptance and
start of execution of
a DMA transfer
request.
Function
These signals
request DMAC
activation.
These signals
request EXDMAC
activation.
Rev.7.00 Mar. 18, 2009 page 27 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Type
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
44,
45,
47,
49
L4,
N4,
L5,
N5
44,
45,
47,
49
44,
45,
47,
49
Input
TIOCA0
TIOCB0
TIOCC0
TIOCD0
42,
43,
44,
45
L3,
M4,
L4,
N4
42,
43,
44,
45
42,
43,
44,
45
Input/ TGRA_0 to
output TGRD_0 input
capture input/output
compare output/
PWM output pins.
TIOCA1
TIOCB1
46,
47
M5,
L5
46,
47
46,
47
Input/ TGRA_1 and
output TGRB_1 input
capture input/output
compare output/
PWM output pins.
TIOCA2
TIOCB2
48,
49
M6,
N5
48,
49
48,
49
Input/ TGRA_2 and
output TGRB_2 input
capture input/output
compare output/
PWM output pins.
TIOCA3
TIOCB3
TIOCC3
TIOCD3
51,
52,
53,
54
L6,
M7,
N6,
K6
51,
52,
53,
54
51,
52,
53,
54
Input/ TGRA_3 to
output TGRD_3 input
capture input/output
compare output/
PWM output pins.
TIOCA4
TIOCB4
55,
56
K7,
K8
55,
56
55,
56
Input/ TGRA_4 and
output TGRB_4 input
capture input/output
compare output/
PWM output pins.
TIOCA5,
TIOCB5
57,
58
N7,
M8
57,
58
57,
58
Input/ TGRA_5 and
output TGRB_5 input
capture input/output
compare output/
PWM output pins.
Symbol
16-bit timer TCLKA
pulse
TCLKB
unit (TPU) TCLKC
TCLKD
Rev.7.00 Mar. 18, 2009 page 28 of 1136
REJ09B0109-0700
Function
External clock input
pins of the timer.
Section 1 Overview
Pin No.
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
Type
Symbol
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
Programmable
pulse
generator
(PPG)
PO15 to
PO0
49 to 42,
58 to 51
N5, M6, L5,
M5, N4, L4,
M4, L3, M8,
N7, K8, K7,
K6, N6, M7,
L6
49 to 42,
58 to 51
49 to 42,
58 to 51
Output Pulse output pins.
8-bit timer TMO0
(TMR)
TMO1
105,
106
C12,
C13
105,
106
105,
106
Output Waveform output
pins with output
compare function.
TMCI0
TMCI1
83,
104
J10,
D10
83,
104
83,
104
Input
External event input
pins.
TMRI0
TMRI1
82,
81
K13,
J12
82,
81
82,
81
Input
Counter reset input
pins.
M3
39
39
Output Counter overflow
signal output pin in
watchdog timer
mode.
Watchdog WDTOVF 39
timer
(WDT)
Serial
communication
interface
(SCI)/
smart card
interface
(SCI_0
with IrDA
function)
Function
TxD4
TxD3
TxD2
TxD1
TxD0/
IrTxD
54,
33,
133,
141,
142
K6,
L2,
A6,
B3,
C4
54,
33,
133,
141,
142
54,
33,
133,
141,
142
Output Data output pins.
RxD4
RxD3
RxD2
RxD1
RxD0/
IrRxD
55,
59,
134,
139,
140
K7,
L7,
B5,
C5,
A4
55,
59,
134,
139,
140
55,
59,
134,
139,
140
Input
SCK4
SCK3
SCK2
SCK1
SCK0
138,
61,
135,
137,
138
B4,
N8,
C6,
A5,
B4
138,
61,
135,
137,
138
138,
61,
135,
137,
138
Input/ Clock input/output
output pins.
Data input pins.
Rev.7.00 Mar. 18, 2009 page 29 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
Type
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
139,
137
C5,
A5
139,
137
139,
137
Input/ I2C clock input/
output output pins.
140,
138
A4,
B4
140,
138
140,
138
Input/ I2C data input/
output output pins.
AN15 to
AN0
128 to 113
D6, D7,
D8, A8,
B7, C8,
D9, A9,
B8, C9, B9,
A10, C10,
B10, C11,
A11
128 to 113 128 to 113
Input
Analog input pins
for the A/D
converter.
ADTRG
136
D4
136
136
Input
Pin for input of an
external trigger to
start A/D
conversion.
Output Analog output pins
for the D/A
converter.
Symbol
I2C bus
SCL1
interface 2 SCL0
(IIC2)
SDA1
SDA0
A/D
converter
D/A
converter
DA5
128
D6
⎯
⎯
DA4
127
D7
⎯
⎯
DA3
126
D8
126
126
DA2
125
A8
125
125
DA1
120
B8
⎯
⎯
DA0
119
C9
⎯
⎯
Rev.7.00 Mar. 18, 2009 page 30 of 1136
REJ09B0109-0700
Function
Section 1 Overview
Pin No.
Type
Symbol
AVCC
A/D
converter,
D/A
converter
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
111
B11
111
111
Input
Function
The analog powersupply pin for the
A/D converter and
D/A converter.
When the A/D
converter and D/A
converter are not
used, this pin
should be
connected to the
system power
supply (+3 V).
AVSS
129
A7
129
129
Input
The ground pin for
the A/D converter
and D/A converter.
This pin should be
connected to the
system power
supply (0 V).
Vref
112
B12
112
112
Input
The reference
voltage input pin for
the A/D converter
and D/A converter.
When the A/D
converter and D/A
converter are not
used, this pin
should be
connected to the
system power
supply (+3 V).
Rev.7.00 Mar. 18, 2009 page 31 of 1136
REJ09B0109-0700
Section 1 Overview
Pin No.
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
Function
Type
Symbol
I/O ports
P17 to
P10
49 to 42
N5, M6, L5,
M5, N4, L4,
M4, L3
49 to 42
49 to 42
Input/ Eight-bit input/
output output pins.
P27 to
P20
58 to 51
M8, N7, K8,
K7, K6, N6,
M7, L6
58 to 51
58 to 51
Input/ Eight-bit input/
output output pins.
P35 to
P30
137 to 142
A5, B4, C5,
A4, B3, C4
137 to
142
137 to 142
Input/ Six-bit input/output
output pins.
P47 to
P40
120 to 113
B8, C9, B9,
A10, C10,
B10, C11,
A11
120 to
113
120 to 113
Input
P53 to
P50
136 to 133
D4, C6, B5,
A6
136 to
133
136 to 133
Input/ Four-bit input/output
output pins.
P65 to
P60
106 to 104,
83 to 81
C13, C12,
D10, J10,
K13, J12
106 to
104,
83 to 81
106 to 104, Input/ Six-bit input/output
83 to 81
output pins.
P85 to
P80
61 to 59,
34, 33, 3
N8, K9, L7,
K3, L2, C2
61 to 59,
34, 33, 3
61 to 59,
34, 33, 3
P97 to
P90
128 to 121
D6, D7, D8,
A8, B7, C8,
D9, A9
128 to 121 128 to 121
Input
PA7 to
PA0
31 to 26,
24, 23
J3, K2, J1,
K4, H3, J2,
J4, G3
31 to 26,
24, 23
31 to 26,
24, 23
Input/ Eight-bit input/
output output pins.
PB7 to
PB0
22 to 19,
17 to 14
H2, G1, H4,
G4, F1, G2,
F3, E4
22 to 19,
17 to 14
22 to 19,
17 to 14
Input/ Eight-bit input/
output output pins.
PC7 to
PC0
13 to 11,
9 to 5
E1, F2, E3,
D1, D3, D2,
C3, C1
13 to 11,
9 to 5
13 to 11,
9 to 5
Input/ Eight-bit input/
output output pins.
Rev.7.00 Mar. 18, 2009 page 32 of 1136
REJ09B0109-0700
Eight-bit input pins.
Input/ Six-bit input/output
output pins.
Eight-bit input pins.
Section 1 Overview
Pin No.
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2375
H8S/2378R
H8S/2373
0.18μm
F-ZTAT Group H8S/2377 H8S/2375R
(LGA-145)
H8S/2377R H8S/2373R I/O
Function
Type
Symbol
I/O ports
PD7 to
PD0
80 to 73
K11, K12,
L13, L11,
M12, L12,
N13, M13
80 to 73
80 to 73
Input/ Eight-bit input/
output output pins.
PE7 to
PE0
71,
69 to 63
N11, M11,
N10, L9,
M10, N9,
K10, L8
71,
69 to 63
71,
69 to 63
Input/ Eight-bit input/
output output pins.
PF7 to
PF0
94,
90 to 84
F10, G10,
G12, H11,
J13, H10,
H12, J11
94,
90 to 84
94,
90 to 84
Input/ Eight-bit input/
output output pins.
PG6 to
PG0
132 to 130,
110 to 107
D5, C7, B6,
A13, A12,
B13, D11
132 to
130,
110 to
107
132 to 130, Input/ Seven-bit input/
110 to 107 output output pins.
PH3 to
PH0
38 to 35
M2, N2, M1,
L1
38 to 35
38 to 35
Input/ Four-bit input/output
output pins.
Notes: 1. Not available for the H8S/2378 Group.
2. Not available for the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
3. Available only for the H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm
F-ZTAT Group.
Rev.7.00 Mar. 18, 2009 page 33 of 1136
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Section 1 Overview
Rev.7.00 Mar. 18, 2009 page 34 of 1136
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Section 2 CPU
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
Features
• Upward-compatibility with H8/300 and H8/300H CPUs
⎯ Can execute H8/300 and H8/300H CPU object programs
• General-register architecture
⎯ Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-five basic instructions
⎯ 8/16/32-bit arithmetic and logic instructions
⎯ Multiply and divide instructions
⎯ Powerful bit-manipulation instructions
• Eight addressing modes
⎯ Register direct [Rn]
⎯ Register indirect [@ERn]
⎯ Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
⎯ Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
⎯ Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
⎯ Immediate [#xx:8, #xx:16, or #xx:32]
⎯ Program-counter relative [@(d:8,PC) or @(d:16,PC)]
⎯ Memory indirect [@@aa:8]
• 16-Mbyte address space
⎯ Program: 16 Mbytes
⎯ Data: 16 Mbytes
• High-speed operation
⎯ All frequently-used instructions are executed in one or two states
⎯ 8/16/32-bit register-register add/subtract: 1 state
⎯ 8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
⎯ 16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
CPUS211A_000020020400
Rev.7.00 Mar. 18, 2009 page 35 of 1136
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Section 2 CPU
⎯ 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
⎯ 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
• Two CPU operating modes
⎯ Normal mode*
⎯ Advanced mode
Note: * For this LSI, normal mode is not available.
• Power-down state
⎯ Transition to power-down state by SLEEP instruction
⎯ Selectable CPU clock speed
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions
Execution States
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
3
12
MULXU.W Rs, ERd
4
20
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
MULXS
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
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Section 2 CPU
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been
added.
• Expanded address space
⎯ Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
⎯ Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
⎯ The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
⎯ Addressing modes of bit-manipulation instructions have been enhanced.
⎯ Signed multiply and divide instructions have been added.
⎯ Two-bit shift and two-bit rotate instructions have been added.
⎯ Instructions for saving and restoring multiple registers have been added.
⎯ A test and set instruction has been added.
• Higher speed
⎯ Basic instructions are executed twice as fast.
2.1.3
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
⎯ One 8-bit control register has been added.
• Enhanced instructions
⎯ Addressing modes of bit-manipulation instructions have been enhanced.
⎯ Two-bit shift and two-bit rotate instructions have been added.
⎯ Instructions for saving and restoring multiple registers have been added.
⎯ A test and set instruction has been added.
• Higher speed
⎯ Basic instructions are executed twice as fast.
Rev.7.00 Mar. 18, 2009 page 37 of 1136
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Section 2 CPU
2.2
CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space.
The mode is selected by the LSI’s mode pins.
2.2.1
Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU in normal
mode.
• Address space
Linear access to a maximum address space of 64 kbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.
When extended register En is used as a 16-bit register it can contain any value, even when the
corresponding general register (Rn) is used as an address register. (If general register Rn is
referenced in the register indirect addressing mode with pre-decrement (@–Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended
register (En) will be affected.)
• Instruction set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
• Exception vector table and memory indirect branch addresses
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode, the operand is a 16-bit (word) operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
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Section 2 CPU
• Stack structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-code register (CCR), and extended control register (EXR) are pushed onto the stack
in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack
in interrupt control mode 0. For details, see section 4, Exception Handling.
Note: For this LSI, normal mode is not available.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
(Reserved for system use)
Exception
vector table
Exception vector 1
Exception vector 2
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC
(16 bits)
EXR*1
SP
(SP
*2
Reserved*1*3
)
CCR
CCR*3
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used, it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Figure 2.2 Stack Structure in Normal Mode
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Section 2 CPU
2.2.2
Advanced Mode
• Address space
Linear access to a maximum address space of 16 Mbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the
upper 16-bit segments of 32-bit registers or address registers.
• Instruction set
All instructions and addressing modes can be used.
• Exception vector table and memory indirect branch addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored
in the lower 24 bits (see figure 2.3). For details of the exception vector table, see section 4,
Exception Handling.
H'00000000
Reserved
Reset exception vector
H'00000003
H'00000004
Reserved
(Reserved for system use)
H'00000007
H'00000008
Exception vector table
H'0000000B
(Reserved for system use)
H'0000000C
H'00000010
Reserved
Exception vector 1
Figure 2.3 Exception Vector Table (Advanced Mode)
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Section 2 CPU
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the top area of this range is also used for the exception vector table.
• Stack structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not
pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception
Handling.
EXR*1
SP
SP
Reserved
PC
(24 bits)
(SP
*2
Reserved*1*3
)
CCR
PC
(24 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used, it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
Figure 2.4 Stack Structure in Advanced Mode
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Section 2 CPU
2.3
Address Space
Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.
H'0000
H'00000000
64 kbyte
16 Mbyte
H'FFFF
Program area
H'00FFFFFF
Data area
Not available
in this LSI
H'FFFFFFFF
(a) Normal Mode*
(b) Advanced Mode
Note: * For this LSI, normal mode is not available.
Figure 2.5 Memory Map
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REJ09B0109-0700
Section 2 CPU
2.4
Register Configuration
The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit
extended control register (EXR), and an 8-bit condition code register (CCR).
General Registers (Rn) and Extended Registers (En)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers
23
0
PC
7 6 5 4 3 2 1 0
- - - - I2 I1 I0
EXR T
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
Legend:
SP
PC
EXR
T
I2 to I0
CCR
I
UI
: Stack pointer
: Program counter
: Extended control register
: Trace bit
: Interrupt mask bits
: Condition-code register
: Interrupt mask bit
: User bit or interrupt mask bit*
H
U
N
Z
V
C
: Half-carry flag
: User bit
: Negative flag
: Zero flag
: Overflow flag
: Carry flag
Note: * For this LSI, the interrupt mask bit is not available.
Figure 2.6 CPU Internal Registers
Rev.7.00 Mar. 18, 2009 page 43 of 1136
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Section 2 CPU
2.4.1
General Registers
The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7)
are also referred to as extended registers.
When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing a maximum sixteen 8-bit registers.
The usage of each register can be selected independently.
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.7 Usage of General Registers
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REJ09B0109-0700
Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.8 Stack
2.4.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3
Extended Control Register (EXR)
EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC
instructions. When an instruction other than STC is executed, all interrupts including NMI are
masked in three states after the instruction is completed.
Bit
Bit Name
Initial Value
R/W
Description
7
T
0
R/W
Trace Bit
When this bit is set to 1, trace exception processing
starts every when an instruction is executed. When
this bit is cleared to 0, instructions are consecutively
executed.
6 to
3
—
2 to
0
I2
I1
I0
All1
—
Reserved
These bits are always read as 1.
1
1
1
R/W
R/W
R/W
Interrupt Mask Bits 2 to 0
Specify interrupt request mask levels (0 to 7). For
details, see section 5, Interrupt Controller.
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Section 2 CPU
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
Bit Name
Initial Value
R/W
7
I
1
R/W
Description
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence.
For details, refer to section 5, Interrupt Controller.
6
UI
Undefined
R/W
User Bit or Interrupt Mask Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
For this LSI, Interrupt Mask Bit is not available.
5
H
Undefined
R/W
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is
a carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined
R/W
User Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
3
N
Undefined
R/W
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2
Z
Undefined
R/W
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
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Section 2 CPU
Bit
Bit Name
Initial Value
R/W
Description
1
V
Undefined
R/W
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.
0
C
Undefined
R/W
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
2.4.5
Initial Register Values
Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the
trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other
CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is
undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed
immediately after a reset.
2.5
Data Formats
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
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Section 2 CPU
2.5.1
General Register Data Formats
Figure 2.9 shows the data formats of general registers.
Data Type
Register Number
Data Format
7
RnH
1-bit data
0
Don't care
7 6 5 4 3 2 1 0
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
4 3
Upper
0
7 6 5 4 3 2 1 0
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
0
Don't care
MSB
Figure 2.9 General Register Data Formats (1)
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REJ09B0109-0700
0
Lower
LSB
Section 2 CPU
Data Type
Register Number
Word data
Rn
Data Format
15
0
MSB
Word data
15
0
MSB
Longword data
LSB
En
LSB
ERn
31
16 15
MSB
En
0
Rn
LSB
Legend:
ERn
En
Rn
RnH
RnL
MSB
LSB
: General register ER
: General register E
: General register R
: General register RH
: General register RL
: Most significant bit
: Least significant bit
Figure 2.9 General Register Data Formats (2)
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Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
Data Type
Address
Data Format
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
7
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
Address 2N+3
Figure 2.10 Memory Data Formats
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LSB
Section 2 CPU
2.6
Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Size
Types
Data transfer
MOV
1
1
POP* , PUSH*
B/W/L
5
W/L
LDM, STM
3
L
3
MOVFPE* , MOVTPE*
B
ADD, SUB, CMP, NEG
B/W/L
ADDX, SUBX, DAA, DAS
B
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
4
TAS*
W/L
B
Logic operations
AND, OR, XOR, NOT
B/W/L
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST,
BAND, BIAND, BOR, BIOR, BXOR, BIXOR
2
BCC* , JMP, BSR, JSR, RTS
B
14
—
5
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
—
9
—
1
Arithmetic
operations
Branch
System control
Block data transfer EEPMOV
19
Total: 65
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. BCC is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2
Operation Notation
Symbol
Description
Rd
Rs
General register (destination)*
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move
∼
NOT (logical complement)
:8/:16/:24/:32
8-, 16-, 24-, or 32-bit length
Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
Cannot be used in this LSI.
MOVTPE
B
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn
PUSH
W/L
Rn → @-SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
LDM
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM
L
Rn (register list) → @-SP
Pushes two or more general registers onto the stack.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Section 2 CPU
Table 2.4
Arithmetic Operations Instructions
Instruction
Size*
Function
ADD
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
1
SUB
ADDX
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Subtraction on
immediate data and data in a general register cannot be performed in
bytes. Use the SUBX or ADD instruction.)
B
SUBX
INC
Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.
B/W/L
DEC
ADDS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
B
DAS
MULXU
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts the value 1 or 2 to or from data in a general register.
(Only the value 1 can be added to or subtracted from byte operands.)
SUBS
DAA
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
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1
Instruction
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets the CCR bits according to the result.
NEG
B/W/L
0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
2
TAS*
B
@ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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Section 2 CPU
Table 2.5
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
∼ Rd → Rd
Takes the one’s complement (logical complement) of data in a general
register.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL
B/W/L
Rd (shift) → Rd
SHAR
Performs an arithmetic shift on data in a general register. 1-bit or 2 bit
shift is possible.
SHLL
B/W/L
SHLR
Performs a logical shift on data in a general register. 1-bit or 2 bit shift is
possible.
ROTL
B/W/L
ROTR
Rd (rotate) → Rd
Rotates data in a general register. 1-bit or 2 bit rotation is possible.
ROTXL
B/W/L
ROTXR
Note:
Rd (shift) → Rd
Rd (rotate) → Rd
Rotates data including the carry flag in a general register. 1-bit or 2 bit
rotation is possible.
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Section 2 CPU
Table 2.7
Bit Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
∼ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIAND
B
C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
Logically ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIOR
B
C ∨ (∼ <bit-No.> of <EAd>) → C
Logically ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
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Section 2 CPU
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the carry flag.
BIXOR
B
C ⊕ ∼ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with the inverse of a specified bit
in a general register or memory operand and stores the result in the
carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
∼ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
∼ C → (<bit-No.>. of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size.
B: Byte
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Section 2 CPU
Table 2.8
Branch Instructions
Instruction
Size
Function
Bcc
—
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
JMP
—
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear
(high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
Branches unconditionally to a specified address.
BSR
—
Branches to a subroutine at a specified address
JSR
—
Branches to a subroutine at a specified address
RTS
—
Returns from a subroutine
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Section 2 CPU
Table 2.9
System Control Instructions
Instruction
Size*
Function
TRAPA
—
Starts trap-instruction exception handling.
RTE
—
Returns from an exception-handling routine.
SLEEP
—
Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits
are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with immediate data.
NOP
—
PC + 2 → PC
Only increments the program counter.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
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Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B
—
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next:
EEPMOV.W
—
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next:
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location
set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2
Basic Instruction Formats
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
• Operation field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields, and some have no register field.
• Effective address extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition field
Specifies the branching condition of Bcc instructions.
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Section 2 CPU
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16, etc.
Figure 2.11 Instruction Formats (Examples)
2.7
Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
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Section 2 CPU
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
2.7.1
Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which
contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7
and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. If the address is a program instruction address, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).
2.7.3
Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction code is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register Indirect with Post-Increment—@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word access, and 4 for longword
access. For word or longword transfer instructions, the register value should be even.
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Section 2 CPU
Register Indirect with Pre-Decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or
longword transfer instructions, the register value should be even.
2.7.5
Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address,
the entire address space is accessed.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.12 Absolute Address Access Ranges
Absolute Address
Data address
Normal Mode
Advanced Mode
8 bits (@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32)
Program instruction
address
2.7.6
H'000000 to H'FFFFFF
24 bits (@aa:24)
Immediate—#xx:8, #xx:16, or #xx:32
The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in a instruction
code can be used directly as an operand.
The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their
instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the
instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data
in its instruction code, specifying a vector address.
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2.7.7
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address
indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this
branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which
the displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.
2.7.8
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand which contains a branch address. The upper bits of
the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to
H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode, the memory operand is a longword operand, the first byte of which is assumed to
be 0 (H'00).
Note that the top area of the address range in which the branch address is stored is also used for
the exception vector area. For further details, refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or the instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(b) Advanced Mode
Note: * For this LSI, normal mode is not available.
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
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Section 2 CPU
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Table 2.13 Effective Address Calculation
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct (Rn)
rm
Operand is general register contents.
rn
Register indirect (@ERn)
0
31
op
3
31
24 23
0
Don't care
General register contents
r
Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
0
31
General register contents
op
r
31
disp
Sign extension
Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
op
disp
0
31
31
24 23
1, 2, or 4
0
31
General register contents
31
24 23
Don't care
op
0
Don't care
General register contents
r
• Register indirect with pre-decrement @-ERn
0
0
31
4
24 23
Don't care
r
1, 2, or 4
Operand Size
Byte
Word
Longword
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Offset
1
2
4
0
Section 2 CPU
No
5
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
31
op
@aa:16
31
op
0
H'FFFF
24 23
16 15
0
Don't care Sign extension
abs
@aa:24
31
op
8 7
24 23
Don't care
abs
24 23
0
Don't care
abs
@aa:32
op
31
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
0
24 23
Don't care
abs
Operand is immediate data.
IMM
0
23
Program-counter relative
PC contents
@(d:8,PC)/@(d:16,PC)
op
disp
23
0
Sign
extension
disp
31
24 23
0
Don't care
8
Memory indirect @@aa:8
• Normal mode*
8 7
31
op
abs
0
abs
H'000000
15
0
31
24 23
Don't care
Memory contents
16 15
0
H'00
• Advanced mode
31
op
abs
8 7
H'000000
31
0
abs
0
31
24 23
Don't care
0
Memory contents
Note: * For this LSI, normal mode is not available.
Rev.7.00 Mar. 18, 2009 page 67 of 1136
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Section 2 CPU
2.8
Processing States
The H8S/2000 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.
• Reset state
In this state the CPU and internal peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-handling state
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
• Program execution state
In this state the CPU executes program instructions in sequence.
• Bus-released state
In a product which has a DMA controller and a data transfer controller (DTC), the bus-released
state occurs when the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
refer to section 24, Power-Down Modes.
Rev.7.00 Mar. 18, 2009 page 68 of 1136
REJ09B0109-0700
Section 2 CPU
End of bus request
Bus request
En
d
En
d
of
Re
ex
qu
ce
es
pt
tf
ion
or
ha
ex
nd
ce
lin
pt
g
ion
ha
nd
lin
g
Sleep mode
st
que
t re
up
terr
=0
BY
SS EEP tion
SL truc
ins
Bus-released state
ion
= 1 ruct
BY nst
SS EP i
E
SL
of
bu
s
re
Bu
qu
sr
es
eq
t
ue
st
Program execution state
In
Exception
handling state
External interrupt request
Software standby
mode
RES = High
Reset state*1
STBY = High,
RES = Low
Hardware standby
mode*2
Reset state
Power down state*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low.
A transition can also be made to the reset state when the watchdog timer overflows.
2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.
3. For details, refer to section 24, Power-Down Modes.
Figure 2.13 State Transitions
2.9
Usage Note
2.9.1
Note on Bit Manipulation Instructions
Bit manipulation instructions such as BSET, BCLR, BNOT, BST, and BIST read data in byte
units, perform bit manipulation, and write data in byte units. Thus, care must be taken when these
bit manipulation instructions are executed for a register or port including write-only bits.
In addition, the BCLR instruction can be used to clear the flag of an internal I/O register. In this
case, if the flag to be cleared has been set by an interrupt processing routine, the flag need not be
read before executing the BCLR instruction.
Rev.7.00 Mar. 18, 2009 page 69 of 1136
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Section 2 CPU
Rev.7.00 Mar. 18, 2009 page 70 of 1136
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Operating Mode Selection
The H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group have six
operating modes (modes 1 to 5 and 7). The H8S/2377 and H8S/2377R have five operating modes
(modes 1 to 4 and 7). The H8S/2375 and H8S/2375R has four operating modes (modes 1, 2, 4, and
7). The H8S/2373 and H8S/2373R has two operating modes (modes 1 and 2). The operating mode
is selected by the setting of mode pins (MD2 to MD0).
Modes 1, 2, and 4 are externally expanded modes in which the CPU can access an external
memory and peripheral devices. In the externally expanded mode, each area can be switched to 8bit or 16-bit address space by the bus controller. If any one of the areas is set to 16-bit address
space, the bus mode is 16 bits. If all areas are set to 8-bit address space, the bus mode is 8 bits.
Mode 7 is a single-chip activation externally expanded mode in which the CPU can switch to
access an external memory and peripheral devices at the beginning of a program execution.
Mode 3 is a boot mode in which the flash memory can be programmed or erased. For details of the
boot mode, refer to section 21, Flash Memory (0.18-μm F-ZTAT Version), or section 20, Flash
Memory (0.35-μm F-ZTAT Version).
The settings for pins MD2 to MD0 should not be changed during operation.
Table 3.1
MCU Operating Mode Selection
MCU
Operating
Mode
MD2
MD1
MD0
CPU
Operating
Mode
1*1
0
0
1
Advanced
2*1
0
1
0
3
0
1
4
1
0
External Data Bus
On-Chip
ROM
Initial
Width
Max.
Value
Expanded mode with
on-chip ROM disabled
Disabled
16 bits
16 bits
Advanced
Expanded mode with
on-chip ROM disabled
Disabled
8 bits
16 bits
1
Advanced
Boot mode
Enabled
⎯
16 bits
0
Advanced
Expanded mode with
on-chip ROM enabled
Enabled
8 bits
16 bits
Description
5*2
1
0
1
Advanced
User boot mode
Enabled
⎯
16 bits
7
1
1
1
Advanced
Single-chip mode
Enabled
⎯
16 bits
Notes: 1. Only modes 1 and 2 may be used on ROM-less versions.
2. Available only for the H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm
F-ZTAT Group.
Rev.7.00 Mar. 18, 2009 page 71 of 1136
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Section 3 MCU Operating Modes
3.2
Register Descriptions
The following registers are related to the operating mode.
• Mode control register (MDCR)
• System control register (SYSCR)
3.2.1
Mode Control Register (MDCR)
MDCR monitors the current operating mode of this LSI.
Bit
Bit Name
Initial Value
R/W
Descriptions
7 to
3
⎯
All 0
⎯
Reserved
2
1
0
MDS2
MDS1
MDS0
Note:
3.2.2
These bits are always read as 0 and cannot be
modified.
*
⎯*
⎯*
⎯*
R
R
R
Mode Select 2 to 0
These bits indicate the input levels at pins MD2 to MD0
(the current operating mode). Bits MDS2 to MDS0
correspond to MD2 to MD0. MDS2 to MDS0 are readonly bits and they cannot be modified. The mode pin
(MD2 to MD0) input levels are latched into these bits
when MDCR is read. These latches are canceled by a
reset.
Determined by pins MD2 to MD0.
System Control Register (SYSCR)
SYSCR controls CPU access to the flash memory control registers, sets external bus mode, and
enables or disables on-chip RAM.
Rev.7.00 Mar. 18, 2009 page 72 of 1136
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Section 3 MCU Operating Modes
• H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group
Bit
Bit Name
Initial Value
R/W
Descriptions
7, 6
⎯
All 1
R/W
Reserved
5, 4
⎯
All 0
R/W
The initial value should not be modified.
Reserved
The initial value should not be modified.
3
FLSHE
0
R/W
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers. If this bit is set to 1, the flash memory control
registers can be read from and written to. If this bit is
cleared to 0, the flash memory control registers are
not selected. At this time, the contents of the flash
memory control registers are maintained. This bit
should be written to 0 in other than flash memory
version.
0: Flash memory control registers are not selected for
area H'FFFFC4 to H'FFFFCF
1: Flash memory control registers are selected for
area H'FFFFC4 to H'FFFFCF
2
⎯
0
⎯
Reserved
This bit is always read as 0 and cannot be modified.
1
EXPE
⎯
R/W
External Bus Mode Enable
Sets external bus mode.
In modes 1, 2, and 4, this bit is fixed at 1 and cannot
be modified. In modes 3, 5, and 7, this bit can be read
from and written to.
Writing of 0 to this bit when its value is 1 should only
be carried out when an external bus cycle is not being
executed.
0: External bus disabled
1: External bus enabled
0
RAME
1
R/W
RAM Enable
Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Rev.7.00 Mar. 18, 2009 page 73 of 1136
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Section 3 MCU Operating Modes
• H8S/2377, H8S/2377R, H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R
Bit
Bit Name
Initial Value
R/W
Descriptions
7, 6
⎯
All 1
R/W
Reserved
5, 4
⎯
All 0
R/W
The initial value should not be modified.
Reserved
The initial value should not be modified.
3
FLSHE
0
R/W
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMCR2, EBR1, and EBR2). If
this bit is set to 1, the flash memory control registers
can be read from and written to. If this bit is cleared to
0, the flash memory control registers are not selected.
At this time, the contents of the flash memory control
registers are maintained. This bit should be written to
0 in other than flash memory version.
0: Flash memory control registers are not selected for
area H'FFFFC8 to H'FFFFCB
1: Flash memory control registers are selected for
area H'FFFFC8 to H'FFFFCB
2
⎯
0
⎯
Reserved
This bit is always read as 0 and cannot be modified.
1
EXPE
⎯
R/W
External Bus Mode Enable
Sets external bus mode.
In modes 1, 2, and 4, this bit is fixed at 1 and cannot
be modified. In modes 3 and 7, this bit can be read
from and written to.
Writing of 0 to this bit when its value is 1 should only
be carried out when an external bus cycle is not being
executed.
0: External bus disabled
1: External bus enabled
0
RAME
1
R/W
RAM Enable
Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Rev.7.00 Mar. 18, 2009 page 74 of 1136
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Section 3 MCU Operating Modes
3.3
Operating Mode Descriptions
3.3.1
Mode 1
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of
ports F and G carry bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access
is designated for all areas by the bus controller, the bus mode switches to 8 bits.
3.3.2
Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of
ports F and G carry bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for any one of the areas by the bus controller, the bus mode switches to 16 bits and
port E functions as a data bus.
3.3.3
Mode 3
This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for the
programming and erasure on the flash memory. Mode 3 is only available in the flash memory
version.
3.3.4
Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in the on-chip ROM connected to the first half of area 0 is executed.
Ports A, B, and C function as input ports immediately after a reset, but can be set to function as an
address bus depending on each port register setting. Ports D functions as a data bus, and parts of
ports F and G carry bus control signals. For details, see section 10, I/O Ports.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for any area by the bus controller, the bus mode switches to 16 bits and port E
functions as a data bus.
Rev.7.00 Mar. 18, 2009 page 75 of 1136
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Section 3 MCU Operating Modes
In the flash memory version, user program mode is entered by setting the SWE bit of FLMCR1 to
1.
3.3.5
Mode 5
This mode is a user boot mode of the flash memory. This mode is the same as mode 7, except for
the programming and erasure on the flash memory. Mode 5 is only available in the H8S/2378
0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT Group.
3.3.6
Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
and the chip starts up in single-chip mode. External address space cannot be used in single-chip
mode.
The initial mode after a reset is single-chip mode, with all I/O ports available for use as
input/output ports. However, the mode can be switched to externally expanded mode by setting 1
to the EXPE bit of SYSCR and then the external address space is enabled. When externally
expanded mode is selected, all areas are initially designated as 16-bit access space. The functions
of pins in ports A to G are the same as in externally expanded mode with on-chip ROM enabled.
In the flash memory version, user program mode is entered by setting the SWE bit of FLMCR1 to
1.
Rev.7.00 Mar. 18, 2009 page 76 of 1136
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Section 3 MCU Operating Modes
3.3.7
Pin Functions
Table 3.2 shows the pin functions in each operating mode.
Table 3.2
Pin Functions in Each Operating Mode
Port
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 7
PA7 to PA5
P*/A
P*/A
P*/A
P*/A
P*/A
P*/A
PA4 to PA0
A
A
Port B
A
A
P*/A
P*/A
P*/A
P*/A
Port C
A
A
P*/A
P*/A
P*/A
P*/A
D
P*/D
P*/D
Port A
Port D
D
D
P*/D
Port E
P/D*
P*/D
P*/D
P*/D
P*/D
P*/D
PF7, PF6
P/C*
P/C*
P*/C
P/C*
P*/C
P*/C
PF5, PF4
C
C
C
PF3
P/C*
P/C*
P/C*
PF2 to PF0
P*/C
P*/C
PG6 to PG1
P*/C
P*/C
P*/C
P*/C
PG0
P/C*
P/C*
Port F
Port G
P*/C
P*/C
P*/C
P*/C
Legend: P: I/O port
A: Address bus output
D: Data bus input/output
C: Control signals, clock input/output
*: After reset
Note: Mode 5 is available only for the H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm
F-ZTAT Group.
Only modes 1 and 2 may be used on ROM-less versions.
Rev.7.00 Mar. 18, 2009 page 77 of 1136
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Section 3 MCU Operating Modes
3.4
Memory Map in Each Operating Mode
Figures 3.1 to 3.17 show memory maps for each product.
RAM: 32 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 512 kbytes
RAM: 32 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
External address
space
H'080000
External address
space/
Reserved area*2*4
H'FF4000
H'FF4000
On-chip RAM/
external address
space*1
H'FFC000
Reserved area*4
On-chip RAM*3
H'FFC000
Reserved area*4
H'FFD000
External address space
H'FFD000
H'FFFC00
Internal I/O registers
H'FFFC00
Internal I/O registers
H'FFFF00
External address space/
reserved area*2*4
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
H'FFFF20
H'FFFFFF
External address space/
reserved area*2*4
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Figure 3.1 Memory Map for H8S/2378 and H8S/2378R (1)
Rev.7.00 Mar. 18, 2009 page 78 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
ROM: 512 kbytes
RAM: 32 kbytes
Mode 5
(User boot mode)
ROM: 512 kbytes
RAM: 32 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'080000
H'FF4000
H'FFD000 External address space
H'FFFC00
H'FFFF00
H'FFFF20
H'FFFFFF
H'080000
External address
space/
reserved area*2*4
On-chip RAM/
external address
space*1
Reserved area*4
Internal I/O registers
External address space
Internal I/O registers
On-chip ROM
On-chip ROM
External address
space
H'FFC000
H'000000
H'080000
H'FF4000
ROM: 512 kbytes
RAM: 32 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
H'FF4000
On-chip
H'FFC000
External address
space/
reserved area*2*4
On-chip RAM/
external address
space *3
RAM *5
Reserved area*4
H'FFC000
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
5. The on-chip RAM is used to program the flash memory. The RAME bit in SYSCR should not be cleared to 0.
Figure 3.2 Memory Map for H8S/2378 and H8S/2378R (2)
Rev.7.00 Mar. 18, 2009 page 79 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
RAM: 24 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 384 kbytes
RAM: 24 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
External address
space
H'060000
External address
space/
Reserved area*2*4
H'FF4000
H'FF6000
H'FFC000
Reserved area*4
On-chip RAM/
external address
space*1
Reserved area*4
H'FF4000
H'FF6000
Reserved area*4
On-chip RAM*3
H'FFC000
Reserved area*4
H'FFC800
External address space
H'FFC800
H'FFFC00
Internal I/O registers
H'FFFC00
Internal I/O registers
H'FFFF00
External address space/
reserved area*2*4
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
H'FFFF20
H'FFFFFF
External address space/
reserved area*2*4
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0.
4. A reserved area should not be accessed.
Figure 3.3 Memory Map for H8S/2377 and H8S/2377R (1)
Rev.7.00 Mar. 18, 2009 page 80 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
ROM: 384 kbytes
RAM: 24 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
ROM: 384 kbytes
RAM: 24 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'060000
On-chip ROM
H'060000
External address
space/
reserved area*2*4
External address
space
H'FF4000
H'FF6000
H'FFC000
Reserved area*4
On-chip RAM/
external address
space*1
Reserved area*4
H'FFC800 External address space
H'FFFC00
H'FFFF00
H'FFFF20
H'FFFFFF
Internal I/O registers
External address space
Internal I/O registers
H'FF4000
H'FF6000
H'FFC000
Reserved area*4
On-chip RAM/
external address
space*3
Reserved area*4
H'FFC800 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
Figure 3.4 Memory Map for H8S/2377 and H8S/2377R (2)
Rev.7.00 Mar. 18, 2009 page 81 of 1136
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Section 3 MCU Operating Modes
ROM: 256 kbytes
RAM: 16 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
RAM: 16 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
H'000000
On-chip ROM
H'040000
External address
space
Reserved area*2
H'060000
External address
space
H'FF4000
H'FF8000
H'FFC000
H'FFC800
H'FFFC00
Reserved area*2
On-chip RAM/
external address
space*1
Reserved area*2
H'FF4000
H'FF8000
H'FFC000
Reserved area*2
On-chip RAM/
external address
space*1
Reserved area*2
External address space
H'FFC800 External address space
Internal I/O registers
H'FFFC00
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
H'FFFF00
H'FFFF20
H'FFFFFF
Internal I/O registers
External address space
Internal I/O registers
Notes: 1. This area is specified as external address space by clearing the RAME bit in SYSCR to 0.
2. A reserved area should not be accessed.
Figure 3.5 Memory Map for H8S/2375 and H8S/2375R (1)
Rev.7.00 Mar. 18, 2009 page 82 of 1136
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Section 3 MCU Operating Modes
ROM: 256 kbytes
RAM: 16 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
H'000000
On-chip ROM
H'040000
Reserved area*3
H'060000
External address
space/
reserved area*1*3
H'FF4000
H'FF8000
Reserved area*3
On-chip RAM/
external address
space*2
H'FFC000
H'FFC800
Reserved area*3
External address space/
reserved area*1*3
H'FFFC00 Internal I/O registers
H'FFFF00 External address space/
reserved area*1*3
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. When EXPE = 1, external address space; when EXPE = 0, reserved area.
2. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
3. A reserved area should not be accessed.
Figure 3.6 Memory Map for H8S/2375 and H8S/2375R (2)
Rev.7.00 Mar. 18, 2009 page 83 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
RAM: 32 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 384 kbytes
RAM: 32 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
H'060000
Reserved area*4
External address
space
H'080000
External address
space/
reserved area*2*4
H'FF4000
H'FF4000
On-chip RAM/
external address
space*1
H'FFC000
Reserved area*4
On-chip RAM*3
H'FFC000
H'FFD000
External address space
H'FFD000
H'FFFC00
Internal I/O registers
H'FFFC00
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
H'FFFF00
H'FFFF20
H'FFFFFF
Reserved area*4
External address space/
reserved area*2*4
Internal I/O registers
External address space/
reserved area*2*4
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Figure 3.7 Memory Map for H8S/2374 and H8S/2374R (1)
Rev.7.00 Mar. 18, 2009 page 84 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
ROM: 384 kbytes
RAM: 32 kbytes
Mode 5
(User boot mode)
ROM: 384 kbytes
RAM: 32 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'060000
Reserved area*4
H'080000
On-chip ROM
H'060000
Reserved area*4
H'FFD000 External address space
H'FFFF00
H'FFFF20
H'FFFFFF
Internal I/O registers
External address space
Internal I/O registers
H'060000
External address
space/
reserved area*2*4
H'FF4000
On-chip
H'FFC000
Reserved area*4
H'080000
H'FF4000
On-chip RAM/
external address
space*1
H'FFFC00
Reserved area*4
On-chip ROM
External address
space/
reserved area*2*4
External address
space
H'FFC000
H'000000
H'080000
H'FF4000
ROM: 384 kbytes
RAM: 32 kbytes
Mode 5
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
On-chip RAM/
external address
space *3
RAM *5
Reserved area*4
H'FFC000
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
Reserved area*4
H'FFD000 External address space/
reserved area*3*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFFF00 External address space/
reserved area*3*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
5. The on-chip RAM is used to program the flash memory. The RAME bit in SYSCR should not be cleared to 0.
Figure 3.8 Memory Map for H8S/2374 and H8S/2374R (2)
Rev.7.00 Mar. 18, 2009 page 85 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
RAM: 16 kbytes
Modes 1 and 2
Expanded mode
with on-chip ROM disabled
H'000000
External address
space
H'FF4000
H'FF8000
Reserved area*2
On-chip
external address
space*1
H'FFC000
H'FFC800
Reserved area*2
External address space
H'FFFC00
H'FFFF00
H'FFFF20
H'FFFFFF
Internal I/O register
External address space
Internal I/O register
Notes: 1. This area is specified as external address space by clearing the RAME bit in SYSCR to 0.
2. A reserved area should not be accessed.
Figure 3.9 Memory Map for H8S/2373 and H8S/2373R
Rev.7.00 Mar. 18, 2009 page 86 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
RAM: 32 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 256 kbytes
RAM: 32 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
H'040000
Reserved area*4
External address
space
H'080000
External address
space/
reserved area*2*4
H'FF4000
H'FF4000
On-chip RAM/
external address
space*1
H'FFC000
Reserved area*4
On-chip RAM*3
H'FFC000
H'FFD000
External address space
H'FFD000
H'FFFC00
Internal I/O registers
H'FFFC00
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
H'FFFF00
H'FFFF20
H'FFFFFF
Reserved area*4
External address space/
reserved area*2*4
Internal I/O registers
External address space/
reserved area*2*4
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Figure 3.10 Memory Map for H8S/2372 and H8S/2372R (1)
Rev.7.00 Mar. 18, 2009 page 87 of 1136
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Section 3 MCU Operating Modes
ROM: 256 kbytes
RAM: 32 kbytes
Mode 5
(User boot mode)
ROM: 256 kbytes
RAM: 32 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'040000
On-chip ROM
Reserved area*4
H'FFD000 External address space
H'FFFF00
H'FFFF20
H'FFFFFF
H'080000
H'FF4000
Reserved area*4
Internal I/O registers
External address space
Internal I/O registers
Reserved area*4
External address
space/
reserved area*2*4
On-chip RAM/
external address
space*1
H'FFFC00
H'040000
H'080000
H'FF4000
On-chip ROM
Reserved area*4
External address
space
H'FFC000
H'000000
H'040000
H'080000
ROM: 256 kbytes
RAM: 32 kbytes
Mode 5
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
H'FF4000
On-chip
H'FFC000
External address
space/
reserved area*2*4
On-chip RAM/
external address
space *3
RAM *5
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFC000
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
5. The on-chip RAM is used to program the flash memory. The RAME bit in SYSCR should not be cleared to 0.
Figure 3.11 Memory Map for H8S/2372 and H8S/2372R (2)
Rev.7.00 Mar. 18, 2009 page 88 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
RAM: 24 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 256 kbytes
RAM: 24 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
H'040000
Reserved area*4
External address
space
H'080000
External address
space/
reserved area*2*4
H'FF4000
H'FF6000
H'FFC000
H'FFD000
H'FFFC00
Reserved area*4
On-chip RAM/
external address
space*1
Reserved area*4
H'FF4000
H'FF6000
Reserved area*4
On-chip RAM*3
H'FFC000
Reserved area*4
External address space
H'FFD000
External address space/
reserved area*2*4
Internal I/O registers
H'FFFC00
Internal I/O registers
H'FFFF00
External address space/
reserved area*2*4
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
H'FFFF20
H'FFFFFF
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Figure 3.12 Memory Map for H8S/2371 and H8S/2371R (1)
Rev.7.00 Mar. 18, 2009 page 89 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
ROM: 256 kbytes
RAM: 24 kbytes
Mode 5
(User boot mode)
ROM: 256 kbytes
RAM: 24 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'040000
On-chip ROM
Reserved area*4
Reserved area*4
H'FF4000
On-chip RAM/
external address
space*1
Reserved area*4
H'FF6000
H'FFFF00
H'FFFF20
H'FFFFFF
External address space
Internal I/O registers
External address space
Internal I/O registers
Reserved area*4
H'080000
External address
space/
reserved area*2*4
H'FF6000
H'FFD000
H'040000
H'080000
H'FF4000
H'FFFC00
On-chip ROM
Reserved area*4
External address
space
H'FFC000
H'000000
H'040000
H'080000
ROM: 256 kbytes
RAM: 24 kbytes
Mode 5
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
Reserved area*4
External address
space/
reserved area*2*4
H'FF4000
Reserved area*4
H'FF6000
On-chip RAM/
external address
space*3
Reserved area*4
On-chip RAM *5
H'FFC000
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFC000
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
5. The on-chip RAM is used to program the flash memory. The RAME bit in SYSCR should not be cleared to 0.
Figure 3.13 Memory Map for H8S/2371 and H8S/2371R (2)
Rev.7.00 Mar. 18, 2009 page 90 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
RAM: 16 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 256 kbytes
RAM: 16 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
H'040000
Reserved area*4
External address
space
H'080000
External address
space/
reserved area*2*4
H'FF4000
H'FF8000
H'FFC000
H'FFD000
H'FFFC00
Reserved area*4
On-chip RAM/
external address
space*1
Reserved area*4
H'FF4000
H'FF8000
Reserved area*4
On-chip RAM*3
H'FFC000
Reserved area*4
External address space
H'FFD000
External address space/
reserved area*2*4
Internal I/O registers
H'FFFC00
Internal I/O registers
H'FFFF00
External address space/
reserved area*2*4
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
H'FFFF20
H'FFFFFF
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Figure 3.14 Memory Map for H8S/2370 and H8S/2370R (1)
Rev.7.00 Mar. 18, 2009 page 91 of 1136
REJ09B0109-0700
Section 3 MCU Operating Modes
ROM: 256 kbytes
RAM: 16 kbytes
Mode 5
(User boot mode)
ROM: 256 kbytes
RAM: 16 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
H'000000
H'040000
H'080000
Reserved area*4
H'FF4000
H'FF8000
On-chip RAM/
external address
space*1
Reserved area*4
H'FF8000
H'FFFF00
H'FFFF20
H'FFFFFF
External address space
Internal I/O registers
External address space
Internal I/O registers
Reserved area*4
H'080000
External address
space/
reserved area*2*4
H'FF4000
H'FFD000
H'040000
H'080000
External address
space
H'FFFC00
On-chip ROM
Reserved area*4
Reserved area*4
H'FFC000
H'000000
On-chip ROM
On-chip ROM
H'040000
ROM: 256 kbytes
RAM: 16 kbytes
Mode 5
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
Reserved area*4
External address
space/
reserved area*2*4
H'FF4000
Reserved area*4
H'FF8000
On-chip RAM/
external address
space*3
Reserved area*4
On-chip RAM *5
H'FFC000
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFC000
H'FFD000
H'FFFC00
H'FFFF00
External address space
Internal I/O registers
External address space
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
5. The on-chip RAM is used to program the flash memory. The RAME bit in SYSCR should not be cleared to 0.
Figure 3.15 Memory Map for H8S/2370 and H8S/2370R (2)
Rev.7.00 Mar. 18, 2009 page 92 of 1136
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Section 4 Exception Handling
Section 4 Exception Handling
4.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low.
1
Trace*
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.
2
Low
Direct transition*
Starts when the direct transition occurs by execution of the
SLEEP instruction.
Interrupt
Starts when execution of the current instruction or exception
3
handling ends, if an interrupt request has been issued.*
4
Trap instruction*
Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Not available in this LSI.
3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
4. Trap instruction exception handling requests are accepted at all times in program
execution state.
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.
Rev.7.00 Mar. 18, 2009 page 93 of 1136
REJ09B0109-0700
Section 4 Exception Handling
Table 4.2
Exception Handling Vector Table
1
Vector Address*
2
Exception Source
Vector Number
Normal Mode*
Advanced Mode
Power-on reset
3
Manual reset*
0
H'0000 to H'0001
H'0000 to H'0003
1
H'0002 to H'0003
H'0004 to H'0007
Reserved for system use
2
H'0004 to H'0005
H'0008 to H'000B
3
H'0006 to H'0007
H'000C to H'000F
4
H'0008 to H'0019
H'0010 to H'0013
Trace
5
H'000A to H'000B
H'0014 to H'0017
3
Interrupt (direct transition)*
6
H'000C to H'000D
H'0018 to H'001B
Interrupt (NMI)
7
H'000E to H'000F
H'001C to H'001F
Trap instruction (#0)
8
H'0010 to H'0011
H'0020 to H'0023
(#1)
9
H'0012 to H'0013
H'0024 to H'0027
(#2)
10
H'0014 to H'0015
H'0028 to H'002B
(#3)
11
H'0016 to H'0017
H'002C to H'002F
12
H'0018 to H'0019
H'0030 to H'0033
13
H'001A to H'001B
H'0034 to H'0037
Reserved for system use
External interrupt
14
H'001C to H'001D
H'0038 to H'003B
15
H'001E to H'001F
H'003C to H'003F
IRQ0
16
H'0020 to H'0021
H'0040 to H'0043
IRQ1
17
H'0022 to H'0023
H'0044 to H'0047
IRQ2
18
H'0024 to H'0025
H'0048 to H'004B
IRQ3
19
H'0026 to H'0027
H'004C to H'004F
IRQ4
20
H'0028 to H'0029
H'0050 to H'0053
IRQ5
21
H'002A to H'002B
H'0054 to H'0057
IRQ6
22
H'002C to H'002D
H'0058 to H'005B
IRQ7
23
H'002E to H'002F
H'005C to H'005F
IRQ8
24
H'0030 to H'0031
H'0060 to H'0063
IRQ9
25
H'0032 to H'0033
H'0064 to H'0067
IRQ10
26
H'0034 to H'0035
H'0068 to H'006B
IRQ11
27
H'0036 to H'0037
H'006C to H'006F
IRQ12
28
H'0038 to H'0039
H'0070 to H'0073
Rev.7.00 Mar. 18, 2009 page 94 of 1136
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Section 4 Exception Handling
1
Vector Address*
External interrupt
4
Internal interrupt*
Notes: 1.
2.
3.
4.
4.3
2
Vector Number
Normal Mode*
Advanced Mode
IRQ13
29
H'003A to H'003B
H'0074 to H'0077
IRQ14
30
H'003C to H'003D
H'0078 to H'007B
IRQ15
31
H'003E to H'003F
H'007C to H'007F
32
⎜
118
H'0040 to H'0041
⎜
H'00EC to H'00ED
H'0080 to H'0083
⎜
H'01D8 to H'01DB
Exception Source
Lower 16 bits of the address.
Not available in this LSI.
Not available in this LSI. It is reserved for system use.
For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.
Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 14,
Watchdog Timer (WDT).
The interrupt control mode is 0 immediately after reset.
4.3.1
Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.1 and 4.2 show examples of the reset sequence.
Rev.7.00 Mar. 18, 2009 page 95 of 1136
REJ09B0109-0700
Section 4 Exception Handling
Vector fetch
Prefetch of first
Internal
processing program instruction
(1)
(3)
φ
RES
Internal
address bus
(5)
Internal read
signal
Internal write
signal
Internal data
bus
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)
Rev.7.00 Mar. 18, 2009 page 96 of 1136
REJ09B0109-0700
Section 4 Exception Handling
Internal
processing
Vector fetch
*
φ
*
Prefetch of first
program instruction
*
RES
Address bus
(1)
(3)
(5)
RD
HWR, LWR
D15 to D0
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Note: * Seven program wait states are inserted.
Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled)
4.3.2
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
On-Chip Peripheral Functions after Reset Release
After reset release, MSTPCR is initialized to H'0FFF and all modules except the DMAC,
EXDMAC and the DTC enter module stop mode.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when module stop mode is exited.
Rev.7.00 Mar. 18, 2009 page 97 of 1136
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Section 4 Exception Handling
4.4
Trace Exception Handling
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows
the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by
clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control
is returned from the trace exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Interrupts are accepted even within the trace exception handling routine.
Table 4.3
Status of CCR and EXR after Trace Exception Handling
Interrupt Control Mode
CCR
I
0
2
EXR
UI
I2 to I0
T
Trace exception handling cannot be used.
1
—
—
0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
4.5
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiplexed interrupt control. The source to start interrupt exception handling and the vector
address differ depending on the product. For details, refer to section 5, Interrupt Controller.
The interrupt exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
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Section 4 Exception Handling
4.6
Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The trap instruction exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.4
Status of CCR and EXR after Trap Instruction Exception Handling
Interrupt Control Mode
CCR
EXR
I
UI
I2 to I0
T
0
1
⎯
⎯
⎯
2
1
⎯
⎯
0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
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Section 4 Exception Handling
4.7
Stack Status after Exception Handling
Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
(a) Normal Modes*2
SP
EXR
Reserved*1
SP
CCR
CCR
CCR*1
CCR*1
PC (16 bits)
PC (16 bits)
Interrupt control mode 0
Interrupt control mode 2
(b) Advanced Modes
SP
EXR
Reserved*1
SP
CCR
PC (24 bits)
Interrupt control mode 0
CCR
PC (24 bits)
Interrupt control mode 2
Notes: 1. Ignored on return.
2. Normal modes are not available in this LSI.
Figure 4.3 Stack Status after Exception Handling
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Section 4 Exception Handling
4.8
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by word transfer instruction or longword transfer instruction, and
the value of the stack pointer (SP, ER7) should always be kept even. Use the following
instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of operation
when the SP value is odd.
Address
CCR
R1L
SP
SP
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFE
SP
H'FFFEFF
TRAP instruction executed
SP set to H'FFFEFF
MOV.B R1L, @-ER7
Data saved above SP
Contents of CCR lost
Legend:
CCR :
PC :
R1L :
SP :
Condition code register
Program counter
General register R1L
Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 4.4 Operation when SP Value Is Odd
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Section 4 Exception Handling
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Features
• Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
interrupt control register (INTCR).
• Priorities settable with IPR
An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI. NMI is assigned the highest
priority level of 8, and can be accepted at all times.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Seventeen external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can
be selected for IRQ15 to IRQ0.
• DTC and DMAC control
DTC and DMAC activations are performed by means of interrupts.
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Section 5 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1.
CPU
INTM1 INTM0
INTCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
SSIER ITSR ISCR IER
Interrupt
request
Vector
number
Priority
determination
Internal
interrupt
sources
SWDTEND
to IICI1
I
I2 to I0
IPR
Interrupt controller
Legend:
ISCR: IRQ sense control register
IER:
IRQ enable register
ISR:
IRQ status register
IPR:
Interrupt priority register
INTCR: Interrupt control register
ITSR: IRQ pin select register
SSIER: Software standby release IRQ enable register
Figure 5.1 Block Diagram of Interrupt Controller
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CCR
EXR
Section 5 Interrupt Controller
5.2
Input/Output Pins
Table 5.1 shows the pin configuration of the interrupt controller.
Table 5.1
Pin Configuration
Name
I/O
Function
NMI
Input
Nonmaskable external interrupt
IRQ15 to IRQ0
Input
Rising or falling edge can be selected.
Maskable external interrupts
Rising, falling, or both edges, or level sensing, can be selected.
5.3
Register Descriptions
The interrupt controller has the following registers.
• Interrupt control register (INTCR)
• IRQ sense control register H (ISCRH)
• IRQ sense control register L (ISCRL)
• IRQ enable register (IER)
• IRQ status register (ISR)
• IRQ pin select register (ITSR)
• Software standby release IRQ enable register (SSIER)
• Interrupt priority register A (IPRA)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
• Interrupt priority register H (IPRH)
• Interrupt priority register I (IPRI)
• Interrupt priority register J (IPRJ)
• Interrupt priority register K (IPRK)
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Section 5 Interrupt Controller
5.3.1
Interrupt Control Register (INTCR)
INTCR selects the interrupt control mode, and the detected edge for NMI.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
—
All 0
—
Reserved
These bits are always read as 0 and the initial value
should not be changed.
5
4
INTM1
INTM0
0
0
R/W
R/W
Interrupt Control Select Mode 1 and 0
These bits select either of two interrupt control modes
for the interrupt controller.
00: Interrupt control mode 0
Interrupts are controlled by I bit.
01: Setting prohibited.
10: Interrupt control mode 2
Interrupts are controlled by bits I2 to I0, and IPR.
11: Setting prohibited.
3
NMIEG
0
R/W
NMI Edge Select
Selects the input edge for the NMI pin.
0: Interrupt request generated at falling edge of NMI
input
1: Interrupt request generated at rising edge of NMI
input
2 to
0
5.3.2
—
All 0
—
Reserved
These bits are always read as 0 and the initial value
should not be changed.
Interrupt Priority Registers A to K (IPRA to IPRK)
IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts
other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt
Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7
in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding
interrupt. IPR should be read in word size.
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
15
—
0
—
Reserved
This bit is always read as 0 and the initial value should
not be changed.
14
13
12
IPR14
IPR13
IPR12
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
11
—
0
—
Reserved
This bit is always read as 0 and the initial value should
not be changed.
10
9
8
IPR10
IPR9
IPR8
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
7
—
0
—
Reserved
This bit is always read as 0 and the initial value should
not be changed.
6
5
4
IPR6
IPR5
IPR4
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
3
—
0
—
Reserved
This bit is always read as 0 and the initial value should
not be changed.
2
1
0
IPR2
IPR1
IPR0
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
5.3.3
IRQ Enable Register (IER)
IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0.
Bit
Bit Name
Initial Value
R/W
Description
15
IRQ15E
0
R/W
IRQ15 Enable
The IRQ15 interrupt request is enabled when this
bit is 1.
14
IRQ14E
0
R/W
IRQ14 Enable
The IRQ14 interrupt request is enabled when this
bit is 1.
13
IRQ13E
0
R/W
IRQ13 Enable
The IRQ13 interrupt request is enabled when this
bit is 1.
12
IRQ12E
0
R/W
IRQ12 Enable
The IRQ12 interrupt request is enabled when this
bit is 1.
11
IRQ11E
0
R/W
IRQ11 Enable
The IRQ11 interrupt request is enabled when this
bit is 1.
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
10
IRQ10E
0
R/W
IRQ10 Enable
The IRQ10 interrupt request is enabled when this
bit is 1.
9
IRQ9E
0
R/W
IRQ9 Enable
The IRQ9 interrupt request is enabled when this
bit is 1.
8
IRQ8E
0
R/W
IRQ8 Enable
The IRQ8 interrupt request is enabled when this
bit is 1.
7
IRQ7E
0
R/W
IRQ7 Enable
The IRQ7 interrupt request is enabled when this
bit is 1.
6
IRQ6E
0
R/W
IRQ6 Enable
The IRQ6 interrupt request is enabled when this
bit is 1.
5
IRQ5E
0
R/W
IRQ5 Enable
The IRQ5 interrupt request is enabled when this
bit is 1.
4
IRQ4E
0
R/W
IRQ4 Enable
The IRQ4 interrupt request is enabled when this
bit is 1.
3
IRQ3E
0
R/W
IRQ3 Enable
The IRQ3 interrupt request is enabled when this
bit is 1.
2
IRQ2E
0
R/W
IRQ2 Enable
The IRQ2 interrupt request is enabled when this
bit is 1.
1
IRQ1E
0
R/W
IRQ1 Enable
The IRQ1 interrupt request is enabled when this
bit is 1.
0
IRQ0E
0
R/W
IRQ0 Enable
The IRQ0 interrupt request is enabled when this
bit is 1.
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Section 5 Interrupt Controller
5.3.4
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0.
• ISCRH
Bit
Bit Name
Initial Value
R/W
Description
15
14
IRQ15SCB
IRQ15SCA
0
0
R/W
R/W
IRQ15 Sense Control B
IRQ15 Sense Control A
00: Interrupt request generated at IRQ15 input low
level
01: Interrupt request generated at falling edge of
IRQ15 input
10: Interrupt request generated at rising edge of
IRQ15 input
11: Interrupt request generated at both falling and
rising edges of IRQ15 input
13
12
IRQ14SCB
IRQ14SCA
0
0
R/W
R/W
IRQ14 Sense Control B
IRQ14 Sense Control A
00: Interrupt request generated at IRQ14 input low
level
01: Interrupt request generated at falling edge of
IRQ14 input
10: Interrupt request generated at rising edge of
IRQ14 input
11: Interrupt request generated at both falling and
rising edges of IRQ14 input
11
10
IRQ13SCB
IRQ13SCA
0
0
R/W
R/W
IRQ13 Sense Control B
IRQ13 Sense Control A
00: Interrupt request generated at IRQ13 input low
level
01: Interrupt request generated at falling edge of
IRQ13 input
10: Interrupt request generated at rising edge of
IRQ13 input
11: Interrupt request generated at both falling and
rising edges of IRQ13 input
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
9
8
IRQ12SCB
IRQ12SCA
0
0
R/W
R/W
IRQ12 Sense Control B
IRQ12 Sense Control A
00: Interrupt request generated at IRQ12 input low
level
01: Interrupt request generated at falling edge of
IRQ12 input
10: Interrupt request generated at rising edge of
IRQ12 input
11: Interrupt request generated at both falling and
rising edges of IRQ12 input
7
6
IRQ11SCB
IRQ11SCA
0
0
R/W
R/W
IRQ11 Sense Control B
IRQ11 Sense Control A
00: Interrupt request generated at IRQ11 input low
level
01: Interrupt request generated at falling edge of
IRQ11 input
10: Interrupt request generated at rising edge of
IRQ11 input
11: Interrupt request generated at both falling and
rising edges of IRQ11 input
5
4
IRQ10SCB
IRQ10SCA
0
0
R/W
R/W
IRQ10 Sense Control B
IRQ10 Sense Control A
00: Interrupt request generated at IRQ10 input low
level
01: Interrupt request generated at falling edge of
IRQ10 input
10: Interrupt request generated at rising edge of
IRQ10 input
11: Interrupt request generated at both falling and
rising edges of IRQ10 input
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
3
2
IRQ9SCB
IRQ9SCA
0
0
R/W
R/W
IRQ9 Sense Control B
IRQ9 Sense Control A
00: Interrupt request generated at IRQ9 input low
level
01: Interrupt request generated at falling edge of
IRQ9 input
10: Interrupt request generated at rising edge of
IRQ9 input
11: Interrupt request generated at both falling and
rising edges of IRQ9 input
1
0
IRQ8SCB
IRQ8SCA
0
0
R/W
R/W
IRQ8 Sense Control B
IRQ8 Sense Control A
00: Interrupt request generated at IRQ8 input low
level
01: Interrupt request generated at falling edge of
IRQ8 input
10: Interrupt request generated at rising edge of
IRQ8 input
11: Interrupt request generated at both falling and
rising edges of IRQ8 input
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Section 5 Interrupt Controller
• ISCRL
Bit
Bit Name
Initial Value
R/W
Description
15
14
IRQ7SCB
IRQ7SCA
0
0
R/W
R/W
IRQ7 Sense Control B
IRQ7 Sense Control A
00: Interrupt request generated at IRQ7 input low
level
01: Interrupt request generated at falling edge of
IRQ7 input
10: Interrupt request generated at rising edge of
IRQ7 input
11: Interrupt request generated at both falling and
rising edges of IRQ7 input
13
12
IRQ6SCB
IRQ6SCA
0
0
R/W
R/W
IRQ6 Sense Control B
IRQ6 Sense Control A
00: Interrupt request generated at IRQ6 input low
level
01: Interrupt request generated at falling edge of
IRQ6 input
10: Interrupt request generated at rising edge of
IRQ6 input
11: Interrupt request generated at both falling and
rising edges of IRQ6 input
11
10
IRQ5SCB
IRQ5SCA
0
0
R/W
R/W
IRQ5 Sense Control B
IRQ5 Sense Control A
00: Interrupt request generated at IRQ5 input low
level
01: Interrupt request generated at falling edge of
IRQ5 input
10: Interrupt request generated at rising edge of
IRQ5 input
11: Interrupt request generated at both falling and
rising edges of IRQ5 input
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
9
8
IRQ4SCB
IRQ4SCA
0
0
R/W
R/W
IRQ4 Sense Control B
IRQ4 Sense Control A
00: Interrupt request generated at IRQ4 input low
level
01: Interrupt request generated at falling edge of
IRQ4 input
10: Interrupt request generated at rising edge of
IRQ4 input
11: Interrupt request generated at both falling and
rising edges of IRQ4 input
7
6
IRQ3SCB
IRQ3SCA
0
0
R/W
R/W
IRQ3 Sense Control B
IRQ3 Sense Control A
00: Interrupt request generated at IRQ3 input low
level
01: Interrupt request generated at falling edge of
IRQ3 input
10: Interrupt request generated at rising edge of
IRQ3 input
11: Interrupt request generated at both falling and
rising edges of IRQ3 input
5
4
IRQ2SCB
IRQ2SCA
0
0
R/W
R/W
IRQ2 Sense Control B
IRQ2 Sense Control A
00: Interrupt request generated at IRQ2 input low
level
01: Interrupt request generated at falling edge of
IRQ2 input
10: Interrupt request generated at rising edge of
IRQ2 input
11: Interrupt request generated at both falling and
rising edges of IRQ2 input
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
3
2
IRQ1SCB
IRQ1SCA
0
0
R/W
R/W
IRQ1 Sense Control B
IRQ1 Sense Control A
00: Interrupt request generated at IRQ1 input low
level
01: Interrupt request generated at falling edge of
IRQ1 input
10: Interrupt request generated at rising edge of
IRQ1 input
11: Interrupt request generated at both falling and
rising edges of IRQ1 input
1
0
IRQ0SCB
IRQ0SCA
0
0
R/W
R/W
IRQ0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request generated at IRQ0 input low
level
01: Interrupt request generated at falling edge of
IRQ0 input
10: Interrupt request generated at rising edge of
IRQ0 input
11: Interrupt request generated at both falling and
rising edges of IRQ0 input
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Section 5 Interrupt Controller
5.3.5
IRQ Status Register (ISR)
ISR is an IRQ15 to IRQ0 interrupt request flag register.
Bit
Bit Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRQ15F
IRQ14F
IRQ13F
IRQ12F
IRQ11F
IRQ10F
IRQ9F
IRQ8F
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Note:
*
Initial Value
R/W
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
[Setting condition]
When the interrupt source selected by ISCR occurs
[Clearing conditions]
•
Cleared by reading IRQnF flag when IRQnF =
1, then writing 0 to IRQnF flag
•
When interrupt exception handling is executed
when low-level detection is set and IRQn input
is high
•
When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
•
When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the DTC
is cleared to 0
(n = 15 to 0)
Only 0 can be written, to clear the flag.
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Section 5 Interrupt Controller
5.3.6
IRQ Pin Select Register (ITSR)
ITSR selects input pins IRQ15 to IRQ0.
Bit
Bit Name
Initial Value
R/W
15
ITS15
0
R/W
Description
Selects IRQ15 input pin.
0: PF2
1: P27
14
ITS14
0
R/W
Selects IRQ14 input pin.
0: PF1
1: P26
13
ITS13
0
R/W
Selects IRQ13 input pin.
0: P65
1: P25
12
ITS12
0
R/W
Selects IRQ12 input pin.
0: P64
1: P24
11
ITS11
0
R/W
Selects IRQ11 input pin.
0: P63
1: P23
10
ITS10
0
R/W
Selects IRQ10 input pin.
0: P62
1: P22
9
ITS9
0
R/W
Selects IRQ9 input pin.
0: P61
1: P21
8
ITS8
0
R/W
Selects IRQ8 input pin.
0: P60
1: P20
7
ITS7
0
R/W
Selects IRQ7 input pin.
0: PA7
1: PH3
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
6
ITS6
0
R/W
Selects IRQ6 input pin.
0: PA6
1: PH2
5
ITS5
0
R/W
Selects IRQ5 input pin.
0: PA5
1: P85
4
ITS4
0
R/W
Selects IRQ4 input pin.
0: PA4
1: P84
3
ITS3
0
R/W
Selects IRQ3 input pin.
0: P53
1: P83
2
ITS2
0
R/W
Selects IRQ2 input pin.
0: P52
1: P82
1
ITS1
0
R/W
Selects IRQ1 input pin.
0: P51
1: P81
0
ITS0
0
R/W
Selects IRQ0 input pin.
0: P50
1: P80
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Section 5 Interrupt Controller
5.3.7
Software Standby Release IRQ Enable Register (SSIER)
SSIER selects the IRQ pins used to recover from the software standby state.
Bit
Bit Name
Initial Value
R/W
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSI15
SSI14
SSI13
SSI12
SSI11
SSI10
SSI9
SSI8
SSI7
SSI6
SSI5
SSI4
SSI3
SSI2
SSI1
SSI0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Software Standby Release IRQ Setting
These bits select the IRQn pins used to recover
from the software standby state.
0: IRQn requests are not sampled in the software
standby state (Initial value when n = 15 to 3)
1: When an IRQn request occurs in the software
standby state, the chip recovers from the
software standby state after the elapse of the
oscillation settling time (Initial value when n = 2
to 0)
(n = 15 to 0)
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Section 5 Interrupt Controller
5.4
Interrupt Sources
5.4.1
External Interrupts
There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to
restore the chip from software standby mode.
NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is
always accepted by the CPU regardless of the interrupt control mode or the status of the CPU
interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is
requested at a rising edge or a falling edge on the NMI pin.
IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins
IRQ15 to IRQ0. Interrupts IRQ15 to IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ15 to IRQ0.
• Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to
0 by software.
When IRQ15 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ
should be held low until an interrupt handling starts. Then the corresponding IRQ should be set to
high in the interrupt handling routine and clear the IRQnF bit (n = 0 to 15) in ISR to 0. Interrupts
may not be executed when the corresponding IRQ is set to high before the interrupt handling
starts.
Detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been set
for input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2.
Rev.7.00 Mar. 18, 2009 page 120 of 1136
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Section 5 Interrupt Controller
IRQnE
IRQnSCA, IRQnSCB
IRQnF
Edge/
level detection
circuit
IRQn
input
S
Q
IRQn interrupt
request
R
Clear signal
Note: n = 15 to 0
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0
5.4.2
Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.
• The interrupt priority level can be set by means of IPR.
• The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request.
• When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt
control mode or CPU interrupt mask bit.
5.5
Interrupt Exception Handling Vector Table
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. When interrupt control
mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
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Section 5 Interrupt Controller
Table 5.2
Interrupt
Source
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt
Source
External pin NMI
IRQ0
Vector
Address*1
Vector
Number
Advanced
Mode
IPR
Priority
DTC
DMAC
Activation Activation
7
H'001C
⎯
High
⎯
16
H'0040
IPRA14 to IPRA12
⎯
⎯
IRQ1
17
H'0044
IPRA10 to IPRA8
⎯
IRQ2
18
H'0048
IPRA6 to IPRA4
⎯
IRQ3
19
H'004C
IPRA2 to IPRA0
⎯
IRQ4
20
H'0050
IPRB14 to IPRB12
⎯
IRQ5
21
H'0054
IPRB10 to IPRB8
⎯
IRQ6
22
H'0058
IPRB6 to IPRB4
⎯
IRQ7
23
H'005C
IPRB2 to IPRB0
⎯
IRQ8
24
H'0060
IPRC14 to IPRC12
⎯
IRQ9
25
H'0064
IPRC10 to IPRC8
⎯
IRQ10
26
H'0068
IPRC6 to IPRC4
⎯
IRQ11
27
H'006C
IPRC2 to IPRC0
⎯
IRQ12
28
H'0070
IPRD14 to IPRD12
⎯
IRQ13
29
H'0074
IPRD10 to IPRD8
⎯
IRQ14
30
H'0078
IPRD6 to IPRD4
⎯
IRQ15
31
H'007C
IPRD2 to IPRD0
⎯
DTC
SWDTEND
32
H'0080
IPRE14 to IPRE12
⎯
WDT
WOVI
33
H'0084
IPRE10 to IPRE8
⎯
⎯
⎯
Reserved for
system use
34
H'0088
IPRE6 to IPRE4
⎯
⎯
Refresh
controller
CMI
35
H'008C
IPRE2 to IPRE0
⎯
⎯
⎯
Reserved for
system use
36
H'0090
IPRF14 to IPRF12
⎯
⎯
37
H'0094
⎯
⎯
A/D
ADI
38
H'0098
Reserved for
system use
39
H'009C
⎯
⎯
Rev.7.00 Mar. 18, 2009 page 122 of 1136
REJ09B0109-0700
IPRF10 to IPRF8
Low
Section 5 Interrupt Controller
Vector
Address*1
Interrupt
Source
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
Priority
TPU_0
TGI0A
40
H'00A0
IPRF6 to IPRF4
High
TGI0B
41
H'00A4
⎯
TGI0C
42
H'00A8
⎯
TGI0D
43
H'00AC
TCI0V
44
H'00B0
⎯
⎯
Reserved for
system use
45
H'00B4
⎯
⎯
46
H'00B8
⎯
⎯
47
H'00BC
⎯
⎯
TPU_1
TPU_2
TPU_3
DTC
DMAC
Activation Activation
⎯
IPRF6 to IPRF4
TGI1A
48
H'00C0
TGI1B
49
H'00C4
IPRF2 to IPRF0
TCI1V
50
H'00C8
⎯
⎯
TCI1U
51
H'00CC
⎯
⎯
TGI2A
52
H'00D0
TGI2B
53
H'00D4
TCI2V
54
H'00D8
⎯
⎯
TCI2U
55
H'00DC
⎯
⎯
TGI3A
56
H'00E0
TGI3B
57
H'00E4
⎯
TGI3C
58
H'00E8
⎯
TGI3D
59
H'00EC
⎯
TCI3V
60
H'00F0
⎯
⎯
Reserved for
system use
61
H'00F4
⎯
⎯
62
H'00F8
⎯
⎯
63
H'00FC
⎯
⎯
⎯
IPRG14 to IPRG12
⎯
IPRG10 to IPRG8
Low
Rev.7.00 Mar. 18, 2009 page 123 of 1136
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Section 5 Interrupt Controller
Vector
Address*1
Interrupt
Source
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
Priority
TPU_4
TGI4A
64
H'0100
IPRG6 to IPRG4
High
TGI4B
65
H'0104
TCI4V
66
H'0108
⎯
⎯
TCI4U
67
H'010C
⎯
⎯
TGI5A
68
H'0110
TGI5B
69
H'0114
TCI5V
70
H'0118
⎯
⎯
⎯
⎯
TPU_5
DTC
DMAC
Activation Activation
⎯
IPRG2 to IPRG0
⎯
TCI5U
71
H'011C
CMIA0
72
H'0120
CMIB0
73
H'0124
OVI0
74
H'0128
Reserved for
system use
75
H'012C
IPRH14 to IPRH12
CMIA1
76
H'0130
IPRH10 to IPRH8
CMIB1
77
H'0134
OVI1
78
H'0138
⎯
⎯
Reserved for
system use
79
H'013C
⎯
⎯
DMTEND0A
80
H'0140
DMTEND0B
81
H'0144
⎯
DMTEND1A
82
H'0148
⎯
DMTEND1B
83
H'014C
⎯
EXDMAC*2 Reserved for
system use
84
H'0150
IPRH0 to IPRH0
⎯
⎯
85
H'0154
IPRI14 to IPRI12
⎯
⎯
EXDMTEND2
86
H'0158
IPRI10 to IPRI8
⎯
⎯
EXDMTEND3
87
H'015C
IPRI6 to IPRI4
⎯
⎯
TMR_0
TMR_1
DMAC
Rev.7.00 Mar. 18, 2009 page 124 of 1136
REJ09B0109-0700
⎯
IPRH14 to IPRH12
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
IPRH6 to IPRH4
Low
Section 5 Interrupt Controller
Vector
Address*1
Interrupt
Source
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
Priority
DTC
DMAC
Activation Activation
SCI_0
ERI0
88
H'0160
IPRI2 to IPRI0
High
⎯
⎯
RXI0
89
H'0164
TXI0
90
H'0168
TEI0
91
H'016C
⎯
⎯
ERI1
92
H'0170
⎯
⎯
RXI1
93
H'0174
TXI1
94
H'0178
TEI1
95
H'017C
⎯
⎯
ERI2
96
H'0180
⎯
⎯
RXI2
97
H'0184
⎯
TXI2
98
H'0188
⎯
TEI2
99
H'018C
ERI3
100
H'0190
RXI3
101
H'0194
TXI3
102
H'0198
SCI_1
SCI_2
SCI_3
SCI_4
IPRJ14 to IPRJ12
IPRJ10 to IPRJ8
IPRJ6 to IPRJ4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TEI3
103
H'019C
ERI4
104
H'01A0
RXI4
105
H'01A4
⎯
TXI4
106
H'01A8
⎯
TEI4
107
H'01AC
Reserved for
system use
108
H'01B0
109
110
⎯
IPRJ2 to IPRJ0
⎯
⎯
⎯
⎯
⎯
H'01B4
⎯
⎯
H'01B8
⎯
⎯
111
H'01BC
⎯
⎯
112
H'01C0
⎯
⎯
⎯
⎯
113
IPRK14 to IPRK12
IPRK10 to IPRK8
H'01C4
114
H'01C8
115
H'01CC
Low
⎯
⎯
⎯
⎯
Rev.7.00 Mar. 18, 2009 page 125 of 1136
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Section 5 Interrupt Controller
Vector
Address*1
Interrupt
Source
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
Priority
DTC
DMAC
Activation Activation
IIC2
IICI0
116
H'01D0
IPRK6 to IPRK4
High
⎯
⎯
Reserved for
system use
117
H'01D4
⎯
⎯
IICI1
118
H'01D8
⎯
⎯
Reserved for
system use
119
H'01DC
⎯
⎯
Reserved for
system use
120
H'01E0
⎯
⎯
121
H'01E4
⎯
⎯
122
H'01E8
⎯
⎯
123
H'01EC
⎯
⎯
124
H'01F0
⎯
⎯
125
H'01F4
⎯
⎯
126
H'01F8
127
H'01EC
IPRK2 to IPRK0
Low
⎯
⎯
⎯
⎯
Notes: 1. Lower 16 bits of the start address.
2. Not supported for the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Rev.7.00 Mar. 18, 2009 page 126 of 1136
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Section 5 Interrupt Controller
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 5.3
Interrupt Control Modes
Interrupt Control Priority Setting
Mode
Registers
Interrupt
Mask Bits
0
Default
I
The priorities of interrupt sources are fixed at
the default settings.
Interrupt sources except for NMI is masked by
the I bit.
2
IPR
I2 to I0
8 priority levels except for NMI can be set with
IPR.
8-level interrupt mask control is performed by
bits I2 to I0.
5.6.1
Description
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit of CCR in the
CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
pending. If the I bit is cleared, an interrupt request is accepted.
3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
the priority system is accepted, and other interrupt requests are held pending.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
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Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program execution status
No
Interrupt generated?
Yes
Yes
NMI
No
I=0
No
Hold
pending
Yes
No
IRQ0
No
Yes
IRQ1
Yes
IICI1
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0
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Section 5 Interrupt Controller
5.6.2
Interrupt Control Mode 2
In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for
NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.
Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.2 is selected.
3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
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Section 5 Interrupt Controller
Program execution status
Interrupt generated?
No
Yes
Yes
NMI
No
Level 7 interrupt?
No
Yes
Mask level 6
or below?
Level 6 interrupt?
No
No
Yes
Level 1 interrupt?
Yes
Mask level 5
or below?
No
No
Yes
Yes
Mask level 0?
No
Yes
Save PC, CCR, and EXR
Hold
pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2
5.6.3
Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Rev.7.00 Mar. 18, 2009 page 130 of 1136
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(1)
(2)
(4)
(3)
Internal
operation
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
(2) (4) Instruction code (Not executed.)
(3)
Instruction prefetch address (Not executed.)
(5)
SP-2
(7)
SP-4
(1)
Internal
data bus
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
φ
Interrupt level determination Instruction
Wait for end of instruction
prefetch
Interrupt
acceptance
(7)
(8)
(10)
(9)
Vector fetch
(12)
(11)
(14)
(13)
Interrupt handling
routine instruction
prefetch
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (Vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling routine
(6)
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(5)
stack
Internal
operation
Section 5 Interrupt Controller
Figure 5.5 Interrupt Exception Handling
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Section 5 Interrupt Controller
5.6.4
Interrupt Response Times
Table 5.4 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.4 are explained in table 5.5.
This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip
ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 5.4
Interrupt Response Times
5
Normal Mode*
Advanced Mode
Interrupt
control
mode 0
Interrupt
control
mode 2
Interrupt
control
mode 0
Interrupt
control
mode 2
3
3
3
3
No.
Execution Status
1
Interrupt priority determination*
2
Number of wait states until executing 1 to 19 +2·SI 1 to 19+2·SI
2
instruction ends*
1 to 19+2·SI 1 to 19+2·SI
3
PC, CCR, EXR stack save
2·SK
3·SK
2·SK
3·SK
4
Vector fetch
SI
SI
2·SI
2·SI
5
3
Instruction fetch*
6
Internal processing*
1
4
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
5.
2·SI
2·SI
2·SI
2·SI
2
2
2
2
11 to 31
12 to 32
12 to 32
13 to 33
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and interrupt handling routine prefetch.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Not available in this LSI.
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Section 5 Interrupt Controller
Table 5.5
Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8 Bit Bus
16 Bit Bus
Symbol
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch SI
1
4
6+2m
2
3+m
Branch address read SJ
Stack manipulation SK
Legend:
m: Number of wait states in an external device access.
5.6.5
DTC and DMAC Activation by Interrupt
The DTC and DMAC can be activated by an interrupt. In this case, the following options are
available:
• Interrupt request to CPU
• Activation request to DTC
• Activation request to DMAC
• Selection of a number of the above
For details of interrupt requests that can be used to activate the DTC and DMAC, see table 5.2 and
section 9, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC).
Rev.7.00 Mar. 18, 2009 page 133 of 1136
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Section 5 Interrupt Controller
5.7
Usage Notes
5.7.1
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt
source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in the TPU’s
TIER_0 register is cleared to 0. The above conflict will not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
TIER_0 write cycle by CPU
TCIV exception handling
φ
Internal
address bus
TIER_0 address
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Figure 5.6 Conflict between Interrupt Generation and Disabling
Rev.7.00 Mar. 18, 2009 page 134 of 1136
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Section 5 Interrupt Controller
5.7.2
Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3
Times when Interrupts Are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
5.7.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1:
5.7.5
EEPMOV.W
MOV.W
R4,R4
BNE
L1
Change of IRQ Pin Select Register (ITSR) Setting
When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 15) of
ISR may be set to 1 at the unintended timing if the selected pin level before the change is different
from the selected pin level after the change. If the IRQn interrupt request (n = 0 to 15) is enabled,
the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR setting
should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be
cleared to 0.
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Section 5 Interrupt Controller
5.7.6
IRQ Status Register (ISR)
Depending on the pin status following a reset, IRQnF may be set to 1. Therefore, always read ISR
and clear it to 0 after resets.
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Section 6 Bus Controller (BSC)
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
mastership⎯the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)*, and data
transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1.
Note: * The EXDMAC is not supported by the H8S/2375, H8S/2375R, H8S/2373, and
H8S/2373R.
6.1
Features
• Manages external address space in area units
Manages the external address space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM, DRAM, or synchronous DRAM interface* can be set
• Basic bus interface
Chip select signals (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
• Burst ROM interface
Burst ROM interface can be set independently for areas 0 and 1
• DRAM interface
DRAM interface can be set for areas 2 to 5
• Synchronous DRAM interface*
Continuous synchronous DRAM space can be set for areas 2 to 5
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, DTC, and
EXDMAC
Note: * The Synchronous DRAM interface is not supported by the H8S/2378 Group.
BSCS201A_010020020400
Rev.7.00 Mar. 18, 2009 page 137 of 1136
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Section 6 Bus Controller (BSC)
EXDMAC address bus
Internal address bus
Address
selector
CS7 to CS0
Area decoder
WAIT
BREQ
BACK
BREQO
External bus controller
Internal bus master bus request signal
EXDMAC bus request signal
Internal bus master bus acknowledge signal
EXDMAC bus acknowledge signal
External bus
arbiter
External bus
control signals
Internal bus control signals
Internal bus controller
CPU bus request signal
DTC bus request signal
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
Internal bus
arbiter
Control registers
Internal data bus
ABWCR
ASTCR
WTCRAH WTCRAL
DRAMCR
DRACCR*
DRACCRH
DRACCRL
WTCRBH WTCRBL
RDNCR
CSACRH
REFCR
RTCNT
RTCOR
CSACRL
BROMCRH BROMCRL
BCR
Legend:
ABWCR
ASTCR
WTCRAH, WTCRAL,
WTCRBH, and WTCRBL
RDNCR
CSACRH and CSACRL
BROMCRH
BROMCRL : Area 1 burst ROM interface control register
BCR
: Bus control register
DRAMCR : DRAM control register
DRACCR : DRAM access control register
: Wait control registers AH, AL, BH, and BL
REFCR
: Refresh control register
: Read strobe timing control register
: Refresh timer counter
: CS assertion period control registers H and L RTCNT
RTCOR
: Refresh time constant register
: Area 0 burst ROM interface control register
: Bus width control register
: Access state control register
Figure 6.1 Block Diagram of Bus Controller
Rev.7.00 Mar. 18, 2009 page 138 of 1136
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Section 6 Bus Controller (BSC)
6.2
Input/Output Pins
Table 6.1 shows the pin configuration of the bus controller.
Table 6.1
Pin Configuration
Name
Symbol
I/O
Function
Address strobe
AS
Output
Strobe signal indicating that normal space
is accessed and address output on
address bus is enabled.
Read
RD
Output
Strobe signal indicating that normal space
is being read.
High write/write enable
HWR/WE
Output
Strobe signal indicating that normal space
is written to, and upper half (D15 to D8) of
data bus is enabled or DRAM space write
enable signal.
Low write
LWR
Output
Strobe signal indicating that normal space
is written to, and lower half (D7 to D0) of
data bus is enabled.
Chip select 0
CS0
Output
Strobe signal indicating that area 0 is
selected.
Chip select 1
CS1
Output
Strobe signal indicating that area 1 is
selected
Chip select 2/
row address strobe 2/
1
row address strobe*
CS2/
RAS2/
1
RAS*
Output
Strobe signal indicating that area 2 is
selected, DRAM row address strobe signal
when area 2 is DRAM space or areas 2 to
5 are set as continuous DRAM space, or
row address strobe signal of the
synchronous DRAM when the
synchronous DRAM interface is selected.
Chip select 3/
row address strobe 3/
1
column address strobe*
CS3/
RAS3/
1
CAS*
Output
Strobe signal indicating that area 3 is
selected, DRAM row address strobe signal
when area 3 is DRAM space, or column
address strobe signal of the synchronous
DRAM when the synchronous DRAM
interface is selected.
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Section 6 Bus Controller (BSC)
Name
Symbol
I/O
Function
Chip select 4/
row address strobe 4/
1
write enable*
CS4/
RAS4/
1
WE*
Output
Strobe signal indicating that area 4 is
selected, DRAM row address strobe signal
when area 4 is DRAM space, or write
enable signal of the synchronous DRAM
when the synchronous DRAM interface is
selected.
Chip select 5/
row address strobe 5/
1
SDRAMφ*
Output
CS5/
RAS5/
1
SDRAMφ*
Strobe signal indicating that area 5 is
selected, DRAM row address strobe signal
when area 5 is DRAM space, or dedicated
clock signal for the synchronous DRAM
when the synchronous DRAM interface is
selected.
Chip select 6
CS6
Output
Strobe signal indicating that area 6 is
selected.
Chip select 7
CS7
Output
Strobe signal indicating that area 7 is
selected.
Upper column address strobe/
1
upper data mask enable*
UCAS/
1
DQMU*
Output
16-bit DRAM space upper column address
strobe signal, 8-bit DRAM space column
address strobe signal, upper data mask
signal of 16-bit synchronous DRAM space,
or data mask signal of 8-bit synchronous
DRAM space.
Lower column address strobe/
1
lower data mask enable*
LCAS/
1
DQML*
Output
16-bit DRAM space lower column address
strobe signal or lower data mask signal for
the 16-bit synchronous DRAM space.
Output enable/clock enable
OE/
1
CKE*
Output
Output enable signal for the DRAM space
or clock enable signal for the synchronous
DRAM space.
Wait
WAIT
Input
Wait request signal when accessing
external address space.
Bus request
BREQ
Input
Request signal for release of bus to
external bus master.
Bus request acknowledge
BACK
Output
Acknowledge signal indicating that bus has
been released to external bus master.
Bus request output
BREQO
Output
External bus request signal used when
internal bus master accesses external
address space when external bus is
released.
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Section 6 Bus Controller (BSC)
Name
Symbol
I/O
Function
Data transfer acknowledge 1
(DMAC)
DACK1
Output
Data transfer acknowledge signal for
single address transfer by DMAC channel
1.
Data transfer acknowledge 0
(DMAC)
DACK0
DACK0
Data transfer acknowledge signal for
single address transfer by DMAC channel
0.
EDACK3*
Output
Data transfer acknowledge signal for
single address transfer by EXDMAC
channel 3.
EDACK2*
Output
Data transfer acknowledge signal for
single address transfer by EXDMAC
channel 2.
2
Data transfer acknowledge 3*
(EXDMAC)
2
Data transfer acknowledge 2*
(EXDMAC)
2
2
Notes: 1. Not supported by the H8S/2378 Group.
2. Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
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Section 6 Bus Controller (BSC)
6.3
Register Descriptions
The bus controller has the following registers.
• Bus width control register (ABWCR)
• Access state control register (ASTCR)
• Wait control register AH (WTCRAH)
• Wait control register AL (WTCRAL)
• Wait control register BH (WTCRBH)
• Wait control register BL (WTCRBL)
• Read strobe timing control register (RDNCR)
• CS assertion period control register H (CSACRH)
• CS assertion period control register L (CSACRL)
• Area 0 burst ROM interface control register (BROMCRH)
• Area 1 burst ROM interface control register (BROMCRL)
• Bus control register (BCR)
• DRAM control register (DRAMCR)
• DRAM access control register (DRACCR)
• Refresh control register (REFCR)
• Refresh timer counter (RTCNT)
• Refresh time constant register (RTCOR)
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Section 6 Bus Controller (BSC)
6.3.1
Bus Width Control Register (ABWCR)
ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.
Bit
Bit Name
Initial Value*
R/W
Description
7
6
5
4
3
2
1
0
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 Bus Width Control
Note:
*
6.3.2
These bits select whether the corresponding
area is to be designated as 8-bit access space
or 16-bit access space.
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
(n = 7 to 0)
In modes 2 and 4, ABWCR is initialized to 1. In modes 1 and 7, ABWCR is initialized
to 0.
Access State Control Register (ASTCR)
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 Access State Control
These bits select whether the corresponding
area is to be designated as 2-state access
space or 3-state access space. Wait state
insertion is enabled or disabled at the same
time.
0: Area n is designated as 2-state access space
Wait state insertion in area n access is
disabled
1: Area n is designated as 3-state access space
Wait state insertion in area n access is
enabled
(n = 7 to 0)
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Section 6 Bus Controller (BSC)
6.3.3
Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH,
and WTCRBL)
WTCRA and WTCRB select the number of program wait states for each area in the external
address space.
In addition, CAS latency is set when a synchronous DRAM is connected.
• WTCRAH
Bit
Bit Name
Initial Value
R/W
Description
15
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
14
13
12
W72
W71
W70
1
1
1
R/W
R/W
R/W
Area 7 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 7 while AST7 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
11
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
9
8
W62
W61
W60
1
1
1
R/W
R/W
R/W
Area 6 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 6 while AST6 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
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Section 6 Bus Controller (BSC)
• WTCRAL
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
6
5
4
W52
W51
W50
1
1
1
R/W
R/W
R/W
Area 5 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 5 while AST5 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
3
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
2
1
0
W42
W41
W40
1
1
1
R/W
R/W
R/W
Area 4 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 4 while AST4 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
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Section 6 Bus Controller (BSC)
• WTCRBH
Bit
Bit Name
Initial Value
R/W
Description
15
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
14
13
12
W32
W31
W30
1
1
1
R/W
R/W
R/W
Area 3 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 3 while AST3 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
11
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
9
8
W22
W21
W20
1
1
1
R/W
R/W
R/W
Area 2 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 2 while AST2 bit in
ASTCR = 1.
A CAS latency is set when the synchronous DRAM
is connected*. The setting of area 2 is reflected to
the setting of areas 2 to 5. A CAS latency can be
set regardless of whether or not an ASTCR wait
state insertion is enabled.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
000: Synchronous DRAM of CAS latency 1 is
connected to areas 2 to 5.
001: Synchronous DRAM of CAS latency 2 is
connected to areas 2 to 5.
010: Synchronous DRAM of CAS latency 3 is
connected to areas 2 to 5.
011: Synchronous DRAM of CAS latency 4 is
connected to areas 2 to 5.
1×××: Setting prohibited.
Legend: ×: Don’t care.
Note: * The synchronous DRAM interface is not supported by the H8S/2378 Group.
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Section 6 Bus Controller (BSC)
• WTCRBL
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
6
5
4
W12
W11
W10
1
1
1
R/W
R/W
R/W
Area 1 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 1 while AST1 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
3
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
2
1
0
W02
W01
W00
1
1
1
R/W
R/W
R/W
Area 0 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 0 while AST0 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
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Section 6 Bus Controller (BSC)
6.3.4
Read Strobe Timing Control Register (RDNCR)
RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Strobe Timing Control 7 to 0
These bits set the negation timing of the read
strobe in a corresponding area read access.
As shown in figure 6.2, the read strobe for an area
for which the RDNn bit is set to 1 is negated one
half-state earlier than that for an area for which the
RDNn bit is cleared to 0. The read data setup and
hold time specifications are also one half-state
earlier.
0: In an area n read access, the RD is negated at
the end of the read cycle
1: In an area n read access, the RD is negated one
half-state before the end of the read cycle
(n = 7 to 0)
Bus cycle
T1
T2
T3
φ
RD
RDNn = 0
Data
RD
RDNn = 1
Data
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)
Rev.7.00 Mar. 18, 2009 page 150 of 1136
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Section 6 Bus Controller (BSC)
6.3.5
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (CSn) and address signals is to be extended. Extending the assertion period of the
CSn and address signals allows flexible interfacing to external I/O devices.
• CSACRH
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS and Address Signal Assertion Period Control 1
These bits specify whether or not the Th cycle is to
be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a onestate Th cycle, in which only the CSn and address
signals are asserted, is inserted before the normal
access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (Th) is not
extended
1: In area n basic bus interface access, the CSn
and address assertion period (Th) is extended
(n = 7 to 0)
• CSACRL
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS and Address Signal Assertion Period Control 2
These bits specify whether or not the Tt cycle
shown in figure 6.3 is to be inserted. When an area
for which the CSXTn bit is set to 1 is accessed, a
one-state Tt cycle, in which only the CSn and
address signals are asserted, is inserted after the
normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (Tt) is not
extended
1: In area n basic bus interface access, the CSn
and address assertion period (Tt) is extended
(n = 7 to 0)
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Section 6 Bus Controller (BSC)
Bus cycle
Th
T1
T2
T3
φ
Address
CS
RD
Read
Data
HWR, LWR
Write
Data
Figure 6.3 CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0)
Rev.7.00 Mar. 18, 2009 page 152 of 1136
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Tt
Section 6 Bus Controller (BSC)
6.3.6
Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL)
BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1
burst ROM interface settings can be made independently in BROMCRH and BROMCRL,
respectively.
Bit
Bit Name
Initial Value
R/W
Description
7
BSRMn
0
R/W
Burst ROM Interface Select
Selects the basic bus interface or burst ROM
interface.
0: Basic bus interface space
1: Burst ROM interface space
6
5
4
BSTSn2
BSTSn1
BSTSn0
0
0
0
R/W
R/W
R/W
Burst Cycle Select
These bits select the number of burst cycle states.
000: 1 state
001: 2 states
010: 3 states
011: 4 states
100: 5 states
101: 6 states
110: 7 states
111: 8 states
3, 2
—
All 0
R/W
Reserved
These bits are always read as 0. The initial value
should not be changed.
1
0
BSWDn1
BSWDn0
0
0
R/W
R/W
Burst Word Number Select
These bits select the number of words that can be
burst-accessed on the burst ROM interface.
00: Maximum 4 words
01: Maximum 8 words
10: Maximum 16 words
11: Maximum 32 words
(n = 1 or 0)
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Section 6 Bus Controller (BSC)
6.3.7
Bus Control Register (BCR)
BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Bit
Bit Name
Initial Value
R/W
Description
15
BRLE
0
R/W
External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
BREQ, BACK, and BREQO pins can be used as
I/O ports
1: External bus release enabled
14
BREQOE
0
R/W
BREQO Pin Enable
Controls outputting the bus request signal
(BREQO) to the external bus master in the external
bus released state, when an internal bus master
performs an external address space access, or
when a refresh request is generated.
0: BREQO output disabled
BREQO pin can be used as I/O port
1: BREQO output enabled
13
—
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
12
IDLC
1
R/W
Idle Cycle State Number Select
Specifies the number of states in the idle cycle set
by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
11
ICIS1
1
R/W
Idle Cycle Insert 1
When consecutive external read cycles are
performed in different areas, an idle cycle can be
inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
ICIS0
1
R/W
Idle Cycle Insert 0
When an external read cycle and external write
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
9
WDBE
0
R/W
Write Data Buffer Enable
The write data buffer function can be used for an
external write cycle or DMAC single address
transfer cycle.
0: Write data buffer function not used
1: Write data buffer function used
8
WAITE
0
R/W
WAIT Pin Enable
Selects enabling or disabling of wait input by the
WAIT pin.
0: Wait input by WAIT pin disabled
WAIT pin can be used as I/O port
1: Wait input by WAIT pin enabled
7
to
3
—
2
ICIS2
All 0
R/W
Reserved
These bits can be read from or written to. However,
the write value should always be 0.
0
R/W
Idle Cycle Insert 2
When an external write cycle and external read
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
1, 0
—
All 0
R/W
Reserved
These bits can be read from or written to. However,
the write value should always be 0.
Rev.7.00 Mar. 18, 2009 page 155 of 1136
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Section 6 Bus Controller (BSC)
6.3.8
DRAM Control Register (DRAMCR)
DRAMCR is used to make DRAM/synchronous DRAM interface settings.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Bit
Bit Name
Initial Value
R/W
Description
15
OEE
0
R/W
OE Output Enable
The OE signal used when EDO page mode DRAM
is connected can be output from the (OE) pin. The
OE signal is common to all areas designated as
DRAM space.
When the synchronous DRAM is connected, the
CKE signal can be output from the (OE) pin. The
CKE signal is common to the continuous
synchronous DRAM space.
0: OE/CKE signal output disabled
(OE)/(CKE) pin can be used as I/O port
1: OE/CKE signal output enabled
14
RAST
0
R/W
RAS Assertion Timing Select
Selects whether, in DRAM access, the RAS signal
is asserted from the start of the Tr cycle (rising
edge of φ) or from the falling edge of φ.
Figure 6.4 shows the relationship between the
RAST bit setting and the RAS assertion timing.
The setting of this bit applies to all areas
designated as DRAM space.
0: RAS is asserted from φ falling edge in Tr cycle
1: RAS is asserted from start of Tr cycle
13
—
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
12
CAST
0
R/W
Column Address Output Cycle Number Select
Selects whether the column address output cycle in
DRAM access comprises 3 states or 2 states. The
setting of this bit applies to all areas designated as
DRAM space.
0: Column address output cycle comprises
2 states
1: Column address output cycle comprises
3 states
11
—
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
9
8
RMTS2
RMTS1
RMTS0
0
0
0
R/W
R/W
R/W
DRAM/Continuous Synchronous DRAM Space
Select
These bits designate DRAM/continuous
synchronous DRAM space for areas 2 to 5.
When continuous DRAM space is set, it is possible
to connect large-capacity DRAM exceeding 2
Mbytes per area. In this case, the RAS signal is
output from the CS2 pin.
When continuous synchronous DRAM space is set,
it is possible to connect large-capacity synchronous
DRAM exceeding 2 Mbytes per area. In this case,
the RAS, CAS, and WE signals are output from
CS2, CS3, and CS4 pins, respectively. When
synchronous DRAM mode is set, the mode
registers of the synchronous DRAM can be set.
000: Normal space
001: Normal space in areas 3 to 5
DRAM space in area 2
010: Normal space in areas 4 and 5
DRAM space in areas 2 and 3
011: DRAM space in areas 2 to 5
100: Continuous synchronous DRAM space
(setting prohibited in the H8S/2378 Group)
101: Synchronous DRAM mode setting (setting
prohibited in the H8S/2378 Group)
110: Setting prohibited
111: Continuous DRAM space in areas 2 to 5
7
BE
0
R/W
Burst Access Enable
Selects enabling or disabling of burst access to
areas designated as DRAM/continuous
synchronous DRAM space. DRAM/continuous
synchronous DRAM space burst access is
performed in fast page mode. When using EDO
page mode DRAM, the OE signal must be
connected.
0: Full access
1: Access in fast page mode
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
6
RCDM
0
R/W
RAS Down Mode
When access to DRAM space is interrupted by an
access to normal space, an access to an internal
I/O register, etc., this bit selects whether the RAS
signal is held low while waiting for the next DRAM
access (RAS down mode), or is driven high again
(RAS up mode). The setting of this bit is valid only
when the BE bit is set to 1.
If this bit is cleared to 0 when set to 1 in the RAS
down state, the RAS down state is cleared at that
point, and RAS goes high.
When continuous synchronous DRAM space is set,
reading from and writing to this bit is enabled.
However, the setting does not affect the operation.
0: RAS up mode selected for DRAM space access
1: RAS down mode selected for DRAM space
access
5
DDS
0
R/W
DMAC Single Address Transfer Option
Selects whether full access is always performed or
burst access is enabled when DMAC single
address transfer is performed on the
DRAM/synchronous DRAM.
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst access,
DMAC single address transfer is performed in full
access mode regardless of the setting of this bit.
This bit has no effect on other bus master external
accesses or DMAC dual address transfers.
0: Full access is always executed
1: Burst access is enabled
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
4
EDDS
0
R/W
EXDMAC Single Address Transfer Option
Selects whether full access is always performed or
burst access is enabled when EXDMAC single
address transfer is performed on the
DRAM/synchronous DRAM.
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst access,
EXDMAC single address transfer is performed in
full access mode regardless of the setting of this
bit.
This bit has no effect on other bus master external
accesses or EXDMAC dual address transfers.
0: Full access is always executed
1: Burst access is enabled
3
—
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
2
1
0
MXC2
MXC1
MXC0
0
0
0
R/W
R/W
R/W
Address Multiplex Select
These bits select the size of the shift toward the
lower half of the row address in row
address/column address multiplexing. In burst
operation on the DRAM/synchronous DRAM
interface, these bits also select the row address
bits to be used for comparison.
When the MXC2 bit is set to 1 while continuous
synchronous DRAM space is set, the address
precharge setting command (Precharge-sel) is
output to the upper column address. For details,
refer to sections 6.6.2 and 6.7.2, Address
Multiplexing.
DRAM interface
000: 8-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A8 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A9 used for
comparison
001: 9-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A9 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A10 used for
comparison
010: 10-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A10 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A11 used for
comparison
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
2
1
0
MXC2
MXC1
MXC0
0
0
0
R/W
R/W
R/W
011: 11-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A11 used for
comparison
When 16-bit access space is designated:
Row address bits A23 to A12 used for
comparison
Synchronous DRAM interface
100: 8-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A8 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A9 used for
comparison
The precharge-sel is A15 to A9 of the column
address.
101: 9-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A9 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A10 used for
comparison
The precharge-sel is A15 to A10 of the column
address.
110: 10-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A10 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A11 used for
comparison
The precharge-sel is A15 to A11 of the column
address.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
2
1
0
MXC2
MXC1
MXC0
0
0
0
R/W
R/W
R/W
111: 11-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A11 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A12 used for
comparison
The precharge-sel is A15 to A12 of the column
address.
Bus cycle
Tp
Tr
Tc1
Tc2
φ
Row address
Address
Column address
RAST = 0 RAS
RAST = 1 RAS
UCAS, LCAS
Figure 6.4 RAS Signal Assertion Timing
(2-State Column Address Output Cycle, Full Access)
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Section 6 Bus Controller (BSC)
6.3.9
DRAM Access Control Register (DRACCR)
DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Bit
Bit Name
Initial Value
R/W
Description
15
DRMI
0
R/W
Idle Cycle Insertion
An idle cycle can be inserted after a
DRAM/synchronous DRAM access cycle when a
continuous normal space access cycle follows a
DRAM/synchronous DRAM access cycle. Idle cycle
insertion conditions, setting of number of states,
etc., comply with settings of bits ICIS2, ICIS1,
ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
14
—
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
13
12
TPC1
TPC0
0
0
R/W
R/W
Precharge State Control
These bits select the number of states in the RAS
precharge cycle in normal access and refreshing.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
11
SDWCD
0*
R/W
CAS Latency Control Cycle Disabled during
Continuous Synchronous DRAM Space Write
Access
Disables CAS latency control cycle (Tcl) inserted
by WTCRB (H) settings during synchronous DRAM
write access (see figure 6.5).
0: Enables CAS latency control cycle
1: Disables CAS latency control cycle
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
9
8
RCD1
RCD0
0
0
R/W
R/W
RAS-CAS Wait Control
These bits select a wait cycle to be inserted
between the RAS assert cycle and CAS assert
cycle. A 1- to 4-state wait cycle can be inserted.
00: Wait cycle not inserted
01: 1-state wait cycle inserted
10: 2-state wait cycle inserted
11: 3-state wait cycle inserted
7 to 4 ⎯
All 0
R/W
Reserved
These bits can be read from or written to. However,
the write value should always be 0.
3
CKSPE*
0
R/W
Clock Suspend Enable
Enables clock suspend mode for extend read data
during DMAC and EXDMAC single address
transfer with the synchronous DRAM interface.
0: Disables clock suspend mode
1: Enables clock suspend mode
2
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
1
0
RDXC1*
RDXC0*
0
0
R/W
R/W
Read Data Extension Cycle Number Selection
Selects the number of read data extension cycle
(Tsp) insertion state in clock suspend mode. These
bits are valid when the CKSPE bit is set to 1.
00: Inserts 1 state
01: Inserts 2 state
10: Inserts 3 state
11: Inserts 4 state
Note:
*
Not used in the H8S/2378 Group. Do not change the initial value.
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address
Precharge-sel
Column address
Row address
Row address
RAS
SDWCD 0
CAS
WE
CKE
High
DQMU, DQML
Data bus
Address bus
PALL
ACTV
NOP
WRIT
Tp
Tr
Tc1
Tc2
Column address
Precharge-sel
Row address
NOP
Column address
Row address
RAS
SDWCD 1
CAS
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous
DRAM Space Write Access (for CAS Latency 2)
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Section 6 Bus Controller (BSC)
6.3.10
Refresh Control Register (REFCR)
REFCR specifies DRAM/synchronous DRAM interface refresh control.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Bit
Bit Name
Initial Value
R/W
Description
15
CMF
0
R/(W)*
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
•
When 0 is written to CMF after reading CMF = 1
while the RFSHE bit is cleared to 0
•
When CBR refreshing is executed while the
RFSHE bit is set to 1
[Setting condition]
When RTCOR = RTCNT
14
CMIE
0
R/W
Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by the
CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is performed,
this bit is always cleared to 0 and cannot be
modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
13
12
RCW1
RCW0
0
0
R/W
R/W
CAS-RAS Wait Control
These bits select the number of wait cycles to be
inserted between the CAS assert cycle and RAS
assert cycle in a DRAM/synchronous DRAM
refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
Note:
*
Only 0 can be written, to clear the flag.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
11
—
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
10
9
8
RTCK2
RTCK1
RTCK0
0
0
0
R/W
R/W
R/W
Refresh Counter Clock Select
These bits select the clock to be used to increment
the refresh counter. When the input clock is
selected with bits RTCK2 to RTCK0, the refresh
counter begins counting up.
000: Count operation halted
001: Count on φ/2
010: Count on φ/8
011: Count on φ/32
100: Count on φ/128
101: Count on φ/512
110: Count on φ/2048
111: Count on φ/4096
7
RFSHE
0
R/W
Refresh Control
Refresh control can be performed. When refresh
control is not performed, the refresh timer can be
used as an interval timer.
0: Refresh control is not performed
1: Refresh control is performed
6
CBRM
0
R/W
CBR Refresh Mode
Selects CBR refreshing performed in parallel with
other external accesses, or execution of CBR
refreshing alone.
When the continuous synchronous DRAM space is
set, this bit can be read/written, but the setting
contents do not affect operations.
0: External access during CAS-before-RAS
refreshing is enabled
1: External access during CAS-before-RAS
refreshing is disabled
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
5
4
RLW1
RLW0
0
0
R/W
R/W
Refresh Cycle Wait Control
These bits select the number of wait states to be
inserted in a DRAM interface CAS-before-RAS
refresh cycle/synchronous DRAM interface autorefresh cycle. This setting applies to all areas
designated as DRAM/continuous synchronous
DRAM space.
00: No wait state inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
3
SLFRF
0
R/W
Self-Refresh Enable
If this bit is set to 1, DRAM/synchronous DRAM
self-refresh mode is selected when a transition is
made to the software standby state. This bit is valid
when the RFSHE bit is set to 1, enabling refresh
operations. It is cleared after recovery from
software standby mode.
0: Self-refreshing is disabled
1: Self-refreshing is enabled
2
1
0
TPCS2
TPCS1
TPCS0
0
0
0
R/W
R/W
R/W
Self-Refresh Precharge Cycle Control
These bits select the number of states in the
precharge cycle immediately after self-refreshing.
The number of states in the precharge cycle
immediately after self-refreshing are added to the
number of states set by bits TPC1 and TPC0 in
DRACCR.
000: [TPC set value] states
001: [TPC set value + 1] states
010: [TPC set value + 2] states
011: [TPC set value + 3] states
100: [TPC set value + 4] states
101: [TPC set value + 5] states
110: [TPC set value + 6] states
111: [TPC set value + 7] states
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Section 6 Bus Controller (BSC)
6.3.11
Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock
selected by bits RTCK2 to RTCK0 in REFCR.
When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and
RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is
started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match
interrupt (CMI) is generated.
RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
6.3.12
Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit readable/writable register that sets the period for compare match operations
with RTCNT.
The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in
REFCR is set to 1 and RTCNT is cleared to H'00.
RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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Section 6 Bus Controller (BSC)
6.4
Bus Control
6.4.1
Area Division
The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units,
and performs bus control for external address space in area units. Chip select signals (CS0 to CS7)
can be output for each area. In normal mode, a part of area 0, 64-kbyte address space, is
controlled. Figure 6.6 shows an outline of the memory map.
H'000000
Area 0
(2 Mbytes)
H'1FFFFF
H'200000
Area 1
(2 Mbytes)
H'3FFFFF
H'400000
Area 2
(2 Mbytes)
H'5FFFFF
H'600000
Area 3
(2 Mbytes)
H'7FFFFF
H'800000
Area 4
(2 Mbytes)
H'9FFFFF
H'A00000
Area 5
(2 Mbytes)
H'BFFFFF
H'C00000
Area 6
(2 Mbytes)
H'DFFFFF
H'E00000
Area 7
(2 Mbytes)
H'FFFFFF
Figure 6.6 Area Divisions
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Section 6 Bus Controller (BSC)
6.4.2
Bus Specifications
The external address space bus specifications consist of five elements: bus width, number of
access states, number of program wait states, read strobe timing, and chip select (CS) assertion
period extension states. The bus width and number of access states for on-chip memory and
internal I/O registers are fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode
is set; if any area is designated as 16-bit access space, 16-bit bus mode is set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for
which 2-state access is selected functions as a 2-state access space, and an area for which 3-state
access is selected functions as a 3-state access space. With the DRAM or synchronous DRAM
interface and burst ROM interface, the number of access states may be determined without regard
to the setting of ASTCR.
When 2-state access space is designated, wait insertion is disabled. When 3-state access space is
designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and
external waits by means of the WAIT pin.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Number of Program Wait States: When 3-state access space is designated by ASTCR, the
number of program wait states to be inserted automatically is selected with WTCRA and WTCRB.
From 0 to 7 program wait states can be selected. Table 6.2 shows the bus specifications (bus
width, and number of access states and program wait states) for each basic bus interface area.
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Section 6 Bus Controller (BSC)
Table 6.2
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR
ASTCR
ABWn
ASTn
Wn2
Wn1
Wn0
Bus Width
Access
States
Program Wait
States
0
0
⎯
⎯
⎯
16
2
0
1
0
0
0
3
0
WTCRA, WTCRB
1
1
1
1
0
2
1
3
0
0
4
1
5
0
6
1
7
1
1
0
⎯
⎯
⎯
1
0
0
0
1
1
Bus Specifications (Basic Bus Interface)
0
1
8
2
0
3
0
1
1
0
2
1
3
0
4
1
5
0
6
1
7
(n = 0 to 7)
Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of
the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in
the basic bus interface space.
Chip Select (CS) Assertion Period Extension States: Some external I/O devices require a setup
time and hold time between address and CS signals and strobe signals such as RD, HWR, and
LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are
asserted before and after a basic bus space access cycle.
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Section 6 Bus Controller (BSC)
6.4.3
Memory Interfaces
The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; a
synchronous DRAM interface that allows direct connection of synchronous DRAM; and a burst
ROM interface that allows direct connection of burst ROM. The interface can be selected
independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, an area for which the
synchronous DRAM interface is designated functions as continuous synchronous DRAM space,
and an area for which the burst ROM interface is designated functions as burst ROM space.
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Area 0: Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the
space excluding on-chip ROM is external address space, and in expanded mode with on-chip
ROM disabled, all of area 0 is external address space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
Area 1: In externally expanded mode, all of area 1 is external address space.
When area 1 external address space is accessed, the CS1 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 1.
Areas 2 to 5: In externally expanded mode, areas 2 to 5 are all external address space.
When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.
Basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for areas 2
to 5. With the DRAM interface, signals CS2 and CS5 are used as RAS signals.
If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM
can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM
space.
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Section 6 Bus Controller (BSC)
If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are
used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The
OE pin is used as the CKE signal.
Area 6: In externally expanded mode, all of area 6 is external space.
When area 6 external space is accessed, the CS6 signal can be output.
Only the basic bus interface can be used for area 6.
Area 7: Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode,
the space excluding the on-chip RAM and internal I/O registers is external address space. The onchip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when
the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external address space.
When area 7 external address space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
6.4.4
Chip Select Signals
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7
signals output timing.
Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit
for the port corresponding to the CS0 to CS7 pins.
In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a
reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits
should be set to 1 when outputting signals CS1 to CS7.
In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state
after a reset and so the corresponding DDR bits should be set to 1 when outputting signals CS0 to
CS7.
When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals.
When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2378R
Group, outputs CS2, CS3, CS4, and CS5 are used as RAS, CAS, WE, and CLK signals.
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
Area n external address
CSn
Figure 6.7 CSn Signal Output Timing (n = 0 to 7)
6.5
Basic Bus Interface
The basic bus interface enables direct connection of ROM, SRAM, and so on.
6.5.1
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external address space, controls
whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space: Figure 6.8 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word access is performed as two byte accesses,
and a longword access, as four byte accesses.
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Section 6 Bus Controller (BSC)
Upper data bus
D15
Lower data bus
D8 D7
D0
Byte size
Word size
1st bus cycle
2nd bus cycle
1st bus cycle
Longword
size
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space)
16-Bit Access Space: Figure 6.9 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Upper data bus
D15
Byte size
• Even address
Byte size
• Odd address
Lower data bus
D8 D7
D0
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space)
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Section 6 Bus Controller (BSC)
6.5.2
Valid Strobes
Table 6.3 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write,
the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.3
Data Buses Used and Valid Strobes
Access
Size
Area
8-bit access
space
Byte
16-bit access
space
Byte
Read/
Write
Address
Valid
Strobe
Upper Data Bus Lower Data Bus
(D15 to D8)
(D7 to D0)
Valid
Read
⎯
RD
Write
⎯
HWR
Read
Even
RD
Odd
Valid
Invalid
Invalid
Valid
Even
HWR
Valid
Hi-Z
Odd
LWR
Hi-Z
Valid
Read
⎯
RD
Valid
Valid
Write
⎯
HWR, LWR
Valid
Valid
Write
Word
Invalid
Hi-Z
Note: Hi-Z: High-impedance state
Invalid: Input state; input value is ignored.
6.5.3
Basic Timing
8-Bit, 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space
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Section 6 Bus Controller (BSC)
8-Bit, 3-State Access Space: Figure 6.11 shows the bus timing for an 8-bit, 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
High
LWR
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space
16-Bit, 2-State Access Space: Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
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Section 6 Bus Controller (BSC)
for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be
inserted.
Bus cycle
T1
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space
(Even Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
High impedance
D15 to D8
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space
(Odd Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space
(Word Access)
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Section 6 Bus Controller (BSC)
16-Bit, 3-State Access Space: Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be
inserted.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space
(Even Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
D7 to D0
High impedance
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space
(Odd Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space
(Word Access)
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Section 6 Bus Controller (BSC)
6.5.4
Wait Control
When accessing external space, this LSI can extend the bus cycle by inserting one or more wait
states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait
insertion using the WAIT pin.
Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T2
state and T3 state on an individual area basis in 3-state access space, according to the settings in
WTCRA and WTCRB.
Pin Wait Insertion: Setting the WAITE bit to 1 in BCR enables wait input by means of the
WAIT pin. When external space is accessed in this state, a program wait is first inserted in
accordance with the settings in WTCRA and WTCRB. If the WAIT pin is low at the falling edge
of φ in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states
are inserted until it goes high. This is useful when inserting seven or more Tw states, or when
changing the number of Tw states to be inserted for different external devices. The WAITE bit
setting applies to all areas. Figure 6.18 shows an example of wait state insertion timing.
The settings after a reset are: 3-state access, insertion of 7 program wait states, and WAIT input
disabled.
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Section 6 Bus Controller (BSC)
By program wait
T1
T2
Tw
By WAIT pin
Tw
Tw
T3
φ
WAIT
Address bus
AS
RD
Read
Data bus
Read data
HWR, LWR
Write
Data bus
Write data
Notes: 1. Downward arrows indicate the timing of WAIT pin sampling.
2. When RDN = 0
Figure 6.18 Example of Wait State Insertion Timing
6.5.5
Read Strobe (RD) Timing
The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to
1 in RDNCR. Figure 6.19 shows an example of the timing when the read strobe timing is changed
in basic bus 3-state access space.
When the DMAC or EXDMAC is used in single address mode, note that if the RD timing is
changed by setting RDNn to 1, the RD timing will change relative to the rise of DACK or
EDACK.
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
RDNn = 0
Data bus
RD
RDNn = 1
Data bus
DACK,
EDACK
Figure 6.19 Example of Read Strobe Timing
6.5.6
Extension of Chip Select (CS) Assertion Period
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
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Section 6 Bus Controller (BSC)
Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Bus cycle
Th
T1
T2
T3
Tt
φ
Address bus
CSn
AS
Read
(when
RDNn = 0)
RD
Data bus
Read data
HWR, LWR
Write
Data bus
Write data
Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended
Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR
register, and for the Tt state with the lower 8 bits (CSXT7 to CSXT0).
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Section 6 Bus Controller (BSC)
6.6
DRAM Interface
In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst
operation is also possible, using fast page mode.
6.6.1
Setting DRAM Space
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.4.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2
to 5), and continuous area (areas 2 to 5).
Table 6.4
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space
RMTS2
RMTS1
RMTS0
Area 5
Area 4
Area 3
Area 2
0
0
1
Normal space
Normal space
Normal space
DRAM space
1
0
Normal space
Normal space
DRAM space
DRAM space
1
DRAM space
DRAM space
DRAM space
1
0
1
0
1
Mode register settings of synchronous DRAM*
0
Reserved (setting prohibited)
1
Note:
*
DRAM space
Continuous synchronous DRAM space*
Continuous
DRAM space
Continuous
DRAM space
Continuous
DRAM space
Continuous
DRAM space
Reserved (setting prohibited) in the H8S/2378 Group.
With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait
states, etc.) for continuous DRAM space conform to the settings for area 2.
6.6.2
Address Multiplexing
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
6.5 shows the relation between the settings of MXC2 to MXC0 and the shift size.
The MXC2 bit should be cleared to 0 when the DRAM interface is used.
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Section 6 Bus Controller (BSC)
Table 6.5
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
DRAMCR
Address Pins
Shift
MXC2 MXC1 MXC0
Size
A23
to A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A16
Row
0
0
0
8 bits
address
A23 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A8
to
A16
1
9 bits
A23 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
to
A16
1
0
10 bits A23 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
to
A16
1
11 bits A23 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
to
A16
Column
1
×
×
0
×
×
address
Reserved (setting prohibited)
⎯
A23 A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2
A1
A0
to
A16
1
×
×
Reserved (setting prohibited)
Legend:
×: Don’t care.
6.6.3
Data Bus
If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.
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Section 6 Bus Controller (BSC)
6.6.4
Pins Used for DRAM Interface
Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2 to CS5
pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2 to RAS5
signals are output.
Table 6.6
DRAM Interface Pins
Pin
With DRAM
Setting
Name
I/O
Function
HWR
WE
Write enable
Output
Write enable for DRAM space
access
CS2
RAS2/RAS
Row address strobe 2/
row address strobe
Output
Row address strobe when area 2
is designated as DRAM space or
row address strobe when areas 2
to 5 are designated as continuous
DRAM space
CS3
RAS3
Row address strobe 3
Output
Row address strobe when area 3
is designated as DRAM space
CS4
RAS4
Row address strobe 4
Output
Row address strobe when area 4
is designated as DRAM space
CS5
RAS5
Row address strobe 5
Output
Row address strobe when area 5
is designated as DRAM space
UCAS
UCAS
Upper column address
strobe
Output
Upper column address strobe for
16-bit DRAM space access or
column address strobe for 8-bit
DRAM space access
LCAS
LCAS
Lower column address
strobe
Output
Lower column address strobe
signal for 16-bit DRAM space
access
RD, OE
OE
Output enable
Output
Output enable signal for DRAM
space access
WAIT
WAIT
Wait
Input
Wait request signal
A15 to A0
A15 to A0
Address pins
Output
Row address/column address
multiplexed output
D15 to D0
D15 to D0
Data pins
I/O
Data input/output pins
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Section 6 Bus Controller (BSC)
6.6.5
Basic Timing
Figure 6.21 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address
output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0)
When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When
connecting DRAM provided with an EDO page mode, the OE signal should be connected to the
(OE ) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM
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Section 6 Bus Controller (BSC)
space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output
from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space,
the signal is output only from the RD pin.
6.6.6
Column Address Output Cycle Control
The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit
to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width,
etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.22
shows an example of the timing when a 3-state column address output cycle is selected.
Tp
Tr
Tc1
Tc2
Tc3
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.22 Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0)
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Section 6 Bus Controller (BSC)
6.6.7
Row Address Output State Control
If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr
state, and the row address hold time and DRAM read access time are changed relative to the fall of
the RAS signal. Use the optimum setting according to the DRAM connected and the operating
frequency of this LSI. Figure 6.23 shows an example of the timing when the RAS signal goes low
from the beginning of the Tr state.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.23 Example of Access Timing when RAS Signal Goes Low from Beginning
of Tr State (CAST = 0)
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Section 6 Bus Controller (BSC)
If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three Trw states, in which row address output is
maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1
cycle, in which the column address is output. Use the setting that gives the optimum row address
signal hold time relative to the falling edge of the RAS signal according to the DRAM connected
and the operating frequency of this LSI. Figure 6.24 shows an example of the timing when one Trw
state is set.
Tp
Tr
Trw
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.24 Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
6.6.8
Precharge State Control
When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is
always inserted when DRAM space is accessed. From one to four Tp states can be selected by
setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the
DRAM connected and the operating frequency of this LSI. Figure 6.25 shows the timing when
two Tp states are inserted. The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh
cycles.
Tp2
Tp1
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.25 Example of Timing with Two-State Precharge Cycle
(RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
6.6.9
Wait Control
There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and
pin wait insertion using the WAIT pin.
Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and
to extend the write data setup time relative to the falling edge of CAS in a write access.
Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM
space is set to 1, from 0 to 7 wait states can be inserted automatically between the Tc1 state and Tc2
state, according to the settings in WTCR.
Pin Wait Insertion: When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait
input by means of the WAIT pin is enabled. When DRAM space is accessed in this state, a
program wait (Tw) is first inserted. If the WAIT pin is low at the falling edge of φ in the last Tc1 or
Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it
goes high.
Figures 6.26 and 6.27 show examples of wait cycle insertion timing in the case of 2-state and 3state column address output cycles.
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Section 6 Bus Controller (BSC)
By program wait
Tp
Tr
Tc1
Tw
By WAIT pin
Tw
φ
WAIT
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
Read
WE (HWR)
High
OE (RD)
Data bus
UCAS, LCAS
Write
WE (HWR)
OE (RD)
High
Data bus
Note: Downward arrows indicate the timing of WAIT pin sampling.
n = 2 to 5
Figure 6.26 Example of Wait State Insertion Timing
(2-State Column Address Output)
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Tc2
Section 6 Bus Controller (BSC)
Tp
Tr
By program wait
By WAIT pin
Tc1
Tw
Tw
Tc2
Tc3
φ
WAIT
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
Read
WE (HWR)
High
OE (RD)
Data bus
UCAS, LCAS
Write
WE (HWR)
OE (RD)
High
Data bus
Note: Downward arrows indicate the timing of WAIT pin sampling.
n = 2 to 5
Figure 6.27 Example of Wait State Insertion Timing
(3-State Column Address Output)
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Section 6 Bus Controller (BSC)
6.6.10
Byte Access Control
When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the
control signals needed for byte access. Figure 6.28 shows the control timing for 2-CAS access,
and figure 6.29 shows an example of 2-CAS DRAM connection.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS
LCAS
High
WE (HWR)
OE (RD)
High
Write data
Upper data bus
High impedance
Lower data bus
Note: n = 2 to 5
Figure 6.28 2-CAS Control Timing
(Upper Byte Write Access: RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
This LSI
(Address shift size
set to 10 bits)
2-CAS type 16-Mbit DRAM
1-Mbyte × 16-bit configuration
10-bit column address
RASn (CSn)
RAS
UCAS
UCAS
LCAS
LCAS
HWR (WE)
RD (OE)
A10
WE
OE
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
D15 to D0
Row address input:
A9 to A0
Column address input:
A9 to A0
D15 to D0
Figure 6.29 Example of 2-CAS DRAM Connection
6.6.11
Burst Operation
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making
consecutive accesses to the same row address. This mode enables fast (burst) access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
Burst Access (Fast Page Mode): Figures 6.30 and 6.31 show the operation timing for burst
access. When there are consecutive access cycles for DRAM space, the CAS signal and column
address output cycles (two states) continue as long as the row address is the same for consecutive
access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in
DRAMCR.
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
Tc1
Tc2
φ
Address bus
Row address
Column address 1 Column address 2
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.30 Operation Timing in Fast Page Mode
(RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
Tc3
Tc1
Tc2
Tc3
φ
Address bus
Row address
Column address 1
Column address 2
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.31 Operation Timing in Fast Page Mode
(RAST = 0, CAST = 1)
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details see section 6.6.9, Wait Control.
RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that
access to DRAM space is not continuous, but is interrupted by access to another space. In this
case, if the RAS signal is held low during the access to the other space, burst operation can be
resumed when the same row address in DRAM space is accessed again.
• RAS Down Mode
To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access
to DRAM space is interrupted and another space is accessed, the RAS signal is held low
during the access to the other space, and burst access is performed when the row address of the
next DRAM space access is the same as the row address of the previous DRAM space access.
Figure 6.32 shows an example of the timing in RAS down mode.
Note, however, that the RAS signal will go high if:
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Section 6 Bus Controller (BSC)
⎯ a refresh operation is initiated in the RAS down state
⎯ self-refreshing is performed
⎯ the chip enters software standby mode
⎯ the external bus is released
⎯ the RCDM bit or BE bit is cleared to 0
If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock
will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the
RCDM bit must be cleared to 0 before executing the SLEEP instruction.
DRAM space read
Tp
Tr
Tc1
Tc2
Normal space
read
DRAM space
read
T1
Tc1
T2
Tc2
φ
Row address
Address bus
Column address 1
External address Column address 2
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
Note: n = 2 to 5
Figure 6.32 Example of Operation Timing in RAS Down Mode
(RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
• RAS Up Mode
To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM
space is interrupted and another space is accessed, the RAS signal goes high again. Burst
operation is only performed if DRAM space is continuous. Figure 6.33 shows an example of
the timing in RAS up mode.
DRAM space read
Tp
Tr
Tc1
Tc2
DRAM space
read
Normal space
read
Tc1
T1
Tc2
T2
φ
Address bus
Row address
Column address 1 Column address 2
External address
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
Note: n = 2 to 5
Figure 6.33 Example of Operation Timing in RAS Up Mode
(RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
6.6.12
Refresh Control
This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing
is used. In addition, self-refreshing can be executed when the chip enters the software standby
state.
Refresh control is enabled when any area is designated as DRAM space in accordance with the
setting of bits RMTS2 to RMTS0 in DRAMCR.
CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit to 1 in
REFCR.
With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0
in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the DRAM used.
When bits RTCK2 to RTCK0 in REFCR are set, RTCNT starts counting up. RTCNT and RTCOR
settings should therefore be completed before setting bits RTCK2 to RTCK0. RTCNT operation is
shown in figure 6.34, compare match timing in figure 6.35, and CBR refresh timing in figure 6.36.
When the CBRM bit in REFCR is cleared to 0, access to external space other than DRAM space is
performed in parallel during the CBR refresh period.
RTCNT
RTCOR
H'00
Refresh request
Figure 6.34 RTCNT Operation
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Section 6 Bus Controller (BSC)
φ
RTCNT
N
H'00
RTCOR
N
Refresh request
signal and CMF bit
setting signal
Figure 6.35 Compare Match Timing
TRp
TRr
TRc1
TRc2
φ
CSn (RASn)
UCAS, LCAS
Figure 6.36 CBR Refresh Timing
A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to
three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The
settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
Figure 6.37 shows the timing when bits RCW1 and RCW0 are set.
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Section 6 Bus Controller (BSC)
TRp
TRrw
TRr
TRc1
TRc2
φ
CSn (RASn)
UCAS, LCAS
Figure 6.37 CBR Refresh Timing
(RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)
Depending on the DRAM used, modification of the WE signal may not be permitted during the
refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will
then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.38 shows an example
of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and
retains its value prior to the start of the refresh period.
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Section 6 Bus Controller (BSC)
Normal space access request
φ
A23 to A0
CS
AS
RD
HWR (WE)
Refresh period
RAS
CAS
Figure 6.38 Example of CBR Refresh Timing (CBRM = 1)
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP
instruction is executed to enter software standby mode, the CAS and RAS signals are output and
DRAM enters self-refresh mode, as shown in figure 6.39.
When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is
exited automatically. If a CBR refresh request occurs when making a transition to software
standby mode, CBR refreshing is executed, then self-refresh mode is entered.
When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register.
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Section 6 Bus Controller (BSC)
TRp
Software
standby
TRr
TRc3
φ
CSn (RASn)
UCAS, LCAS
HWR (WE)
High
Note: n = 2 to 5
Figure 6.39 Self-Refresh Timing
In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately
after self-refreshing is longer than the normal precharge time. A setting can be made in bits
TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1
to 7 states longer than the normal precharge time. In this case, too, normal precharging is
performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting
should be made to give the optimum post-self-refresh precharge time, including this time. Figure
6.40 shows an example of the timing when the precharge time immediately after self-refreshing is
extended by 2 states.
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Section 6 Bus Controller (BSC)
Software
standby
DRAM space write
Trc3
Trp1
Trp2
Tp
Tr
Tc1
Tc2
φ
Address bus
RASn (CSn)
UCAS, LCAS
OE (RD)
WR (HWR)
Data bus
Note: n = 2 to 5
Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States
Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit
timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the
sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O
port clocks are also stopped. As the bus controller clock is also stopped in this mode, CBR
refreshing is not executed. If DRAM is connected externally and DRAM data is to be retained in
sleep mode, the ACSE bit must be cleared to 0 in MSTPCRH.
6.6.13
DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can
be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC
or EXDMAC single address mode at the same time, these bits select whether or not burst access is
to be performed.
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Section 6 Bus Controller (BSC)
When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,
irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low
from the Tc1 state.
Figure 6.41 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or
EDDS = 1.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
DACK or EDACK
Note: n = 2 to 5
Figure 6.41 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1
(RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
When DDS = 0 or EDDS = 0: When DRAM space is accessed in DMAC or EXDMAC single
address transfer mode, full access (normal access) is always performed. With the DRAM interface,
the DACK or EDACK output goes low from the Tr state.
In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing DRAM space.
Figure 6.42 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or
EDDS = 0.
Tp
Tr
Tc1
Tc2
Tc3
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
DACK or EDACK
Note: n = 2 to 5
Figure 6.42 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1)
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Section 6 Bus Controller (BSC)
6.7
Synchronous DRAM Interface
In the H8S/2378R Group, external address space areas 2 to 5 can be designated as continuous
synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous
DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous
DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
Synchronous DRAM of CAS latency 1 to 4 can be connected.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
6.7.1
Setting Continuous Synchronous DRAM Space
Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to
RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and
synchronous DRAM space is shown in table 6.7. Possible synchronous DRAM interface settings
are and continuous area (areas 2 to 5).
Table 6.7
Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM
Space
RMTS2
RMTS1
RMTS0
Area 5
Area 4
Area 3
Area 2
0
0
1
Normal space
Normal space
Normal space
DRAM space
1
0
Normal space
Normal space
DRAM space
DRAM space
1
DRAM space
DRAM space
DRAM space
DRAM space
1
0
0
Continuous synchronous DRAM space
1
Mode settings of synchronous DRAM
1
0
Reserved (setting prohibited)
1
Continuous DRAM space
With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE
signal. The (OE) pin of the synchronous DRAM is used as the CKE signal, and the CS5 pin is
used as synchronous DRAM clock (SDRAMφ). The bus specifications for continuous
synchronous DRAM space conform to the settings for area 2. The pin wait and program wait for
the continuous synchronous DRAM are invalid.
Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and
address-precharge-setting command (Precharge-sel) output on the upper column addresses.
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Section 6 Bus Controller (BSC)
Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all
bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT),
and mode-register write (MRS). Commands for bank control cannot be used.
6.7.2
Address Multiplexing
With continuous synchronous DRAM space, the row address and column address are multiplexed.
In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to
MXC0 in DRAMCR. The address-precharge-setting command (Precharge-sel) can be output on
the upper column address. Table 6.8 shows the relation between the settings of MXC2 to MXC0
and the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is
used.
Table 6.8
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
DRAMCR
Address Pins
Shift
A23 to
MXC2 MXC1 MXC0 Size
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A16
Row
address
0
×
×
1
0
0
8
bits
A23 to A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
A16
1
9
bits
A23 to A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A16
0
10
bits
A23 to A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A16
1
11
bits
A23 to A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
A16
1
Column
address
Reserved (setting prohibited)
0
×
×
1
0
0
⎯
A23 to
A16
P
P
P
P
P
P
P
A8 A7 A6 A5 A4
A3 A2 A1 A0
1
⎯
A23 to
A16
P
P
P
P
P
P
A9 A8 A7 A6 A5 A4
A3 A2 A1 A0
0
⎯
A23 to
A16
P
P
P
P
P
A10 A9 A8 A7 A6 A5 A4
A3 A2 A1 A0
1
⎯
A23 to
A16
P
P
P
P
A11 A10 A9 A8 A7 A6 A5 A4
A3 A2 A1 A0
1
Reserved (setting prohibited)
Legend:
×: Don’t care.
P: Precharge-sel
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Section 6 Bus Controller (BSC)
6.7.3
Data Bus
If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous
DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space;
if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space.
In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be
connected directly.
In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is
enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of
the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.
6.7.4
Pins Used for Synchronous DRAM Interface
Table 6.9 shows pins used for the synchronous DRAM interface and their functions. To enable the
synchronous DRAM interface, fix the DCTL pin to 1. Do not vary the DCTL pin during operation.
Since the CS2 to CS4 pins are in the input state after a reset, set DDR to 1 when RAS, CAS, and
WE signals are output. For details, see section 10, I/O Ports. Set the OEE bit of the DRAMCR
register to 1 when the CKE signal is output.
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Section 6 Bus Controller (BSC)
Table 6.9
Synchronous DRAM Interface Pins
Pin
With
Synchronous
DRAM Setting
Name
I/O
Function
CS2
RAS
Row address strobe
Output
Row address strobe when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
CS3
CAS
Column address strobe
Output
Column address strobe when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
CS4
WE
Write enable
Output
Write enable strobe when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
CS5
SDRAMφ
Clock
Output
Clock only for synchronous
DRAM
(OE)
(CKE)
Clock enable
Output
Clock enable signal when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
UCAS
DQMU
Upper data mask enable Output
Upper data mask enable for
16-bit continuous synchronous
DRAM space access/data
mask enable for 8-bit
continuous synchronous
DRAM space access
LCAS
DQML
Lower data mask enable Output
Lower data mask enable
signal for 16-bit continuous
synchronous DRAM space
access
A15 to A0
A15 to A0
Address pins
Output
Row address/column address
multiplexed output pins
D15 to D0
D15 to D0
Data pins
I/O
Data input/output pins
DCTL
DCTL
Device control pin
Input
Output enable pin for SDRAMφ
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Section 6 Bus Controller (BSC)
6.7.5
Synchronous DRAM Clock
When the DCTL pin is fixed to 1, synchronous clock (SDRAMφ) is output from the CS5 pin.
When the frequency multiplication factor of the PLL circuit of this LSI is set to ×1 or ×2,
SDRAMφ is 90° phase shift from φ. Therefore, a stable margin is ensured for the synchronous
DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between φ
and SDRAMφ. When the frequency multiplication factor of the PLL circuit is ×4, the phase of
SDRAMφ and that of φ are the same.
When the CLK pin of the synchronous DRAM is directly connected to SDRAMφ of this LSI, it is
recommended to set the frequency multiplication factor of the PLL circuit to ×1 or ×2.
Note: SDRAMφ output timing is shown when the frequency multiplication factor of the PLL
circuit is ×1 or ×2.
Tcyc
φ
1/4 Tcyc (90°)
SDRAMφ
Figure 6.43 Relationship between φ and SDRAMφ (when PLL Frequency Multiplication
Factor Is ×1 or ×2)
6.7.6
Basic Timing
The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address
output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states.
When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.
Figure 6.44 shows the basic timing for synchronous DRAM.
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Section 6 Bus Controller (BSC)
Tp
Tr
Column address
Row address
Tc1
Tc2
φ
SDRAMφ
Address bus
Precharge-sel
Column address
Row address
RAS
CAS
WE
Read
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
READ
NOP
RAS
CAS
WE
Write
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1)
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Section 6 Bus Controller (BSC)
6.7.7
CAS Latency Control
CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency
count, as shown in table 6.10, by the setting of synchronous DRAM. Depending on the setting, the
CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless of the setting of the
AST2 bit of ASTCR. Figure 6.45 shows the CAS latency control timing when synchronous
DRAM of CAS latency 3 is connected.
The initial value of W22 to W20 is H'7. Set the register according to the CAS latency of
synchronous DRAM to be connected.
Table 6.10 Setting CAS Latency
CAS Latency Control
Cycle Inserted
W22
W21
W20
Description
0
0
0
Connect synchronous DRAM of CAS
latency 1
0 state
1
Connect synchronous DRAM of CAS
latency 2
1 state
0
Connect synchronous DRAM of CAS
latency 3
2 states
1
Connect synchronous DRAM of CAS
latency 4
3 states
0
Reserved (must not used)
⎯
1
Reserved (must not used)
⎯
0
Reserved (must not used)
⎯
1
Reserved (must not used)
⎯
1
1
0
1
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl1
Tcl2
Tc2
φ
SDRAMφ
Address bus
Column address Row address
Precharge-sel
Row address
Column address
RAS
CAS
WE
Read
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
READ
NOP
RAS
CAS
WE
Write
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
NOP
Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3)
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Section 6 Bus Controller (BSC)
6.7.8
Row Address Output State Control
When the command interval specification from the ACTV command to the next READ/WRIT
command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted
between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column
address by setting the RCD1 and RCD0 bits of DRACCR. Use the optimum setting for the wait
time according to the synchronous DRAM connected and the operating frequency of this LSI.
Figure 6.46 shows an example of the timing when the one Trw state is set.
Tp
Tr
Trw
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column
address
Column address
Row address
Row address
Precharge-sel
RAS
CAS
Read
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
READ
NOP
RAS
CAS
Write
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
NOP
Figure 6.46 Example of Access Timing when Row Address Output Hold State Is 1 State
(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2)
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Section 6 Bus Controller (BSC)
6.7.9
Precharge State Count
When the interval specification from the PALL command to the next ACTV/REF command
cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in
DRACCR. Set the optimum number of Tp cycles according to the synchronous DRAM connected
and the operating frequency of this LSI. Figure 6.47 shows the timing when two Tp states are
inserted.
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Section 6 Bus Controller (BSC)
The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles.
Tp1
Tp2
Tr
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address
Row address
Column address
Row address
Precharge-sel
RAS
CAS
Read
WE
CKE
High
DQMU, DQML
Data bus
PALL
NOP
ACTV
READ
NOP
RAS
CAS
Write
WE
CKE
High
DQMU, DQML
Data bus
PALL
NOP
ACTV
NOP
WRIT
NOP
Figure 6.47 Example of Timing with Two-State Precharge Cycle
(TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)
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Section 6 Bus Controller (BSC)
6.7.10
Bus Cycle Control in Write Cycle
By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is
inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled.
Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to
synchronous DRAM read access. Figure 6.48 shows the write access timing when the CAS
latency control cycle is disabled.
Tp
Tr
Column address
Row address
Tc1
Tc2
φ
SDRAMφ
Address bus
Precharge-sel
Column address
Row address
RAS
CAS
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled
(SDWCD = 1)
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Section 6 Bus Controller (BSC)
6.7.11
Byte Access Control
When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are
used for the control signals needed for byte access.
Figures 6.49 and 6.50 show the control timing for DQM, and figure 6.51 shows an example of
connection of byte control by DQMU and DQML.
Tp
Tr
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address Row address
Precharge-sel
Row address
Column address
RAS
CAS
WE
CKE
High
DQMU
DQML
High
Upper data bus
Lower data bus
High impedance
PALL
ACTV
NOP
WRIT
NOP
Figure 6.49 DQMU and DQML Control Timing
(Upper Byte Write Access: SDWCD = 0, CAS Latency 2)
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address Row address
Precharge-sel
Row address
Column address
RAS
CAS
WE
CKE
High
DQMU
High
DQML
Upper data bus
High impedance
Lower data bus
PALL
ACTV
READ
NOP
Figure 6.50 DQMU and DQML Control Timing
(Lower Byte Read Access: CAS Latency 2)
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Section 6 Bus Controller (BSC)
This LSI
(Address shift size set to 8 bits)
CS2 (RAS)
RAS
CS3 (CAS)
CAS
CS4 (WE)
WE
UCAS (DQMU)
DQMU
LCAS (DQML)
DQML
CS5 (SDRAMφ)
CLK
A23
A13 (BS1)
A21
A12 (BS0)
A12
A11
A11
A10
A10
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
D15 to D0
DCTL
64-Mbit synchronous DRAM
1 Mword × 16 bits × 4-bank configuration
8-bit column address
OE (CKE)
I/O PORT
Row address
input: A11 to A0
Column address
input: A7 to A0
Bank select
address: A13/A12
DQ15 to DQ0
CKE
CS
Notes: 1. Bank control is not available.
2. The CKE and CS pins must be fixed to 1 when the power supply is input.
3. The CS pin must be fixed to 0 before accessing synchronous DRAM.
Figure 6.51 Example of DQMU and DQML Byte Control
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Section 6 Bus Controller (BSC)
6.7.12
Burst Operation
With synchronous DRAM, in addition to full access (normal access) in which data is accessed by
outputting a row address for each access, burst access is also provided which can be used when
making consecutive accesses to the same row address. This access enables fast access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal
cannot be specified to the Tc2 cycle data output if Tc1 cycle is performed for second or following
column address when the CAS latency is set to 1 to issue the READ command. Do not set the BE
bit to 1 when synchronous DRAM of CAS latency 1 is connected.
Burst Access Operation Timing: Figure 6.52 shows the operation timing for burst access. When
there are consecutive access cycles for continuous synchronous DRAM space, the column address
output cycles continue as long as the row address is the same for consecutive access cycles. The
row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR.
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Section 6 Bus Controller (BSC)
Tp
Tr
Column
address 1
Row address
Tc1
Tcl
Tc2
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address
Column address 2
Row address
Precharge-sel
RAS
CAS
Read
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
READ
NOP
READ
NOP
RAS
CAS
Write
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
NOP
Figure 6.52 Operation Timing of Burst Access
(BE = 1, SDWCD = 0, CAS Latency 2)
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WRIT
NOP
Section 6 Bus Controller (BSC)
RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous
synchronous DRAM space is not continuous, but is interrupted by access to another space. In this
case, if the row address active state is held during the access to the other space, the read or write
command can be issued without ACTV command generation similarly to DRAM RAS down
mode.
To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings.
The operation corresponding to DRAM RAS up mode is not supported by this LSI.
Figure 6.53 shows an example of the timing in RAS down mode.
Note, however, the next continuous synchronous DRAM space access is a full access if:
• a refresh operation is initiated in the RAS down state
• self-refreshing is performed
• the chip enters software standby mode
• the external bus is released
• the BE bit is cleared to 0
• the mode register of the synchronous DRAM is set
There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not
guaranteed that other row address are accessed in a period in which program execution ensures the
value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of
the maximum active state time of each bank must be satisfied. When refresh is not used, programs
must be developed so that the bank is not in the active state for more than the specified time.
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Section 6 Bus Controller (BSC)
Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
External
space read
Tc2
T1
T2
Continuous synchronous
DRAM space read
Tc1
Tcl
Tc2
φ
Address bus
Column
Row
address address
Precharge-sel
Row
address
Column address
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
Data bus
PALL ACTV READ
NOP
READ
NOP
Figure 6.53 Example of Operation Timing in RAS Down Mode
(BE = 1, CAS Latency 2)
6.7.13
Refresh Control
This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used.
In addition, self-refreshing can be executed when the chip enters the software standby state.
Refresh control is enabled when any area is designated as continuous synchronous DRAM space
in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.
Auto Refreshing: To select auto refreshing, set the RFSHE bit to 1 in REFCR.
With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0
in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
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Section 6 Bus Controller (BSC)
Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the synchronous DRAM used.
When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings
should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown
in figure 6.54.
Since the refresh counter operation is the same as the operation in the DRAM interface, see
section 6.6.12, Refresh Control.
When the continuous synchronous DRAM space is set, access to external address space other than
continuous synchronous DRAM space cannot be performed in parallel during the auto refresh
period, since the setting of the CBRM bit of REFCR is ignored.
TRp
TRr
TRc1
TRc2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
REF
NOP
Figure 6.54 Auto Refresh Timing
When the interval specification from the PALL command to the REF command cannot be
satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be
inserted after the TRp cycle that is set by the TPC1 and TPC0 bits of DRACCR. Set the optimum
number of waits according to the synchronous DRAM connected and the operating frequency of
this LSI. Figure 6.55 shows the timing when one wait state is inserted. Since the setting of bits
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Section 6 Bus Controller (BSC)
TPC1 and TPC0 of DRACCR is also valid in refresh cycles, the command interval can be
extended by the RCW1 and RCW0 bits after the precharge cycles.
TRp1
TRrw
TRp2
TRr
TRc1
TRc2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
NOP
REF
NOP
Figure 6.55 Auto Refresh Timing
(TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1)
When the interval specification from the REF command to the ACTV cannot be satisfied, setting
the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh
cycle. Set the optimum number of waits according to the synchronous DRAM connected and the
operating frequency of this LSI. Figure 6.56 shows the timing when one wait state is inserted.
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Section 6 Bus Controller (BSC)
TRp
TRr
TRr1
TRcw
TRc2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
REF
NOP
Figure 6.56 Auto Refresh Timing
(TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1)
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for synchronous DRAM
as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within
the synchronous DRAM.
To select self-refreshing, set the RFSHE bit to 1 in REFCR. When a SLEEP instruction is
executed to enter software standby mode, the SELF command is issued, as shown in figure 6.57.
When software standby mode is exited, the SLFRF bit in REFCR is cleared to 0 and self-refresh
mode is exited automatically. If an auto refresh request occurs when making a transition to
software standby mode, auto refreshing is executed, then self-refresh mode is entered.
When using self-refresh mode, the OPE bit must not be cleared to 0 in SBYCR.
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Section 6 Bus Controller (BSC)
TRp
TRr
PALL
SELF
Software standby
TRc2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
CKE
NOP
Figure 6.57 Self-Refresh Timing
(TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0)
In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing
self-refreshing and the next command is specified. A setting can be made in bits TPCS2 to TPCS0
in REFCR to make the precharge time after self-refreshing from 1 to 7 states longer than the
normal precharge time. In this case, too, normal precharging is performed according to the setting
of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum
post-self-refresh precharge time, including this time. Figure 6.58 shows an example of the timing
when the precharge time after self-refreshing is extended by 2 states.
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Section 6 Bus Controller (BSC)
Continuous synchronous DRAM space write
Software
standby
TRc2
TRp1
TRp2
Tp
Tr
Column address
Row address
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Precharge-sel
Column address
Row address
RAS
CAS
WE
CKE
DQMU, DQML
Data bus
NOP
PALL
ACTV
NOP
NOP
NOP
Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)
Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit
timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the
sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O
port clocks are also stopped.
As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If
synchronous DRAM is connected to the external address space and DRAM data is to be retained
in sleep mode, the ACSE bit must be cleared to 0 in MSTPCR.
Software Standby: When a transition is made to normal software standby, the PALL command is
not output. If synchronous DRAM is connected and DRAM data is to be retained in software
standby, self-refreshing must be set.
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Section 6 Bus Controller (BSC)
6.7.14
Mode Register Setting of Synchronous DRAM
To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to
RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After
that, access the continuous synchronous DRAM space in bytes. When the value to be set in the
synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register
by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus
configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of
address H'400000 + 2X for 16-bit bus configuration synchronous DRAM.
The value of the address signal is fetched at the issuance time of the MRS command as the setting
value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the
synchronous DRAM is not supported by this LSI. For setting the mode register of the
synchronous DRAM, set the burst read/single write with the burst length of 1. Figure 6.59 shows
the setting timing of the mode in the synchronous DRAM.
Tr
Tp
Tc1
Tc2
φ
SDRAMφ
Address bus
Mode setting value
Mode setting value
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
NOP
MRS
NOP
Figure 6.59 Synchronous DRAM Mode Setting Timing
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Section 6 Bus Controller (BSC)
6.7.15
DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM
Interface
When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output
timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous
DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits
select whether or not burst access is to be performed. The establishment time for the read data can
be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits.
(1) Output Timing of DACK or EDACK
When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,
irrespective of the bus master. With the synchronous DRAM interface, the DACK or EDACK
output goes low from the Tc1 state.
Figure 6.60 shows the DACK or EDACK output timing for the synchronous DRAM interface
when DDS = 1 or EDDS = 1.
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Section 6 Bus Controller (BSC)
Tp
Tr
Column address
Row address
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Precharge-sel
Column address
Row address
RAS
CAS
WE
Read
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
READ
NOP
RAS
CAS
WE
Write
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
NOP
DACK or EDACK
Figure 6.60 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1
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Section 6 Bus Controller (BSC)
When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in
DMAC or EXDMAC single address transfer mode, full access (normal access) is always
performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from
the Tr state.
In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing continuous synchronous DRAM space.
Figure 6.61 shows the DACK or EDACK output timing for connecting the synchronous DRAM
interface when DDS = 0 or EDDS = 0.
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Section 6 Bus Controller (BSC)
Tr
Tp
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address Row address
Precharge-sel
Row address
Column address
RAS
CAS
WE
Read
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
READ
NOP
RAS
CAS
WE
Write
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
NOP
DACK or RDACK
Figure 6.61 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0
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Section 6 Bus Controller (BSC)
(2) Read Data Extension
If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is readaccessed in DMAC/EXDMAC single address mode, the establishment time for the read data can
be extended by clock suspend mode. The number of states for insertion of the read data extension
cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in
DRAMCR when the read data will be extended. The extension of the read data is not in
accordance with the bits DDS and EDDS.
Figure 6.62 shows the timing chart when the read data is extended by two cycles.
Tp
Tr
Tc1
Tcl
Tc2
Tsp1
Tsp2
φ
SDRAMφ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address
RAS
CAS
WE
CKE
DQMU, DQML
Data bus
DACK or EDACK
PALL ACTV READ
NOP
Figure 6.62 Example of Timing when the Read Data Is Extended by Two States
(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2)
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Section 6 Bus Controller (BSC)
6.8
Burst ROM Interface
In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst
ROM interfacing performed. The burst ROM space enables ROM with burst access capability to
be accessed at high speed.
Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in
BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the
setting of the BSWD11 and BSWD10 bits in BROMCR. From 1 to 8 states can be selected for
burst access.
Settings can be made independently for area 0 and area 1.
In burst ROM space, burst access covers only CPU read accesses.
6.8.1
Basic Timing
The number of access states in the initial cycle (full access) on the burst ROM interface is
determined by the basic bus interface settings in ASTCR, ABWCR, WTCRA, WTCRB, and
CSACRH. When area 0 or area 1 is designated as burst ROM space, the settings in RDNCR and
CSACRL are ignored.
From 1 to 8 states can be selected for the burst cycle, according to the settings of bits BSTS02 to
BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait states cannot be inserted. Burst access of up
to 32 words is performed, according to the settings of bits BSTS01, BSTS00, BSTS11, and
BSTS10 in BROMCR.
The basic access timing for burst ROM space is shown in figures 6.63 and 6.64.
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Section 6 Bus Controller (BSC)
Full access
T1
T2
Burst access
T3
T1
T2
T1
T2
φ
Upper address bus
Lower address bus
CSn
AS
RD
Data bus
Note: n = 1 and 0
Figure 6.63 Example of Burst ROM Access Timing
(ASTn = 1, 2-State Burst Cycle)
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Section 6 Bus Controller (BSC)
Full access
T1
T2
Burst access
T1
T1
φ
Upper address bus
Lower address bus
CSn
AS
RD
Data bus
Note: n = 1 and 0
Figure 6.64 Example of Burst ROM Access Timing
(ASTn = 0, 1-State Burst Cycle)
6.8.2
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4,
Wait Control. Wait states cannot be inserted in a burst cycle.
6.8.3
Write Access
When a write access to burst ROM space is executed, burst access is interrupted at that point and
the write access is executed in line with the basic bus interface settings. Write accesses are not
performed in burst mode even though burst ROM space is designated.
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Section 6 Bus Controller (BSC)
6.9
Idle Cycle
6.9.1
Operation
When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles
in the following three cases: (1) when read accesses in different areas occur consecutively, (2)
when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs
immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the
IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions
between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and
so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.65 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T1
T2
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS1 = 0)
T2
T3
Data collision
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
Figure 6.65 Example of Idle Cycle Operation
(Consecutive Reads in Different Areas)
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Section 6 Bus Controller (BSC)
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.66 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
HWR
HWR
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS0 = 0)
Data collision
T2
T3
Bus cycle B
Ti
T1
Idle cycle
(b) Idle cycle insertion
(ICIS0 = 1, initial value)
Figure 6.66 Example of Idle Cycle Operation (Write after Read)
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Section 6 Bus Controller (BSC)
Read after Write: If an external read occurs after an external write while the ICIS2 bit is set to 1
in BCR, an idle cycle is inserted at the start of the read cycle.
Figure 6.67 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not
inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an
external device. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
HWR, LWR
HWR
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS2 = 0)
Data collision
T2
T3
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS2 = 1, initial value)
Figure 6.67 Example of Idle Cycle Operation (Read after Write)
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Section 6 Bus Controller (BSC)
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.68. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
Overlap period between CS (area B)
and RD may occur
(a) No idle cycle insertion
(ICIS1 = 0)
T2
T3
Bus cycle B
Ti
T1
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
Figure 6.68 Relationship between Chip Select (CS) and Read (RD)
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Section 6 Bus Controller (BSC)
Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in
BCR are valid. However, in the case of consecutive reads in different areas, for example, if the
second read is a full access to DRAM space, only a Tp cycle is inserted, and a Ti cycle is not. The
timing in this case is shown in figure 6.69.
External read
T1
T2
T3
DRAM space read
Tp
Tr
Tc1
Tc2
φ
Address bus
RD
Data bus
Figure 6.69 Example of DRAM Full Access after External Read
(CAST = 0)
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. The timing in this case is illustrated in figures 6.70 and 6.71.
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Section 6 Bus Controller (BSC)
DRAM space read
Tp
Tr
Tc1
External read
Tc2
T1
T2
T3
DRAM space read
Ti
Tc1
Tc2
φ
Address bus
RD
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
DRAM space read
Tp
Tr
Tc1
External read
Tc2
T1
T2
T3
DRAM space write
Ti
Tc1
Tc2
φ
Address bus
RD
HWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space
Access: In a continuous synchronous DRAM space access following a normal space access, the
settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of
consecutive reads in different areas, for example, if the second read is a full access to continuous
synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case
is shown in figure 6.72.
Note: In the H8S/2378 Group, the synchronous DRAM interface is not supported.
External space read
T1
T2
T3
Synchronous DRAM space read
Tp
Tr
Tc1
Tcl
Tc2
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address
RAS
CAS
WE
CKE
DQMU, DQML
RD
Data bus
NOP
PALL ACTV READ
NOP
Figure 6.72 Example of Synchronous DRAM Full Access after External Read
(CAS Latency 2)
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML
differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures
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Section 6 Bus Controller (BSC)
6.73 and 6.74. In write access, DQMU and DQML are not in accordance with the settings of the
IDLC bit. The timing in this case is illustrated in figure 6.75.
Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
External space read
Tc2
T1
T2
T3
Continuous synchronous
DRAM space read
Ti
Tc1
TCl
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address 1
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
RD
HWR, LWR
High
Data bus
PALL ACTV READ
NOP
READ
Idle cycle
Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode
(Read in Different Area) (IDLC = 0, CAS Latency 2)
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NOP
Tc2
Section 6 Bus Controller (BSC)
Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
Continuous synchronous
DRAM space read
External space read
Tc2
T1
T2
T3
Ti
Ti
Tc1
TCl
Tc2
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address 1
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
RD
HWR, LWR
High
Data bus
PALL ACTV READ
NOP
READ
NOP
Idle cycle
Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode
(Read in Different Area) (IDLC = 1, CAS Latency 2)
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Section 6 Bus Controller (BSC)
Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
External space read
Tc2
T1
T2
T3
Continuous synchronous
DRAM space write
Ti
Tc1
TCl
Tc2
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address 1
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
RD
HWR, LWR
High
Data bus
PALL ACTV READ
NOP
WRIT
Idle cycle
Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, CAS Latency 2)
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NOP
Section 6 Bus Controller (BSC)
Idle Cycle in Case of Normal Space Access after DRAM Space Access:
• Normal space access after DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access
is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI
bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance
with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.76 and 6.77 show
examples of idle cycle operation when the DRMI bit is set to 1.
When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even
if bits ICIS1 and ICIS0 are set to 1.
DRAM space read
Tp
Tr
Tc1
External address space read
Tc2
Ti
T1
T2
T3
DRAM space read
Ti
Tc1
Tc2
φ
Address bus
RD
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.76 Example of Idle Cycle Operation after DRAM Access
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
DRAM space read
Tp
Tr
Tc1
External address space write DRAM space read
Tc2
Ti
T1
T2
T3
Tc1
Tc2
φ
Address bus
RD
HWR, LWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.77 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
• Normal space access after DRAM space write access
While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM
space write access, idle cycle is inserted in the first read cycle. The number of states of the idle
cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the
DRMI bit in DRACCR. Figure 6.78 shows an example of idle cycle operation when the ICIS2
bit is set to 1.
DRAM space read
Tp
Tr
Tc1
External space read
Tc2
Ti
T1
T2
DRAM space read
T3
Tc1
Tc2
φ
Address bus
RD
HWR, LWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
Idle Cycle in Case of Normal Space Access after Continuous Synchronous DRAM Space
Access:
Note: In the H8S/2378 Group, the synchronous DRAM interface is not supported.
• Normal space access after a continuous synchronous DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous
synchronous DRAM space read access is disabled. Idle cycle insertion after continuous
synchronous DRAM space read access can be enabled by setting the DRMI bit to 1. The
conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in RCR. Figure 6.79 shows an example of idle cycle
operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is
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Section 6 Bus Controller (BSC)
not inserted after continuous synchronous DRAM space read access even if bits ICIS1 and
ICIS0 are set to 1.
Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
Continuous synchronous
DRAM space read
External space read
Tc2
Ti
T1
T2
T3
Ti
Tc1
TCl
Tc2
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address 1
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
RD
Data bus
PALL ACTV READ
NOP
READ
NOP
Idle cycle
Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)
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Section 6 Bus Controller (BSC)
• Normal space access after a continuous synchronous DRAM space write access
If a normal space read cycle occurs after a continuous synchronous DRAM space write access
while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The
number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC.
It is not in accordance with the DRMI bit in DRACCR.
Figure 6.80 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
Continuous synchronous
DRAM space write
Tp
Tr
Tc1
Tc2
Synchronous
External address space read DRAM space read
Ti
T1
T2
T3
Tc1
TCl
Tc2
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column
address
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
RD
HWR, LWR
Data bus
PALL ACTV
NOP WRIT
NOP
READ
NOP
Idle cycle
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)
Table 6.11 shows whether there is an idle cycle insertion or not in the case of mixed accesses to
normal space and DRAM space/continuous synchronous DRAM space.
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Section 6 Bus Controller (BSC)
Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space
Previous Access
Next Access
ICIS2
ICIS1
ICIS0
DRMI
IDLC
Idle cycle
Normal space read
Normal space read
(different area)
⎯
0
⎯
⎯
⎯
Disabled
⎯
1
⎯
⎯
0
1 state inserted
1
2 states inserted
DRAM*/continuous
synchronous DRAM
space read
Normal space write
DRAM*/continuous
synchronous DRAM
space write
DRAM/continuous
Normal space read
synchronous DRAM*
space read
DRAM*/continuous
synchronous DRAM
space read
Normal space write
DRAM*/continuous
synchronous DRAM
space write
⎯
0
⎯
⎯
⎯
Disabled
⎯
1
⎯
⎯
0
1 state inserted
1
2 states inserted
⎯
⎯
0
⎯
⎯
Disabled
⎯
⎯
1
⎯
0
1 state inserted
1
2 states inserted
⎯
⎯
0
⎯
⎯
Disabled
⎯
⎯
1
⎯
0
1 state inserted
1
2 states inserted
⎯
0
⎯
⎯
⎯
Disabled
⎯
1
⎯
0
⎯
Disabled
1
0
1 state inserted
1
2 states inserted
⎯
0
⎯
⎯
⎯
Disabled
⎯
1
⎯
0
⎯
Disabled
1
0
1 state inserted
1
2 states inserted
⎯
⎯
0
⎯
⎯
Disabled
⎯
⎯
1
0
⎯
Disabled
1
0
1 state inserted
1
2 states inserted
⎯
⎯
0
⎯
⎯
Disabled
⎯
⎯
1
0
⎯
Disabled
1
0
1 state inserted
1
2 states inserted
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Section 6 Bus Controller (BSC)
Previous Access
Next Access
Normal space write
Normal space read
DRAM*/continuous
synchronous DRAM
space read
DRAM/continuous
Normal space read
synchronous DRAM*
space write
DRAM*/continuous
synchronous DRAM
space read
Note:
*
ICIS2
ICIS1
ICIS0
DRMI
IDLC
Idle cycle
0
⎯
⎯
⎯
⎯
Disabled
1
⎯
⎯
⎯
0
1 state inserted
1
2 states inserted
0
⎯
⎯
⎯
⎯
Disabled
1
⎯
⎯
⎯
0
1 state inserted
1
2 states inserted
0
⎯
⎯
⎯
⎯
Disabled
1
⎯
⎯
⎯
0
1 state inserted
1
2 states inserted
0
⎯
⎯
⎯
⎯
Disabled
1
⎯
⎯
⎯
0
1 state inserted
1
2 states inserted
Not supported by the H8S/2378 Group.
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/continuous synchronous DRAM space burst
access. Figures 6.81 and 6.82 show an example of the timing for idle cycle insertion in the case of
consecutive read and write accesses to DRAM/continuous synchronous DRAM space.
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Section 6 Bus Controller (BSC)
DRAM space read
φ
Tp
Tr
Tc1
DRAM space write
Tc2
Ti
Tc1
Tc2
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
Note: n = 2 to 5
Idle cycle
Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to DRAM Space in RAS Down Mode
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Section 6 Bus Controller (BSC)
Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
Continuous synchronous
DRAM space write
Tc2
Ti
Tc1
Tc2
φ
Address bus
Column Row
address address
Column
address
External address
Precharge-sel
RAS
CAS
WE
CKE
High
DQMU, DQML
Data bus
PALL ACTV READ
NOP
WRIT
Idle cycle
Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode
(SDWCD = 1, CAS Latency 2)
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Section 6 Bus Controller (BSC)
6.9.2
Pin States in Idle Cycle
Table 6.12 shows the pin states in an idle cycle.
Table 6.12 Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of following bus cycle
D15 to D0
CSn (n = 7 to 0)
High impedance
1 2
High* *
UCAS, LCAS
High*
AS
High
RD
High
2
(OE)
High
HWR, LWR
High
DACKn (n = 1, 0)
High
EDACKn (n = 3, 2)
High
Notes: 1. Remains low in DRAM space RAS down mode.
2. Remains low in a DRAM space refresh cycle.
6.10
Write Data Buffer Function
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables external writes and DMA single address mode transfers to be executed in parallel
with internal accesses. The write data buffer function is made available by setting the WDBE bit
to 1 in BCR.
Figure 6.83 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external address space write or DMA single address mode transfer continues
for two states or longer, and there is an internal access next, an external write only is executed in
the first state, but from the next state onward an internal access (on-chip memory or internal I/O
register read/write) is executed in parallel with the external address space write rather than waiting
until it ends.
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Section 6 Bus Controller (BSC)
On-chip memory read Internal I/O register read
External write cycle
T1
T2
TW
TW
T3
φ
Internal address bus
Internal memory
Internal I/O register address
Internal read signal
A23 to A0
External address
CSn
External space
write
HWR, LWR
D15 to D0
Figure 6.83 Example of Timing when Write Data Buffer Function Is Used
6.11
Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters except the EXDMAC* continue to operate as long
as there is no external access. If any of the following requests are issued in the external bus
released state, the BREQO signal can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode
Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
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Section 6 Bus Controller (BSC)
6.11.1
Operation
In externally expanded mode, the bus can be released to an external device by setting the BRLE
bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus released state.
In the external bus released state, internal bus masters except the EXDMAC can perform accesses
using the internal bus. When an internal bus master wants to make an external access, it
temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus
master to be canceled. If a refresh request is generated in the external bus released state, or if a
SLEEP instruction is executed to place the chip in software standby mode or all-module-clocksstopped mode, refresh control and software standby or all-module-clocks-stopped control is
deferred until the bus request from the external bus master is canceled.
If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the
following requests are issued, to request cancellation of the bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
If an external bus release request and external access occur simultaneously, the order of priority is
as follows:
(High) External bus release > External access by internal bus master (Low)
If a refresh request and external bus release request occur simultaneously, the order of priority is
as follows:
(High) Refresh > External bus release (Low)
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Section 6 Bus Controller (BSC)
6.11.2
Pin States in External Bus Released State
Table 6.13 shows pin states in the external bus released state.
Table 6.13 Pin States in Bus Released State
Pins
Pin State
A23 to A0
High impedance
D15 to D0
High impedance
CSn (n = 7 to 0)
High impedance
UCAS, LCAS
High impedance
AS
High impedance
RD
High impedance
(OE)
High impedance
HWR, LWR
High impedance
DACKn (n = 1, 0)
High
EDACKn (n = 3 to 0)
High
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Section 6 Bus Controller (BSC)
6.11.3
Transition Timing
Figure 6.84 shows the timing for transition to the bus released state.
External space
access cycle
CPU
cycle
External bus released state
T1
T2
φ
High impedance
Address bus
High impedance
Data bus
High impedance
AS
High impedance
RD
High impedance
HWR, LWR
BREQ
BACK
BREQO
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[1] Low level of BREQ signal is sampled at rise of φ.
[2] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
bus release while BREQOE bit is set to 1, BREQO signal goes low.
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal.
Figure 6.84 Bus Released State Transition Timing
Figure 6.85 shows the timing for transition to the bus released state with the synchronous DRAM
interface.
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Section 6 Bus Controller (BSC)
External space read
T1
CPU
cycle
External bus released state
T2
φ
SDRAMφ
High impedance
Address bus
High impedance
Data bus
Row
address
Precharge-sel
High impedance
High impedance
RAS
High impedance
CAS
High impedance
WE
High impedance
CKE
High impedance
DQMU, DQML
BREQ
BACK
BREQO
NOP
PALL
[1]
[2]
NOP
[3]
NOP
[4]
[5]
[8]
[6]
[7]
[9]
[1] Low level of BREQ signal is sampled at rise of φ.
[2] PALL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.
Note: In the H8S/2373 Group, the synchronous DRAM interface is not supported.
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface
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Section 6 Bus Controller (BSC)
6.12
Bus Arbitration
This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration).
There are four bus masters⎯the CPU, DTC, DMAC, and EXDMAC*⎯that perform read/write
operations when they have possession of the bus. Each bus master requests the bus by means of a
bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use
of the bus by means of a bus request acknowledge signal. The selected bus master then takes
possession of the bus and begins its operation.
Note: * The EXDMAC is not supported by the H8S/2375, H8S/2375R, H8S/2373, and
H8S/2373R.
6.12.1
Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.
The order of priority of the bus mastership is as follows:
(High) EXDMAC* > DMAC > DTC > CPU (Low)
An internal bus access by internal bus masters except the EXDMAC* and external bus release, a
refresh when the CBRM bit is 0, and an external bus access by the EXDMAC* can be executed in
parallel.
If an external bus release request, a refresh request, and an external access by an internal bus
master occur simultaneously, the order of priority is as follows:
(High) Refresh > EXDMAC* > External bus release (Low)
(High) External bus release > External access by internal bus master except EXDMAC* (Low)
As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to
DRAM space by an internal bus master can be executed simultaneously, there is no relative order
of priority for these two operations.
Note: * The EXDMAC is not supported by the H8S/2375, H8S/2375R, H8S/2373, and
H8S/2373R.
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Section 6 Bus Controller (BSC)
6.12.2
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific timings at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
DMAC, or EXDMAC*, the bus arbiter transfers the bus to the bus master that issued the request.
The timing for transfer of the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the component operations.
• With bit manipulation instructions such as BSET and BCLR, the sequence of operations is:
data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is
not transferred during this read-modify-write cycle, which is executed as a series of bus cycles.
• If the CPU is in sleep mode, the bus is transferred immediately.
Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is
generated.
In the case of an external request in short address mode or normal mode, and in cycle steal mode,
the DMAC releases the bus after a single transfer.
In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after
completion of the transfer. However, in the event of an EXDMAC or external bus release request,
which have a higher priority than the DMAC, the bus may be transferred to the bus master even if
block or burst transfer is in progress.
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Section 6 Bus Controller (BSC)
EXDMAC: The EXDMAC sends the bus arbiter a request for the bus when an activation request
is generated.
As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is
transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in
parallel.
In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single
transfer.
In block transfer mode, it releases the bus after transfer of one block, and in burst transfer mode,
after completion of the transfer. By setting the BGUP bit to 1 in EDMDR, it is possible to specify
temporary release of the bus in the event of an external access request from an internal bus master.
For details see section 8, EXDMA Controller (EXDMAC).
Note: Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
External Bus Release: When the BREQ pin goes low and an external bus release request is
issued while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
6.13
Bus Controller Operation in Reset
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
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Section 6 Bus Controller (BSC)
6.14
Usage Notes
6.14.1
External Bus Release Function and All-Module-Clocks-Stopped Mode
In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with
the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR =
H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR =
H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered
in which the clock is also stopped for the bus controller and I/O ports. In this state, the external
bus release function is halted. To use the external bus release function in sleep mode, the ACSE
bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in allmodule-clocks-stopped mode is executed in the external bus released state, the transition to allmodule-clocks-stopped mode is deferred and performed until after the bus is recovered.
6.14.2
External Bus Release Function and Software Standby
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode,
indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby state.
6.14.3
External Bus Release Function and CBR Refreshing/Auto Refreshing
CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the
BREQOE bit to 1 in BCR beforehand enables the BREQO signal to be output when a CBR
refresh/auto refresh request is issued.
Note: The auto refresh control is not supported by the H8S/2378 Group.
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Section 6 Bus Controller (BSC)
6.14.4
BREQO Output Timing
When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before
the BACK signal.
This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of BREQ.
6.14.5
Notes on Usage of the Synchronous DRAM
Setting of Synchronous DRAM Interface: The DCTL pin must be fixed to 1 to enable the
synchronous DRAM interface. Do not change the DCTL pin during operation.
Connection Clock: Be sure to set the clock to be connected to the synchronous DRAM to
SDRAMφ.
WAIT Pin: In the continuous synchronous DRAM space, insertion of the wait state by the WAIT
pin is disabled regardless of the setting of the WAITE bit in BCR.
Bank Control: This LSI cannot carry out the bank control of the synchronous DRAM. All banks
are selected.
Burst Access: The burst read/burst write mode of the synchronous DRAM is not supported.
When setting the mode register of the synchronous DRAM, set to the burst read/single write and
set the burst length to 1.
CAS Latency: When connecting a synchronous DRAM having CAS latency of 1, set the BE bit
to 0 in the DRAMCR.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
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Section 7 DMA Controller (DMAC)
Section 7 DMA Controller (DMAC)
This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4
channels.
7.1
Features
• Selectable as short address mode or full address mode
Short address mode
⎯ Maximum of 4 channels can be used
⎯ Dual address mode or single address mode can be selected
⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as 16 bits
⎯ In single address mode, transfer source or transfer destination address only is specified as
24 bits
⎯ In single address mode, transfer can be performed in one bus cycle
⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode
Full address mode
⎯ Maximum of 2 channels can be used
⎯ Transfer source and transfer destination addresses as specified as 24 bits
⎯ Choice of normal mode or block transfer mode
• 16-Mbyte address space can be specified directly
• Byte or word can be set as the transfer unit
• Activation sources: internal interrupt, external request, auto-request (depending on transfer
mode)
⎯ Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts
⎯ Serial communication interface (SCI_0, SCI_1) transmission complete interrupt, reception
complete interrupt
⎯ A/D converter conversion end interrupt
⎯ External request
⎯ Auto-request
• Module stop mode can be set
DMAS260A_010020020400
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Section 7 DMA Controller (DMAC)
A block diagram of the DMAC is shown in figure 7.1.
Internal address bus
Address buffer
DMAWER
DMACR0A
DMACR0B
DMACR1A
DMACR1B
DMABCR
Channel 1
DMATCR
MAR_0AH
ETCR_0A
MAR_0BH
IOAR_0B
MAR_1AH
MAR_1AL
IOAR_1A
ETCR_1A
MAR_1BH
Internal data bus
: DMA write enable register
: DMA terminal control register
: DMA band control register (for all channels)
: DMA control register
: Memory address register
: I/O address register
: Execute transfer count register
Figure 7.1 Block Diagram of DMAC
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MAR_0BL
ETCR_0B
Data buffer
Legend:
DMAWER
DMATCR
DMABCR
DMACR
MAR
IOAR
ETCR
MAR_0AL
IOAR_0A
MAR_1BL
IOAR_1B
ETCR_1B
Module data bus
Control logic
Channel 0
Processor
Channel 1B Channel 1A Channel 0B Channel 0A
Internal interrupts
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI
External pins
DREQ0
DREQ1
TEND0
TEND1
DACK0
DACK1
Interrupt signals
DMTEND0A
DMTEND0B
DMTEND1A
DMTEND1B
Section 7 DMA Controller (DMAC)
7.2
Input/Output Pins
Table 7.1 shows the pin configuration of the interrupt controller.
Table 7.1
Pin Configuration
Channel
Pin Name
Symbol
I/O
Function
0
DMA request 0
DREQ0
Input
Channel 0 external request
DMA transfer acknowledge 0
DACK0
Output
Channel 0 single address
transfer acknowledge
DMA transfer end 0
TEND0
Output
Channel 0 transfer end
DMA request 1
DREQ1
Input
Channel 1 external request
DMA transfer acknowledge 1
DACK1
Output
Channel 1 single address
transfer acknowledge
DMA transfer end 1
TEND1
Output
Channel 1 transfer end
1
7.3
Register Descriptions
• Memory address register_0AH (MAR_0AH)
• Memory address register_0AL (MAR_0AL)
• I/O address register_0A (IOAR_0A)
• Transfer count register_0A (ECTR_0A)
• Memory address register_0BH (MAR_0BH)
• Memory address register_0BL (MAR_0BL)
• I/O address register_0B (IOAR_0B)
• Transfer count register_0B (ECTR_0B)
• Memory address register_1AH (MAR_1AH)
• Memory address register_1AL (MAR_1AL)
• I/O address register_1A (IOAR_1A)
• Transfer count register_1A (ETCR_1B)
• Memory address register_1BH (MAR_1BH)
• Memory address register_1BL (MAR_1BL)
• I/O address register_1B (IOAR_1B)
• Transfer count register_1B (ETCR_1B)
• DMA control register_0A (DMACR_0A)
• DMA control register_0B (DMACR_0B)
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Section 7 DMA Controller (DMAC)
• DMA control register_1A (DMACR_1A)
• DMA control register_1B (DMACR_1B)
• DMA band control register H (DMABCRH)
• DMA band control register L (DMABCRL)
• DMA write enable register (DMAWER)
• DMA terminal control register (DMATCR)
The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer
mode (short address mode or full address mode). The transfer mode can be selected by means of
the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and
full address mode of channel 0 are shown in table 7.2.
Table 7.2
Short Address Mode and Full Address Mode (Channel 0)
0
Short address mode specified (channels 0A and 0B operate independently)
1
Channel 0A
Description
MAR_0AH
Channel 0B
FAE0
MAR_0BH
MAR_0AL
Specifies transfer source/transfer destination address
IOAR_0A
Specifies transfer destination/transfer source address
ETCR_0A
Specifies number of transfers
DMACR_0A
MAR_0BL
Specifies transfer size, mode, activation source.
Specifies transfer source/transfer destination address
IOAR_0B
Specifies transfer destination/transfer source address
ETCR_0B
Specifies number of transfers
DMACR_0B
Specifies transfer size, mode, activation source.
Full address mode specified (channels 0A and 0B operate in combination as channel 0)
MAR_0AH
Channel 0
MAR_0BH
MAR_0AL
Specifies transfer source address
MAR_0BL
Specifies transfer destination address
IOAR_0A
IOAR_0B
ETCR_0A
ETCR_0B
DMACR_0A DMACR_0B
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Not used
Not used
Specifies number of transfers
Specifies number of transfers (used in block transfer
mode only)
Specifies transfer size, mode, activation source, etc.
Section 7 DMA Controller (DMAC)
7.3.1
Memory Address Registers (MARA and MARB)
MAR is a 32-bit readable/writable register that specifies the source address (transfer source
address) or destination address (transfer destination address). MAR consists of two 16-bit registers
MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and
cannot be modified.
The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0
(channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B).
MAR is not initialized by a reset or in standby mode.
Short Address Mode: In short address mode, MARA and MARB operate independently.
Whether MAR functions as the source address register or as the destination address register can be
selected by means of the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated.
Full Address Mode: In full address mode, MARA functions as the source address register, and
MARB as the destination address register.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination address is constantly updated.
7.3.2
I/O Address Registers (IOARA and IOARB)
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address
(transfer source address) or destination address (transfer destination address). The upper 8 bits of
the transfer address are automatically set to H'FF.
The DMA has four IOAR registers: IOAR_0A in channel 0 (channel 0A), IOAR_0B in channel 0
(channel 0B), IOAR_1A in channel 1 (channel 1A), and IOAR_1B in channel 1 (channel 1B).
Whether IOAR functions as the source address register or as the destination address register can
be selected by means of the DTDIR bit in DMACR.
IOAR is not incremented or decremented each time a data transfer is executed, so the address
specified by IOAR is fixed.
IOAR is not initialized by a reset or in standby mode.
IOAR can be used in short address mode but not in full address mode.
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Section 7 DMA Controller (DMAC)
7.3.3
Execute Transfer Count Registers (ETCRA and ETCRB)
ETCR is a 16-bit readable/writable register that specifies the number of transfers.
The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0
(channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B).
ETCR is not initialized by a reset or in standby mode.
Short Address Mode: The function of ETCR in sequential mode and idle mode differs from that
in repeat mode.
In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is
decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit
in DMABCRL is cleared, and transfer ends.
In repeat mode, ETCRL functions as an 8-bit transfer counter and ETCRH functions as a transfer
count holding register. ETCRL is decremented by 1 each time a transfer is performed, and when
the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is
automatically restored to the value it had when the count was started. The DTE bit in DMABCRL
is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the
user.
Full Address Mode: The function of ETCR in normal mode differs from that in block transfer
mode.
In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each
time a data transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not
used in normal mode.
In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH functions
as a block size holding register. ETCRAL is decremented by 1 each time a 1-byte or 1-word
transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in
ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly
transfer blocks consisting of any desired number of bytes or words.
In block transfer mode, ETCRB functions as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time a block is transferred, and transfer ends when the count reaches
H'0000.
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Section 7 DMA Controller (DMAC)
7.3.4
DMA Control Registers (DMACRA and DMACRB)
DMACR controls the operation of each DMAC channel.
The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in
channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1
(channel 1B).
In short address mode, channels A and B operate independently, and in full address mode,
channels A and B operate together. The bit functions in the DMACR registers differ according to
the transfer mode.
Short Address Mode:
• DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B
Bit
Bit Name
Initial Value
R/W
7
DTSZ
0
R/W
Description
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
6
DTID
0
R/W
Data Transfer Increment/Decrement
Selects incrementing or decrementing of MAR after
every data transfer in sequential mode or repeat
mode. In idle mode, MAR is neither incremented
nor decremented.
0: MAR is incremented after a data transfer
(Initial value)
•
When DTSZ = 0, MAR is incremented by 1
•
When DTSZ = 1, MAR is incremented by 2
1: MAR is decremented after a data transfer
•
When DTSZ = 0, MAR is decremented by 1
•
When DTSZ = 1, MAR is decremented by 2
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
5
RPE
0
R/W
Repeat Enable
Used in combination with the DTIE bit in DMABCR
to select the mode (sequential, idle, or repeat) in
which transfer is to be performed.
•
When DTIE = 0 (no transfer end interrupt)
0: Transfer in sequential mode
1: Transfer in repeat mode
•
When DTIE = 1 (with transfer end interrupt)
0: Transfer in sequential mode
1: Transfer in idle mode
4
DTDIR
0
R/W
Data Transfer Direction
Used in combination with the SAE bit in DMABCR
to specify the data transfer direction (source or
destination). The function of this bit is therefore
different in dual address mode and single address
mode.
•
When SAE = 0
0: Transfer with MAR as source address and IOAR
as destination address
1: Transfer with IOAR as source address and MAR
as destination address
•
When SAE = 1
0: Transfer with MAR as source address and DACK
pin as write strobe
1: Transfer with DACK pin as read strobe and MAR
as destination address
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
Data Transfer Factor 3 to 0
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
These bits select the data transfer factor (activation
source). There are some differences in activation
sources for channel A and channel B.
•
Channel A
0000: Setting prohibited
0001: Activated by A/D converter conversion end
interrupt
0010: Setting prohibited
0011: Setting prohibited
0100: Activated by SCI channel 0 transmission
complete interrupt
0101: Activated by SCI channel 0 reception
complete interrupt
0110: Activated by SCI channel 1 transmission
complete interrupt
0111: Activated by SCI channel 1 reception
complete interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
•
2
DTF2
0
R/W
0000: Setting prohibited
1
DTF1
0
R/W
0
DTF0
0
R/W
0001: Activated by A/D converter conversion end
interrupt
Channel B
0010: Activated by DREQ pin falling edge input
(detected as a low level in the first transfer
after transfer is enabled)
0011: Activated by DREQ pin low-level input
0100: Activated by SCI channel 0 transmission
complete interrupt
0101: Activated by SCI channel 0 reception
complete interrupt
0110: Activated by SCI channel 1 transmission
complete interrupt
0111: Activated by SCI channel 1 reception
complete interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
The same factor can be selected for more than one
channel. In this case, activation starts with the
highest-priority channel according to the relative
channel priorities. For relative channel priorities,
see section 7.5.12, Multi-Channel Operation.
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Section 7 DMA Controller (DMAC)
Full Address Mode:
• DMACR_0A and DMACR_1A
Bit
Bit Name
Initial Value
R/W
15
DTSZ
0
R/W
Description
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
14
SAID
0
R/W
Source Address Increment/Decrement
13
SAIDE
0
R/W
Source Address Increment/Decrement Enable
These bits specify whether source address register
MARA is to be incremented, decremented, or left
unchanged, when data transfer is performed.
00: MARA is fixed
01: MARA is incremented after a data transfer
•
When DTSZ = 0, MARA is incremented by 1
•
When DTSZ = 1, MARA is incremented by 2
10: MARA is fixed
11: MARA is decremented after a data transfer
•
When DTSZ = 0, MARA is decremented by 1
•
When DTSZ = 1, MARA is decremented by 2
12
BLKDIR
0
R/W
Block Direction
11
BLKE
0
R/W
Block Enable
These bits specify whether normal mode or block
transfer mode is to be used for data transfer. If
block transfer mode is specified, the BLKDIR bit
specifies whether the source side or the destination
side is to be the block area.
x0: Transfer in normal mode
01: Transfer in block transfer mode (destination
side is block area)
11: Transfer in block transfer mode (source side is
block area)
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
10 to
8
⎯
All 0
R/W
Reserved
These bits can be read from or written to. However,
the write value should always be 0.
Legend:
x: Don’t care
• DMACR_0B and DMACR_1B
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
6
5
DAID
DAIDE
0
0
R/W
R/W
Destination Address Increment/Decrement
Destination Address Increment/Decrement Enable
These bits specify whether destination address
register MARB is to be incremented, decremented,
or left unchanged, when data transfer is performed.
00: MARB is fixed
01: MARB is incremented after a data transfer
•
When DTSZ = 0, MARB is incremented by 1
•
When DTSZ = 1, MARB is incremented by 2
10: MARB is fixed
11: MARB is decremented after a data transfer
4
—
0
R/W
•
When DTSZ = 0, MARB is decremented by 1
•
When DTSZ = 1, MARB is decremented by 2
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
Data Transfer Factor 3 to 0
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
These bits select the data transfer factor (activation
source). The factors that can be specified differ
between normal mode and block transfer mode.
•
Normal Mode
0000: Setting prohibited
0001: Setting prohibited
0010: Activated by DREQ pin falling edge input
(detected as a low level in the first transfer
after transfer is enabled)
0011: Activated by DREQ pin low-level input
010x: Setting prohibited
0110: Auto-request (cycle steal)
0111: Auto-request (burst)
1×××: Setting prohibited
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
•
2
DTF2
0
R/W
0000: Setting prohibited
1
DTF1
0
R/W
0
DTF0
0
R/W
0001: Activated by A/D converter conversion end
interrupt
Block Transfer Mode
0010: Activated by DREQ pin falling edge input
0011: Activated by DREQ pin low-level input
0100: Activated by SCI channel 0 transmission
complete interrupt
0101: Activated by SCI channel 0 reception
complete interrupt
0110: Activated by SCI channel 1 transmission
complete interrupt
0111: Activated by SCI channel 1 reception
complete interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
The same factor can be selected for more than one
channel. In this case, activation starts with the
highest-priority channel according to the relative
channel priorities. For relative channel priorities,
see section 7.5.12, Multi-Channel Operation.
Legend:
×: Don’t care
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Section 7 DMA Controller (DMAC)
7.3.5
DMA Band Control Registers H and L (DMABCRH and DMABCRL)
DMABCR controls the operation of each DMAC channel. The bit functions in the DMACR
registers differ according to the transfer mode.
Short Address Mode:
• DMABCRH
Bit
Bit Name
Initial Value
R/W
Description
15
FAE1
0
R/W
Full Address Enable 1
Specifies whether channel 1 is to be used in short
address mode or full address mode. In short
address mode, channels 1A and 1B can be used
as independent channels.
0: Short address mode
1: Full address mode
14
FAE0
0
R/W
Full Address Enable 0
Specifies whether channel 0 is to be used in short
address mode or full address mode. In short
address mode, channels 0A and 0B can be used
as independent channels.
0: Short address mode
1: Full address mode
13
SAE1
0
R/W
Single Address Enable 1
Specifies whether channel 1B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
12
SAE0
0
R/W
Single Address Enable 0
Specifies whether channel 0B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
11
DTA1B
0
R/W
Data Transfer Acknowledge 1B
10
DTA1A
0
R/W
Data Transfer Acknowledge 1A
9
DTA0B
0
R/W
Data Transfer Acknowledge 0B
8
DTA0A
0
R/W
Data Transfer Acknowledge 0A
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR.
It the DTA bit is set to 1 when DTE = 1, the internal
interrupt source is cleared automatically by DMA
transfer. When DTE = 1 and DTA = 1, the internal
interrupt source does not issue an interrupt request
to the CPU or DTC.
If the DTA bit is cleared to 0 when DTE = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this case,
the interrupt source should be cleared by the CPU
or DTC transfer.
When DTE = 0, the internal interrupt source issues
an interrupt request to the CPU or DTC regardless
of the DTA bit setting.
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Section 7 DMA Controller (DMAC)
• DMABCRL
Bit
Bit Name
Initial Value
R/W
Description
7
DTE1B
0
R/W
Data Transfer Enable 1B
6
DTE1A
0
R/W
Data Transfer Enable 1A
5
DTE0B
0
R/W
Data Transfer Enable 0B
4
DTE0A
0
R/W
Data Transfer Enable 0A
If the DTE bit is cleared to 0 when DTIE = 1, the
DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt request
to the CPU or DTC.
When DTE = 0, data transfer is disabled and the
DMAC ignores the activation source selected by
the DTF3 to DTF0 bits in DMACR.
When DTE = 1, data transfer is enabled and the
DMAC waits for a request by the activation source
selected by the DTF3 to DTF0 bits in DMACR.
When a request is issued by the activation source,
DMA transfer is executed.
[Clearing conditions]
•
When initialization is performed
•
When the specified number of transfers have
been completed in a transfer mode other than
repeat mode
•
When 0 is written to the DTE bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE bit after reading DTE
=0
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTIE1B
0
R/W
Data Transfer End Interrupt Enable 1B
2
DTIE1A
0
R/W
Data Transfer End Interrupt Enable 1A
1
DTIE0B
0
R/W
Data Transfer End Interrupt Enable 0B
0
DTIE0A
0
R/W
Data Transfer End Interrupt Enable 0A
These bits enable or disable an interrupt to the
CPU or DTC when transfer ends. If the DTIE bit is
set to 1 when DTE = 0, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE bit to 0 in the interrupt handling
routine, or by performing processing to continue
transfer by setting the transfer counter and address
register again, and then setting the DTE bit to 1.
Full Address Mode:
• DMABCRH
Bit
Bit Name
Initial Value
R/W
Description
15
FAE1
0
R/W
Full Address Enable 1
Specifies whether channel 1 is to be used in short
address mode or full address mode.
In full address mode, channels 1A and 1B are used
together as channel 1.
0: Short address mode
1: Full address mode
14
FAE0
0
R/W
Full Address Enable 0
Specifies whether channel 0 is to be used in short
address mode or full address mode.
In full address mode, channels 0A and 0B are used
together as channel 0.
0: Short address mode
1: Full address mode
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
13, 12 —
Initial Value
R/W
Description
All 0
R/W
Reserved
These bits can be read from or written to. However,
the write value should always be 0.
11
DTA1
0
R/W
Data Transfer Acknowledge 1
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR of channel 1.
It the DTA1 bit is set to 1 when DTE1 = 1, the
internal interrupt source is cleared automatically by
DMA transfer. When DTE1 = 1 and DTA1 = 1, the
internal interrupt source does not issue an interrupt
request to the CPU or DTC.
It the DTA1 bit is cleared to 0 when DTE1 = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this case,
the interrupt source should be cleared by the CPU
or DTC transfer.
When DTE1 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA1 bit setting.
The state of the DTME1 bit does not affect the
above operations.
10
—
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
9
DTA0
0
R/W
Data Transfer Acknowledge 0
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR of channel 0.
It the DTA0 bit is set to 1 when DTE0 = 1, the
internal interrupt source is cleared automatically by
DMA transfer. When DTE0 = 1 and DTA0 = 1, the
internal interrupt source does not issue an interrupt
request to the CPU or DTC.
It the DTA0 bit is cleared to 0 when DTE0 = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this case,
the interrupt source should be cleared by the CPU
or DTC transfer.
When DTE0 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA0 bit setting.
The state of the DTME0 bit does not affect the
above operations.
8
—
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Section 7 DMA Controller (DMAC)
• DMABCRL
Bit
Bit Name
Initial Value
R/W
Description
7
DTME1
0
R/W
Data Transfer Master Enable 1
Together with the DTE1 bit, this bit controls
enabling or disabling of data transfer on channel 1.
When both the DTME1 bit and DTE1 bit are set to
1, transfer is enabled for channel 1.
If channel 1 is in the middle of a burst mode
transfer when an NMI interrupt is generated, the
DTME1 bit is cleared, the transfer is interrupted,
and bus mastership passes to the CPU. When the
DTME1 bit is subsequently set to 1 again, the
interrupted transfer is resumed. In block transfer
mode, however, the DTME1 bit is not cleared by an
NMI interrupt, and transfer is not interrupted.
[Clearing conditions]
•
When initialization is performed
•
When NMI is input in burst mode
•
When 0 is written to the DTME1 bit
[Setting condition]
When 1 is written to DTME1 after reading DTME1 =
0
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
6
DTE1
0
R/W
Data Transfer Enable 1
Enables or disables DMA transfer for the activation
source selected by the DTF3 to DTF0 bits in
DMACR of channel 1.
When DTE1 = 0, data transfer is disabled and the
activation source is ignored. If the activation source
is an internal interrupt, an interrupt request is
issued to the CPU or DTC. If the DTE1 bit is
cleared to 0 when DTIE1 = 1, the DMAC regards
this as indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU.
When DTE1 = 1 and DTME1 = 1, data transfer is
enabled and the DMAC waits for a request by the
activation source. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
•
When initialization is performed
•
When the specified number of transfers have
been completed
•
When 0 is written to the DTE1 bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE1 bit after reading
DTE1 = 0
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
5
DTME0
0
R/W
Data Transfer Master Enable 0
Together with the DTE0 bit, this bit controls
enabling or disabling of data transfer on channel 0.
When both the DTME0 bit and DTE0 bit are set to
1, transfer is enabled for channel 0.
If channel 0 is in the middle of a burst mode
transfer when an NMI interrupt is generated, the
DTME0 bit is cleared, the transfer is interrupted,
and bus mastership passes to the CPU. When the
DTME0 bit is subsequently set to 1 again, the
interrupted transfer is resumed. In block transfer
mode, however, the DTME0 bit is not cleared by an
NMI interrupt, and transfer is not interrupted.
[Clearing conditions]
•
When initialization is performed
•
When NMI is input in burst mode
•
When 0 is written to the DTME0 bit
[Setting condition]
When 1 is written to DTME0 after reading DTME0 =
0
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
4
DTE0
0
R/W
Data Transfer Enable 0
Enables or disables DMA transfer for the activation
source selected by the DTF3 to DTF0 bits in
DMACR of channel 0.
When DTE0 = 0, data transfer is disabled and the
activation source is ignored. If the activation source
is an internal interrupt, an interrupt request is
issued to the CPU or DTC. If the DTE0 bit is
cleared to 0 when DTIE0 = 1, the DMAC regards
this as indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU.
When DTE0 = 1 and DTME0 = 1, data transfer is
enabled and the DMAC waits for a request by the
activation source. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
•
When initialization is performed
•
When the specified number of transfers have
been completed
•
When 0 is written to the DTE0 bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE0 bit after reading
DTE0 = 0
3
DTIE1B
0
R/W
Data Transfer Interrupt Enable 1B
Enables or disables an interrupt to the CPU or DTC
when transfer on channel 1 is interrupted. If the
DTME1 bit is cleared to 0 when DTIE1B = 1, the
DMAC regards this as indicating a break in the
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either by
clearing the DTIE1B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME1 bit to 1.
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Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
2
DTIE1A
0
R/W
Data Transfer End Interrupt Enable 1A
Enables or disables an interrupt to the CPU or DTC
when transfer ends. If the DTE1 bit is cleared to 1
when DTIE1A = 1, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE1A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE1 bit to 1.
1
DTIE0B
0
R/W
Data Transfer Interrupt Enable 0B
Enables or disables an interrupt to the CPU or DTC
when transfer on channel 1 is interrupted. If the
DTME0 bit is cleared to 0 when DTIE0B = 1, the
DMAC regards this as indicating a break in the
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either by
clearing the DTIE0B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME0 bit to 1.
0
DTIE0A
0
R/W
Data Transfer End Interrupt Enable 0A
Enables or disables an interrupt to the CPU or DTC
when transfer ends. If the DTE0 bit is cleared to 0
when DTIE0A = 1, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE0A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE0 bit to 1.
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Section 7 DMA Controller (DMAC)
7.3.6
DMA Write Enable Register (DMAWER)
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies
restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for
the specific channel, to prevent inadvertent rewriting of registers other than those for the channel
concerned. The restrictions applied by DMAWER are valid for the DTC.
Bit
Bit Name
Initial Value
R/W
7
to
4
⎯
All 0
—
3
WE1B
Description
Reserved
These bits are always read as 0 and cannot be
modified.
0
R/W
Write Enable 1B
Enables or disables writes to all bits in DMACR1B,
bits 11, 7, and 3 in DMABCR, and bit 5 in
DMATCR.
0: Writes are disabled
1: Writes are enabled
2
WE1A
0
R/W
Write Enable 1A
Enables or disables writes to all bits in DMACR1A,
and bits 10, 6, and 2 in DMABCR.
0: Writes are disabled
1: Writes are enabled
1
WE0B
0
R/W
Write Enable 0B
Enables or disables writes to all bits in DMACR0B,
bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR.
0: Writes are disabled
1: Writes are enabled
0
WE0A
0
R/W
Write Enable 0A
Enables or disables writes to all bits in DMACR0A,
and bits 8, 4, and 0 in DMABCR.
0: Writes are disabled
1: Writes are enabled
Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt
request, and reactivating channel 0A. The address register and count register areas are set again
during the first DTC transfer, then the control register area is set again during the second DTC
Rev.7.00 Mar. 18, 2009 page 304 of 1136
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Section 7 DMA Controller (DMAC)
chain transfer. When re-setting the control register area, perform masking by setting bits in
DMAWER to prevent modification of the contents of other channels.
First transfer area
MAR_0A
IOAR_0A
ETCR_0A
MAR_0B
IOAR_0B
ETCR_0B
MAR_1A
DTC
IOAR_1A
ETCR_1A
MAR_1B
IOAR_1B
ETCR_1B
Second transfer area
using chain transfer
DMAWER
DMATCR
DMACR_0A
DMACR_0B
DMACR_1A
DMACR_1B
DMABCR
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When
modifying these registers, the channel to be modified should be halted.
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Section 7 DMA Controller (DMAC)
7.3.7
DMA Terminal Control Register (DMATCR)
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The
TEND pin is available only for channel B in short address mode. Except for the block transfer
mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents
reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal
asserts in the transfer cycle in which the block counter contents reaches 0.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
5
TEE1
0
R/W
Transfer End Enable 1
Enables or disables transfer end pin 1 (TEND1)
output.
0: TEND1 pin output disabled
1: TEND1 pin output enabled
4
TEE0
0
R/W
Transfer End Enable 0
Enables or disables transfer end pin 0 (TEND0)
output.
0: TEND0 pin output disabled
1: TEND0 pin output enabled
3
to
0
⎯
All 0
⎯
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Reserved
These bits are always read as 0 and cannot be
modified.
Section 7 DMA Controller (DMAC)
7.4
Activation Sources
DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and
channel, as shown in table 7.3.
Table 7.3
DMAC Activation Sources
Activation Source
Internal
interrupts
Short Address Mode
Full Address Mode
Channels
0A and 1A
Normal
Mode
Channels
0B and 1B
ADI
×
TXI0
×
RXI0
×
TXI1
×
RXI1
×
TGI0A
×
TGI1A
×
TGI2A
×
TGI3A
×
TGI4A
×
×
TGI5A
External
requests
DREQ pin falling edge input
×
DREQ pin low-level input
×
Auto-request
Block
Transfer
Mode
×
×
×
Legend:
: Can be specified
×: Cannot be specified
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Section 7 DMA Controller (DMAC)
7.4.1
Activation by Internal Interrupt Request
An interrupt request selected as a DMAC activation source can also simultaneously generate an
interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt request, the DMAC accepts the interrupt request
independently of the interrupt controller. Consequently, interrupt controller priority settings are
irrelevant.
If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a
DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA
transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared
unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an
activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated. Transfer requests for other channels are held pending in the DMAC,
and activation is carried out in order of priority.
When DTE = 0 after completion of a transfer, an interrupt request from the selected activation
source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant
interrupt request is sent to the CPU or DTC.
When an interrupt request signal for DMAC activation is also used for an interrupt request to the
CPU or DTC activation (DTA = 0), the interrupt request flag is not cleared by the DMAC.
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Section 7 DMA Controller (DMAC)
7.4.2
Activation by External Request
If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port
should be set to input mode in advance*. Level sensing or edge sensing can be used for external
requests.
External request operation in normal mode of short address mode or full address mode is
described below.
When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is
detected on the DREQ pin. The next data transfer may not be performed if the next edge is input
before data transfer is completed.
When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is
held high. While the DREQ pin is held low, transfers continue in succession, with the bus being
released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
Note: * If the relevant port is set as an output pin for another function, DMA transfers using the
channel in question cannot be guaranteed.
7.4.3
Activation by Auto-Request
Auto-request is activated by register setting only, and transfer continues to the end. With autorequest activation, cycle steal mode or burst mode can be selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC
keeps possession of the bus until the end of the transfer so that transfer is performed continuously.
7.5
Operation
7.5.1
Transfer Modes
Table 7.4 lists the DMAC transfer modes.
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Section 7 DMA Controller (DMAC)
Table 7.4
DMAC Transfer Modes
Transfer Mode
Short
address
mode
Transfer Source
Dual address mode
• TPU channel 0 to 5
compare match/input
• 1-byte or 1-word transfer
for a single transfer request capture A interrupt
• SCI transmission
• Specify source and
complete interrupt
destination addresses to
transfer data in two bus
cycles.
(1) Sequential mode
• Memory address
incremented or
decremented by 1 or 2
• SCI reception complete
interrupt
Remarks
• Up to 4 channels can
operate independently
• External request applies
to channel B only
• Single address mode
applies to channel B only
• A/D converter
conversion end
interrupt
• External request
• Number of transfers: 1 to
65,536
(2) Idle mode
• Memory address fixed
• Number of transfers: 1 to
65,536
(3) Repeat mode
• Memory address
incremented or
decremented by 1 or 2
• Continues transfer after
sending number of
transfers (1 to 256) and
restoring the initial value
Single address mode
• 1-byte or 1-word transfer
for a single transfer request
• 1-bus cycle transfer by
means of DACK pin instead
of using address for
specifying I/O
• Sequential mode, idle
mode, or repeat mode can
be specified
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• External request
• Up to 4 channels can
operate independently
• External request applies
to channel B only
• Single address mode
applies to channel B only
Section 7 DMA Controller (DMAC)
Transfer Mode
Full
address
mode
Normal mode
Transfer Source
Remarks
• Auto-request
• Max. 2-channel
operation, combining
channels A and B
(1) Auto-request
• Transfer request is
internally held
• Number of transfers (1 to
65,536) is continuously
sent
• Burst/cycle steal transfer
can be selected
(2) External request
• External request
• 1-byte or 1-word transfer
for a single transfer request
• Number of transfers: 1 to
65,536
Block transfer mode
• Transfer of 1-block, size
selected for a single
transfer request
• Number of transfers: 1 to
65,536
• Source or destination can
be selected as block area
• Block size: 1 to 256 bytes
or word
• TPU channel 0 to 5
compare match/input
capture A interrupt
• SCI transmission
complete interrupt
• SCI reception complete
interrupt
• A/D converter
conversion end
interrupt
• External request
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Section 7 DMA Controller (DMAC)
7.5.2
Sequential Mode
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.5 summarizes register functions in sequential mode.
Table 7.5
Register Functions in Sequential Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
15
H'FF
IOAR
15
0
Incremented/
Destination Start address of
transfer destination decremented every
address
transfer
or transfer source
register
0
Source
address
register
0
Destination Source
address
address
register
register
Start address of
Fixed
transfer source or
transfer destination
Transfer counter
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
MAR
23
Operation
ETCR
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Figure 7.3 illustrates operation in sequential mode.
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Section 7 DMA Controller (DMAC)
Address T
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Address B
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7.3 Operation in Sequential Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data
transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or
DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
Figure 7.4 shows an example of the setting procedure for sequential mode.
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Section 7 DMA Controller (DMAC)
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Sequential mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Sequential mode
Figure 7.4 Example of Sequential Mode Setting Procedure
7.5.3
Idle Mode
Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In
idle mode, one byte or word is transferred in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6
summarizes register functions in idle mode.
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Section 7 DMA Controller (DMAC)
Table 7.6
Register Functions in Idle Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0
Source
address
register
0
Destination Source
address
address
register
register
Fixed
Start address of
transfer source or
transfer destination
Transfer counter
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
MAR
23
15
H'FF
IOAR
15
0
Operation
Destination Start address of
Fixed
address
transfer destination
register
or transfer source
ETCR
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the
other address. The upper 8 bits of IOAR have a value of H'FF.
Figure 7.5 illustrates operation in idle mode.
MAR
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Figure 7.5 Operation in Idle Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer
ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The
maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
Figure 7.6 shows an example of the setting procedure for idle mode.
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Section 7 DMA Controller (DMAC)
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Idle mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Set the DTIE bit to 1.
• Set the DTE bit to 1 to enable transfer.
Read DMABCRL
[5]
Set DMABCRL
[6]
Idle mode
Figure 7.6 Example of Idle Mode Setting Procedure
7.5.4
Repeat Mode
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in
DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to
a single transfer request, and this is executed the number of times specified in ETCRL. On
completion of the specified number of transfers, MAR and ETCRL are automatically restored to
their original settings and operation continues. One address is specified by MAR, and the other by
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Section 7 DMA Controller (DMAC)
IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7
summarizes register functions in repeat mode.
Table 7.7
Register Functions in Repeat Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0
Source
address
register
0
Destination Source
address
address
register
register
Fixed
Start address of
transfer source or
transfer destination
Holds number of
transfers
Number of transfers Fixed
Transfer counter
Number of transfers Decremented every
transfer.
Loaded with ETCRH
value when count
reaches H'00
MAR
23
15
H'FF
IOAR
7
0
ETCRH
7
0
Operation
Destination Start address of
Incremented/
address
transfer destination decremented every
register
or transfer source
transfer.
Initial setting is
restored when value
reaches H'0000
ETCRL
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of
transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when
H'00 is set in both ETCRH and ETCRL, is 256.
In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number
of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value
reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is
restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR
restoration operation is as shown below.
MAR = MAR – (–1)DTID · 2DTSZ · ETCRH
The same value should be set in ETCRH and ETCRL.
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Section 7 DMA Controller (DMAC)
In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the
transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is
not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the
operation can be restarted from the transfer after that terminated when the DTE bit was cleared.
Figure 7.7 illustrates operation in repeat mode.
Transfer
Address T
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Address B
Figure 7.7 Operation in Repeat mode
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
Figure 7.8 shows an example of the setting procedure for repeat mode.
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Section 7 DMA Controller (DMAC)
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Repeat mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in both ETCRH and
ETCRL.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Clear the DTIE bit to 0.
• Set the DTE bit to 1 to enable transfer.
Repeat mode
Figure 7.8 Example of Repeat Mode Setting Procedure
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Section 7 DMA Controller (DMAC)
7.5.5
Single Address Mode
Single address mode can only be specified for channel B. This mode can be specified by setting
the SAE bit in DMABCRH to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.8 summarizes register functions in single address mode.
Table 7.8
Register Functions in Single Address Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0
MAR
DACK pin
15
0
Operation
Source
address
register
See sections 7.5.2,
Destination Start address of
transfer destination Sequential Mode,
address
7.5.3, Idle Mode, and
or transfer source
register
7.5.4, Repeat Mode.
Write
strobe
Read
strobe
Transfer counter
ETCR
(Set automatically Strobe for external
by SAE bit; IOAR is device
invalid)
Number of transfers See sections 7.5.2,
Sequential Mode,
7.5.3, Idle Mode, and
7.5.4, Repeat Mode.
MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is
invalid; in its place the strobe for external devices (DACK) is output.
Figure 7.9 illustrates operation in single address mode (when sequential mode is specified).
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Section 7 DMA Controller (DMAC)
Address T
DACK
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Address B
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified)
Figure 7.10 shows an example of the setting procedure for single address mode (when sequential
mode is specified).
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Section 7 DMA Controller (DMAC)
Single address
mode setting
Set DMABCRH
Set transfer source and
transfer destination
addresses
[1]
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Set the SAE bit to 1 to select single address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
[2] Set the transfer source address/transfer
destination address in MAR.
[2]
Set number of transfers
[3]
Set DMACR
[4]
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Single address mode
Figure 7.10 Example of Single Address Mode Setting Procedure (When Sequential Mode Is
Specified)
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Section 7 DMA Controller (DMAC)
7.5.6
Normal Mode
In normal mode, transfer is performed with channels A and B used in combination. Normal mode
can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in
DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response
to a single transfer request, and this is executed the number of times specified in ETCRA. The
transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9
summarizes register functions in normal mode.
Table 7.9
Register Functions in Normal Mode
Register
23
Function
Initial Setting
Operation
0
Source address
register
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
0
Destination
address register
Start address of
Incremented/decremented
transfer destination every transfer, or fixed
MARA
23
MARB
15
0
ETCRA
Transfer counter Number of transfers Decremented every
transfer; transfer ends
when count reaches
H'0000
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time
a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCRL is cleared
and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this time, an interrupt request is sent
to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
Figure 7.11 illustrates operation in normal mode.
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Section 7 DMA Controller (DMAC)
Transfer
Address TA
Address BB
Address BA
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
Address TB
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRA
Figure 7.11 Operation in Normal Mode
Transfer requests (activation sources) are external requests and auto-requests. With auto-request,
the DMAC is only activated by register setting, and the specified number of transfers are
performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In
cycle steal mode, the bus is released to another bus master each time a transfer is performed. In
burst mode, the bus is held continuously until transfer ends.
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Section 7 DMA Controller (DMAC)
Figure 7.12 shows an example of the setting procedure for normal mode.
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Normal mode setting
Set DMABCRH
[1]
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the number of transfers in ETCRA.
Set transfer source and
transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Clear the BLKE bit to 0 to select normal
mode.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Normal mode
Figure 7.12 Example of Normal Mode Setting Procedure
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Section 7 DMA Controller (DMAC)
7.5.7
Block Transfer Mode
In block transfer mode, data transfer is performed with channels A and B used in combination.
Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in
DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in
response to a single transfer request, and this is executed for the number of times specified in
ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either
the transfer source or the transfer destination can be selected as a block area (an area composed of
a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode.
Table 7.10 Register Functions in Block Transfer Mode
Register
23
Function
Initial Setting
Operation
0
Source address
register
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
0
Destination
address register
Start address of
Incremented/decremented
transfer destination every transfer, or fixed
Holds block
size
Block size
Fixed
Block size
counter
Block size
Decremented every
transfer; ETCRH value
copied when count reaches
H'00
Block transfer
counter
Number of block
transfers
Decremented every block
transfer; transfer ends
when count reaches
H'0000
MARA
23
MARB
7
0
ETCRAH
7
0
ETCRAL
15
0
ETCRB
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB. Whether a block is to be designated for MARA or for
MARB is specified by the BLKDIR bit in DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area.
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Section 7 DMA Controller (DMAC)
Address TB
Address TA
1st block
2nd block
Block area
Transfer
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Address BB
Nth block
Address BA
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
M
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (M·N – 1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0)
Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area.
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Section 7 DMA Controller (DMAC)
Address TA
Address TB
Block area
Transfer
1st block
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Address BA
2nd block
Nth block
Address BB
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
M
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (M·N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1)
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
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Section 7 DMA Controller (DMAC)
ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the
DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at
this point, an interrupt request is sent to the CPU or DTC.
Figure 7.15 shows the operation flow in block transfer mode.
Start
(DTE = DTME = 1)
Transfer request?
No
Yes
Acquire bus
Read address specified by MARA
MARA = MARA + SAIDE·(–1)SAID·2DTSZ
Write to address specified by MARB
MARB = MARB + DAIDE·(–1)DAID ·2DTSZ
ETCRAL = ETCRAL – 1
ETCRAL = H'00
No
Yes
Release bus
ETCRAL = ETCRAH
BLKDIR = 0
No
Yes
MARB = MARB – DAIDE·(–1)DAID·2DTSZ·ETCRAH
MARA = MARA – SAIDE·(–1)SAID·2DTSZ·ETCRAH
ETCRB = ETCRB – 1
No
ETCRB = H'0000
Yes
Clear DTE bit to 0
to end transfer
Figure 7.15 Operation Flow in Block Transfer Mode
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Section 7 DMA Controller (DMAC)
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts.
Figure 7.16 shows an example of the setting procedure for block transfer mode.
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Block transfer
mode setting
Set DMABCRH
Set transfer source
and transfer destination
addresses
[1]
[2]
Set number of transfers
[3]
Set DMACR
[4]
Read DMABCRL
[5]
Set DMABCRL
[6]
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the block size in both ETCRAH and
ETCRAL. Set the number of transfers in
ETCRB.
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Set the BLKE bit to 1 to select block transfer
mode.
• Specify whether the transfer source or the
transfer destination is a block area with the
BLKDIR bit.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
Block transfer mode
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts to the CPU with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Figure 7.16 Example of Block Transfer Mode Setting Procedure
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Section 7 DMA Controller (DMAC)
7.5.8
Basic Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between
these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller
settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
CPU cycle
DMAC cycle (1-word transfer)
T1
T2
T1
T2
T3
T1
T2
CPU cycle
T3
φ
Source
address
Destination address
Address bus
RD
HWR
LWR
Figure 7.17 Example of DMA Transfer Bus Timing
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Section 7 DMA Controller (DMAC)
7.5.9
DMA Transfer (Dual Address Mode) Bus Cycles
Short Address Mode: Figure 7.18 shows a transfer example in which TEND output is enabled
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Bus release
Bus release
Last transfer
cycle
Bus
release
Figure 7.18 Example of Short Address Mode Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle.
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Section 7 DMA Controller (DMAC)
Full Address Mode (Cycle Steal Mode): Figure 7.19 shows a transfer example in which TEND
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Bus release
Bus release
Last transfer
cycle
Bus
release
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one bus cycle is executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
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Section 7 DMA Controller (DMAC)
Full Address Mode (Burst Mode): Figure 7.20 shows a transfer example in which TEND output
is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Last transfer cycle
Bus release
Bus release
Burst transfer
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode)
In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that
channel has to wait until the burst transfer ends.
If an NMI interrupt is generated while a channel designated for burst transfer is in the transfer
enabled state, the DTME bit in DMABCRL is cleared and the channel is placed in the transfer
disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on
completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is
suspended. If the last transfer cycle of the burst transfer has already been activated inside the
DMAC, execution continues to the end of the transfer even if the DTME bit is cleared.
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Section 7 DMA Controller (DMAC)
Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which
TEND output is enabled and word-size full address mode transfer (block transfer mode) is
performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Block transfer
Bus release
Last block transfer
Bus
release
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)
A one-block transfer is performed for a single transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is generated
during data transfer, block transfer operation is not affected until data transfer for one block has
ended.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.
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Section 7 DMA Controller (DMAC)
DMA
read
Bus release
DMA
write
Bus
release
DMA
read
DMA
write
Bus
release
Transfer source
Transfer destination
φ
DREQ
Address
bus
DMA
control
Channel
Transfer source Transfer destination
Idle
Read
Write
Idle
Read
Request clear period
Request
[1]
[2]
Idle
Request clear period
Request
Minimum
of 2 cycles
Write
Minimum
of 2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA write cycle ends, acceptance
resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin falling
edge.
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Section 7 DMA Controller (DMAC)
1 block transfer
1 block transfer
DMA
read
Bus release
DMA
write
DMA Bus
dead release
DMA
read
DMA
write
DMA
dead
Bus
release
φ
DREQ
Address
bus
DMA
control
Channel
Transfer source
Read
Idle
Request
Transfer destination
Write
Idle
Dead
Request clear period
[2]
Read
Write
Transfer destination
Dead
Idle
Request clear period
Request
Minimum
of 2 cycles
[1]
Transfer source
Minimum
of 2 cycles
[3]
[4]
[5]
[6]
Acceptance resumes
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA dead cycle ends, acceptance
resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this
operation is repeated until the transfer ends.
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Section 7 DMA Controller (DMAC)
DREQ Pin Low Level Activation Timing (Normal Mode): Set the DTA bit in DMABCRH to 1
for the channel for which the DREQ pin is selected.
Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level.
DMA
read
DMA
write
Transfer source
Transfer destination
Bus
release
DMA
read
DMA
write
Transfer source
Transfer destination
Bus
release
Bus
release
φ
DREQ
Address
bus
DMA
control
Idle
Read
Channel
Request
Write
Idle
Read
Request clear period
[1]
[2]
Idle
Request clear period
Request
Minimum
of 2 cycles
Write
Minimum
of 2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level.
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Section 7 DMA Controller (DMAC)
1 block transfer
DMA
read
Bus release
1 block transfer
DMA
write
DMA
Bus
dead release
DMA
read
DMA
write
DMA
dead
Bus
release
φ
DREQ
Address
bus
DMA
control
Channel
Transfer source
Read
Idle
Dead
Write
Request clear period
Request
Idle
[2]
Read
Write
Transfer destination
Dead
Idle
Request clear period
Request
Minimum
of 2 cycles
[1]
Transfer source
Transfer destination
Minimum
of 2 cycles
[3]
[4]
[5]
[6]
Acceptance resumes
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
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Section 7 DMA Controller (DMAC)
7.5.10
DMA Transfer (Single Address Mode) Bus Cycles
Single Address Mode (Read): Figure 7.26 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state
access space to an external device.
DMA read
DMA read
DMA read
DMA
DMA read dead
φ
Address bus
RD
DACK
TEND
Bus
release
Bus
release
Bus
release
Bus Last transfer
cycle
release
Bus
release
Figure 7.26 Example of Single Address Mode Transfer (Byte Read)
Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
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Section 7 DMA Controller (DMAC)
DMA read
DMA read
DMA read
DMA
dead
φ
Address bus
RD
DACK
TEND
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Bus
release
Figure 7.27 Example of Single Address Mode (Word Read) Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
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Section 7 DMA Controller (DMAC)
Single Address Mode (Write): Figure 7.28 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (write) is performed from an external device to
external 8-bit, 2-state access space.
DMA write
DMA write
DMA write
DMA
DMA write dead
φ
Address bus
HWR
LWR
DACK
TEND
Bus
release
Bus
release
Bus
release
Bus Last transfer
release
cycle
Bus
release
Figure 7.28 Example of Single Address Mode Transfer (Byte Write)
Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
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Section 7 DMA Controller (DMAC)
DMA write
DMA write
DMA write
DMA
dead
φ
Address bus
HWR
LWR
DACK
TEND
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Bus
release
Figure 7.29 Example of Single Address Mode Transfer (Word Write)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling
edge.
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Section 7 DMA Controller (DMAC)
Bus release
DMA single
Bus release
DMA single
Bus release
φ
DREQ
Transfer source/
destination
Address bus
Transfer source/
destination
DACK
DMA control
Channel
Idle
Single
Request
Idle
Request clear
period
Single
[1]
[2]
Request clear
period
Request
Minimum of
2 cycles
Idle
Minimum of
2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single
cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and
the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA single cycle ends, acceptance
resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
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Section 7 DMA Controller (DMAC)
DREQ Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low
level.
Bus release
DMA single
Bus release
Bus
release
DMA single
φ
DREQ
Transfer source/
destination
Address bus
Transfer source/
destination
DACK
DMA control
Single
Idle
Channel
Single
Idle
Request clear
period
Request
[1]
[2]
Request clear
period
Request
Minimum of
2 cycles
Idle
Minimum of
2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
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Section 7 DMA Controller (DMAC)
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
7.5.11
Write Data Buffer Function
DMAC internal-to-external dual address transfers and single address transfers can be executed at
high speed using the write data buffer function, enabling system throughput to be improved.
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, dual address transfer external write cycles or single address transfer and internal accesses
(on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are
independent of the bus mastership, and DMAC dead cycles are regarded as internal accesses.
A low level can always be output from the TEND pin if the bus cycle in which a low level is to be
output from the TEND pin is an external bus cycle. However, a low level is not output from the
TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal
bus cycle, and an external write cycle is executed in parallel with this cycle.
Figure 7.32 shows an example of dual address transfer using the write data buffer function. The
data is transferred from on-chip RAM to external memory.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Internal address
Internal read signal
External address
HWR, LWR
TEND
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function
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Section 7 DMA Controller (DMAC)
Figure 7.33 shows an example of single address transfer using the write data buffer function. In
this example, the CPU program area is in on-chip memory.
DMA
read
DMA
single
CPU
read
DMA
single
CPU
read
φ
Internal address
Internal read signal
External address
RD
DACK
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function
When the write data buffer function is activated, the DMAC recognizes that the bus cycle
concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one
state after the start of the DMA write cycle or single address transfer.
7.5.12
Multi-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table
7.11 summarizes the priority order for DMAC channels.
Table 7.11 DMAC Channel Priority Order
Short Address Mode
Full Address Mode
Priority
Channel 0A
Channel 0
High
Channel 0B
Channel 1A
Channel 1B
Channel 1
Low
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Section 7 DMA Controller (DMAC)
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released, the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the
channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in
which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
DMA read
DMA write
DMA read
DMA write
DMA read
DMA
DMA write read
φ
Address bus
RD
HWR
LWR
DMA control Idle Read
Channel 0A
Write
Idle
Read
Write
Idle
Read
Write
Read
Request clear
Channel 0B
Request
hold
Selection
Channel 1
Request
hold
Nonselection
Bus
release
Channel 0A
transfer
Request clear
Request
hold
Bus
release
Selection
Channel 0B
transfer
Request clear
Bus
release
Figure 7.34 Example of Multi-Channel Transfer
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Channel 1 transfer
Section 7 DMA Controller (DMAC)
7.5.13
Relation between DMAC and External Bus Requests, Refresh Cycles,
and EXDMAC
When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle, or
external bus release cycle may arise. In this case, the bus controller will suspend the transfer and
insert a refresh cycle, EXDMAC cycle, or external bus release cycle, in accordance with the
external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An
external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed
until the DMAC releases the external bus.)
When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after
an external write cycle. The external read cycle and external write cycle are inseparable, and so the
bus cannot be released between these two cycles.
When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC
cycle may be executed at the same time as a refresh cycle, EXDMAC cycle, or external bus
release cycle.
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Section 7 DMA Controller (DMAC)
7.5.14
DMAC and NMI Interrupts
When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An
NMI interrupt does not affect the operation of the DMAC in other modes.
In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are
set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on
completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the
CPU.
The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again.
Figure 7.35 shows the procedure for continuing transfer when it has been interrupted by an NMI
interrupt on a channel designated for burst mode transfer.
Resumption of
transfer on interrupted
channel
DTE = 1
DTME = 0
[1]
Check that DTE = 1 and
DTME = 0 in DMABCRL.
[2]
Write 1 to the DTME bit.
[1]
No
Yes
Set DTME bit to 1
[2]
Transfer continues
Transfer ends
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted by
NMI Interrupt
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Section 7 DMA Controller (DMAC)
7.5.15
Forced Termination of DMAC Operation
If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops
on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the
DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL.
Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software.
[1]
Forced termination
of DMAC
Clear DTE bit to 0
Clear the DTE bit in DMABCRL to 0.
To prevent interrupt generation after forced
termination of DMAC operation, clear the DTIE bit
to 0 at the same time.
[1]
Forced termination
Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation
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Section 7 DMA Controller (DMAC)
7.5.16
Clearing Full Address Mode
Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address
mode. After full address mode has been cleared, the channel can be set to another transfer mode
using the appropriate setting procedure.
[1] Clear both the DTE bit and DTME bit in
DMABCRL to 0, or wait until the transfer ends
and the DTE bit is cleared to 0, then clear the
DTME bit to 0. Also clear the corresponding
DTIE bit to 0 at the same time.
Clearing full
address mode
Stop the channel
[1]
[2] Clear all bits in DMACRA and DMACRB to 0.
[3] Clear the FAE bit in DMABCRH to 0.
Initialize DMACR
[2]
Clear FAE bit to 0
[3]
Initialization;
operation halted
Figure 7.37 Example of Procedure for Clearing Full Address Mode
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Section 7 DMA Controller (DMAC)
7.6
Interrupt Sources
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12
shows the interrupt sources and their priority order.
Table 7.12 Interrupt Sources and Priority Order
Interrupt Source
Interrupt
Priority Order
Interrupt Name
Short Address Mode
Full Address Mode
DMTEND0A
Interrupt due to end of
transfer on channel 0A
Interrupt due to end of
transfer on channel 0
DMTEND0B
Interrupt due to end of
transfer on channel 0B
Interrupt due to break in
transfer on channel 0
DMTEND1A
Interrupt due to end of
transfer on channel 1A
Interrupt due to end of
transfer on channel 1
DMTEND1B
Interrupt due to end of
transfer on channel 1B
Interrupt due to break in
transfer on channel 1
High
Low
Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for
the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt
controller independently. The priority of transfer end interrupts on each channel is decided by the
interrupt controller, as shown in table 7.12.
Figure 7.38 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is
always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0.
DTE/
DTME
Transfer end/transfer
break interrupt
DTIE
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt
In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0
while the DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR
should be set so as to prevent the occurrence of a combination that constitutes a condition for
interrupt generation during setting.
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Section 7 DMA Controller (DMAC)
7.7
Usage Notes
7.7.1
DMAC Register Access during Operation
Except for forced termination of the DMAC, the operating (including transfer waiting state)
channel setting should not be changed. The operating channel setting should only be changed
when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
• DMAC control starts one cycle before the bus cycle, with output of the internal address.
Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 7.39 shows an
example of the update timing for DMAC registers in dual address transfer mode.
DMA last transfer cycle
DMA transfer cycle
DMA read
DMA read
DMA write
DMA write
DMA
dead
φ
DMA Internal
address
DMA control
DMA register
operation
Idle
[1]
Transfer
source
Transfer
destination
Read
Write
[2]
Transfer
destination
Transfer
source
Read
Idle
[1]
Write
[2']
Dead
Idle
[3]
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2']Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
Note: In single address transfer mode, the update timing is the same as [1].
The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Figure 7.39 DMAC Register Update Timing
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Section 7 DMA Controller (DMAC)
• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
register is read as shown in figure 7.40.
DMA transfer cycle
CPU longword read
MAR upper
word read
MAR lower
word read
DMA read
DMA write
φ
DMA internal
address
DMA control
DMA register
operation
Idle
[1]
Transfe
source
Transfer
destination
Read
Write
Idle
[2]
Note: The lower word of MAR is the updated value after the operation in [1].
Figure 7.40 Contention between DMAC Register Update and CPU Read
7.7.2
Module Stop
When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state
is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
• Transfer end/break interrupt (DTE = 0 and DTIE = 1)
• TEND pin enable (TEE = 1)
• DACK pin enable (FAE = 0 and SAE = 1)
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Section 7 DMA Controller (DMAC)
7.7.3
Write Data Buffer Function
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, dual address transfer external write cycles or single address transfers and internal
accesses (on-chip memory or internal I/O registers) are executed in parallel.
• Write data buffer function and DMAC register setting
If the setting of a register that controls external accesses is changed during execution of an
external access by means of the write data buffer function, the external access may not be
performed normally. Registers that control external accesses should only be manipulated when
external reads, etc., are used with DMAC operation disabled, and the operation is not
performed in parallel with external access.
• Write data buffer function and DMAC operation timing
The DMAC can start its next operation during external access using the write data buffer
function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are
different from the case in which the write data buffer function is disabled. Also, internal bus
cycles maybe hidden, and not visible.
7.7.4
TEND Output
If the last transfer cycle is for an internal address, note that even if low-level output at the TEND
pin has been set, a low level may not be output at the TEND pin under the following external bus
conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed
in parallel.
1. EXDMAC cycle
2. Write cycle with write buffer mode enabled
3. DMAC single address cycle for a different channel with write buffer mode enabled
4. Bus release cycle
5. CBR refresh cycle
Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2
above.
If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in
synchronization with the bus cycle.
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Section 7 DMA Controller (DMAC)
However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the
CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in
this case for the refresh cycle.
DMA
read
DMA
write
φ
Internal address
Internal read signal
Internal write signal
External address
HWR, LWR
TEND
Not output
External write by CPU, etc.
Figure 7.41 Example in which Low Level Is Not Output at TEND Pin
7.7.5
Activation by Falling Edge on DREQ Pin
DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
switches to [1].
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer
is enabled is performed on detection of a low level.
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Section 7 DMA Controller (DMAC)
7.7.6
Activation Source Acceptance
At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge
sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request
is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that
occurs before write to DMABCRL to enable transfer.
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ
pin low level remaining from the end of the previous transfer, etc.
7.7.7
Internal Interrupt after End of Transfer
When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible
termination, the selected internal interrupt request will be sent to the CPU or DTC even if the
DTA bit in DMABCRH is set to 1.
Also, if internal DMAC activation has already been initiated when operation is forcibly
terminated, the transfer is executed but flag clearing is not performed for the selected internal
interrupt even if the DTA bit is set to 1.
An internal interrupt request following the end of transfer or a forcible termination should be
handled by the CPU as necessary.
7.7.8
Channel Re-Setting
To reactivate a number of channels when multiple channels are enabled, use exclusive handling of
transfer end interrupts, and perform DMABCR control bit operations exclusively.
Note, in particular, that in cases where multiple interrupts are generated between reading and
writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the
DMABCR write data in the original interrupt handling routine will be incorrect, and the write may
invalidate the results of the operations by the multiple interrupts. Ensure that overlapping
DMABCR operations are not performed by multiple interrupts, and that there is no separation
between read and write operations by the use of a bit-manipulation instruction.
Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must
first be read while cleared to 0 before the CPU can write 1 to them.
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Section 8 EXDMA Controller (EXDMAC)
Section 8 EXDMA Controller (EXDMAC)
This LSI has a built-in dual-channel external bus transfer DMA controller (EXDMAC). The
EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external
devices and external memory with a DACK (DMA transfer notification) facility.
8.1
Features
• Direct specification of 16-Mbyte address space
• Selection of byte or word transfer data length
• Maximum number of transfers: 16M (16,777,215)/infinite (free-running)
• Selection of dual address mode or single address mode
• Selection of cycle steal mode or burst mode as bus mode
• Selection of normal mode or block transfer mode as transfer mode
• Two kinds of transfer requests: external request and auto-request
• An interrupt request can be sent to the CPU at the end of the specified number of transfers.
• Repeat area designation function:
• Operation in parallel with internal bus master:
• Acceptance of a transfer request and the start of transfer processing can be reported to an
external device via the EDRAK pin.
• Module stop mode can be set.
Note: This EXDMAC is not supported by the H8S/2375, H8S/2375R, H8S/2373, and
H8S/2373R.
EDMA261A_000120020400
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Section 8 EXDMA Controller (EXDMAC)
Figure 8.1 shows a block diagram of the EXDMAC.
Bus controller
Data buffer
Control logic
EDRAK
Processor
ETEND
EDACK
Interrupt request
signals to CPU
for individual
channels
Address buffer
EDSAR
EDDAR
EDMDR
EDACR
EDTCR
Internal data bus
Legend:
EDSAR:
EDDAR:
EDTCR:
EDMDR:
EDACR:
EXDMA source address register
EXDMA destination address register
EXDMA transfer count register
EXDMA mode control register
EXDMA address control register
Figure 8.1 Block Diagram of EXDMAC
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Module data bus
External pins
EDREQ
Section 8 EXDMA Controller (EXDMAC)
8.2
Input/Output Pins
Table 8.1 shows the pin configuration of the EXDMAC.
Table 8.1
Pin Configuration
Channel
Name
Abbreviation
I/O
Function
2
EXDMA transfer request 2
EDREQ2
Input
Channel 2 external request
EXDMA transfer
acknowledge 2
EDACK2
Output
Channel 2 single address transfer
acknowledge
EXDMA transfer end 2
ETEND2
Output
Channel 2 transfer end
EDREQ2 acceptance
acknowledge
EDRAK2
Output
Notification to external device of
channel 2 external request
acceptance and start of transfer
processing
EXDMA transfer request 3
EDREQ3
Input
Channel 3 external request
EXDMA transfer
acknowledge 3
EDACK3
Output
Channel 3 single address transfer
acknowledge
EXDMA transfer end 3
ETEND3
Output
Channel 3 transfer end
EDREQ3 acceptance
acknowledge
EDRAK3
Output
Notification to external device of
channel 3 external request
acceptance and start of transfer
processing
3
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Section 8 EXDMA Controller (EXDMAC)
8.3
Register Descriptions
The EXDMAC has the following registers.
• EXDMA source address register_2 (EDSAR_2)
• EXDMA destination address register_2 (EDDAR_2)
• EXDMA transfer count register_2 (EDTCR_2)
• EXDMA mode control register_2 (EDMDR_2)
• EXDMA address control register_2 (EDACR_2)
• EXDMA source address register_3 (EDSAR_3)
• EXDMA destination address register_3 (EDDAR_3)
• EXDMA transfer count register_3 (EDTCR_3)
• EXDMA mode control register_3 (EDMDR_3)
• EXDMA address control register_3 (EDACR_3)
8.3.1
EXDMA Source Address Register (EDSAR)
EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address
update function is provided that updates the register contents to the next transfer source address
each time transfer processing is performed. In single address mode, the EDSAR value is ignored
when a device with DACK is specified as the transfer source.
The upper 8 bits of EDSAR are reserved; they are always read as 0 and cannot be modified. Only
0 should be written to these bits.
EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDSAR for a channel on which EXDMA transfer is in progress. The initial values of EDSAR
are undefined.
8.3.2
EXDMA Destination Address Register (EDDAR)
EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An
address update function is provided that updates the register contents to the next transfer
destination address each time transfer processing is performed. In single address mode, the
EDDAR value is ignored when a device with DACK is specified as the transfer destination.
The upper 8 bits of EDDAR are reserved; they are always read as 0 and cannot be modified. Only
0 should be written to these bits.
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Section 8 EXDMA Controller (EXDMAC)
EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR
are undefined.
8.3.3
EXDMA Transfer Count Register (EDTCR)
EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do
not write to EDTCR for a channel on which EXDMA transfer is in progress.
Normal Transfer Mode:
Bit
Bit Name
Initial Value
R/W
Description
31
to
24
—
All 0
—
Reserved
23
to
0
These bits are always read as 0 and cannot be
modified.
All 0
R/W
24-Bit Transfer Counter
These bits specify the number of transfers. Setting
H'000001 specifies one transfer. Setting H'000000
means no specification for the number of transfers,
and the transfer counter function is halted. In this
case, there is no transfer end interrupt by the
transfer counter. Setting H'FFFFFF specifies the
maximum number of transfers, that is 16,777,215.
During EXDMA transfer, this counter shows the
remaining number of transfers.
This counter can be read at all times. When
reading EDTCR for a channel on which EXDMA
transfer processing is in progress, a longword-size
read must be executed.
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Section 8 EXDMA Controller (EXDMAC)
Block Transfer Mode:
Bit
Bit Name
Initial Value
R/W
Description
31
to
24
—
All 0
—
Reserved
These bits are always read as 0 and cannot be
modified.
23
to
16
Undefined
15
to
0
Undefined
R/W
Block Size
These bits specify the block size (number of bytes
or number of words) for block transfer. Setting H'01
specifies one as the block, while setting H'00
specifies the maximum block size, that is 256. The
register value always indicates the specified block
size.
R/W
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16-Bit Transfer Counter
These bits specify the number of block transfers.
Setting H'0001 specifies one block transfer. Setting
H'0000 means no specification for the number of
transfers, and the transfer counter function is
halted. In this case, there is no transfer end
interrupt by the transfer counter. Setting H'FFFF
specifies the maximum number of block transfers,
that is 65,535. During EXDMA transfer, this counter
shows the remaining number of block transfers.
Section 8 EXDMA Controller (EXDMAC)
8.3.4
EXDMA Mode Control Register (EDMDR)
EDMDR controls EXDMAC operations.
Bit
Bit Name
Initial Value
R/W
15
EDA
0
R/(W)
Description
EXDMA Active
Enables or disables data transfer on the
corresponding channel. When this bit is set to 1,
this indicates that an EXDMA operation is in
progress.
When auto request mode is specified (by bits
MDS1 and MDS0), transfer processing begins
when this bit is set to 1. With external requests,
transfer processing begins when a transfer request
is issued after this bit has been set to 1. When this
bit is cleared to 0 during an EXDMA operation,
transfer is halted. If this bit is cleared to 0 during an
EXDMA operation in block transfer mode, transfer
processing is continued for the currently executing
one-block transfer, and the bit is cleared on
completion of the currently executing one-block
transfer.
If an external source that ends (aborts) transfer
occurs, this bit is automatically cleared to 0 and
transfer is terminated. Do not change the operating
mode, transfer method, or other parameters while
this bit is set to 1.
0: Data transfer disabled on corresponding channel
[Clearing conditions]
•
When the specified number of transfers end
•
When operation is halted by a repeat area
overflow interrupt
•
When 0 is written to EDA while EDA = 1
(In block transfer mode, write is effective after
end of one-block transfer)
•
Reset, NMI interrupt, hardware standby mode
1: Data transfer enabled on corresponding channel
Note: The value written in the EDA bit may not be
effective immediately.
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
14
BEF
0
R/(W)*
Block Transfer Error Flag
Flag that indicates the occurrence of an error
during block transfer. If an NMI interrupt is
generated during block transfer, the EXDMAC
immediately terminates the EXDMA operation and
sets this bit to 1. The address registers indicate the
next transfer addresses, but the data for which
transfer has been performed within the block size is
lost.
0: No block transfer error
[Clearing condition]
Writing 0 to BEF after reading BEF = 1
1: Block transfer error
[Setting condition]
NMI interrupt during block transfer
13
EDRAKE
0
R/W
EDRAK Pin Output Enable
Enables output from the EDREQ
acknowledge/transfer processing start (EDRAK)
pin.
0: EDRAK pin output disabled
1: EDRAK pin output enabled
12
ETENDE
0
R/W
ETEND Pin Output Enable
Enables output from the EXDMA transfer end
(ETEND) pin.
0: ETEND pin output disabled
1: ETEND pin output enabled
11
EDREQS
0
R/W
EDREQ Select
Specifies low level sensing or falling edge sensing
as the sampling method for the EDREQ pin used in
external request mode.
0: Low level sensing (Low level sensing is used for
the first transfer after transfer is enabled.)
1: Falling edge sensing
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
10
AMS
0
R/W
Address Mode Select
Selects single address mode or dual address
mode. When single address mode is selected, the
EDACK pin is valid.
0: Dual address mode
1: Single address mode
9
8
MDS1
MDS0
0
0
R/W
R/W
Mode Select 1 and 0
These bits specify the activation source, bus
mode, and transfer mode.
00: Auto request, cycle steal mode, normal
transfer mode
01: Auto request, burst mode, normal transfer
mode
10: External request, cycle steal mode, normal
transfer mode
11: External request, cycle steal mode, block
transfer mode
7
EDIE
0
R/W
EXDMA Interrupt Enable
Enables or disables interrupt requests. When this
bit is set to 1, an interrupt is requested when the
IRF bit is set to 1. The interrupt request is cleared
by clearing this bit or the IRF bit to 0.
0: Interrupt request is not generated
1: Interrupt request is generated
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
6
IRF
0
R/(W)*
Interrupt Request Flag
Flag indicating that an interrupt request has
occurred and transfer has ended.
0: No interrupt request
[Clearing conditions]
•
Writing 1 to the EDA bit
•
Writing 0 to IRF after reading IRF = 1
1: Interrupt request occurrence
[Setting conditions]
5
TCEIE
0
R/W
•
Transfer end interrupt request generated by
transfer counter
•
Source address repeat area overflow interrupt
request
•
Destination address repeat area overflow
interrupt request
Transfer Counter End Interrupt Enable
Enables or disables transfer end interrupt
requests by the transfer counter. When
transfer ends according to the transfer counter
while this bit is set to 1, the IRF bit is set to 1,
indicating that an interrupt request has
occurred.
0: Transfer end interrupt requests by transfer
counter are disabled
1: Transfer end interrupt requests by transfer
counter are enabled
4
SDIR
0
R/W
Single Address Direction
Specifies the data transfer direction in single
address mode. In dual address mode, the
specification by this bit is ignored.
0: Transfer direction: EDSAR → external
device with DACK
1: Transfer direction: External device with
DACK→ EDDAR
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTSIZE
0
R/W
Data Transmit Size
Specifies the size of data to be transferred.
0: Byte-size
1: Word-size
2
BGUP
0
R/W
Bus Give-Up
When this bit is set to 1, the bus can be
transferred to an internal bus master in burst
mode or block transfer mode. This setting is
ignored in normal mode and cycle steal mode.
0: Bus is not released
1: Bus is transferred if requested by an
internal bus master
1, 0
—
All 0
R/W
Reserved
These bits are always read as 0. The initial
values should not be modified.
Note:
*
Only 0 can be written, to clear the flag.
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Section 8 EXDMA Controller (EXDMAC)
8.3.5
EXDMA Address Control Register (EDACR)
EDACR specifies address register incrementing/decrementing and use of the repeat area function.
Bit
Bit Name
Initial Value
R/W
Description
15
14
SAT1
SAT0
0
0
R/W
R/W
Source Address Update Mode
These bits specify incrementing/decrementing of
the transfer source address (EDSAR). When an
external device with DACK is designated as the
transfer source in single address mode, the
specification by these bits is ignored.
0×: Fixed
10: Incremented (+1 in byte transfer, +2 in word
transfer)
11: Decremented (–1 in byte transfer, –2 in word
transfer)
13
SARIE
0
R/W
Source Address Repeat Interrupt Enable
When this bit is set to 1, in the event of source
address repeat area overflow, the IRF bit is set to 1
and the EDA bit cleared to 0 in EDMDR, and
transfer is terminated. If the EDIE bit in EDMDR is
1 when the IRF bit in EDMDR is set to 1, an
interrupt request is sent to the CPU.
When used together with block transfer mode, a
source address repeat interrupt is requested at the
end of a block-size transfer. If the EDA bit is set to
1 in EDMDR for the channel on which transfer is
terminated by a source address repeat interrupt,
transfer can be resumed from the state in which it
ended. If a source address repeat area has not
been designated, this bit is ignored.
0: Source address repeat interrupt is not requested
1: When source address repeat area overflow
occurs, the IRF bit in EDMDR is set to 1 and an
interrupt is requested
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
12
11
10
9
8
SARA4
SARA3
SARA2
SARA1
SARA0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Source Address Repeat Area
These bits specify the source address (EDSAR)
repeat area. The repeat area function updates the
specified lower address bits, leaving the remaining
upper address bits always the same. A repeat area
size of 2 bytes to 8 Mbytes can be specified. The
setting interval is a power-of-two number of bytes.
When repeat area overflow results from
incrementing or decrementing an address, the
lower address is the start address of the repeat
area in the case of address incrementing, or the
last address of the repeat area in the case of
address decrementing. If the SARIE bit is set to 1,
an interrupt can be requested when repeat area
overflow occurs.
00000: Not designated as repeat area
00001: Lower 1 bit (2-byte area) designated as
repeat area
00010: Lower 2 bits (4-byte area) designated as
repeat area
00011: Lower 3 bits (8-byte area) designated as
repeat area
00100: Lower 4 bits (16-byte area) designated as
repeat area
:
:
10011: Lower 19 bits (512-kbyte area) designated
as repeat area
10100: Lower 20 bits (1-Mbyte area) designated as
repeat area
10101: Lower 21 bits (2-Mbyte area) designated as
repeat area
10110: Lower 22 bits (4-Mbyte area) designated as
repeat area
10111: Lower 23 bits (8-Mbyte area) designated as
repeat area
11×××: Setting prohibited
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
7
6
DAT1
DAT0
0
0
R/W
R/W
Destination Address Update Mode
These bits specify incrementing/decrementing of
the transfer destination address (EDDAR). When
an external device with DACK is designated as the
transfer destination in single address mode, the
specification by these bits is ignored.
0×: Fixed
10: Incremented (+1 in byte transfer, +2 in word
transfer)
11: Decremented (–1 in byte transfer, –2 in word
transfer)
5
DARIE
0
R/W
Destination Address Repeat Interrupt Enable
When this bit is set to 1, in the event of destination
address repeat area overflow the IRF bit is set to 1
and the EDA bit cleared to 0 in EDMDR, and
transfer is terminated. If the EDIE bit in EDMDR is
1 when the IRF bit in EDMDR is set to 1, an
interrupt request is sent to the CPU. When used
together with block transfer mode, a destination
address repeat interrupt is requested at the end of
a block-size transfer. If the EDA bit is set to 1 in
EDMDR for the channel on which transfer is
terminated by a destination address repeat
interrupt, transfer can be resumed from the state in
which it ended. If a destination address repeat area
has not been designated, this bit is ignored.
0: Destination address repeat interrupt is not
requested
1: When destination address repeat area overflow
occurs, the IRF bit in EDMDR is set to 1 and an
interrupt is requested
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
4
3
2
1
0
DARA4
DARA3
DARA2
DARA1
DARA0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Destination Address Repeat Area
These bits specify the destination address
(EDDAR) repeat area. The repeat area function
updates the specified lower address bits, leaving
the remaining upper address bits always the same.
A repeat area size of 2 bytes to 8 Mbytes can be
specified. The setting interval is a power-of-two
number of bytes. When repeat area overflow
results from incrementing or decrementing an
address, the lower address is the start address of
the repeat area in the case of address
incrementing, or the last address of the repeat area
in the case of address decrementing. If the DARIE
bit is set to 1, an interrupt can be requested when
repeat area overflow occurs.
00000: Not designated as repeat area
00001: Lower 1 bit (2-byte area) designated as
repeat area
00010: Lower 2 bits (4-byte area) designated as
repeat area
00011: Lower 3 bits (8-byte area) designated as
repeat area
00100: Lower 4 bits (16-byte area) designated as
repeat area
:
:
10011: Lower 19 bits (512-kbyte area) designated
as repeat area
10100: Lower 20 bits (1-Mbyte area) designated as
repeat area
10101: Lower 21 bits (2-Mbyte area) designated as
repeat area
10110: Lower 22 bits (4-Mbyte area) designated as
repeat area
10111: Lower 23 bits (8-Mbyte area) designated as
repeat area
11×××: Setting prohibited
Legend:
×: Don’t care
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Section 8 EXDMA Controller (EXDMAC)
8.4
Operation
8.4.1
Transfer Modes
The transfer modes of the EXDMAC are summarized in table 8.2.
Table 8.2
EXDMAC Transfer Modes
Transfer Mode
Dual
address
mode
Normal
transfer
mode
Auto request mode
• Burst/cycle steal
mode
External request
mode
Transfer
Origin
Auto
request
Number of
Transfers
Address Registers
Source
1 to
EDSAR
16,777,215
or no
specification
Destination
EDDAR
External
request
• Cycle steal mode
Block
transfer
mode
External request
mode
External
request
• Burst transfer of
specified block size
for a single transfer
request
1 to 65,535
or no
specification
• Block size: 1 to
256 bytes or words
Single
address
mode
• Direct data transfer to/from external device using EDACK EDSAR/
pin instead of source or destination address register
EDACK
EDACK/
EDDAR
• Above transfer mode can be specified in addition to
address register setting
• One transfer possible in one bus cycle
(Transfer mode variations are the same as in dual address
mode.)
The transfer mode can be set independently for each channel.
In normal transfer mode, a one-byte or one-word transfer is executed in response to one transfer
request. With auto requests, burst or cycle steal transfer mode can be set. In burst transfer mode,
continuous, high-speed transfer can be performed until the specified number of transfers have been
executed or the transfer enable bit is cleared to 0.
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Section 8 EXDMA Controller (EXDMAC)
In block transfer mode, a transfer of the specified block size is executed in response to one transfer
request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be
performed at the same high speed as in block transfer mode.
When the “no specification” setting (EDTCR = H'000000) is made for the number of transfers, the
transfer counter is halted and there is no limit on the number of transfers, allowing transfer to be
performed endlessly.
Incrementing or decrementing the memory address by 1 or 2, or leaving the address unchanged,
can be specified independently for each address register.
In all transfer modes, it is possible to set a repeat area comprising a power-of-two number of
bytes.
8.4.2
Address Modes
Dual Address Mode: In dual address mode, both the transfer source and transfer destination are
specified by registers in the EXDMAC, and one transfer is executed in two bus cycles.
The transfer source address is set in the source address register (EDSAR), and the transfer
destination address is set in the transfer destination address register (EDDAR).
In a transfer operation, the value in external memory specified by the transfer source address is
read in the first bus cycle, and is written to the external memory specified by the transfer
destination address in the next bus cycle.
These consecutive read and write cycles are indivisible: another bus cycle (external access by an
internal bus master, refresh cycle, or external bus release cycle) does not occur between these two
cycles.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for two consecutive bus cycles. The EDACK signal is not output.
Figure 8.2 shows an example of the timing in dual address mode.
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Section 8 EXDMA Controller (EXDMAC)
EXDMA
read cycle
EXDMA
write cycle
φ
Address bus
EDSAR
EDDAR
RD
WR
ETEND
Figure 8.2 Example of Timing in Dual Address Mode
Single Address Mode: In single address mode, the EDACK signal is used instead of the source or
destination address register to transfer data directly between an external device and external
memory. In this mode, the EXDMAC accesses the transfer source or transfer destination external
device by outputting the external I/O strobe signal (EDACK), and at the same time accesses the
other external device in the transfer by outputting an address. In this way, DMA transfer can be
executed in one bus cycle. In the example of transfer between external memory and an external
device with DACK shown in figure 8.3, data is output to the data bus by the external device and
written to external memory in the same bus cycle.
The transfer direction, that is whether the external device with DACK is the transfer source or
transfer destination, can be specified with the SDIR bit in EDMDR. Transfer is performed from
the external memory (EDSAR) to the external device with DACK when SDIR = 0, and from the
external device with DACK to the external memory (EDDAR) when SDIR = 1.
The setting in the source or destination address register not used in the transfer is ignored.
The EDACK pin becomes valid automatically when single address mode is selected. The EDACK
pin is active-low. ETEND pin output can be enabled or disabled by means of the ETENDE bit in
EDMDR. ETEND is output for one bus cycle.
Figure 8.3 shows the data flow in single address mode, and figure 8.4 shows an example of the
timing.
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Section 8 EXDMA Controller (EXDMAC)
External
address bus
External
data bus
Microcomputer
External
memory
EXDMAC
External device
with DACK
EDACK
EDREQ
Data flow
Figure 8.3 Data Flow in Single Address Mode
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Section 8 EXDMA Controller (EXDMAC)
Transfer from external memory to external device with DACK
EXDMA cycle
φ
Address bus
EDSAR
RD
Address to external memory space
RD signal to external memory space
WR
EDACK
Data output from external memory
Data bus
ETEND
Transfer from external device with DACK to external memory
EXDMA cycle
φ
Address bus
EDDAR
Address to external memory space
RD
WR
WR signal to external memory space
EDACK
Data output from external device
with DACK
Data bus
ETEND
Figure 8.4 Example of Timing in Single Address Mode
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Section 8 EXDMA Controller (EXDMAC)
8.4.3
DMA Transfer Requests
Auto Request Mode: In auto request mode, transfer request signals are automatically generated
within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in
transfer between two memories, or between a peripheral module that is not capable of generating
transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to
1 in EDMDR.
In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode.
Block transfer mode cannot be used.
External Request Mode: In external request mode, transfer is started by a transfer request signal
(EDREQ) from a device external to this LSI. DMA transfer is started when EDREQ is input while
DMA transfer is enabled (EDA = 1).
The transfer request source need not be the data transfer source or data transfer destination.
The transfer request signal is accepted via the EDREQ pin. Either falling edge sensing or low level
sensing can be selected for the EDREQ pin by means of the EDREQS bit in EDMDR (low level
sensing when EDREQS = 0, falling edge sensing when EDREQS = 1).
Setting the EDRAKE bit to 1 in EDMDR enables a signal confirming transfer request acceptance
to be output from the EDRAK pin. The EDRAK signal is output when acceptance and transfer
processing has been started in response to a single external request. The EDRAK signal enables
the external device to determine the timing of EDREQ signal negation, and makes it possible to
provide handshaking between the transfer request source and the EXDMAC.
In external request mode, block transfer mode can be used instead of burst mode. Block transfer
mode allows continuous execution (burst operation) of the specified number of transfers (the block
size) in response to a single transfer request. In block transfer mode, the EDRAK signal is output
only once for a one-block transfer, since the transfer request via the EDREQ pin is for a block
unit.
8.4.4
Bus Modes
There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto
request, either cycle steal mode or burst mode can be selected. When the activation source is an
external request, cycle steal mode is used.
Cycle Steal Mode: In cycle steal mode, the EXDMAC releases the bus at the end of each transfer
of a transfer unit (byte, word, or block). If there is a subsequent transfer request, the EXDMAC
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Section 8 EXDMA Controller (EXDMAC)
takes back the bus, performs another transfer-unit transfer, and then releases the bus again. This
procedure is repeated until the transfer end condition is satisfied.
If a transfer request occurs in another channel during DMA transfer, the bus is temporarily
released, then transfer is performed on the channel for which the transfer request was issued. If
there is no external space bus request from another bus master, a one-cycle bus release interval is
inserted. For details on the operation when there are requests for a number of channels, see section
8.4.8, Channel Priority Order.
Figure 8.5 shows an example of the timing in cycle steal mode.
EDREQ
EDRAK
Bus cycle
CPU
CPU
EXDMAC
CPU
CPU
EXDMAC
Bus returned temporarily to CPU
Transfer conditions:
· Single address mode, normal transfer mode
· EDREQ low level sensing
· CPU internal bus master is operating in external space
Figure 8.5 Example of Timing in Cycle Steal Mode
Burst Mode: In burst mode, once the EXDMAC acquires the bus it continues transferring data,
without releasing the bus, until the transfer end condition is satisfied. There is no burst mode in
external request mode.
In burst mode, once transfer is started it is not interrupted even if there is a transfer request from
another channel with higher priority. When the burst mode channel finishes its transfer, it releases
the bus in the next cycle in the same way as in cycle steal mode.
When the EDA bit is cleared to 0 in EDMDR, DMA transfer is halted. However, DMA transfer is
executed for all transfer requests generated within the EXDMAC up until the EDA bit was cleared
to 0.
If a repeat area overflow interrupt is generated, the EDA bit is cleared to 0 and transfer is
terminated.
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Section 8 EXDMA Controller (EXDMAC)
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during burst transfer. If there is no bus request, burst transfer is executed even if the
BGUP bit is set to 1.
Figure 8.6 shows examples of the timing in burst mode.
Bus cycle
CPU
CPU
EXDMAC
EXDMAC
EXDMAC
CPU
CPU
CPU cycle not generated
Transfer conditions:
Auto request mode, BGUP = 0
Bus cycle
CPU
EXDMAC
CPU
EXDMAC
CPU
EXDMAC
CPU
EXDMAC operates alternately with CPU
Transfer conditions:
Auto request mode, BGUP = 1
Figure 8.6 Examples of Timing in Burst Mode
8.4.5
Transfer Modes
There are two transfer modes: normal transfer mode and block transfer mode. When the activation
source is an external request, either normal transfer mode or block transfer mode can be selected.
When the activation source is an auto request, normal transfer mode is used.
Normal Transfer Mode: In normal transfer mode, transfer of one transfer unit is processed in
response to one transfer request. EDTCR functions as a 24-bit transfer counter.
The ETEND signal is output only for the last DMA transfer. The EDRAK signal is output each
time a transfer request is accepted and transfer processing is started.
Figure 8.7 shows examples of DMA transfer timing in normal transfer mode.
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Section 8 EXDMA Controller (EXDMAC)
Bus cycle
EXDMA
transfer cycle
Last EXDMA
transfer cycle
Read
Read
Write
Write
ETEND
Transfer conditions:
Dual address mode, auto request mode
EDREQ
EDRAK
Bus cycle
EXDMA
EXDMA
EDACK
Transfer conditions:
Single address mode, external request mode
Figure 8.7 Examples of Timing in Normal Transfer Mode
Block Transfer Mode: In block transfer mode, the number of bytes or words specified by the
block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify
the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256
can be specified. During transfer of a block, transfer requests for other higher-priority channels are
held pending. When transfer of one block is completed, the bus is released in the next cycle.
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during block transfer.
Address register values are updated in the same way as in normal mode. There is no function for
restoring the initial address register values after each block transfer.
The ETEND signal is output for each block transfer in the DMA transfer cycle in which the block
ends. The EDRAK signal is output once for one transfer request (for transfer of one block).
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Section 8 EXDMA Controller (EXDMAC)
Caution is required when setting the repeat area overflow interrupt of the repeat area function in
block transfer mode. See section 8.4.6, Repeat Area Function, for details.
Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA
Transfer, for details.
Figure 8.8 shows an example of DMA transfer timing in block transfer mode.
EDREQ
EDRAK
One-block transfer cycle
Bus cycle
CPU
CPU
CPU
EXDMAC
EXDMAC
EXDMAC
CPU
CPU cycle not generated
ETEND
Transfer conditions:
· Single address mode
· BGUP = 0
· Block size (EDTCR[23:16]) = 3
Figure 8.8 Example of Timing in Block Transfer Mode
8.4.6
Repeat Area Function
The EXDMAC has a function for designating a repeat area for source addresses and/or destination
addresses. When a repeat area is designated, the address register values repeat within the range
specified as the repeat area. Normally, when a ring buffer is involved in a transfer, an operation is
required to restore the address register value to the buffer start address each time the address
register value is the last address in the buffer (i.e. when ring buffer address overflow occurs), but if
the repeat area function is used, the operation that restores the address register value to the buffer
start address is performed automatically within the EXDMAC.
The repeat area function can be set independently for the source address register and the
destination address register.
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Section 8 EXDMA Controller (EXDMAC)
The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the
destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat
area can be specified independently.
When the address register value is the last address in the repeat area and repeat area overflow
occurs, DMA transfer can be temporarily halted and an interrupt request sent to the CPU. If the
SARIE bit in EDACR is set to 1, when the source address register overflows the repeat area, the
IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If EDIE = 1
in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to
the destination address register.
If the EDA bit in EDMDR is set to 1 during interrupt generation, transfer is resumed. Figure 8.9
illustrates the operation of the repeat area function.
When lower 3 bits (8-byte area) of EDSAR are designated as repeat area
(SARA4 to SARA0 = 3)
External memory
:
Range of
EDSAR values
H'23FFFE
H'23FFFF
H'240000
H'240000
H'240001
H'240001
H'240002
H'240002
H'240003
H'240003
H'240004
H'240004
H'240005
H'240005
H'240006
H'240006
H'240007
H'240007
H'240008
H'240009
Repeated
Repeat area overflow
interrupt can be
requested
:
Figure 8.9 Example of Repeat Area Function Operation
Caution is required when the repeat area overflow interrupt function is used together with block
transfer mode. If transfer is always terminated when repeat area overflow occurs in block transfer
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Section 8 EXDMA Controller (EXDMAC)
mode, the block size must be a power of two, or alternatively, the address register value must be
set so that the end of a block coincides with the end of the repeat area range.
If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat
interrupt request is held pending until the end of the block, and transfer overrun will occur. Figure
8.10 shows an example in which block transfer mode is used together with the repeat area
function.
When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3),
and block size of 5 (EDTCR[23–16] = 5) is set in block transfer mode
External memory
Range of
EDSAR values
First block
transfer
Second block
transfer
H'240000
H'240000
H'240000
H'240000
H'240001
H'240001
H'240001
H'240001
H'240002
H'240002
H'240002
H'240003
H'240003
H'240003
H'240004
H'240004
H'240004
H'240005
H'240005
H'240005
H'240006
H'240006
H'240006
H'240007
H'240007
H'240007
:
H'23FFFE
H'23FFFF
H'240008
Interrupt
requested
Block transfer
in progress
H'240009
:
Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode
8.4.7
Registers during DMA Transfer Operation
EXDMAC register values are updated as DMA transfer processing is performed. The updated
values depend on various settings and the transfer status. The following registers and bits are
updated: EDSAR, EDDAR, EDTCR, and bits EDA, BEF, and IRF in EDMDR,
EXDMA Source Address Register (EDSAR): When the EDSAR address is accessed as the
transfer source, after the EDSAR value is output, EDSAR is updated with the address to be
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Section 8 EXDMA Controller (EXDMAC)
accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The
address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented
when SAT1 = 1 and SAT0 = 1.
The size of the increment or decrement is determined by the size of the data transferred. When the
DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented
by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by
2.
When a repeat area setting is made, the operation conforms to that setting. The upper part of the
address set for the repeat area function is fixed, and is not affected by address updating.
When EDSAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. In a longword
access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output.
Do not write to EDSAR for a channel on which a transfer operation is in progress.
EXDMA Destination Address Register (EDDAR): When the EDDAR address is accessed as the
transfer destination, after the EDDAR value is output, EDDAR is updated with the address to be
accessed next. Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The
address is fixed when DAT1 = 0, incremented when DAT1 = 1 and DAT0 = 0, and decremented
when DAT1 = 1 and DAT0 = 1.
The size of the increment or decrement is determined by the size of the data transferred. When the
DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented
by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by
2.
When a repeat area setting is made, the operation conforms to that setting. The upper part of the
address set for the repeat area function is fixed, and is not affected by address updating.
When EDDAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. In a longword
access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output.
Do not write to EDDAR for a channel on which a transfer operation is in progress.
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Section 8 EXDMA Controller (EXDMAC)
EXDMA Transfer Count Register (EDTCR): When a DMA transfer is performed, the value in
EDTCR is decremented by 1. However, when the EDTCR value is 0, transfers are not counted and
the EDTCR value does not change.
EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to
specify the block size, and their value does not change. The lower 16 bits, EDTCR[15:0], function
as a transfer counter, the value of which is decremented by 1 when a DMA transfer is performed.
However, when the EDTCR[15:0] value is 0, transfers are not counted and the EDTCR[15:0]
value does not change.
In normal transfer mode, all of the lower 24 bits of EDTCR may change, so when EDTCR is read
by the CPU during DMA transfer, a longword access must be used. During a transfer operation,
EDTCR may be updated without regard to accesses from the CPU, and the correct values may not
be read if the upper and lower words are read separately. In a longword access, the EXDMAC
buffers the EDTCR value to ensure that the correct value is output.
In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word
access.
Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is
contention between an address update associated with DMA transfer and a write by the CPU, the
CPU write has priority.
In the event of contention between an EDTCR update from 1 to 0 and a write (of a nonzero value)
by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated.
Transfer does not end if the CPU writes 0 to EDTCR.
Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode.
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Section 8 EXDMA Controller (EXDMAC)
EDTCR in normal transfer mode
Before update
23
EDTCR
Fixed
23
0
0
23
EDTCR
After update
0
0
0
–1
23
1 to H'FFFFFF
0
0 to H'FFFFFE
EDTCR in block transfer mode
EDTCR
Before update
23
16 15
Block
0
size
EDTCR
23
16 15
Block
1 to H'FFFF
size
0
0
Fixed
–1
After update
23
16 15
Block
0
size
23
16 15
Block
0 to H'FFFE
size
0
0
Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and
Block Transfer Mode
EDA Bit in EDMDR: The EDA bit in EDMDR is written to by the CPU to control enabling and
disabling of data transfer, but may be cleared automatically by the EXDMAC due to the DMA
transfer status. There are also periods during transfer when a 0-write to the EDA bit by the CPU is
not immediately effective.
Conditions for EDA bit clearing by the EXDMAC include the following:
• When the EDTCR value changes from 1 to 0, and transfer ends
• When a repeat area overflow interrupt is requested, and transfer ends
• When an NMI interrupt is generated, and transfer halts
• A reset
• Hardware standby mode
• When 0 is written to the EDA bit, and transfer halts
When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA
transfer period. In block transfer mode, since a block-size transfer is carried out without
interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current
block-size transfer.
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Section 8 EXDMA Controller (EXDMAC)
In burst mode, transfer is halted for up to three DMA transfers following the bus cycle in which 0
is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until the end
of the last DMA cycle.
Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set
to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that
the EDA bit has been cleared to 0.
Figure 8.12 shows the procedure for changing register settings in an operating channel.
[1] Write 0 to the EDA bit in EDMDR.
Changing register settings
in operating channel
Write 0 to EDA bit
[2] Read the EDA bit.
[1]
[3] Confirm that EDA = 0. If EDA = 1, this
indicates that DMA transfer is in progress.
[4] Write the required set values to the
registers.
Read EDA bit
[2]
EDA bit = 0?
[3]
No
Yes
Change register settings
[4]
Register setting
changes completed
Figure 8.12 Procedure for Changing Register Settings in Operating Channel
BEF Bit in EDMDR: In block transfer mode, the specified number of transfers (equivalent to the
block size) is performed in response to a single transfer request. To ensure that the correct number
of transfers is carried out, a block-size transfer is always executed, except in the event of a reset,
transition to standby mode, or generation of an NMI interrupt.
If an NMI interrupt is generated during block transfer, operation is halted midway through a
block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation. In this case
the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1.
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Section 8 EXDMA Controller (EXDMAC)
IRF Bit in EDMDR: The IRF bit in EDMDR is set to 1 when an interrupt request source occurs.
If the EDIE bit in EDMDR is 1 at this time, an interrupt is requested.
The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer
ends following the end of the DMA transfer bus cycle in which the source generating the interrupt
occurred.
If the EDA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is
automatically cleared to 0 and the interrupt request is cleared.
For details on interrupts, see section 8.5, Interrupt Sources.
8.4.8
Channel Priority Order
The priority order of the EXDMAC channels is: channel 2 > channel 3. Table 8.3 shows the
EXDMAC channel priority order.
Table 8.3
EXDMAC Channel Priority Order
Channel
Channel 2
Priority
High
Channel 3
Low
If transfer requests occur simultaneously for a number of channels, the highest-priority channel
according to the priority order in table 8.3 is selected for transfer.
Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode): If
transfer requests for different channels are issued during a transfer operation, the highest-priority
channel (excluding the currently transferring channel) is selected. The selected channel begins
transfer after the currently transferring channel releases the bus. If there is a bus request from a bus
master other than the EXDMAC at this time, a cycle for the other bus master is initiated. If there is
no other bus request, the bus is released for one cycle.
Channel switching does not take place during a burst transfer or a block transfer of a single block.
Figure 8.13 shows a case in which transfer requests for channels 2 and 3 are issued
simultaneously. The example shown in the figure illustrates the handling of external requests in
the cycle steal mode.
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Section 8 EXDMA Controller (EXDMAC)
Channel 2 transfer
Channel 3 transfer
φ
Channel 2
Address bus
EXDMA control
Idle
Channel 2
Channel 2
Request cleared
Channel 3
Request Selected
held
Bus
release
Channel 3
Bus
release
Channel 3
Request cleared
Figure 8.13 Example of Channel Priority Timing
Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode: If transfer
requests for different channels are issued during a transfer in auto request cycle steal mode, the
operation depends on the channel priority. If the channel that made the transfer request is of higher
priority than the channel currently performing transfer, the channel that made the transfer request
is selected.
If the channel that made the transfer request is of lower priority than the channel currently
performing transfer, that channel’s transfer request is held pending, and the currently transferring
channel remains selected.
The selected channel begins transfer after the currently transferring channel releases the bus. If
there is a bus request from a bus master other than the EXDMAC at this time, a cycle for the other
bus master is initiated. If there is no other bus request, the bus is released for one cycle.
Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode.
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Section 8 EXDMA Controller (EXDMAC)
Conditions (1)
Channel 0: Auto request, cycle steal mode
Channel 1: External request, cycle steal mode, low level activation
Bus
Channel 0
*
Channel 0
*
Channel 0
*
Channel 1
*
*
Channel 1
Channel 0
EDA bit
Channel 1/
EDREQ1 pin
Conditions (2)
Channel 1: External request, cycle steal mode, low level activation
Channel 2: Auto request, cycle steal mode
Bus
Channel 2
*
Channel 2
*
Channel 1
*
Channel 2
*
Channel 1
*
Channel 0
*
Channel 0
*
Channel 2
*
Channel 1
Channel 1/
EDREQ1 pin
Channel 2
EDA bit
Conditions (3)
Channel 0: Auto request, cycle steal mode
Channel 2: Auto request, cycle steal mode
Bus
Channel 2
*
Channel 2
Channel 0
EDA bit
Channel 2
EDA bit
*:
Bus release
Figure 8.14 Examples of Channel Priority Timing
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*
Section 8 EXDMA Controller (EXDMAC)
8.4.9
EXDMAC Bus Cycles (Dual Address Mode)
Normal Transfer Mode (Cycle Steal Mode): Figure 8.15 shows an example of transfer when
ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed
from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
After one byte or word has been transferred, the bus is released. While the bus is released, one
CPU, DMAC, or DTC bus cycle is initiated.
DMA read DMA write
DMA read DMA write
DMA read DMA write
φ
Address bus
RD
HWR
LWR
ETEND
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Bus
release
Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer
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Section 8 EXDMA Controller (EXDMAC)
Normal Transfer Mode (Burst Mode): Figure 8.16 shows an example of transfer when ETEND
output is enabled, and word-size, normal transfer mode (burst mode) is performed from external
16-bit, 2-state access space to external 16-bit, 2-state access space.
In burst mode, one-byte or one-word transfers are executed continuously until transfer ends.
Once burst transfer starts, requests from other channels, even of higher priority, are held pending
until transfer ends.
DMA read DMA write DMA read DMA write DMA read DMA write
φ
Address bus
RD
HWR
LWR
ETEND
Bus
release
Last transfer cycle
Burst transfer
Bus
release
Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer
If an NMI interrupt is generated while a channel designated for burst transfer is enabled for
transfer, the EDA bit is cleared and transfer is disabled. If a block transfer has already been
initiated within the EXDMAC, the bus is released on completion of the currently executing byte or
word transfer, and burst transfer is aborted. If the last transfer cycle in burst transfer has been
initiated within the EXDMAC, transfer is executed to the end even if the EDA bit is cleared.
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Section 8 EXDMA Controller (EXDMAC)
Block Transfer Mode (Cycle Steal Mode): Figure 8.17 shows an example of transfer when
ETEND output is enabled, and word-size, block transfer mode (cycle steal mode) is performed
from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
One block is transferred in response to one transfer request, and after the transfer, the bus is
released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
φ
Address bus
RD
HWR
LWR
ETEND
Bus
release
Block transfer
Bus
release
Last block transfer
Bus
release
Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer
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Section 8 EXDMA Controller (EXDMAC)
EDREQ Pin Falling Edge Activation Timing: Figure 8.18 shows an example of normal mode
transfer activated by the EDREQ pin falling edge.
DMA read
DMA write
Transfer source
Transfer
destination
Write
Idle
Bus release
DMA read
Bus release
DMA write Bus release
φ
EDREQ
Address bus
DMA control
Read
Idle
Channel
Transfer source
Read
Request clearance period
Request
[1]
[2]
[3]
Minimum 3 cycles
[4]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Idle
Request clearance period
Request
Minimum 3 cycles
Write
Transfer
destination
[5]
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
DMA cycle start; EDREQ pin high level sampling is started at rise of φ.
When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after
the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence
of operations is repeated until the end of the transfer.
Figure 8.19 shows an example of block transfer mode transfer activated by the EDREQ pin falling
edge.
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Section 8 EXDMA Controller (EXDMAC)
One block transfer
Bus release
One block transfer
DMA read
DMA write
Transfer source
Transfer
destination
Bus release
DMA read
DMA write
Bus release
φ
EDREQ
Address bus
DMA control Idle
Read
Channel
Idle
Read Write
Request clearance period
Request
Minimum 3 cycles
[1]
Write
Transfer source
[2]
[3]
Idle
Request clearance period
Request
Minimum 3 cycles
[4]
[5]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Transfer
destination
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
DMA cycle start; EDREQ pin high level sampling is started at rise of φ.
When EDREQ pin high level has been sampled, acceptance is resumed after completion of dead cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling
Edge
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after
the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence
of operations is repeated until the end of the transfer.
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Section 8 EXDMA Controller (EXDMAC)
EDREQ Pin Low Level Activation Timing: Figure 8.20 shows an example of normal mode
transfer activated by the EDREQ pin low level.
Bus release
DMA read
DMA write
Transfer source
Transfer
destination
Bus release
DMA read
DMA write Bus release
φ
EDREQ
Address bus
DMA control Idle
Channel
Read
Write
Idle
Request clearance period
Request
Minimum 3 cycles
[1]
[2]
[3]
Transfer source
Read
Idle
Request clearance period
Request
Minimum 3 cycles
[4]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Write
Transfer
destination
[5]
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
DMA cycle is started.
Acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
Figure 8.21 shows an example of block transfer mode transfer activated by the EDREQ pin low
level.
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Section 8 EXDMA Controller (EXDMAC)
One block transfer
Bus release
One block transfer
DMA read
DMA write
Transfer source
Transfer
destination
Bus release
DMA read
DMA write Bus release
φ
EDREQ
Address bus
DMA control
Read
Idle
Channel
Write
Transfer source
Idle
Read Write
Request clearance period
Request
[2]
[3]
Minimum 3 cycles
[4]
[5]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Idle
Request clearance period
Request
Minimum 3 cycles
[1]
Transfer
destination
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
DMA cycle is started.
Acceptance is resumed after completion of dead cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
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Section 8 EXDMA Controller (EXDMAC)
8.4.10
EXDMAC Bus Cycles (Single Address Mode)
Single Address Mode (Read): Figure 8.22 shows an example of transfer when ETEND output is
enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2state access space to an external device.
DMA read
DMA read
DMA read
DMA read
φ
Address bus
RD
EDACK
ETEND
Bus release
Bus release
Bus release
Bus release
Last
Bus release
transfer
cycle
Figure 8.22 Example of Single Address Mode (Byte Read) Transfer
Figure 8.23 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
DMA read
DMA read
DMA read
φ
Address bus
RD
EDACK
ETEND
Bus release
Bus release
Bus release
Last transfer cycle
Figure 8.23 Example of Single Address Mode (Word Read) Transfer
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Bus
release
Section 8 EXDMA Controller (EXDMAC)
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
Single Address Mode (Write): Figure 8.24 shows an example of transfer when ETEND output is
enabled, and byte-size, single address mode transfer (write) is performed from an external device
to external 8-bit, 2-state access space.
DMA write
DMA write
DMA write
DMA write
φ
Address bus
HWR
LWR
EDACK
ETEND
Bus release
Bus release
Bus release
Bus release
Last
Bus release
transfer
cycle
Figure 8.24 Example of Single Address Mode (Byte Write) Transfer
Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
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Section 8 EXDMA Controller (EXDMAC)
DMA write
DMA write
DMA write
φ
Address bus
HWR
LWR
EDACK
ETEND
Bus release
Bus release
Bus release
Last transfer cycle
Bus
release
Figure 8.25 Example of Single Address Mode (Word Write) Transfer
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
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Section 8 EXDMA Controller (EXDMAC)
EDREQ Pin Falling Edge Activation Timing: Figure 8.26 shows an example of single address
mode transfer activated by the EDREQ pin falling edge.
DMA single
Bus release
DMA single Bus release
Bus release
φ
EDREQ
Transfer source/
destination
Address bus
Transfer source/
destination
EDACK
DMA control
Idle
Single
Channel
Request
Minimum 3 cycles
[1]
Idle
Single
Request
clearance period
[2]
[3]
Request
Minimum 3 cycles
[4]
[5]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Idle
Request
clearance period
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
DMA cycle start; EDREQ pin high level sampling is started at rise of φ.
When EDREQ pin high level has been sampled, acceptance is resumed after completion of single cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.26 Example of Single Address Mode Transfer Activated by EDREQ Pin Falling
Edge
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the DMA single cycle, acceptance resumes
after the end of the single cycle, and EDREQ pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.
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Section 8 EXDMA Controller (EXDMAC)
EDREQ Pin Low Level Activation Timing: Figure 8.27 shows an example of single address
mode transfer activated by the EDREQ pin low level.
DMA single
Bus release
DMA single Bus release
Bus release
φ
EDREQ
Transfer source/
destination
Address bus
Transfer source/
destination
EDACK
DMA control
Idle
Single
Channel
Request
Minimum 3 cycles
[1]
Idle
Single
Request
clearance period
[2]
[3]
Request
Minimum 3 cycles
[4]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Idle
Request
clearance period
[5]
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
DMA cycle is started.
Acceptance is resumed after completion of single cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.27 Example of Single Address Mode Transfer Activated by EDREQ Pin Low Level
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the single cycle, acceptance resumes and EDREQ pin low
level sampling is performed again; this sequence of operations is repeated until the end of the
transfer.
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Section 8 EXDMA Controller (EXDMAC)
8.4.11
Examples of Operation Timing in Each Mode
Auto Request/Cycle Steal Mode/Normal Transfer Mode: When the EDA bit is set to 1 in
EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a onecycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the
next transfer.
If there is a transfer request for another channel of higher priority, the transfer request by the
original channel is held pending, and transfer is performed on the higher-priority channel from the
next transfer. Transfer on the original channel is resumed on completion of the higher-priority
channel transfer.
Figures 8.28 to 8.30 show operation timing examples for various conditions.
φ pin
1 cycle
3 cycles
Bus release
Bus cycle
EXDMA
read
EXDMA
write
EXDMA
read
Bus
release
CPU
operation
EDA = 1
write
Last transfer cycle
EXDMA
write
EXDMA
read
EXDMA
write
Bus
release
Internal bus space
cycles
ETEND
EDA bit
0
1
0
Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Dual Address Mode)
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Section 8 EXDMA Controller (EXDMAC)
φ pin
1 bus cycle
Bus cycle
CPU cycle
CPU
operation
External
space
EXDMA single
transfer cycle
CPU cycle
External space
Last transfer cycle
EXDMA single
transfer cycle
CPU cycle
EXDMA single
transfer cycle
External space
CPU cycle
External space
EDACK
ETEND
Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode)
φ pin
1 cycle
Bus cycle
EXDMA
single cycle
EXDMA
single cycle
Bus
release
1 cycle
1 cycle
EXDMA
single cycle
Bus
release
EXDMA
single cycle
Higher-priority channel EXDMA cycle
Bus
release
Bus
release
Current
channel
EDACK
Other
channel
transfer
request
(EDREQ)
Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(Contention with Another Channel/Single Address Mode)
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Bus
release
Section 8 EXDMA Controller (EXDMAC)
Auto Request/Burst Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR,
an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it
continues (as a burst) until the transfer end condition is satisfied.
If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another
bus master.
Transfer requests for other channels are held pending until the end of transfer on the current
channel.
Figures 8.31 to 8.34 show operation timing examples for various conditions.
φ pin
Last transfer cycle
Bus cycle
CPU
operation
CPU cycle CPU cycle
External
space
External
space
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
EXDMA
write
CPU cycle
External
space
ETEND
EDA bit
1
0
Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Dual Address Mode/BGUP = 0)
φ pin
1 bus cycle
Bus cycle
CPU
operation
CPU cycle CPU cycle
External
space
External
space
EXDMA
read
External
space
EXDMA
write
CPU cycle
1 bus cycle
EXDMA
read
EXDMA
write
CPU cycle
EXDMA
read
EXDMA
write
External
space
Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Dual Address Mode/BGUP = 1)
Rev.7.00 Mar. 18, 2009 page 407 of 1136
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Section 8 EXDMA Controller (EXDMAC)
φ pin
Last transfer cycle
1 bus cycle
Bus cycle
CPU
operation
EXDMA
EXDMA
EXDMA
EXDMA
EXDMA
CPU cycle CPU cycle single
cycle single cycle CPU cycle single cycle single cycle CPU cycle single cycle CPU cycle
External
space
External
space
External
space
External
space
External
space
EDACK
ETEND
Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode/BGUP = 1)
φ pin
Last transfer
cycle
Bus cycle
Bus release
EXDMA single
transfer cycle
EXDMA single
transfer cycle
1 cycle
EXDMA single
transfer cycle
Other channel EXDMA cycle
Bus
release
Original
channel
EDACK
Original
channel
ETEND
Other
channel
transfer
request
(EDREQ)
Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode
(Contention with Another Channel/Single Address Mode)
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Bus
release
Section 8 EXDMA Controller (EXDMAC)
External Request/Cycle Steal Mode/Normal Transfer Mode: In external request mode, an
EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted.
The next transfer request is accepted after the end of a one-transfer-unit EXDMA cycle. For
external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA
cycle.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next EXDMA cycle.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 8.35 to 8.38 show operation timing examples for various conditions.
φ pin
EDREQ
EDRAK
3 cycles
Bus release
Bus cycle
EXDMA
read
EXDMA
write
Bus release
Last transfer cycle
EXDMA
read
EXDMA
write
Bus release
ETEND
EDA bit
1
0
Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Dual Address Mode/Low Level Sensing)
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Section 8 EXDMA Controller (EXDMAC)
φ pin
EDREQ
EDRAK
2 bus cycles
Bus cycle
CPU
operation
CPU cycle CPU cycle CPU cycle
External
space
External
space
External
space
EXDMA single
transfer cycle
CPU cycle CPU cycle
External
space
External
space
Last transfer cycle
EXDMA single
transfer cycle
CPU cycle
External
space
EDACK
ETEND
Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing)
φ pin
EDREQ
EDRAK
EDREQ
acceptance
internal
processing
state
Edge confirmation
Start of transfer
processing
Start of high
level sensing
Bus cycle
Bus release
EXDMA single
transfer cycle
Edge confirmation
Start of transfer
processing
Bus release
Start of high
level sensing
EXDMA single
transfer cycle
Edge confirmation
Start of transfer
processing
Bus release
Start of high
level sensing
EXDMA single
transfer cycle
EDACK
Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing)
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Section 8 EXDMA Controller (EXDMAC)
φ pin
Original
channel
EDREQ
Original
channel
EDRAK
1 cycle
3 cycles
Bus cycle
EXDMA transfer
cycle
Bus release
EXDMA
read
1 cycle
Other channel
transfer cycle
EXDMA
write
Bus
release
EXDMA
read
EXDMA
write
Bus
release
Other
channel
EDREQ
Other
channel
EDRAK
Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention
with Another Channel/Dual Address Mode/Low Level Sensing
External Request/Cycle Steal Mode/Block Transfer Mode: In block transfer mode, transfer of
one block is performed continuously in the same way as in burst mode. The timing of the start of
the next block transfer is the same as in normal transfer mode.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next block transfer.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 8.39 to 8.44 show operation timing examples for various conditions.
Rev.7.00 Mar. 18, 2009 page 411 of 1136
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Rev.7.00 Mar. 18, 2009 page 412 of 1136
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EDA bit
ETEND
Bus cycle
EDRAK
EDREQ
φ pin
1
Bus release
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
Last transfer
in block
Repeated
1-block-size transfer period
Bus release
3 cycles
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
0
EXDMA
write
Bus
release
Last transfer cycle
Last block
Section 8 EXDMA Controller (EXDMAC)
Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0)
ETEND
EDACK
Bus cycle
EDRAK
EDREQ
φ pin
Bus release
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
Last transfer
in block
Repeated
1-block-size transfer period
Bus release
3 cycles
EXDMA single
transfer cycle
Repeated
EXDMA single
transfer cycle
Bus
release
Last transfer cycle
Last block
Section 8 EXDMA Controller (EXDMAC)
Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0)
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External
space
CPU
operation
ETEND
EDACK
CPU
cycle
Bus cycle
EDRAK
EDREQ
φ pin
External
space
CPU
cycle
External
space
CPU
cycle
External
space
EXDMA single
transfer cycle
Repeated
EXDMA single
transfer cycle
Last transfer
in block
1-block-size transfer period
CPU
cycle
External
space
CPU
cycle
2 bus cycles
External
space
EXDMA single
transfer cycle
Repeated
EXDMA single
transfer cycle
Last transfer
in block
1-block-size transfer period
CPU
cycle
Section 8 EXDMA Controller (EXDMAC)
Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0)
External
space
CPU
operation
ETEND
CPU
cycle
Bus cycle
EDRAK
EDREQ
φ pin
External
space
CPU
cycle
External
space
CPU
cycle
External
space
EXDMA
read
EXDMA
write
CPU
cycle
1 bus cycle
External
space
EXDMA
read
EXDMA
write
CPU
cycle
1 bus cycle
External
space
CPU
cycle
1 bus cycle
Repeated
EXDMA
read
1-block-size transfer period
External
space
EXDMA
read
EXDMA
write
Last transfer
in block
CPU
cycle
External
space
CPU
cycle
Section 8 EXDMA Controller (EXDMAC)
Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1)
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External
space
External
space
CPU
operation
ETEND
EDACK
CPU
cycle
CPU
cycle
Bus cycle
EDRAK
EDREQ
φ pin
External
space
CPU
cycle
External
space
EXDMA
EXDMA
transfer cycle transfer cycle
CPU
cycle
1 bus cycle
External
space
EXDMA
EXDMA
transfer cycle transfer cycle
CPU
cycle
1 bus cycle
External
space
Repeated
EXDMA
transfer cycle
1-block-size transfer period
CPU
cycle
1 bus cycle
External
space
EXDMA
EXDMA
transfer cycle transfer cycle
Last transfer
in block
CPU
cycle
External
space
CPU
cycle
Section 8 EXDMA Controller (EXDMAC)
Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1)
Other
channel
EDRAK
Other
channel
EDREQ
ETEND
Bus cycle
EDRAK
EDREQ
φ pin
Bus release
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
EXDMA
write
Last transfer
in block
1-block-size transfer period
Bus
release
Other channel
EXDMA cycle
Bus
release
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
EXDMA
write
Last transfer
in block
1-block-size transfer period
Section 8 EXDMA Controller (EXDMAC)
Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode
(Contention with Another Channel/Dual Address Mode/Low Level Sensing)
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Section 8 EXDMA Controller (EXDMAC)
8.4.12
Ending DMA Transfer
The operation for ending DMA transfer depends on the transfer end conditions. When DMA
transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has
ended.
Transfer End by 1 → 0 Transition of EDTCR: When the value of EDTCR changes from 1 to 0,
DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0. If
the TCEIE bit in EDMDR is set at this time, a transfer end interrupt request is generated by the
transfer counter and the IRF bit in EDMDR is set to 1.
In block transfer mode, DMA transfer ends when the value of bits 15 to 0 in EDTCR changes
from 1 to 0.
DMA transfer does not end if the EDTCR value has been 0 since before the start of transfer.
Transfer End by Repeat Area Overflow Interrupt: If an address overflows the repeat area
when a repeat area specification has been made and repeat interrupts have been enabled (with the
SARIE or DARIE bit in EDACR), a repeat area overflow interrupt is requested. DMA transfer
ends, the EDA bit in EDMDR is cleared to 0, and the IRF bit in EDMDR is set to 1.
In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the
following write cycle processing is still executed.
In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block,
transfer continues to the end of the block. Transfer end by means of a repeat area overflow
interrupt occurs between block-size transfers.
Transfer End by 0-Write to EDA Bit in EDMDR: When 0 is written to the EDA bit in EDMDR
by the CPU, etc., transfer ends after completion of the DMA cycle in which transfer is in progress
or a transfer request was accepted.
In block transfer mode, DMA transfer halts after completion of one-block-size transfer.
The EDA bit in EDMDR is not cleared to 0 until all transfer processing has ended. Up to that
point, the value of the EDA bit will be read as 1.
Transfer Abort by NMI Interrupt: DMA transfer is aborted when an NMI interrupt is
generated. The EDA bit is cleared to 0 in all channels. In external request mode, DMA transfer is
performed for all transfer requests for which EDRAK has been output. In dual address mode,
processing is executed for the write cycle following the read cycle.
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Section 8 EXDMA Controller (EXDMAC)
In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the
transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the
block transfer was not carried out normally.
When transfer is aborted, register values are retained, and as the address registers indicate the next
transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit
is 1 in EDMDR, transfer can be resumed from midway through a block.
Hardware Standby Mode and Reset Input: The EXDMAC is initialized in hardware standby
mode and by a reset. DMA transfer is not guaranteed in these cases.
8.4.13
Relationship between EXDMAC and Other Bus Masters
The read and write operations in a DMA transfer cycle are indivisible, and a refresh cycle, external
bus release cycle, or internal bus master (CPU, DTC, or DMAC) external space access cycle never
occurs between the two.
When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh or
external bus release state may be inserted after the write cycle. As the internal bus masters are of
lower priority than the EXDMAC, external space accesses by internal bus masters are not
executed until the EXDMAC releases the bus.
The EXDMAC releases the bus in the following cases:
1. When DMA transfer is performed in cycle steal mode
2. When switching to a different channel
3. When transfer ends in burst transfer mode
4. When transfer of one block ends in block transfer mode
5. When burst transfer or block transfer is performed with the BGUP bit in EDMDR set to 1
(however, the bus is not released between read and write cycles)
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Section 8 EXDMA Controller (EXDMAC)
8.5
Interrupt Sources
EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area
overflow interrupts. Table 8.4 shows the interrupt sources and their priority order.
Table 8.4
Interrupt Sources and Priority Order
Interrupt
Interrupt source
Interrupt Priority
EXDMTEND2
Transfer end indicated by channel 2 transfer counter
High
Channel 2 source address repeat area overflow
Channel 2 destination address repeat area overflow
EXDMTEND3
Transfer end indicated by channel 3 transfer counter
Channel 3 source address repeat area overflow
Channel 3 destination address repeat area overflow
Low
Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant
channel, and can be sent to the interrupt controller independently. The relative priority order of the
channels is determined by the interrupt controller (see table 8.4).
Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever
the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR.
IRF bit
Transfer end interrupt
EDIE bit
Figure 8.45 Transfer End Interrupt Logic
Interrupt source settings are made individually with the interrupt enable bits in the registers for the
relevant channels. The transfer counter’s transfer end interrupt is enabled or disabled by means of
the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of
the SARIE bit in EDACR, and the destination address register repeat area overflow interrupt by
means of the DARIE bit in EDACR. When an interrupt source occurs while the corresponding
interrupt enable bit is set to 1, the IRF bit in EDMDR is set to 1. The IRF bit is set by all interrupt
sources indiscriminately.
The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the
interrupt handling routine, or by re-setting the transfer counter and address registers and then
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Section 8 EXDMA Controller (EXDMAC)
setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of
the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46.
Transfer end interrupt
exception handling routine
Transfer restart after end
of interrupt handling routine
Transfer continuation
processing
Change register settings
[1]
Clear IRF bit to 0
[4]
Write 1 to EDA bit
[2]
End of interrupt handling
routine
[5]
End of interrupt handling
routine
(RTE instruction execution)
[3]
Change register settings
[6]
Write 1 to EDA bit
[7]
End of transfer restart
processing
End of transfer restart
processing
[1] Write set values to the registers (transfer counter, address registers, etc.).
[2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the EDA
bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is cleared.
[3] The interrupt handling routine is ended with an RTE instruction, etc.
[4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0.
[5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt masking is
cleared.
[6] Write set values to the registers (transfer counter, address registers, etc.).
[7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation.
Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer
End Interrupt Occurred
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Section 8 EXDMA Controller (EXDMAC)
8.6
Usage Notes
8.6.1
EXDMAC Register Access during Operation
Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in
operation (including the transfer standby state). Transfer must be disabled before changing a
setting for an operational channel.
8.6.2
Module Stop State
When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC
enters the module stop state. However, 1 cannot be written to the MSTP14 bit when any of the
EXDMAC’s channels is enabled for transfer, or when an interrupt is being requested. Before
setting the MSTP14 bit, first clear the EDA bit in EDMDR to 0, then clear the IRF or EDIE bit in
EDMDR to 0.
When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following
EXDMAC register settings remain valid in the module stop state, and so should be changed, if
necessary, before making the module stop transition.
• ETENDE = 1 in EDMDR (ETEND pin enable)
• EDRAKE = 1 in EDMDR (EDRAK pin enable)
• AMS = 1 in EDMDR (EDACK pin enable)
8.6.3
EDREQ Pin Falling Edge Activation
Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC internal
operations, as indicated below.
[1] Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to [2].
[2] Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3].
[3] Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to [1].
After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used
for the initial activation after transfer is enabled.
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Section 8 EXDMA Controller (EXDMAC)
8.6.4
Activation Source Acceptance
At the start of activation source acceptance, low level sensing is used for both falling edge sensing
and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low
level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transferenabled state.
When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the
EDREQ pin from the previous end of transfer, etc.
8.6.5
Enabling Interrupt Requests when IRF = 1 in EDMDR
When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in
EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be
requested since EDIE = 1 and IRF = 1. To prevent the occurrence of an erroneous interrupt request
when transfer starts, ensure that the IRF bit is cleared to 0 before the EDIE bit is set to 1.
8.6.6
ETEND Pin and CBR Refresh Cycle
If the last EXDMAC transfer cycle and a CBR refresh cycle occur simultaneously, note that
although the CBR refresh and the last transfer cycle may be executed consecutively, ETEND may
also go low in this case for the refresh cycle.
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Section 8 EXDMA Controller (EXDMAC)
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Section 9 Data Transfer Controller (DTC)
Section 9 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 9.1 shows a block diagram of the DTC.
9.1
Features
• Transfer possible over any number of channels
• Three transfer modes
⎯ Normal mode
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
From 1 to 65,536 transfers can be specified.
⎯ Repeat mode
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
Once the specified number of transfers (1 to 256) has ended, the initial state is restored, and
transfer is repeated.
⎯ Block transfer mode
One operation transfers one block of data.
The block size is 1 to 256 bytes or words.
From 1 to 65,536 transfers can be specified.
Either the transfer source or the transfer destination is designated as a block area.
• One activation source can trigger a number of data transfers (chain transfer)
• Direct specification of 16-Mbyte address space possible
• Activation by software is possible
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Module stop mode can be set
The DTC’s register information is stored in the on-chip RAM. When the DTC is used, the RAME
bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte),
enabling 32-bit/1-state reading and writing of the DTC register information.
DTCH803A_010020020400
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Section 9 Data Transfer Controller (DTC)
Internal address bus
On-chip
RAM
CPU interrupt
request
Register information
MRA MRB
CRA
CRB
DAR
SAR
DTC
Control logic
DTC activation
request
DTVECR
Interrupt
request
DTCERA
to
DTCERH
Interrupt controller
Internal data bus
Legend:
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERH
DTVECR
: DTC mode registers A and B
: DTC transfer count registers A and B
: DTC source address register
: DTC destination address register
: DTC enable registers A to H
: DTC vector register
Figure 9.1 Block Diagram of DTC
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Section 9 Data Transfer Controller (DTC)
9.2
Register Descriptions
DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set
of register information that is stored in an on-chip RAM to the corresponding DTC registers and
transfers data. After the data transfer, it writes a set of updated register information back to the
RAM.
• DTC enable registers A to H (DTCERA to DTCERH)
• DTC vector register (DTVECR)
9.2.1
DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Bit
Bit Name
Initial Value
R/W
Description
7
6
SM1
SM0
Undefined
Undefined
—
—
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0×: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
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Section 9 Data Transfer Controller (DTC)
Bit
Bit Name
Initial Value
R/W
Description
5
4
DM1
DM0
Undefined
Undefined
—
—
Destination Address Mode 1 and 0
These bits specify a DAR operation after a data
transfer.
0×: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
3
2
MD1
MD0
Undefined
Undefined
—
—
DTC Mode
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
1
DTS
Undefined
—
DTC Transfer Mode Select
Specifies whether the source side or the
destination side is set to be a repeat area or block
area, in repeat mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
0
Sz
Undefined
—
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Legend:
× : Don’t care
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Section 9 Data Transfer Controller (DTC)
9.2.2
DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit
Bit Name
Initial Value
R/W
7
CHNE
Undefined
—
Description
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 9.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination
of the end of the specified number of transfers,
clearing of the activation source flag, and clearing
of DTCER is not performed.
6
DISEL
Undefined
—
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
5
CHNS
Undefined
—
DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
4
to
0
9.2.3
—
Undefined
—
Reserved
These bits have no effect on DTC operation, and
should always be written with 0.
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
9.2.4
DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
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Section 9 Data Transfer Controller (DTC)
9.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
9.2.6
DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000. The CRB is not
available in normal and repeat modes.
9.2.7
DTC Enable Registers A to H (DTCERA to DTCERH)
DTCER which is comprised of seven registers, DTCERA to DTCERH, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 9.2. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set
at one time (only at the initial setting) by writing data after executing a dummy read on the
relevant register.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt source
to a DTC activation source.
[Clearing conditions]
• When the DISEL bit is 1 and the data transfer has
ended
• When the specified number of transfers have ended
These bits are not automatically cleared when the
DISEL bit is 0 and the specified number of transfers
have not ended
•
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When 0 is written to DTCE after reading DTCE = 1
Section 9 Data Transfer Controller (DTC)
9.2.8
DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit
Bit Name
Initial Value
R/W
Description
7
SWDTE
0
R/W
DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be
written to this bit.
[Clearing conditions]
•
When the DISEL bit is 0 and the specified
number of transfers have not ended
•
When 0 is written to the DISEL bit after a
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the
CPU.
When the DISEL bit is 1 and data transfer has
ended or when the specified number of transfers
have ended, this bit will not be cleared.
6
5
4
3
2
1
0
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
DTVEC0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTC Software Activation Vectors 6 to 0
These bits specify a vector number for DTC
software activation.
The vector address is expressed as H'0400 +
(vector number × 2). For example, when DTVEC6
to DTVEC0 = H'10, the vector address is H'0420.
When the bit SWDTE is 0, these bits can be
written.
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Section 9 Data Transfer Controller (DTC)
9.3
Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER
bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source or corresponding DTCER bit is cleared. The activation source flag, in the case
of RXI0, for example, is the RDRF flag of SCI_0.
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
Table 9.1 shows a relationship between activation sources and DTCER clear conditions. Figure
9.2 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
Table 9.1
Relationship between Activation Sources and DTCER Clearing
Activation Source
DISEL = 0 and Specified
Number of Transfers Has
Not Ended
DISEL = 1 or Specified Number
of Transfers Has Ended
Activation by software
SWDTE bit is cleared to 0
•
SWDTE bit remains set to 1
•
Interrupt request to CPU
Activation by an interrupt
•
Corresponding DTCER bit
remains set to 1.
•
Corresponding DTCER bit is
cleared to 0.
•
Activation source flag is
cleared to 0.
•
Activation source flag remains
set to 1.
•
Interrupt that became the
activation source is requested
to the CPU.
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Section 9 Data Transfer Controller (DTC)
Source flag cleared
Clear
controller
Clear
DTCER
On-chip
supporting
module
IRQ interrupt
Interrupt
request
DTVECR
Selection circuit
Select
Clear request
DTC
CPU
Interrupt controller
Interrupt mask
Figure 9.2 Block Diagram of DTC Activation Source Control
9.4
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF).
Register information should be located at the address that is multiple of four within the range.
Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 9.3 and the register information start address should be located at the
corresponding vector address to the activation source. Figure 9.4 shows correspondences between
the DTC vector address and register information. The DTC reads the start address of the register
information from the vector address set for each activation source, and then reads the register
information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the register information
start address.
Note: * Not available in this LSI.
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Section 9 Data Transfer Controller (DTC)
Lower addresses
0
Start address of
register information
1
2
MRA
SAR
MRB
DAR
3
Register information
CRB
CRA
Chain transfer
MRA
SAR
MRB
DAR
CRB
CRA
Register information
for second transfer
in case of chain
transfer
Four bytes
Figure 9.3 Correspondence between DTC Vector Address and Register Information
DTC vector
address
Register information
start address
Register information
Chain transfer
Figure 9.4 Correspondence between DTC Vector Address and Register Information
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Section 9 Data Transfer Controller (DTC)
Table 9.2
Origin of
Activation
Source
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Activation
Source
Vector
Number
DTC Vector
Address
Software
Write to
DTVECR
DTVECR
External pin
IRQ0
DTCE*
Priority
H'0400 + (DTVECR
[6:0] × 2)
—
High
16
H'0420
DTCEA7
IRQ1
17
H'0422
DTCEA6
IRQ2
18
H'0424
DTCEA5
IRQ3
19
H'0426
DTCEA4
IRQ4
20
H'0428
DTCEA3
IRQ5
21
H'042A
DTCEA2
IRQ6
22
H'042C
DTCEA1
IRQ7
23
H'042E
DTCEA0
IRQ8
24
H'0430
DTCEB7
IRQ9
25
H'0432
DTCEB6
IRQ10
26
H'0434
DTCEB5
IRQ11
17
H'0436
DTCEB4
IRQ12
18
H'0438
DTCEB3
IRQ13
19
H'043A
DTCEB2
IRQ14
30
H'043C
DTCEB1
IRQ15
31
H'043E
DTCEB0
A/D
ADI
38
H'044C
DTCEC6
TPU_0
TGI0A
40
H'0450
DTCEC5
TGI0B
41
H'0452
DTCEC4
TGI0C
42
H'0454
DTCEC3
TGI0D
43
H'0456
DTCEC2
TGI1A
48
H'0460
DTCEC1
TGI1B
49
H'0462
DTCEC0
TGI2A
52
H'0468
DTCED7
TGI2B
53
H'046A
DTCED6
TPU_1
TPU_2
Low
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Section 9 Data Transfer Controller (DTC)
Origin of
Activation
Source
Activation
Source
Vector
Number
DTC Vector
Address
DTCE*
Priority
TPU_3
TGI3A
56
H'0470
DTCED5
High
TGI3B
57
H'0472
DTCED4
TGI3C
58
H'0474
DTCED3
TGI3D
59
H'0476
DTCED2
TGI4A
64
H'0480
DTCED1
TGI4B
65
H'0482
DTCED0
TGI5A
68
H'0488
DTCEE7
TGI5B
69
H'048A
DTCEE6
CMIA0
72
H'0490
DTCEE3
CMIB0
73
H'0492
DTCEE2
CMIA1
76
H'0498
DTCEE1
CMIB1
77
H'049A
DTCEE0
DMTEND0A
80
H'04A0
DTCEF7
DMTEND0B
81
H'04A2
DTCEF6
DMTEND1A
82
H'04A4
DTCEF5
DMTEND1B
83
H'04A6
DTCEF4
TPU_4
TPU_5
TMR_0
TMR_1
DMAC
SCI_0
SCI_1
SCI_2
SCI_3
SCI_4
Note:
*
RXI0
89
H'04B2
DTCEF3
TXI0
90
H'04B4
DTCEF2
RXI1
93
H'04BA
DTCEF1
TXI1
94
H'04BC
DTCEF0
RXI2
97
H'04C2
DTCEG7
TXI2
98
H'04C4
DTCEG6
RXI3
101
H'04CA
DTCEF5
TXI3
102
H'04CC
DTCEF4
RXI4
105
H'04D2
DTCEG3
TXI4
106
H'04D4
DTCEG2
Low
DTCE bits with no corresponding interrupt are reserved, and 0 should be written to.
When clearing the software standby state or all-module-clocks-stop mode with an
interrupt, write 0 to the corresponding DTCE bit.
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Section 9 Data Transfer Controller (DTC)
9.5
Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information that is already stored in the on-chip RAM and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to the onchip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer
data over any required number of channels. There are three transfer modes: normal mode, repeat
mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number
of transfers with a single activation (chain transfer). A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Figure 9.5 shows a flowchart of DTC operation, and table 9.3 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
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Section 9 Data Transfer Controller (DTC)
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE = 1?
Yes
No
CHNS = 0?
Yes
Transfer counter = 0
or DISEL = 1?
No
Yes
No
Transfer
counter = 0?
Yes
No
DISEL = 1?
Yes
No
Clear activation flag
Clear DTCER
End
Interrupt exception
handling
Figure 9.5 Flowchart of DTC Operation
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Section 9 Data Transfer Controller (DTC)
Table 9.3
Chain Transfer Conditions
1st Transfer
2nd Transfer
CHNE
CHNS
DISEL
CR
CHNE
CHNS
DISEL
CR
DTC Transfer
0
—
0
Not 0
—
—
—
—
Ends at 1st transfer
0
—
0
0
—
—
—
—
Ends at 1st transfer
0
—
1
—
—
—
—
—
Interrupt request to CPU
1
0
—
—
0
—
0
Not 0
Ends at 2nd transfer
0
—
0
0
Ends at 2nd transfer
0
—
1
—
Interrupt request to CPU
1
1
0
Not 0
—
—
—
—
Ends at 1st transfer
1
1
—
0
0
—
0
Not 0
Ends at 2nd transfer
0
—
0
0
Ends at 2nd transfer
0
—
1
—
Interrupt request to CPU
—
—
—
—
Ends at 1st transfer
1
1
1
Not 0
Interrupt request to CPU
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Section 9 Data Transfer Controller (DTC)
9.5.1
Normal Mode
In normal mode, one operation transfers one byte or one word of data. Table 9.4 lists the register
function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number
of transfers has ended, a CPU interrupt can be requested.
Table 9.4
Register Function in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register A
CRA
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR
DAR
Transfer
Figure 9.6 Memory Mapping in Normal Mode
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Section 9 Data Transfer Controller (DTC)
9.5.2
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data. Table 9.5 lists the register
function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of
transfers has ended, the initial state of the transfer counter and the address register specified as the
repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not
reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0.
Table 9.5
Register Function in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR
or
DAR
DAR
or
SAR
Repeat area
Transfer
Figure 9.7 Memory Mapping in Repeat Mode
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Section 9 Data Transfer Controller (DTC)
9.5.3
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 9.6 lists the register function in block
transfer mode.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified as the block area is restored. The other address register
is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once
the specified number of transfers has ended, a CPU interrupt is requested.
Table 9.6
Register Function in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Designates block size count
DTC transfer count register B
CRB
Designates transfer count
First block
SAR
or
DAR
Block area
Transfer
Nth block
Figure 9.8 Memory Mapping in Block Transfer Mode
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DAR
or
SAR
Section 9 Data Transfer Controller (DTC)
9.5.4
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 9.9 shows the operation of chain transfer. When activated, the DTC reads the register
information start address stored at the vector address, and then reads the first register information
at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is
1, the next register information, which is located consecutively, is read and transfer is performed.
This operation is repeated until the end of data transfer of register information with CHNE = 0. It
is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain
transfer only when the transfer counter value is 0.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Source
Destination
Register information
CHNE=1
DTC vector
address
Register information
start address
Register information
CHNE=0
Source
Destination
Figure 9.9 Operation of Chain Transfer
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Section 9 Data Transfer Controller (DTC)
9.5.5
Interrupt Sources
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,
the interrupt set as the activation source is generated. These interrupts to the CPU are subject to
CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has
ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
9.5.6
Operation Timing
φ
DTC activation
request
DTC
request
Vector read
Data transfer
Address
Read Write
Transfer
information read
Transfer
information write
Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
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Section 9 Data Transfer Controller (DTC)
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Read Write Read Write
Address
Transfer
information read
Transfer
information write
Figure 9.11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
φ
DTC activation
request
DTC
request
Data transfer
Data transfer
Read Write
Read Write
Vector read
Address
Transfer
information read
Transfer
information
write
Transfer
information
read
Transfer
information write
Figure 9.12 DTC Operation Timing (Example of Chain Transfer)
9.5.7
Number of DTC Execution States
Table 9.7 lists execution status for a single DTC data transfer, and table 9.8 shows the number of
states required for each execution status.
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Section 9 Data Transfer Controller (DTC)
Table 9.7
DTC Execution Status
Mode
Vector Read
I
Register Information
Data Read
Read/Write
K
J
Data Write
L
Internal
Operations
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 9.8
Number of States Required for Each Execution Status
OnChip
RAM
OnChip
ROM
Bus width
32
16
8
16
Access states
1
1
2
2
2
3
2
3
SI
—
1
—
—
4
6+2m
2
3+m
Register information
read/write
SJ
1
—
—
—
—
—
—
—
Byte data read
SK
1
1
2
2
2
3+m
2
3+m
Word data read
SK
1
1
4
2
4
6+2m
2
3+m
Byte data write
SL
1
1
2
2
2
3+m
2
3+m
Word data write
SL
1
1
4
2
4
6+2m
2
3+m
Internal operation
SM
Object to be Accessed
Execution
status
Vector read
On-Chip I/O
Registers
External Devices
8
16
1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
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Section 9 Data Transfer Controller (DTC)
9.6
Procedures for Using DTC
9.6.1
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
5. After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue
transferring data, set the DTCE bit to 1.
9.6.2
Activation by Software
The procedure for using the DTC with software activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Check that the SWDTE bit is 0.
4. Write 1 to SWDTE bit and the vector number to DTVECR.
5. Check the vector number written to DTVECR.
6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested.
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Section 9 Data Transfer Controller (DTC)
9.7
Examples of Use of the DTC
9.7.1
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start address of the RAM area where the data will be received in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
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Section 9 Data Transfer Controller (DTC)
9.7.2
Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG.
Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle
updating. Repeat mode transfer to NDR of the PPG is performed in the first half of the chain
transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing
of the activation source and interrupt generation at the end of the specified number of transfers are
restricted to the second half of the chain transfer (transfer when CHNE = 0).
1. Perform settings for transfer to NDR of the PPG. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to
chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH
address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.
2. Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0
= 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in
DAR, and the data table size in CRA. CRB can be set to any value.
3. Locate the TPU transfer register information consecutively after the NDR transfer register
information.
4. Set the start address of the NDR transfer register information to the DTC vector address.
5. Set the bit corresponding to TGIA in DTCER to 1.
6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
interrupt with TIER.
7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to
be used as the output trigger.
8. Set the CST bit in TSTR to 1, and start the TCNT count operation.
9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the
set value of the next output trigger period is transferred to TGRA. The activation source TGFA
flag is cleared.
10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the
CPU. Termination processing should be performed in the interrupt handling routine.
Rev.7.00 Mar. 18, 2009 page 449 of 1136
REJ09B0109-0700
Section 9 Data Transfer Controller (DTC)
9.7.3
Chain Transfer when Counter = 0
By executing a second data transfer, and performing re-setting of the first data transfer, only when
the counter value is 0, it is possible to perform 256 or more repeat transfers.
An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed
to have been set to start at lower address H'0000. Figure 9.13 shows the chain transfer when the
counter value is 0.
1. For the first transfer, set the normal mode for input data. Set fixed transfer source address
(G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0.
2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start
addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input
buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20.
3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting
the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the
first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above
input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter
for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of
the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer
destination address of the first data transfer and the transfer counter are H'0000.
5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by
means of interrupts. When the transfer counter for the first data transfer reaches 0, the second
data transfer is started. Set the upper 8 bits of the transfer source address for the first data
transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer
and the transfer counter are H'0000.
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
an interrupt request is not sent to the CPU.
Rev.7.00 Mar. 18, 2009 page 450 of 1136
REJ09B0109-0700
Section 9 Data Transfer Controller (DTC)
Input circuit
Input buffer
First data
transfer register
information
Chain transfer
(counter = 0)
Second data
transfer register
information
Upper 8 bits
of DAR
Figure 9.13 Chain Transfer when Counter = 0
Rev.7.00 Mar. 18, 2009 page 451 of 1136
REJ09B0109-0700
Section 9 Data Transfer Controller (DTC)
9.7.4
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
2. Set the start address of the register information at the DTC vector address (H'04C0).
3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
9.8
Usage Notes
9.8.1
Module Stop Mode Setting
DTC operation can be disabled or enabled using the module stop control register. The initial
setting is for DTC operation to be enabled. Register access is disabled by setting module stop
mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 24,
Power-Down Modes.
9.8.2
On-Chip RAM
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0.
Rev.7.00 Mar. 18, 2009 page 452 of 1136
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Section 9 Data Transfer Controller (DTC)
9.8.3
DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are disabled, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
9.8.4
DMAC Transfer End Interrupt
When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer
counter and DISEL bit, the DMAC’s DTE bit is not subject to DTC control, and the write data has
priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer
counter reaches 0.
9.8.5
Chain Transfer
When chain transfer is used, clearing of the activation source or DTCER is performed when the
last of the chain of data transfers is executed. SCI and A/D converter interrupt/activation sources,
on the other hand, are cleared when the DTC reads or writes to the prescribed register.
Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the
relevant register is not included in the last chained data transfer, the interrupt or activation source
will be retained.
Rev.7.00 Mar. 18, 2009 page 453 of 1136
REJ09B0109-0700
Section 9 Data Transfer Controller (DTC)
Rev.7.00 Mar. 18, 2009 page 454 of 1136
REJ09B0109-0700
Section 10 I/O Ports
Section 10 I/O Ports
Table 10.1 summarizes the port functions. The pins of each port also have other functions such as
input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes
a data direction register (DDR) that controls input/output, a data register (DR) that stores output
data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR
or DDR register.
Ports A to E have a built-in pull-up MOS function and a pull-up MOS control register (PCR) to
control the on/off state of input pull-up MOS.
Ports 3 and A include an open-drain control register (ODR) that controls the on/off state of the
output buffer PMOS.
Ports 1 to 3, 5 (P50 to P53), and 6 to 8 can drive a single TTL load and 30 pF capacitive load.
Ports A to H can drive a single TTL load and 50 pF capacitive load.
All of the I/O ports can drive a Darlington transistor when outputting data.
Ports 1 and 2 are Schmitt-triggered inputs. Ports 5, 6, 8, A (PA4, PA5, PA6, PA7), F (PF1, PF2),
and H (PH2, PH3) are Schmitt-triggered inputs when used as the IRQ input.
Rev.7.00 Mar. 18, 2009 page 455 of 1136
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Section 10 I/O Ports
Table 10.1 Port Functions
Mode 7
Port
Description
Mode 1*3 Mode 2*3 Mode 4
EXPE = 1
P17/PO15/TIOCB2/TCLKD/EDRAK3*2
Port General I/O port
1 also functioning
as PPG outputs,
P16/PO14/TIOCA2/EDRAK2*2
TPU I/Os, and
EXDMAC outputs P15/PO13/TIOCB1/TCLKC
EXPE = 0
Input/
Output
Type
P17/PO15/TIOCB2/ SchmittTCLKD
triggered
input
P16/PO14/TIOCA2
P14/PO12/TIOCA1
P13/PO11/TIOCD0/TCLKB
P12/PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0
P10/PO8/TIOCA0
Port General I/O port
2 also functioning
as PPG outputs,
TPU I/Os, and
interrupt inputs
P27/PO7/TIOCB5/(IRQ15)
Schmitttriggered
input
P26/PO6/TIOCA5/(IRQ14)
P25/PO5/TIOCB4/(IRQ13)
P24/PO4/TIOCA4/RxD4/(IRQ12)
P23/PO3/TIOCD3/TxD4/ (IRQ11)
P22/PO2/TIOCC3/(IRQ10)
P21/PO1/TIOCB3/(IRQ9)
P20/PO0/TIOCA3/(IRQ8)
Port General I/O port
3 also functioning
as SCI I/Os, I2C
I/Os, and bus
control I/Os
P35/SCK1/SCL0(OE)/(CKE*1)
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
Port General I/O port
4 also functioning
as A/D converter
analog inputs and
D/A converter
analog outputs
P47/AN7/DA1*2
P46/AN6/DA0*2
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
Rev.7.00 Mar. 18, 2009 page 456 of 1136
REJ09B0109-0700
P35/SCK1/SCL0
Opendrain
output
capability
Section 10 I/O Ports
Mode 7
Port
Description
Mode 1*3 Mode 2*3 Mode 4
EXPE = 1
Port General I/O port
5 also functioning
as interrupt
inputs, A/D
converter inputs,
and SCI I/Os
P53/ADTRG/IRQ3
Port General I/O port
6 also functioning
as interrupt
inputs, TMR I/Os,
and DMAC I/Os
P65/TMO1/DACK1/IRQ13
EXPE = 0
Input/
Output
Type
Schmitttriggered
input
when
used as
IRQ input
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
Schmitttriggered
input
when
used as
IRQ input
P64/TMO0/DACK0/IRQ12
P63/TMCI1/TEND1/IRQ11
P62/TMCI0/TEND0/IRQ10
P61/TMRI1/DREQ1/IRQ9
P60/TMRI0/DREQ0/IRQ8
Port General I/O port
8 also functioning
as EXDMAC I/Os
and interrupt
inputs
P85/EDACK3*2/(IRQ5)/SCK3
P84/EDACK2*2/(IRQ4)
P85/(IRQ5)/SCK3
P83/ETEND3*2/(IRQ3)/RxD3
P82/ETEND2*2/(IRQ2)
P83/(IRQ3)/RXD3
P81/EDREQ3*2/(IRQ1)/TxD3
80/EDREQ2*2/(IRQ0)
P81/EDREQ3/
(IRQ1)
P84/(IRQ4)
P82/(IRQ2)
Schmitttriggered
input
when
used as
IRQ input
P80/EDREQ2/
(IRQ0)
Port Dedicated input
9 port also
functioning as
A/D converter
analog inputs and
D/A converter
analog outputs
P97/AN15/DA5*2
P96/AN14/DA4*2
P95/AN13/DA3
P94/AN12/DA2
P93/AN11
P92/AN10
P91/AN9
P90/AN8
Rev.7.00 Mar. 18, 2009 page 457 of 1136
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Section 10 I/O Ports
Mode 7
Port
Description
Mode 1*3 Mode 2*3 Mode 4
EXPE = 1
Port General I/O port
A also functioning
as address
outputs
EXPE = 0
PA7/A23/IRQ7
PA7/A23/IRQ7
PA7/IRQ7
PA6/A22/IRQ6
PA6/A22/IRQ6
PA6/IRQ6
PA5/A21/IRQ5
PA5/A21/IRQ5
PA5/IRQ5
A20/IRQ4
PA4/A20/IRQ4
PA4/IRQ4
A19
PA3/A19
PA3
A18
PA2/A18
PA2
A17
PA1/A17
PA1
A16
PA0/A16
PA0
Input/
Output
Type
Only PA4
to PA7
are
Schmitttriggered
input
when
used as
IRQ
input.
Built-in
input pullup MOS
Opendrain
output
capability
Port General I/O port
B also functioning
as address
outputs
Port General I/O port
C also functioning
as address
outputs
A15
PB7/A15
PB7
A14
PB6/A14
PB6
A13
PB5/A13
PB5
A12
PB4/A12
PB4
A11
PB3/A11
PB3
A10
PB2/A10
PB2
A9
PB1/A9
PB1
A8
PB0/A8
PB0
A7
PC7/A7
PC7
A6
PC6/A6
PC6
A5
PC5/A5
PC5
A4
PC4/A4
PC4
A3
PC3/A3
PC3
A2
PC2/A2
PC2
A1
PC1/A1
PC1
A0
PC0/A0
PC0
Rev.7.00 Mar. 18, 2009 page 458 of 1136
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Built-in
input pullup MOS
Built-in
input pullup MOS
Section 10 I/O Ports
Mode 7
Port
Description
Mode 1*3 Mode 2*3 Mode 4
EXPE = 1
Port General I/O port
D also functioning
as data I/Os
Port General I/O port
E also functioning
as data I/Os
Port General I/O port
F also functioning
as interrupt inputs
and bus control
I/Os
D15
PD7
D14
PD6
D13
PD5
D12
PD4
D11
PD3
D10
PD2
D9
PD1
D8
PD0
PE7/D7
PE7
PE6/D6
PE6
PE5/D5
PE5
PE4/D4
PE4
PE3/D3
PE3
PE2/D2
PE2
PE1/D1
PE1
PE0/D0
PE0
PF7/φ
PF7φ
PF6/AS
PF6
RD
PF5
HWR
PF4
PF3/LWR
PF3
PF2/LCAS/DQML*1/IRQ15
*1
PF1/UCAS/DQMU /IRQ14
Port General I/O port
G also functioning
as bus control
I/Os
EXPE = 0
PF2/IRQ15
PF1/IRQ14
PF0/WAIT
PF0
PG6/BREQ
PG6
PG5/BACK
PG5
PG4/BREQO
PG4
PG3/CS3/RAS3/CAS*
PG3
PG2/CS2/RAS2/RAS
PG2
PG1/CS1
PG1
PG0/CS0
PG0
Input/
Output
Type
Built-in
input pullup MOS
Built-in
input pullup MOS
Only PF1
and PF2
are
Schmitttriggered
inputs
when
used as
the IRQ
input
Rev.7.00 Mar. 18, 2009 page 459 of 1136
REJ09B0109-0700
Section 10 I/O Ports
Mode 7
Port
Mode 1*3 Mode 2*3 Mode 4
Description
EXPE = 1
Port General I/O port
H also functioning
as interrupt inputs
and bus control
I/Os
EXPE = 0
PH3/CS7/(IRQ7)/OE/CKE*1
PH3/(IRQ7)
PH2/CS6/(IRQ6)
PH2/(IRQ6)
PH1/CS5/RAS5/SDRAMφ*1
PH0/CS4/RAS4/WE
*1
PH1/SDRAMφ*1
PH0
Input/
Output
Type
Only PH2
and PH3
are
Schmitttriggered
inputs
when
used as
the IRQ
input
Notes: 1. Not supported by the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
2. Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
3. Only modes 1 and 2 are supported on ROM-less versions.
10.1
Port 1
Port 1 is an 8-bit I/O port that also has other functions. The port 1 has the following registers.
• Port 1 data direction register (P1DDR)
• Port 1 data register (P1DR)
• Port 1 register (PORT1)
10.1.1
Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
When a pin function is specified to a general
purpose I/O, setting this bit to 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
4
P14DDR
0
W
3
P13DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
0
P10DDR
0
W
Rev.7.00 Mar. 18, 2009 page 460 of 1136
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Section 10 I/O Ports
10.1.2
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DR
0
R/W
6
P16DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
10.1.3
Port 1 Register (PORT1)
PORT1 shows the pin states.
PORT1 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P17
—*
R
6
P16
—*
R
5
P15
—*
R
If a port 1 read is performed while P1DDR bits are
set to 1, the P1DR values are read. If a port 1 read
is performed while P1DDR bits are cleared to 0, the
pin states are read.
4
P14
—*
R
3
P13
—*
R
2
P12
—*
R
1
P11
—*
R
0
P10
—*
R
Note:
*
Determined by the states of pins P17 to P10.
Rev.7.00 Mar. 18, 2009 page 461 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.1.4
Pin Functions
Port 1 pins also function as the pins for PPG outputs, TPU I/Os, and EXDMAC outputs*. The
correspondence between the register specification and the pin functions is shown below.
• P17/PO15/TIOCB2/TCLKD/EDRAK3*3
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in
NDERH, bit EDRAKE in EDMDR_3, and bit P17DDR.
Modes 1, 2, 4, 7 (EXPE = 1)
EDRAKE
TPU channel 2
settings
0
(1) in table
below
1
⎯
(2) in table below
P17DDR
⎯
0
1
1
⎯
NDER15
⎯
⎯
0
1
⎯
TIOCB2 output
P17
input
P17
output
PO15
output
EDRAK3 output
Pin function
1
TIOCB2 input*
2
TCLKD input*
Rev.7.00 Mar. 18, 2009 page 462 of 1136
REJ09B0109-0700
Section 10 I/O Ports
Mode 7 (EXPE = 0)
⎯
EDRAKE
TPU channel 2
settings
(1) in table
below
(2) in table below
P17DDR
⎯
0
1
1
NDER15
⎯
⎯
0
1
TIOCB2 output
P17 input
P17 output
Pin function
TIOCB2 input
2
TCLKD input*
PO15 output
*1
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000, B'000, and B'01×× and IOB3 = 1.
2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111.
TCLKD input when channels 2 and 4 are set to phase counting mode.
3. Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
TPU channel 2
settings
MD3 to MD0
(2)
(1)
B'0000, B'01××
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
⎯
B'××00
CCLR1, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'10
B'10
Output function
⎯
Output
compare output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'××00
Legend:
×: Don’t care
Rev.7.00 Mar. 18, 2009 page 463 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P16/PO14/TIOCA2/EDRAK2*3
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2), bit NDER14 in NDERH, bit EDRAKE in EDMDR_2 and bit
P16DDR.
Modes 1, 2, 4, 7 (EXPE = 1)
EDRAKE
TPU channel 2
settings
P16DDR
NDER14
Pin function
(1) in table
below
⎯
0
0
1
(2) in table below
⎯
1
1
⎯
⎯
⎯
0
1
⎯
TIOCA2 output
P16
input
P16
output
PO14
output
EDRAK2 output
1
TIOCA input*
Rev.7.00 Mar. 18, 2009 page 464 of 1136
REJ09B0109-0700
Section 10 I/O Ports
Mode 7 (EXPE = 0)
⎯
EDRAKE
TPU channel 2
settings
(1) in table
below
(2) in table below
P16DDR
⎯
0
1
1
NDER14
⎯
⎯
0
1
TIOCA2 output
P16 input
P16 output
Pin function
TIOCA2 input
TPU channel 2
settings
(2)
MD3 to MD0
B'0000, B'01××
IOA3 to IOA0
(1)
(2)
(1)
B'001×
B'0010
PO14 output
*1
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other than B'××00
CCLR1, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
2
PWM*
mode 1
output
PWM
mode 2
output
⎯
Legend:
×: Don’t care
Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000, B'000, and B'01×× and IOB3 = 1.
2. TIOCB2 output disabled.
3. Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Rev.7.00 Mar. 18, 2009 page 465 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P15/PO13/TIOCB1/TCLKC
The pin function is switched as shown below according to the combination of the TPU channel
1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit
NDER13 in NDERH, and bit P15DDR.
TPU channel 1
settings
(1) in table
below
(2) in table below
P15DDR
⎯
0
1
1
NDER13
⎯
⎯
0
1
TIOCB1 output
P15 input
P15 output
PO13 output
Pin function
1
TIOCB1 input*
2
TCLKC input*
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××.
2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'110,
or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101.
TCLKC input when phase counting mode is set for channels 2 and 4.
TPU channel 1
settings
MD3 to MD0
(2)
(1)
B'0000, B'01××
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
⎯
B'××00
CCLR1, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Legend:
×: Don’t care
Rev.7.00 Mar. 18, 2009 page 466 of 1136
REJ09B0109-0700
Other than B'××00
Section 10 I/O Ports
• P14/PO12/TIOCA1
The pin function is switched as shown below according to the combination of the TPU channel
1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1), bit NDER12 in NDERH, and bit P14DDR.
TPU channel 1
settings
(1) in table
below
(2) in table below
P14DDR
⎯
0
1
1
NDER12
⎯
⎯
0
1
TIOCA1 output
P14 input
Pin function
P14 output
PO12 output
1
TIOCA1 input*
TPU channel 1
settings
MD3 to MD0
(2)
(1)
B'0000, B'01××
(2)
(1)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other
than B'××00
CCLR1, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'01
B'01
Output function
⎯
Output
compare
output
⎯
2
PWM*
mode 1
output
PWM mode
2 output
⎯
IOA3 to IOA0
Legend:
×: Don’t care
Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 to IOA0 = B'10××.
2. TIOCB1 output disabled.
Rev.7.00 Mar. 18, 2009 page 467 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P13/PO11/TIOCD0/TCLKB
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2
to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH,
and bit P13DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P13DDR
⎯
0
1
1
NDER11
⎯
⎯
0
1
TIOCD0 output
P13 input
Pin function
P13 output
PO11 output
1
TIOCD0 input*
2
TCLKB input*
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××.
2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101.
TCLKB input when phase counting mode is set for channels 1 and 5.
TPU channel 0
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
⎯
B'××00
CCLR2, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'110
B'110
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOD3 to IOD0
Legend:
×: Don’t care
Rev.7.00 Mar. 18, 2009 page 468 of 1136
REJ09B0109-0700
Other than B'××00
Section 10 I/O Ports
• P12/PO10/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2
to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH,
and bit P12DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P12DDR
⎯
0
1
1
NDER10
⎯
⎯
0
1
TIOCC0 output
P12 input
P12 output
PO10 output
Pin function
1
TIOCC0 input*
2
TCLKA input*
TPU channel 0
settings
(2)
MD3 to MD0
IOC3 to IOC0
(1)
B'0000
(2)
(1)
(1)
(2)
B'001×
B'0010
B''0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other
than B'××00
CCLR2, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'101
B'101
Output function
⎯
Output
compare
output
⎯
3
PWM*
mode 1
output
PWM mode
2 output
⎯
Legend:
×: Don’t care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××.
2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100.
TCLKA input when phase counting mode is set for channels 1 and 5.
3. TIOCD0 output disabled.
Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0.
Rev.7.00 Mar. 18, 2009 page 469 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P11/PO9/TIOCB0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH, and bit P11DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P11DDR
⎯
0
1
1
NDER9
⎯
⎯
0
1
TIOCB0 output
P11 input
P11 output
PO9 output
Pin function
TIOCB0 input*
Note:
*
TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10××.
TPU channel 0
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
⎯
B'××00
CCLR2, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'010
B'010
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Legend:
×: Don’t care
Rev.7.00 Mar. 18, 2009 page 470 of 1136
REJ09B0109-0700
Other than B'××00
Section 10 I/O Ports
• P10/PO8/TIOCA0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH, and bit P10DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P10DDR
⎯
0
1
1
NDER8
⎯
⎯
0
1
TIOCA0 output
P10 input
Pin function
P10 output
PO8 output
1
TIOCA0 input*
TPU channel 0
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(1)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other
than B'××00
CCLR2, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'001
B'001
Output function
⎯
Output
compare
output
⎯
2
PWM*
mode 1
output
PWM
mode 2
output
⎯
IOA3 to IOA0
Legend:
×: Don’t care
Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××.
2. TIOCB0 output disabled.
Rev.7.00 Mar. 18, 2009 page 471 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.2
Port 2
Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers.
• Port 2 data direction register (P2DDR)
• Port 2 data register (P2DR)
• Port 2 register (PORT2)
10.2.1
Port 2 Data Direction Register (P2DDR)
The individual bits of P2DDR specify input or output for the pins of port 2.
P2DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DDR
0
W
6
P26DDR
0
W
5
P25DDR
0
W
When a pin function is specified to a general
purpose I/O, setting this bit to 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
4
P24DDR
0
W
3
P23DDR
0
W
2
P22DDR
0
W
1
P21DDR
0
W
0
P20DDR
0
W
Rev.7.00 Mar. 18, 2009 page 472 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.2.2
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DR
0
R/W
6
P26DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
0
P20DR
0
R/W
10.2.3
Port 2 Register (PORT2)
PORT2 shows the pin states.
PORT2 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P27
⎯*
R
6
P26
⎯*
R
5
P25
⎯*
R
If a port 2 read is performed while P2DDR bits are
set to 1, the P2DR values are read. If a port 2 read
is performed while P2DDR bits are cleared to 0, the
pin states are read.
4
P24
⎯*
R
3
P23
⎯*
R
2
P22
⎯*
R
1
P21
⎯*
R
0
P20
⎯*
R
Note:
*
Determined by the states of pins P27 to P20.
Rev.7.00 Mar. 18, 2009 page 473 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.2.4
Pin Functions
Port 2 pins also function as PPG outputs, TPU I/Os, and interrupt inputs. The correspondence
between the register specification and the pin functions is shown below.
• P27/PO7/TIOCB5/(IRQ15)
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER7 in NDERL, bit P27DDR, and bit ITS15 in ITSR.
TPU channel 5
settings
(1) in table
below
(2) in table below
P27DDR
⎯
0
1
1
NDER7
⎯
⎯
0
1
TIOCB5 output
P27 input
P27 output
Pin function
TIOCB5 input
2
IRQ5 interrupt input*
PO7 output
*1
Notes: 1. TIOCB5 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1.
2. IRQ15 input when ITS15 = 1.
TPU channel 5
settings
MD3 to MD0
IOB3 to IOB0
(2)
(1)
B'0000, B'01××
(2)
(2)
(1)
B'0010
B'0011
Other than B'××00
(2)
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
CCLR1, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
Legend:
×: Don’t care
Rev.7.00 Mar. 18, 2009 page 474 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P26/PO6/TIOCA5/(IRQ14)
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER6 in NDERL, bit P26DDR, and bit ITS14 in ITSR.
TPU channel 5
settings
(1) in table
below
(2) in table below
P26DDR
⎯
0
1
1
NDER6
⎯
⎯
0
1
TIOCA5 output
P26 input
Pin function
P26 output
PO6 output
1
TIOCA5 input*
IRQ14 interrupt input*
2
TPU channel 5
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01××
(2)
(2)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other than
B'××00
CCLR1, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'01
B'01
Output function
⎯
Output
compare
output
⎯
3
PWM*
mode 1
output
PWM mode
2 output
⎯
Legend:
×: Don’t care
Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1.
2. IRQ14 input when ITS14 = 1.
3. TIOCB5 output disabled.
Rev.7.00 Mar. 18, 2009 page 475 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P25/PO5/TIOCB4/(IRQ13)
The pin function is switched as shown below according to the combination of the TPU channel
4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1
and CCLR0 in TCR_4), bit NDER5 in NDERL, bit P25DDR, and bit ITS13 in ITSR.
TPU channel 4
settings
(1) in table
below
(2) in table below
P25DDR
⎯
0
1
1
NDER5
⎯
⎯
0
1
TIOCB4 output
P25 input
Pin function
P25 output
PO5 output
1
TIOCB4 input*
IRQ13 interrupt input*
2
Notes: 1. TIOCB4 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××.
2. IRQ13 input when ITS13 = 1.
TPU channel 4
settings
MD3 to MD0
(2)
(1)
B'0000, B'01××
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
⎯
B'××00
CCLR1, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Legend:
×: Don’t care
Rev.7.00 Mar. 18, 2009 page 476 of 1136
REJ09B0109-0700
Other than B'××00
Section 10 I/O Ports
• P24/PO4/TIOCA4/RxD4/(IRQ12)
The pin function is switched as shown below according to the combination of the TPU channel
4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1
and CCLR0 in TCR_4), bit NDER4 in NDERL, bit RE in SCR of SCI_4, bit P24DDR, and bit
ITS12 in ITSR.
RE
TPU channel 4
settings
(1) in table
below
0
1
(2) in table below
⎯
P24DDR
⎯
0
1
1
⎯
NDER4
⎯
⎯
0
1
⎯
TIOCA4 output
P24 input
P24 output
PO4 output
RXD4 input
pin
Pin function
1
TIOCA4 input*
IRQ12 interrupt input*
2
TPU channel 4
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01××
(2)
(1)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other
than B'××00
CCLR1, CCLR0
⎯
⎯
⎯
⎯
Other
than
B'01
B'01
Output function
⎯
Output
compare
output
⎯
3
PWM*
mode 1
output
PWM mode
2 output
⎯
Legend:
×: Don’t care
Notes: 1. TIOCA4 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 to IOA0 = B'10××.
2. IRQ12 input when ITS12 = 1.
3. TIOCB4 output disabled.
Rev.7.00 Mar. 18, 2009 page 477 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P23/PO3/TIOCD3/TxD4/(IRQ11)
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL, bit TE in SCR of SCI_4, bit P23DDR,
and bit ITS11 in ITSR.
TE
TPU channel 3
settings
0
(1) in table
below
1
⎯
(2) in table below
P23DDR
⎯
0
1
1
⎯
NDER3
⎯
⎯
0
1
⎯
TIOCD3 output
P23 input
P23 output
PO3 output
TXD4 output
Pin function
1
TIOCA3 input*
IRQ11 interrupt input*
2
Notes: 1. TIOCD3 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××.
2. IRQ11 input when ITS11 = 1.
TPU channel 3
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
⎯
B'××00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other
than
B'110
B'110
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOD3 to IOD0
Legend:
×: Don’t care
Rev.7.00 Mar. 18, 2009 page 478 of 1136
REJ09B0109-0700
Other than B'××00
Section 10 I/O Ports
• P22/PO2/TIOCC3/(IRQ10)
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2
to CCLR0 in TCR_3), bit NDER2 in NDERL, bit P22DDR, and bit ITS10 in ITSR.
TPU channel 3
settings
(1) in table
below
(2) in table below
P22DDR
⎯
0
1
1
NDER2
⎯
⎯
0
1
TIOCC3 output
P22 input
Pin function
P22 output
PO2 output
1
TIOCC3 input*
IRQ10 interrupt input*
2
TPU channel 3
settings
(2)
MD3 to MD0
IOC3 to IOC0
(1)
B'0000
(2)
(1)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other
than B'××00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other
than
B'101
B'101
Output function
⎯
Output
compare
output
⎯
3
PWM*
mode 1
output
PWM mode
2 output
⎯
Legend:
×: Don’t care
Notes: 1. TIOCC3 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××.
2. IRQ10 input when ITS10 = 1.
3. TIOCD3 output disabled.
Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_3.
Rev.7.00 Mar. 18, 2009 page 479 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P21/PO1/TIOCB3/(IRQ9)
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL, bit P21DDR, and bit ITS9 in ITSR.
TPU channel 3
settings
(1) in table
below
(2) in table below
P21DDR
⎯
0
1
1
NDER1
⎯
⎯
0
1
TIOCB3 output
P21 input
Pin function
P21 output
PO1 output
1
TIOCB3 input*
IRQ9 interrupt input*
2
Notes: 1. TIOCB3 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10××.
2. IRQ9 input when ITS9 = 1.
TPU channel 3
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
⎯
B'××00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other
than
B'010
B'010
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Legend:
×: Don’t care
Rev.7.00 Mar. 18, 2009 page 480 of 1136
REJ09B0109-0700
Other than B'××00
Section 10 I/O Ports
• P20/PO0/TIOCA3/(IRQ8)
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL, bit P20DDR, and bit ITS8 in ITSR.
TPU channel 3
settings
(1) in table
below
(2) in table below
P20DDR
⎯
0
1
1
NDER0
⎯
⎯
0
1
TIOCA3 output
P20 input
Pin function
P20 output
PO0 output
1
TIOCA3 input*
IRQ8 interrupt input*
2
TPU channel 3
settings
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000
(2)
(1)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other
than B'××00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other
than
B'001
B'001
Output function
⎯
Output
compare
output
⎯
3
PWM*
mode 1
output
PWM mode
2 output
⎯
Legend:
×: Don’t care
Notes: 1. TIOCA3 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××.
2. IRQ8 input when ITS8 = 1.
3. TIOCB3 output disabled.
Rev.7.00 Mar. 18, 2009 page 481 of 1136
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Section 10 I/O Ports
10.3
Port 3
Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers.
• Port 3 data direction register (P3DDR)
• Port 3 data register (P3DR)
• Port 3 register (PORT3)
• Port 3 open drain control register (P3ODR)
• Port function control register 2(PFCR2)
10.3.1
Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the pins of port 3.
P3DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
7, 6
⎯
All 0
⎯
Description
Reserved
These bits are always read as 0 and cannot be
modified.
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
2
P32DDR
0
W
1
P31DDR
0
W
0
P30DDR
0
W
Rev.7.00 Mar. 18, 2009 page 482 of 1136
REJ09B0109-0700
When a pin function is specified to a general
purpose I/O, setting this bit to 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
Section 10 I/O Ports
10.3.2
Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit
Bit Name
Initial Value
R/W
7, 6
⎯
All 0
⎯
Description
Reserved
These bits are always read as 0 and cannot be
modified.
5
P35DR
0
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
0
P30DR
0
R/W
10.3.3
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
Port 3 Register (PORT3)
PORT3 shows the pin states.
PORT3 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
5
P35
⎯*
R
4
P34
⎯*
R
3
P33
⎯*
R
2
P32
⎯*
R
1
P31
⎯*
R
0
P30
⎯*
R
Note:
*
If a port 3 read is performed while P3DDR bits are
set to 1, the P3DR values are read. If a port 1 read
is performed while P3DDR bits are cleared to 0, the
pin states are read.
Determined by the states of pins P35 to P30.
Rev.7.00 Mar. 18, 2009 page 483 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.3.4
Port 3 Open Drain Control Register (P3ODR)
P3ODR controls the output status for each port 3 pin.
Bit
Bit Name
Initial Value
R/W
7, 6
⎯
All 0
⎯
Description
Reserved
These bits are always read as 0 and cannot be
modified.
5
P35ODR
0
R/W
4
P34ODR
0
R/W
3
P33ODR
0
R/W
2
P32ODR
0
R/W
1
P31ODR
0
R/W
0
P30ODR
0
R/W
Rev.7.00 Mar. 18, 2009 page 484 of 1136
REJ09B0109-0700
Setting a P3ODR bit to 1 makes the corresponding
port 3 pin an NMOS open-drain output pin, while
clearing the bit to 0 makes the pin a CMOS output
pin.
Section 10 I/O Ports
10.3.5
Port Function Control Register 2 (PFCR2)
P3ODR controls the I/O port.
Bit
Bit Name
Initial Value
R/W
7
to
4
⎯
All 0
⎯
3
ASOE
Description
Reserved
These bits are always read as 0 and cannot be
modified.
1
R/W
AS Output Enable
Selects to enable or disable the AS output pin.
0: PF6 is designated as I/O port
1: PF6 is designated as AS output pin
2
LWROE
1
R/W
LWR Output Enable
Selects to enable or disable the LWR output pin.
0: PF3 is designated as I/O port
1: PF3 is designated as LWR output pin
1
OES
1
R/W
OE Output Select
Selects the OE/CKE output pin port when the OEE
bit is set to 1 in DRAMCR (enabling OE/CKE output).
0: P35 is designated as OE/CKE output pin
1: PH3 is designated as OE/CKE output pin
0
⎯
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev.7.00 Mar. 18, 2009 page 485 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.3.6
Pin Functions
Port 3 pins also function as the pins for SCI I/Os, I2C output, and a bus control signal output. The
correspondence between the register specification and the pin functions is shown below.
• P35/SCK1/SCL0/(OE)/(CKE*3)
The pin function is switched as shown below according to the combination of the ICE bit in
ICCRA of I2C_0, C/A bit in SMR of SCI_1, bits CKE0 and CKE1 in SCR, bits OEE and
RMTS2 to RMTS0 in DRAMCR, bit OES in PFCR2, and bit P35DDR.
Modes 1, 2, 4, 7 (EXPE = 1)
OEE
0
1
OES
⎯
1
0
SDRAM
space
⎯
⎯
Normal continuor
ous
DRAM SDRAM
space space
⎯
ICE
CKE1
1
1
⎯
1
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
0
C/A
0
CKE0
0
P35DDR
0
Pin
function
P35
input
1
P35
SCK1 SCK1
output output output
*1
*1
*1
0
⎯
⎯
0
SCK1
input
SCL0
2
I/O*
P35
input
Rev.7.00 Mar. 18, 2009 page 486 of 1136
REJ09B0109-0700
1
⎯
⎯
1
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
0
0
1
P35
SCK1 SCK1
output output output
*1
*1
*1
⎯
SCK1
input
OE
SCL0
2
I/O* output
⎯
CKE
output
Section 10 I/O Ports
Mode 7 (EXPE = 0)
OEE
⎯
OES
⎯
SDRAM space
⎯
ICE
0
CKE1
C/A
⎯
1
⎯
⎯
1
⎯
⎯
⎯
0
CKE0
0
0
1
⎯
⎯
⎯
⎯
P35
input
P35
1
output*
SCK1
1
output*
SCK1
1
output*
SCK1
input
SCL0
2
I/O*
P35DDR
Pin function
1
1
0
Notes: 1. NMOS open-drain output when P35ODR = 1.
2. NMOS open-drain output regardless of P35ODR.
3. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
• P34/SCK0/SCK4/SDA0
The pin function is switched as shown below according to the combination of bit ICE in
ICCRA of I2C_0, bit C/A in SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR.
ICE
0
CKE1
⎯
⎯
⎯
1
⎯
⎯
⎯
0
CKE0
Pin function
1
1
0
C/A
P34DDR
1
0
0
1
⎯
⎯
⎯
⎯
P34
input
P34
1
output*
SCK0/SCK4
1 3
output* *
SCK0/SCK4
1 3
output* *
SCK0/SCK4
input
SDA0
2
I/O*
Notes: 1. NMOS open-drain output when P34ODR = 1.
2. NMOS open-drain output regardless of P34ODR.
3. Simultaneous output of SCK0 and SCK4 cannot be set.
Rev.7.00 Mar. 18, 2009 page 487 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P33/RxD1/SCL1
The pin function is switched as shown below according to the combination of bit ICE in
ICCRA of I2C_0, bit RE in SCR of SCI_1 and bit P33DDR.
ICE
0
RE
1
0
P33DDR
Pin function
1
⎯
0
1
⎯
⎯
P33 input
1
P33 output*
RxD1 input
SCL1 I/O*
2
Notes: 1. NMOS open-drain output when P33ODR = 1.
2. NMOS open-drain output regardless of P33ODR.
• P32/RxD0/IrRxD/SDA1
The pin function is switched as shown below according to the combination of bit ICE in
ICCRA of I2C_0, bit RE in SCR of SCI_0 and bit P32DDR.
ICE
0
RE
1
1
⎯
⎯
⎯
RxD0/IrRxD
input
SDA1 I/O*
0
P32DDR
0
Pin function
1
P32 input
P32 output
*1
2
Notes: 1. NMOS open-drain output when P32ODR = 1.
2. NMOS open-drain output regardless of P32ODR.
• P31/TxD1
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_1 and bit P31DDR.
TE
0
P31DDR
Pin function
Note:
*
1
0
1
⎯
P31 input
P31 output*
TxD1 output*
NMOS open-drain output when P31ODR = 1.
Rev.7.00 Mar. 18, 2009 page 488 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P30/TxD0/IrTxD
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_0 and bit P30DDR.
TE
0
0
1
⎯
P30 input
P30 output*
RxD0/IrRxD
output*
P30DDR
Pin function
Note:
NMOS open-drain output when P30ODR = 1.
*
10.4
1
Port 4
Port 4 is an 8-bit input-only port. Port 4 has the following register.
• Port 4 register (PORT4)
10.4.1
Port 4 Register (PORT4)
PORT4 is an 8-bit read-only register that shows port 4 pin states.
PORT4 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P47
⎯*
R
The pin states are always read from this register.
6
P46
⎯*
R
5
P45
⎯*
R
4
P44
⎯*
R
3
P43
⎯*
R
2
P42
⎯*
R
1
P41
⎯*
R
0
P40
⎯*
R
Note:
*
Determined by the states of pins P47 to P40.
Rev.7.00 Mar. 18, 2009 page 489 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.4.2
Pin Functions
Port 4 also functions as the pins for A/D converter analog input and D/A converter analog output.
The correspondence between pins are as follows.
• P47/AN7/DA1*
Pin function
AN7 input
DA1 output
Note:
*
Not available for the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
• P46/AN6/DA0*
Pin function
AN6 input
DA0 output
Note:
*
Not available for the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
• P45/AN5
Pin function
AN5 input
• P44/AN4
Pin function
AN4 input
• P43/AN3
Pin function
AN3 input
• P42/AN2
Pin function
AN2 input
• P41/AN1
Pin function
AN1 input
• P40/AN0
Pin function
Rev.7.00 Mar. 18, 2009 page 490 of 1136
REJ09B0109-0700
AN0 input
Section 10 I/O Ports
10.5
Port 5
Port 5 is a 4-bit I/O port. The port 5 has the following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
• Port 5 register (PORT5)
10.5.1
Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the pins of port 5.
P5DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
⎯
All 0
⎯
Reserved
3
P53DDR
0
W
2
P52DDR
0
W
1
P51DDR
0
W
0
P50DDR
0
W
These bits are always read as 0 and cannot be
modified.
10.5.2
When a pin function is specified to a general
purpose I/O, setting this bit to 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
⎯
All 0
⎯
Reserved
3
P53DR
0
R/W
2
P52DR
0
R/W
1
P51DR
0
R/W
0
P50DR
0
R/W
These bits are always read as 0 and cannot be
modified.
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
Rev.7.00 Mar. 18, 2009 page 491 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.5.3
Port 5 Register (PORT5)
PORT5 shows the pin states. PORT5 cannot be modified.
Bit
Bit Name
7to 4 ⎯
Initial Value
R/W
Description
Undefined
R
Reserved
Undefined values are read from these bits.
3
P53
⎯*
R
2
P52
⎯*
R
1
P51
⎯*
R
0
P50
⎯*
R
Note:
*
10.5.4
If bits P53 to P50 are read while P5DDR bits are set
to 1, the P5DR values are read. If a port 5 read is
performed while P5DDR bits are cleared to 0, the
pin states are read.
Determined by the states of pins P53 to P50.
Pin Functions
Port 5 pins also function as the pins for SCI I/Os, A/D converter inputs, and interrupt inputs. The
correspondence between the register specification and the pin functions is shown below.
• P53/ADTRG/IRQ3
The pin function is switched as shown below according to the combination of bits TRGS1 and
TRGS0 in the A/D control register (ADCR), bit ITS3 in ITSR, and bit P53DDR.
P53DDR
Pin function
0
1
P53 input
P53 output
1
ADTRG input*
IRQ3 interrupt input*
2
Notes: 1. ADTRG input when TRGS1 = TRGS0 = 1.
2. IRQ3 input when ITS3 = 0.
Rev.7.00 Mar. 18, 2009 page 492 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P52/SCK2/IRQ2
The pin function is switched as shown below according to the combination of bit C/A in SMR
of SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR.
CKE1
0
C/A
1
0
CKE0
0
P52DDR
Pin function
1
1
⎯
⎯
⎯
0
1
⎯
⎯
⎯
P52
input
P52
output
SCK2 output
SCK2 output
SCK2
input
IRQ2 interrupt input*
Note:
*
IRQ2 input when ITS2 = 0.
• P51/RxD2/IRQ1
The pin function is switched as shown below according to the combination of bit RE in SCR of
SCI_2, bit ITS1 in ITSR, and bit P51DDR.
RE
0
P51DDR
0
Pin function
P51 input
1
1
⎯
P51 output
RxD2 input
IRQ1 interrupt input*
Note:
*
IRQ1 input when ITS1 = 0.
• P50/TxD2/IRQ0
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_2, bit ITS0 in ITSR, and bit P50DDR.
TE
0
P50DDR
Pin function
1
0
1
⎯
P50 input
P50 output
TxD2 input
IRQ0 interrupt input*
Note:
*
IRQ0 input when ITS0 = 0.
Rev.7.00 Mar. 18, 2009 page 493 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.6
Port 6
Port 6 is a 6-bit I/O port that also has other functions. The port 6 has the following registers.
• Port 6 data direction register (P6DDR)
• Port 6 data register (P6DR)
• Port 6 register (PORT6)
10.6.1
Port 6 Data Direction Register (P6DDR)
The individual bits of P6DDR specify input or output for the pins of port 6.
P6DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
5
P65DDR
0
W
4
P64DDR
0
W
3
P63DDR
0
W
When a pin function is specified to a general
purpose I/O, setting this bit to 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
2
P62DDR
0
W
1
P61DDR
0
W
0
P60DDR
0
W
Rev.7.00 Mar. 18, 2009 page 494 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.6.2
Port 6 Data Register (P6DR)
P6DR stores output data for the port 6 pins.
Bit
Bit Name
Initial Value
R/W
7, 6
⎯
All 0
⎯
Description
Reserved
These bits are always read as 0 and cannot be
modified.
5
P65DR
0
R/W
4
P64DR
0
R/W
3
P63DR
0
R/W
2
P62DR
0
R/W
1
P61DR
0
R/W
0
P60DR
0
R/W
10.6.3
An output data for a pin is stored when the pin
function is specified to a general purpose I/O.
Port 6 Register (PORT6)
PORT6 shows the pin states.
PORT6 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
Undefined
⎯
Reserved
These bits are reserved, if read they will return an
undefined value.
5
P65
⎯*
R
4
P64
⎯*
R
3
P63
⎯*
R
2
P62
⎯*
R
1
P61
⎯*
R
0
P60
⎯*
R
Note:
*
If a port 6 read is performed while P6DDR bits are
set to 1, the P6DR values are read. If a port 6 read
is performed while P6DDR bits are cleared to 0, the
pin states are read.
Determined by the states of pins P65 to P60.
Rev.7.00 Mar. 18, 2009 page 495 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.6.4
Pin Functions
Port 6 pins also function as 8-bit timer I/Os, interrupt inputs, and DMAC I/Os. The
correspondence between the register specification and the pin functions is shown below.
• P65/TMO1/DACK1/IRQ13
The pin function is switched as shown below according to the combination of bit SAE1 in
DMABCRH of the DMAC, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit P65DDR, and
bit ITS13 in ITSR.
SAE1
0
OS3 to OS0
P65DDR
Pin function
1
All 0
Not
all 0
⎯
0
1
⎯
⎯
P65
input
P65
output
TMO1
output
DACK1
output
IRQ13 interrupt input*
Note:
*
IRQ13 interrupt input when ITS13 = 0.
• P64/TMO0/DACK0/IRQ12
The pin function is switched as shown below according to the combination of bit SAE0 in
DMABCRH of the DMAC, bits OS3 to OS0 in TCSR_0 of the 8-bit timer, bit P64DDR, and
bit ITS12 in ITSR.
SAE1
0
OS3 to OS0
P64DDR
Pin function
1
All 0
Not
all 0
⎯
0
1
⎯
⎯
P64
input
P64
output
TMO0
output
DACK0
output
IRQ12 interrupt input*
Note:
*
IRQ12 interrupt input when ITS12 = 0.
Rev.7.00 Mar. 18, 2009 page 496 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P63/TMCI1/TEND1/IRQ11
The pin function is switched as shown below according to the combination of bit TEE1 in
DMATCR of the DMAC, bit P63DDR, and bit ITS11 in ITSR.
TEE1
P63DDR
Pin function
0
1
0
1
⎯
P63
input
P63
output
TEND1
output
IRQ11 interrupt input*
2
TMCI1 input*
1
Notes: 1. IRQ11 interrupt input when ITS11 = 0.
2. When used as the external clock input pin for the TMR, its pin function should be
specified to the external clock input by the CKS2 to CKS0 bits in TCR_1.
• P62/TMCI0/TEND0/IRQ10
The pin function is switched as shown below according to the combination of bit TEE0 in
DMATCR of the DMAC, bit P62DDR, and bit ITS10 in ITSR.
TEE0
P62DDR
Pin function
0
1
0
1
⎯
P62
input
P62
output
TEND0
output
IRQ10 interrupt input*
2
TMCI0 input*
1
Notes: 1. IRQ10 interrupt input when ITS10 = 0.
2. When used as the external clock input pin for the TMR, its pin function should be
specified to the external clock input by the CKS2 to CKS0 bits in TCR_0.
Rev.7.00 Mar. 18, 2009 page 497 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• P61/TMRI1/DREQ1/IRQ9
The pin function is switched as shown below according to the combination of bit P61DDR and
bit ITS9 in ITSR.
P61DDR
Pin function
0
1
P61 input
P61 output
1
TMRI1 input*
DREQ1 input
IRQ9 interrupt input*
2
Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits
in TCR_1 should be set to 1.
2. IRQ9 interrupt input when ITS9 = 0.
• P60/TMRI0/DREQ0/IRQ8
The pin function is switched as shown below according to the combination of bit and bit ITS8
in ITSR.
P60DDR
Pin function
0
1
P60 input
P60 output
1
TMRI0 input*
DREQ0 input
IRQ8 interrupt input*
2
Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits
in TCR_0 should be set to 1.
2. IRQ8 interrupt input when ITS8 = 0.
Rev.7.00 Mar. 18, 2009 page 498 of 1136
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Section 10 I/O Ports
10.7
Port 8
Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers.
• Port 8 data direction register (P8DDR)
• Port 8 data register (P8DR)
• Port 8 register (PORT8)
10.7.1
Port 8 Data Direction Register (P8DDR)
The individual bits of P8DDR specify input or output for the pins of port 8.
P8DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
5
P85DDR
0
W
4
P84DDR
0
W
3
P83DDR
0
W
2
P82DDR
0
W
1
P81DDR
0
W
0
P80DDR
0
W
When a pin function is specified to a general
purpose I/O, setting this bit to 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
Rev.7.00 Mar. 18, 2009 page 499 of 1136
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Section 10 I/O Ports
10.7.2
Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins.
Bit
Bit Name
Initial Value
R/W
7, 6
⎯
0
⎯
Description
Reserved
These bits are always read as 0 and cannot be
modified.
5
P85DR
0
R/W
4
P84DR
0
R/W
3
P83DR
0
R/W
2
P82DR
0
R/W
1
P81DR
0
R/W
0
P80DR
0
R/W
10.7.3
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
Port 8 Register (PORT8)
PORT8 shows the pin states.
PORT8 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
Undefined
⎯
Reserved
These bits are reserved, if read they will return an
undefined value.
5
P85
⎯*
R
4
P84
⎯*
R
3
P83
⎯*
R
2
P82
⎯*
R
1
P81
⎯*
R
0
P80
⎯*
R
Note:
*
If a port 8 read is performed while P8DDR bits are
set to 1, the P8DR values are read. If a port 8 read
is performed while P8DDR bits are cleared to 0, the
pin states are read.
Determined by the states of pins P85 to P80.
Rev.7.00 Mar. 18, 2009 page 500 of 1136
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Section 10 I/O Ports
10.7.4
Pin Functions
Port 8 pins also function as SCI I/Os, interrupt inputs, and EXDMAC I/Os. The correspondence
between the register specification and the pin functions is shown below.
• P85/EDACK3*/(IRQ5)/SCK3
The pin function is switched as shown below according to the combination of bit AMS in
EDMDR_3 of the EXDMAC, bit C/A in SMR in SCI_3, bit P85DDR, and bit ITS5 in ITSR.
Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Modes 1, 2, 4, 7 (EXPE = 1)
AMS
0
CKE1
1
1
⎯
1
⎯
⎯
1
⎯
⎯
⎯
0
C/A
0
CKE0
0
P85DDR
Pin function
0
1
⎯
⎯
⎯
⎯
P85
input
P85
output
SCK3
output
SCK3
output
SCK3
input
EDACK3
output
IRQ5 interrupt input*
Note:
*
IRQ5 input when ITS5 = 1.
Mode 7 (EXPE = 0)
⎯
AMS
CKE1
0
C/A
1
0
1
⎯
⎯
1
⎯
⎯
⎯
P85
input
P85
output
SCK3
output
SCK3
output
SCK3
input
0
Pin function
⎯
0
CKE0
P85DDR
1
IRQ5 interrupt input*
Note:
*
IRQ5 input when ITS5 = 1.
Rev.7.00 Mar. 18, 2009 page 501 of 1136
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Section 10 I/O Ports
• P84/EDACK2*/(IRQ4)
The pin function is switched as shown below according to the combination of bit AMS in
EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR.
Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Modes 1, 2, 4, 7 (EXPE = 1)
AMS
0
0
1
⎯
P84 input
P84 input/output
EDACK2 output
P84DDR
Pin function
1
IRQ4 interrupt input*
Note:
*
IRQ4 input when ITS4 = 1.
Mode 7 (EXPE = 0)
⎯
AMS
P84DDR
0
Pin function
1
P84 input
P84 output
IRQ4 interrupt input*
Note:
*
IRQ4 input when ITS4 = 1.
• P83/ETEND3*/(IRQ3)/RXD3
The pin function is switched as shown below according to the combination of bit ETENDE in
EDMDR_3 of the EXDMAC, bit RE in SCR of SCI_3, bit P83DDR, and bit ITS3 in ITSR.
Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Modes 1, 2, 4, 7 (EXPE = 1)
ETENDE
0
RE
0
P83DDR
Pin function
Note:
*
0
1
P83 input
P83 output
IRQ3 input when ITS3 = 1.
Rev.7.00 Mar. 18, 2009 page 502 of 1136
REJ09B0109-0700
1
1
⎯
⎯
⎯
RXD3 output
IRQ3 interrupt input*
ETEND3 output
Section 10 I/O Ports
Mode 7 (EXPE = 0)
⎯
ETENDE
RE
0
P83DDR
0
Pin function
1
⎯
1
P83 input
P83 output
RXD3 input
IRQ3 interrupt input*
Note:
*
IRQ3 input when ITS3 = 1.
• P82/ETEND2*/(IRQ2)
The pin function is switched as shown below according to the combination of bit ETENDE in
EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR.
Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Modes 1, 2, 4, 7 (EXPE = 1)
ETENDE
0
P82DDR
Pin function
1
0
1
⎯
P82 input
P82 output
ETEND2 output
IRQ2 interrupt input*
Note:
*
IRQ2 input when ITS2 = 1.
Mode 7 (EXPE = 0)
⎯
ETENDE
P82DDR
0
Pin function
1
P82 input
P82 output
IRQ2 interrupt input*
Note:
*
IRQ2 input when ITS2 = 1.
Rev.7.00 Mar. 18, 2009 page 503 of 1136
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Section 10 I/O Ports
• P81/EDREQ3*/(IRQ1)/TxD3
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_3, bit P81DDR and bit ITS1 in ITSR.
Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
TE
0
0
1
⎯
P81 input
P81 output
TxD3 output
P81DDR
Pin function
1
EDREQ3 input
IRQ1 interrupt input*
Note:
*
IRQ1 input when ITS1 = 1.
• P80/EDREQ2*/(IRQ0)
The pin function is switched as shown below according to the combination of bit P80DDR and
bit ITS0 in ITSR.
Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
P80DDR
0
Pin function
1
P80 input
P80 output
EDREQ2 input
IRQ0 interrupt input*
Note:
*
IRQ0 input when ITS0 = 1.
Rev.7.00 Mar. 18, 2009 page 504 of 1136
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Section 10 I/O Ports
10.8
Port 9
Port 9 is an 8-bit input-only port. Port 4 has the following register.
• Port 9 register (PORT4)
10.8.1
Port 9 Register (PORT9)
PORT9 is an 8-bit read-only register that shows port 4 pin states.
PORT9 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P97
⎯*
R
6
P96
⎯*
R
The pin states are always read when a port 9 read is
performed.
5
P95
⎯*
R
4
P99
⎯*
R
3
P93
⎯*
R
2
P92
⎯*
R
1
P91
⎯*
R
0
P90
⎯*
R
Note:
*
Determined by the states of pins P97 to P90.
Rev.7.00 Mar. 18, 2009 page 505 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.8.2
Pin Functions
Port 9 also functions as the pins for A/D converter analog input and D/A converter analog output.
The correspondence between pins are as follows.
• P97/AN15/DA5*
Pin function
AN15 input
DA5 output
Note:
*
Not available for the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
• P96/AN14/DA4*
Pin function
AN14 input
DA4 output
Note:
*
Not available for the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
• P95/AN13/DA3
Pin function
AN13 input
DA3 output
• P94/AN12/DA2
Pin function
AN12 input
DA2 output
• P93/AN11
Pin function
AN11 input
• P92/AN10
Pin function
AN10 input
• P91/AN9
Pin function
AN9 input
• P90/AN8
Pin function
Rev.7.00 Mar. 18, 2009 page 506 of 1136
REJ09B0109-0700
AN8 input
Section 10 I/O Ports
10.9
Port A
Port A is an 8-bit I/O port that also has other functions. The port A has the following registers.
• Port A data direction register (PADDR)
• Port A data register (PADR)
• Port A register (PORTA)
• Port A pull-up MOS control register (PAPCR)
• Port A open-drain control register (PAODR)
• Port function control register 1 (PFCR1)
10.9.1
Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7DDR
0
W
•
6
PA6DDR
0
W
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
0
PA0DDR
0
W
Modes 1 and 2
Pins PA4 to PA0 are address outputs regardless
of the PADDR settings.
For pins PA7 to PA5, when the corresponding bit
of A23E to A21E is set to 1, setting a PADDR bit
to 1 makes the corresponding port A pin an
address output, while clearing the bit to 0 makes
the pin an input port. Clearing one of bits A23E to
A21E to 0 makes the corresponding port A pin an
I/O port, and its function can be switched with
PADDR.
•
Modes 7 (when EXPE = 1) and 4
When the corresponding bit of A23E to A16E is
set to 1, setting a PADDR bit to 1 makes the
corresponding port A pin an address output,
while clearing the bit to 0 makes the pin an input
port. Clearing one of bits A23E to A16E to 0
makes the corresponding port A pin an I/O port,
and its function can be switched with PADDR.
•
Mode 7 (when EXPE = 0)
Port A is an I/O port, and its pin functions can be
switched with PADDR.
Rev.7.00 Mar. 18, 2009 page 507 of 1136
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Section 10 I/O Ports
10.9.2
Port A Data Register (PADR)
PADR stores output data for the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7DR
0
R/W
6
PA6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PA5DR
0
R/W
4
PA4DR
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
10.9.3
Port A Register (PORTA)
PORTA shows port A pin states.
PORTA cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7
⎯*
R
6
PA6
⎯*
R
5
PA5
⎯*
R
If a port A read is performed while PADDR bits are
set to 1, the PADR values are read. If a port A read
is performed while PADDR bits are cleared to 0, the
pin states are read.
4
PA4
⎯*
R
3
PA3
⎯*
R
2
PA2
⎯*
R
1
PA1
⎯*
R
0
PA0
⎯*
R
Note:
*
Determined by the states of pins PA7 to PA0.
Rev.7.00 Mar. 18, 2009 page 508 of 1136
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Section 10 I/O Ports
10.9.4
Port A Pull-Up MOS Control Register (PAPCR)
PAPCR controls the input pull-up MOS function. Bits 7 to 5 are valid in modes 1 and 2 and all the
bits are valid in modes 4 and 7.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7PCR
0
R/W
6
PA6PCR
0
R/W
When PADDR = 0 (input port), setting the
corresponding bit to 1 turns on the input pull-up
MOS for that pin.
5
PA5PCR
0
R/W
4
PA4PCR
0
R/W
3
PA3PCR
0
R/W
2
PA2PCR
0
R/W
1
PA1PCR
0
R/W
0
PA0PCR
0
R/W
10.9.5
Port A Open Drain Control Register (PAODR)
PAODR specifies an output type of port A.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7ODR
0
R/W
6
PA6ODR
0
R/W
5
PA5ODR
0
R/W
When not specified for address output, setting the
corresponding bit to 1 specifies a pin output type to
NMOS open-drain output, while clearing this bit to 0
specifies that to CMOS output.
4
PA4ODR
0
R/W
3
PA3ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
0
PA0ODR
0
R/W
10.9.6
Port Function Control Register 1 (PFCR1)
PFCR1 performs I/O port control. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid
in modes 4 and 7.
Rev.7.00 Mar. 18, 2009 page 509 of 1136
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Section 10 I/O Ports
Bit
Bit Name
Initial Value
R/W
Description
7
A23E
1
R/W
Address 23 Enable
Enables or disables output for address output 23 (A23).
0: DR output when PA7DDR = 1
1: A23 output when PA7DDR = 1
6
A22E
1
R/W
Address 22 Enable
Enables or disables output for address output 22 (A22).
0: DR output when PA6DDR = 1
1: A22 output when PA6DDR = 1
5
A21E
1
R/W
Address 21 Enable
Enables or disables output for address output 21 (A21).
0: DR output when PA5DDR = 1
1: A21 output when PA5DDR = 1
4
A20E
1
R/W
Address 20 Enable
Enables or disables output for address output 20 (A20).
0: DR output when PA4DDR = 1
1: A20 output when PA4DDR = 1
3
A19E
1
R/W
Address 19 Enable
Enables or disables output for address output 19 (A19).
0: DR output when PA3DDR = 1
1: A19 output when PA3DDR = 1
2
A18E
1
R/W
Address 18 Enable
Enables or disables output for address output 18 (A18).
0: DR output when PA2DDR = 1
1: A18 output when PA2DDR = 1
1
A17E
1
R/W
Address 17 Enable
Enables or disables output for address output 17 (A17).
0: DR output when PA1DDR = 1
1: A17 output when PA1DDR = 1
0
A16E
1
R/W
Address 16 Enable
Enables or disables output for address output 16 (A16).
0: DR output when PA0DDR = 1
1: A16 output when PA0DDR = 1
Rev.7.00 Mar. 18, 2009 page 510 of 1136
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Section 10 I/O Ports
10.9.7
Pin Functions
Port A pins also function as the pins for address outputs and interrupt inputs. The correspondence
between the register specification and the pin functions is shown below.
• PA7/A23/IRQ7, PA6/A22/IRQ6, PA5/A21/IRQ5
The pin function is switched as shown below according to the operating mode, bit EXPE, bits
A23E to A21E, bits ITS7 to ITS5 in ITSR, and bit PADDR.
Operating
mode
1, 2, 4
7
⎯
EXPE
AxxE
0
0
1
⎯
1
0
1
PAnDDR
0
1
0
1
0
1
0
1
0
1
Pin
function
PAn
input
PAn
output
PAn
input
Address
output
PAn
input
PAn
output
PAn
input
PAn
output
PAn
input
Address
output
IRQn interrupt input*
xx = 23 to 21, n = 7 to 5
Note: * IRQn input when ITSn = 0.
• PA4/A20/IRQ4
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
A20E and bit PA4DDR.
Operating
mode
1, 2
4
EXPE
⎯
⎯
A20E
⎯
7
0
0
1
⎯
1
0
1
PA4DDR
⎯
0
1
0
1
0
1
0
1
0
1
Pin
function
Address
output
PA4
input
PA4
output
PA4
input
Address
output
PA4
input
PA4
output
PA4
input
PA4
output
PA4
input
Address
output
IRQ4 interrupt input*
Note:
*
IRQ4 input when ITS4 = 0.
Rev.7.00 Mar. 18, 2009 page 511 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• PA3/A19, PA2/A18, PA1/A17, PA20/A16
The pin function is switched as shown below according to the operating mode, bit EXPE, bits
A19E to A16E, and bit PADDR.
Operating
mode
1, 2
EXPE
⎯
AxxE
⎯
4
7
⎯
0
0
1
⎯
1
0
1
PAnDDR
⎯
0
1
0
1
0
1
0
1
0
1
Pin
function
Address
output
PAn
input
PAn
output
PAn
input
Address
output
PAn
input
PAn
output
PAn
input
PAn
output
PAn
input
Address
output
xx = 19 to 16, n = 3 to 0
10.9.8
Port A Input Pull-Up MOS States
Port A has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used by pins PA7 to PA5 in modes 1, 2, 5, and 6, and by all pins in
modes 4, and 7. input pull-up MOS can be specified as on or off on a bit-by-bit basis.
Table 10.2 summarizes the Input Pull-Up MOS states.
Table 10.2 Input Pull-Up MOS States (Port A)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Off
Off
On/Off
On/Off
4, 7
PA7 to PA0
1, 2
PA7 to PA5
On/Off
On/Off
PA4 to PA0
Off
Off
Legend:
Off:
Input pull-up MOS is always off.
On/Off: On when PADDR = 0 and PAPCR = 1; otherwise off.
Rev.7.00 Mar. 18, 2009 page 512 of 1136
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Section 10 I/O Ports
10.10
Port B
Port B is an 8-bit I/O port that also has other functions. The port B has the following registers.
• Port B data direction register (PBDDR)
• Port B data register (PBDR)
• Port B register (PORTB)
• Port B pull-up MOS control register (PBPCR)
10.10.1 Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B.
PBDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7DDR
0
W
•
6
PB6DDR
0
W
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
0
PB0DDR
0
W
Modes 1 and 2
Port B pins are address outputs regardless of the
PBDDR settings.
•
Modes 7 (when EXPE = 1) and 4
Setting a PBDDR bit to 1 makes the
corresponding port B pin an address output,
while clearing the bit to 0 makes the pin an input
port.
•
Modes 7 (when EXPE = 0)
Port B is an I/O port, and its pin functions can be
switched with PBDDR.
Rev.7.00 Mar. 18, 2009 page 513 of 1136
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Section 10 I/O Ports
10.10.2 Port B Data Register (PBDR)
PBDR is stores output data for the port B pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7DR
0
R/W
6
PB6DR
0
R/W
An output data for a pin is stored when the pin
function is specified to a general purpose I/O.
5
PB5DR
0
R/W
4
PB4DR
0
R/W
3
PB3DR
0
R/W
2
PB2DR
0
R/W
1
PB1DR
0
R/W
0
PB0DR
0
R/W
10.10.3 Port B Register (PORTB)
PORTB shows port B pin states. PORTB cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7
⎯*
R
6
PB6
⎯*
R
5
PB5
⎯*
R
If this register is read is while PBDDR bits are set to
1, the PBDR values are read. If a port B read is
performed while PBDDR bits are cleared to 0, the
pin states are read.
4
PB4
⎯*
R
3
PB3
⎯*
R
2
PB2
⎯*
R
1
PB1
⎯*
R
0
PB0
⎯*
R
Note:
*
Determined by the states of pins PB7 to PB0.
Rev.7.00 Mar. 18, 2009 page 514 of 1136
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Section 10 I/O Ports
10.10.4 Port B Pull-Up MOS Control Register (PBPCR)
PBPCR controls the on/off state of input pull-up MOS of port B. PBPCR is valid in modes 4 and
7.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7PCR
0
R/W
6
PB6PCR
0
R/W
When PBDDR = 0 (input port), setting the
corresponding bit to 1 turns on the input pull-up
MOS for that pin.
5
PB5PCR
0
R/W
4
PB4PCR
0
R/W
3
PB3PCR
0
R/W
2
PB2PCR
0
R/W
1
PB1PCR
0
R/W
0
PB0PCR
0
R/W
10.10.5 Pin Functions
Port B pins also function as the pins for address outputs. The correspondence between the register
specification and the pin functions is shown below.
• PB7/A15, PB6/A14, PB5/A13, PB4/A12, PB3/A11, PB2/A10, PB1/A9, PB0/A8
The pin function is switched as shown below according to the operating mode, bit EXPE, and
bit PBDDR.
Operating
mode
1, 2
4
EXPE
⎯
⎯
PBnDDR
⎯
0
1
0
1
0
1
Address
output
PBn
input
Address
output
PBn
input
PBn
output
PBn
input
Address
output
Pin function
7
0
1
Legend: n = 7 to 0
Rev.7.00 Mar. 18, 2009 page 515 of 1136
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Section 10 I/O Ports
10.10.6 Port B Input Pull-Up MOS States
Port B has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in modes 4 and 7. Input pull-up MOS can be specified as on or
off on a bit-by-bit basis.
In modes 4 and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1
turns on the input pull-up MOS for that pin.
Table 10.3 summarizes the input pull-up MOS states.
Table 10.3 Input Pull-Up MOS States (Port B)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2
Off
Off
Off
Off
On/Off
On/Off
4, 7
Legend:
Off:
Input pull-up MOS is always off.
On/Off: On when PBDDR = 0 and PBPCR = 1; otherwise off.
Rev.7.00 Mar. 18, 2009 page 516 of 1136
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Section 10 I/O Ports
10.11
Port C
Port C is an 8-bit I/O port that also has other functions. The port C has the following registers.
• Port C data direction register (PCDDR)
• Port C data register (PCDR)
• Port C register (PORTC)
• Port C pull-up MOS control register (PCPCR)
10.11.1 Port C Data Direction Register (PCDDR)
The individual bits of PCDDR specify input or output for the pins of port C.
PCDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DDR
0
W
•
6
PC6DDR
0
W
5
PC5DDR
0
W
4
PC4DDR
0
W
3
PC3DDR
0
W
2
PC2DDR
0
W
1
PC1DDR
0
W
0
PC0DDR
0
W
Modes 1 and 2
Port C pins are address outputs regardless of the
PCDDR settings.
•
Modes 7 (when EXPE = 1)and 4
Setting a PCDDR bit to 1 makes the
corresponding port C pin an address output,
while clearing the bit to 0 makes the pin an input
port.
•
Mode 7 (when EXPE = 0)
Port C is an I/O port, and its pin functions can be
switched with PCDDR.
Rev.7.00 Mar. 18, 2009 page 517 of 1136
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Section 10 I/O Ports
10.11.2 Port C Data Register (PCDR)
PCDR stores output data for the port C pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DR
0
R/W
6
PC6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PC5DR
0
R/W
4
PC4DR
0
R/W
3
PC3DR
0
R/W
2
PC2DR
0
R/W
1
PC1DR
0
R/W
0
PC0DR
0
R/W
10.11.3 Port C Register (PORTC)
PORTC is shows port C pin states.
PORTC cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7
⎯*
R
6
PC6
⎯*
R
5
PC5
⎯*
R
If a port C read is performed while PCDDR bits are
set to 1, the PCDR values are read. If a port C read
is performed while PCDDR bits are cleared to 0, the
pin states are read.
4
PC4
⎯*
R
3
PC3
⎯*
R
2
PC2
⎯*
R
1
PC1
⎯*
R
0
PC0
⎯*
R
Note:
*
Determined by the states of pins PC7 to PC0.
Rev.7.00 Mar. 18, 2009 page 518 of 1136
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Section 10 I/O Ports
10.11.4 Port C Pull-Up MOS Control Register (PCPCR)
PCPCR controls the on/off state of input pull-up MOS of port C. PCPCR is valid in modes 4 and
7.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7PCR
0
R/W
6
PC6PCR
0
R/W
When PCDDR = 0 (input port), setting the
corresponding bit to 1 turns on the input pull-up
MOS for that pin.
5
PC5PCR
0
R/W
4
PC4PCR
0
R/W
3
PC3PCR
0
R/W
2
PC2PCR
0
R/W
1
PC1PCR
0
R/W
0
PC0PCR
0
R/W
10.11.5 Pin Functions
Port C pins also function as the pins for address outputs. The correspondence between the register
specification and the pin functions is shown below.
• PC7/A7, PC6/A6, PC5/A5, PC4/A4, PC3/A3, PC2/A2, PC1/A1, PC0/A0
The pin function is switched as shown below according to the operating mode, bit EXPE, and
bit PCDDR.
Operating
mode
1, 2
4
EXPE
⎯
⎯
PCnDDR
⎯
0
1
0
1
0
1
Address
output
PCn
input
Address
output
PCn
input
PCn
output
PCn
input
Address
output
Pin function
7
0
1
Rev.7.00 Mar. 18, 2009 page 519 of 1136
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Section 10 I/O Ports
10.11.6 Port C Input Pull-Up MOS States
Port C has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in modes 4 and 7. Input pull-up MOS can be specified as on or
off on a bit-by-bit basis.
In modes 4 and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1
turns on the input pull-up MOS for that pin.
Table 10.4 summarizes the input pull-up MOS states.
Table 10.4 Input Pull-Up MOS States (Port C)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2
Off
Off
Off
Off
On/Off
On/Off
4, 7
Legend:
Off:
Input pull-up MOS is always off.
On/Off: On when PCDDR = 0 and PCPCR = 1; otherwise off.
Rev.7.00 Mar. 18, 2009 page 520 of 1136
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Section 10 I/O Ports
10.12
Port D
Port D is an 8-bit I/O port that also has other functions. The port D has the following registers.
• Port D data direction register (PDDDR)
• Port D data register (PDDR)
• Port D register (PORTD)
• Port D pull-up MOS control register (PDPCR)
10.12.1 Port D Data Direction Register (PDDDR)
The individual bits of PDDDR specify input or output for the pins of port D.
PDDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DDR
0
W
•
6
PD6DDR
0
W
5
PD5DDR
0
W
4
PD4DDR
0
W
3
PD3DDR
0
W
2
PD2DDR
0
W
1
PD1DDR
0
W
0
PD0DDR
0
W
Modes 7 (when EXPE = 1), 1, 2, and 4
Port D is automatically designated for data
input/output.
•
Mode 7 (when EXPE = 0)
Port D is an I/O port, and its pin functions can be
switched with PDDDR.
Rev.7.00 Mar. 18, 2009 page 521 of 1136
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Section 10 I/O Ports
10.12.2 Port D Data Register (PDDR)
PDDR stores output data for the port D pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DR
0
R/W
6
PD6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
10.12.3 Port D Register (PORTD)
PORTD shows port D pin states.
PORTD cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7
⎯*
R
6
PD6
⎯*
R
5
PD5
⎯*
R
If a port D read is performed while PDDDR bits are
set to 1, the PDDR values are read. If a port D read
is performed while PDDDR bits are cleared to 0, the
pin states are read.
4
PD4
⎯*
R
3
PD3
⎯*
R
2
PD2
⎯*
R
1
PD1
⎯*
R
0
PD0
⎯*
R
Note:
*
Determined by the states of pins PD7 to PD0.
Rev.7.00 Mar. 18, 2009 page 522 of 1136
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Section 10 I/O Ports
10.12.4 Port D Pull-up Control Register (PDPCR)
PDPCR controls on/off states of the input pull-up MOS of port D. PDPCR is valid in mode 7.
Bit
Bit Name
Initial Value
R/W
7
PD7PCR
0
R/W
6
PD6PCR
0
R/W
5
PD5PCR
0
R/W
4
PD4PCR
0
R/W
3
PD3PCR
0
R/W
2
PD2PCR
0
R/W
1
PD1PCR
0
R/W
0
PD0PCR
0
R/W
Description
When PDDDR = 0 (input port), the input pull-up
MOS of the input pin is on when the corresponding
bit is set to 1.
10.12.5 Pin Functions
Port D pins also function as the pins for data I/Os. The correspondence between the register
specification and the pin functions is shown below.
• PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8
The pin function is switched as shown below according to the operating mode, bit EXPE, and
bit PDDDR.
Operating
mode
EXPE
PDnDDR
Pin function
1, 2, 4
7
⎯
0
1
⎯
0
1
⎯
Data I/O
PDn input
PDn output
Data I/O
Legend: n = 7 to 0
Rev.7.00 Mar. 18, 2009 page 523 of 1136
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Section 10 I/O Ports
10.12.6 Port D Input Pull-Up MOS States
Port D has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in mode 7. Input pull-up MOS can be specified as on or off on
a bit-by-bit basis.
In mode 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on
the input pull-up MOS for that pin.
Table 10.5 summarizes the input pull-up MOS states.
Table 10.5 Input Pull-Up MOS States (Port D)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2, 4
Off
Off
Off
Off
On/Off
On/Off
7
Legend:
OFF: Input pull-up MOS is always off.
On/Off: On when PDDDR = 0 and PDPCR = 1; otherwise off.
Rev.7.00 Mar. 18, 2009 page 524 of 1136
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Section 10 I/O Ports
10.13
Port E
Port E is an 8-bit I/O port that also has other functions. The port E has the following registers.
• Port E data direction register (PEDDR)
• Port E data register (PEDR)
• Port E register (PORTE)
• Port E pull-up MOS control register (PEPCR)
10.13.1 Port E Data Direction Register (PEDDR)
The individual bits of PEDDR specify input or output for the pins of port E.
PEDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DDR
0
W
•
6
PE6DDR
0
W
5
PE5DDR
0
W
4
PE4DDR
0
W
3
PE3DDR
0
W
2
PE2DDR
0
W
1
PE1DDR
0
W
0
PE0DDR
0
W
Modes 1, 2, and 4
When 8-bit bus mode is selected, port E
functions as an I/O port. The pin states can be
changed with PEDDR.
When 16-bit bus mode is selected, port E is
designated for data input/output.
For details on 8-bit and 16-bit bus modes, see
section 6, Bus Controller (BSC).
•
Mode 7 (when EXPE = 1)
When 8-bit bus mode is selected, port E
functions as an I/O port. Setting a PEDDR bit to 1
makes the corresponding port E pin an output
port, while clearing the bit to 0 makes the pin an
input port.
When 16-bit bus mode is selected, port E is
designated for data input/output.
•
Mode 7 (when EXPE = 0)
Port E is an I/O port, and its pin functions can be
switched with PEDDR.
Rev.7.00 Mar. 18, 2009 page 525 of 1136
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Section 10 I/O Ports
10.13.2 Port E Data Register (PEDR)
PEDR stores output data for the port E pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DR
0
R/W
6
PE6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PE5DR
0
R/W
4
PE4DR
0
R/W
3
PE3DR
0
R/W
2
PE2DR
0
R/W
1
PE1DR
0
R/W
0
PE0DR
0
R/W
10.13.3 Port E Register (PORTE)
PORTE shows port E pin states.
PORTE cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7
⎯*
R
6
PE6
⎯*
R
5
PE5
⎯*
R
If a port E read is performed while PEDDR bits are
set to 1, the PEDR values are read. If a port E read
is performed while PEDDR bits are cleared to 0, the
pin states are read.
4
PE4
⎯*
R
3
PE3
⎯*
R
2
PE2
⎯*
R
1
PE1
⎯*
R
0
PE0
⎯*
R
Note:
*
Determined by the states of pins PE7 to PE0.
Rev.7.00 Mar. 18, 2009 page 526 of 1136
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Section 10 I/O Ports
10.13.4 Port E Pull-up Control Register (PEPCR)
PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus
mode.
Bit
Bit Name
Initial Value
R/W
7
PE7PCR
0
R/W
6
PE6PCR
0
R/W
5
PE5PCR
0
R/W
4
PE4PCR
0
R/W
3
PE3PCR
0
R/W
2
PE2PCR
0
R/W
1
PE1PCR
0
R/W
0
PE0PCR
0
R/W
Description
When PEDDR = 0 (input port), the input pull-up
MOS of the input pin is on when the corresponding
bit is set to 1.
10.13.5 Pin Functions
Port E pins also function as the pins for data I/Os. The correspondence between the register
specification and the pin functions is shown below.
• PE7/D7, PE6/D6, PE5/D5, PE4/D4, PE3/D3, PE2/D2, PE1/D1, PE0/D0
The pin function is switched as shown below according to the operating mode, bus mode, bit
EXPE, and bit PEDDR.
Operating
mode
Bus mode
1, 2, 4
All areas
8-bit space
At least one
area 16-bit
space
⎯
All areas
8-bit space
At least one area
16-bit space
⎯
⎯
0
1
1
EXPE
PEnDDR
Pin function
7
0
1
⎯
0
1
0
1
⎯
PEn
input
PEn
output
Data I/O
PEn
input
PEn
output
PEn
input
PEn
output
Data I/O
Legend: n = 7 to 0
Rev.7.00 Mar. 18, 2009 page 527 of 1136
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Section 10 I/O Ports
10.13.6 Port E Input Pull-Up MOS States
Port E has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in 8-bit bus mode. Input pull-up MOS can be specified as on or
off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the
corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin.
Table 10.6 summarizes the input pull-up MOS states.
Table 10.6 Input Pull-Up MOS States (Port E)
Mode
1, 2, 4
8-bit bus
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Off
Off
On/Off
On/Off
Off
Off
16-bit bus
Legend:
Off:
Input pull-up MOS is always off.
On/Off: On when PEDDR = 0 and PEPCR = 1; otherwise off.
10.14
Port F
Port F is an 8-bit I/O port that also has other functions. The port F has the following registers. For
details on the port function control register 2, refer to section 10.3.5, Port Function Control
Register 2 (PFCR2).
• Port F data direction register (PFDDR)
• Port F data register (PFDR)
• Port F register (PORTF)
• Port Function Control Register 2 (PFCR2)
Rev.7.00 Mar. 18, 2009 page 528 of 1136
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Section 10 I/O Ports
10.14.1 Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the pins of port F.
PFDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7DDR
1/0*
W
•
6
PF6DDR
0
W
5
PF5DDR
0
W
4
PF4DDR
0
W
3
PF3DDR
0
W
2
PF2DDR
0
W
1
PF1DDR
0
W
0
PF0DDR
0
W
Modes 7 (when EXPE = 1), 1, 2, and 4
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pin PF6 functions as the AS output pin when
ASOE is set to 1. When ASOE is cleared to 0, pin
PF6 is an I/O port and its function can be
switched with PF6DDR.
Pins PF5 and PF4 are automatically designated
as bus control outputs (RD and HWR).
Pin PF3 functions as the LWR output pin when
LWROE is set to 1. When LWROE is cleared to
0, pin PF3 is an I/O port and its function can be
switched with PF3DDR.
Pins PF2 to PF0 function as bus control
input/output pins (LCAS, UCAS, and WAIT) when
the appropriate bus controller settings are made.
Otherwise, these pins are output ports when
PFDDR is set to 1 and are input ports when
PFDDR is cleared to 0.
•
Mode 7 (when EXPE = 0)
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pins PF6 to PF0 are I/O ports, and their functions
can be switched with PFDDR.
Note:
*
PF7DDR is initialized to 1 in modes 1, 2, and 4, and to 0 in mode 7.
Rev.7.00 Mar. 18, 2009 page 529 of 1136
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Section 10 I/O Ports
10.14.2 Port F Data Register (PFDR)
PFDR stores output data for the port F pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7DR
0
R/W
6
PF6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1
PF1DR
0
R/W
0
PF0DR
0
R/W
10.14.3 Port F Register (PORTF)
PORTF shows port F pin states.
PORTF cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7
⎯*
R
6
PF6
⎯*
R
5
PF5
⎯*
R
If a port F read is performed while PFDDR bits are
set to 1, the PFDR values are read. If a port F read
is performed while PFDDR bits are cleared to 0, the
pin states are read.
4
PF4
⎯*
R
3
PF3
⎯*
R
2
PF2
⎯*
R
1
PF1
⎯*
R
0
PF0
⎯*
R
Note:
*
Determined by the states of pins PF7 to PF0.
Rev.7.00 Mar. 18, 2009 page 530 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.14.4 Pin Functions
Port F pins also function as the pins for external interrupt inputs, bus control signal I/Os, and
system clock outputs (φ). The correspondence between the register specification and the pin
functions is shown below.
• PF7/φ
The pin function is switched as shown below according to bit PF7DDR.
Operating
mode
1, 2, 4, 7
PF7DDR
Pin function
0
1
PF7 input
φ output
• PF6/AS
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
ASOE, and bit PF6DDR.
Operating
mode
1, 2, 4
7
⎯
EXPE
ASOE
1
PF6DDR
⎯
0
⎯
0
0
Pin function AS output PF6 input
1
1
1
0
1
PF6
output
PF6 input
PF6
output
⎯
0
0
1
AS output PF6 input
PF6
output
• PF5/RD
The pin function is switched as shown below according to the operating mode, bit EXPE, and
bit PF5DDR.
Operating
mode
1, 2, 4
7
EXPE
⎯
PF5DDR
⎯
0
1
⎯
RD output
PF5 input
PF5 output
RD output
Pin function
0
1
Rev.7.00 Mar. 18, 2009 page 531 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• PF4/HWR
The pin function is switched as shown below according to the operating mode, bit EXPE, and
bit PF4DDR.
Operating
mode
1, 2, 4
7
EXPE
⎯
PF4DDR
⎯
0
1
⎯
HWR output
PF4 input
PF4 output
HWR output
Pin function
0
1
• PF3/LWR
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
LWROE, and bit PF3DDR.
Operating
mode
1, 2, 4
⎯
EXPE
LWROD
1
PF3DDR
⎯
0
LWR
output
PF3
input
Pin function
7
0
1
⎯
0
1
0
PF3 PF3 input
output
Rev.7.00 Mar. 18, 2009 page 532 of 1136
REJ09B0109-0700
1
1
PF3
output
⎯
0
0
1
LWR output PF3 input PF3 output
Section 10 I/O Ports
• PF2/LCAS/IRQ15/DQML*2
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, bits ABW5 to ABW2 in ABWCR, and
bit PF2DDR.
Operating
mode
⎯
EXPE
Areas
2 to 5
PF2DDR
Pin function
2
3* , 7
1, 2, 4
Any
DRAM /
synchronous
2
DRAM*
space
area is
16-bit bus
space
⎯
0
⎯
All DRAM/
synchronous
2
DRAM* space
areas are 8-bit bus
space, or areas 2 to
5 are all normal
space
0
LCAS/ PF2 input
2
DQML*
output
1
Any
DRAM/
synchronous
2
DRAM*
space
area is
16-bit bus
space
1
0
1
PF2
output
PF2 input
PF2
output
⎯
All DRAM/
synchronous
2
DRAM* space
areas are 8-bit bus
space, or areas 2 to
5 are all normal
space
0
LCAS/ PF2 input
2
DQML *
output
1
PF2
output
IRQ15 interrupt input*
1
Notes: 1. IRQ15 interrupt input when bit ITS15 is cleared to 0 in ITSR.
2. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
Rev.7.00 Mar. 18, 2009 page 533 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• PF1/UCAS/IRQ14/DQMU*2
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR.
Operating
mode
1, 2, 4
7
EXPE
⎯
0
1
Areas
2 to 5
Any of
Areas 2 to 5 are all
areas 2 normal space
to 5 is
DRAM/
synchronous
2
DRAM*
space
⎯
Any of
Areas 2 to 5 are all
areas 2 normal space
to 5 is
DRAM/
synchronous
2
DRAM*
space
⎯
PF1DDR
Pin function
0
UCAS/ PF1 input
2
(DQMU)*
output
⎯
1
0
1
PF1
output
PF1 input
PF1
output
0
UCAS/ PF1 input
2
(DQMU)*
output
1
PF1
output
IRQ14 interrupt*
1
Notes: 1. IRQ14 interrupt input when bit ITS14 in ITSR is cleared to 0.
2. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
• PF0/WAIT
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
WAITE in BCR, and bit PF0DDR.
Operating
mode
1, 2, 4
⎯
EXPE
WAITE
PF0DDR
7
0
0
Pin function PF0 input
0
1
⎯
1
0
1
⎯
0
1
PF0
output
WAIT
input
PF0
input
PF0
output
Rev.7.00 Mar. 18, 2009 page 534 of 1136
REJ09B0109-0700
0
1
1
⎯
PF0 input PF0 output WAIT input
Section 10 I/O Ports
10.15
Port G
Port G is a 7-bit I/O port that also has other functions. The port G has the following registers.
• Port G data direction register (PGDDR)
• Port G data register (PGDR)
• Port G register (PORTG)
• Port Function Control Register 0 (PFCR0)
10.15.1 Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G.
PGDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
0
⎯
Reserved
6
PG6DDR
0
W
•
5
PG5DDR
0
W
4
PG4DDR
0
W
3
PG3DDR
0
W
2
PG2DDR
0
W
1
PG1DDR
0
W
0
PG0DDR
1/0*
W
Modes 7 (when EXPE = 1), 1, 2, and 4
Pins PG6 to PG4 function as bus control
input/output pins (BREQO, BACK, and BREQ)
when the appropriate bus controller settings are
made. Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS output
pins when the corresponding PGDDR bit is set to 1,
and as input ports when the bit is cleared to 0.
When CS3E to CS0E are cleared to 0, pins PG3 to
PG0 are I/O ports, and their functions can be
switched with PGDDR.
•
Mode 7 (when EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Note:
*
PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 4 and 7.
Rev.7.00 Mar. 18, 2009 page 535 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.15.2 Port G Data Register (PGDR)
PGDR stores output data for the port G pins.
Bit
Bit Name
Initial Value
R/W
7
⎯
0
⎯
Description
Reserved
This bit is always read as 0, and cannot be modified.
6
PG6DR
0
R/W
5
PG5DR
0
R/W
4
PG4DR
0
R/W
3
PG3DR
0
R/W
2
PG2DR
0
R/W
1
PG1DR
0
R/W
0
PG0DR
0
R/W
An output data for a pin is stored when the pin
function is specified to a general purpose I/O.
10.15.3 Port G Register (PORTG)
PORTG shows port G pin states.
PORTG cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
Undefined
⎯
Reserved
If this bit is read, it will return an undefined value.
6
PG6
⎯*
R
5
PG5
⎯*
R
4
PG4
⎯*
R
3
PG3
⎯*
R
2
PG2
⎯*
R
1
PG1
⎯*
R
0
PG0
⎯*
R
Note:
*
If a port G read is performed while PGDDR bits are
set to 1, the PGDR values are read. If a port G read
is performed while PGDDR bits are cleared to 0, the
pin states are read.
Determined by the states of pins PG6 to PG0.
Rev.7.00 Mar. 18, 2009 page 536 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.15.4 Port Function Control Register 0 (PFCR0)
PFCR0 performs I/O port control.
Bit
Bit Name
Initial Value
R/W
Description
7
CS7E
1
R/W
CS7 to CS0 Enable
6
CS6E
1
R/W
5
CS5E
1
R/W
These bits enable or disable the corresponding CSn
output.
4
CS4E
1
R/W
3
CS3E
1
R/W
2
CS2E
1
R/W
1
CS1E
1
R/W
0
CS0E
1
R/W
0: Pin is designated as I/O port
1: Pin is designated as CSn output pin
(n = 7 to 0)
10.15.5 Pin Functions
Port G pins also function as the pins for bus control signal I/Os. The correspondence between the
register specification and the pin functions is shown below.
Note: Only modes 1 and 2 are supported on ROM-less versions.
• PG6/BREQ
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
BRLE, and bit PG6DDR.
Operating
mode
1, 2, 4
⎯
EXPE
BRLE
PG6DDR
Pin
function
7
0
0
1
⎯
1
0
1
0
1
⎯
0
1
0
1
⎯
PG6
input
PG6
output
BREQ
input
PG6 input
PG6
output
PG6
input
PG6
output
BREQ input
Rev.7.00 Mar. 18, 2009 page 537 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• PG5/BACK
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
BRLE, and bit PG5DDR.
Operating
mode
1, 2, 4
7
⎯
EXPE
BRLE
0
0
0
1
⎯
0
PG5 input
PG5
output
BACK
output
PG5
input
PG5DDR
Pin
function
1
⎯
1
0
1
0
PG5 PG5 input
output
1
1
⎯
PG5
output
BACK output
• PG4/BREQO
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
BRLE, bit BREQO, and bit PG4DDR.
Operating
mode
⎯
EXPE
BRLE
0
BREQO
⎯
PG4DDR
Pin
function
7
1, 2, 4
0
0
1
0
1
0
1
1
⎯
PG4 PG4 PG4 PG4 BREQO
input output input output output
1
⎯
0
⎯
⎯
0
1
0
PG4
input
PG4
output
PG4
input
Rev.7.00 Mar. 18, 2009 page 538 of 1136
REJ09B0109-0700
1
0
1
0
PG4 PG4 input
output
1
1
⎯
PG4
output
BREQO output
Section 10 I/O Ports
• PG3/CS3/RAS3/CAS*
The pin function is switched as shown below according to the operating mode, bit PG3DDR,
bit CS3E, and bits RMTS2 to RMTS0.
Operating
mode
1, 2, 4
7
⎯
EXPE
CS3E
0
RMTS2 to
⎯
0
1
Area 3 is in
RMTS0
Area 3 is in
normal space DRAM space
PG3DDR
0
1
Pin function PG3
PG3
0
PG3
⎯
RAS3 output
CAS* output
input output input output
Note:
*
0
⎯
⎯
1
Area 3 is in
are in
synchronous
DRAM* space
⎯
1
CS3
Areas 2 to 5
1
⎯
Area 3 is in
normal space DRAM space
0
1
PG3
PG3
0
1
PG3
PG3
0
1
CS3
PG3
Areas 2 to 5
are in
synchronous
DRAM* space
⎯
⎯
RAS3 output
CAS* output
input output input output input output
Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
• PG2/CS2/RAS2/RAS
The pin function is switched as shown below according to the operating mode, bit PG2DDR,
bit CS2E, and bits RMTS2 to RMTS0.
Operating
1, 2, 4
7
mode
⎯
EXPE
CS2E
0
RMTS2 to
⎯
1
Area 2 is in
RMTS0
Area 2 is in
normal space DRAM space
PG2DDR
0
Pin function PG2
*
Areas 2 to 5
1
⎯
0
⎯
⎯
1
Area 2 is in
are in
synchronous
DRAM* space
Area 2 is in
normal space DRAM space
Areas 2 to 5
are in
synchronous
DRAM* space
1
0
1
⎯
⎯
0
1
0
1
0
1
⎯
⎯
PG2
PG2
CS2
RAS2 output
RAS* output
PG2
PG2
PG2
PG2
PG2
CS2
RAS2 output
RAS* output
input output input output
Note:
0
input output input output input output
Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
Rev.7.00 Mar. 18, 2009 page 539 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• PG1/CS1, PG0/CS0
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
CSnE, and bit PGnDDR.
Operating
mode
1, 2, 4
7
⎯
EXPE
CSnE
0
0
PGnDDR
Pin function
1
⎯
1
0
1
0
1
0
1
0
1
0
1
0
1
PG2
input
PG2
output
PG2
input
CSn
output
PG2
input
PG2
output
PG2
input
PG2
output
PG2
input
CSn
output
(n =1 or 0)
10.16
Port H
Port H is a 4-bit I/O port that also has other functions. The port H has the following registers. For
details on the port function control register 0, refer to section 10.15.4, Port Function Control
Register 0 (PFCR0), and for details on the port function control register 2, refer to section 10.3.5,
Port Function Control Register 2 (PFCR2).
• Port H data direction register (PHDDR)
• Port H data register (PHDR)
• Port H register (PORTH)
• Port Function Control Register 0 (PFCR0)
• Port Function Control Register 2 (PFCR2)
10.16.1 Port H Data Direction Register (PHDDR)
The individual bits of PHDDR specify input or output for the pins of port H.
PHDDR cannot be read; if it is, an undefined value will be read.
Rev.7.00 Mar. 18, 2009 page 540 of 1136
REJ09B0109-0700
Section 10 I/O Ports
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
—
All 0
—
Reserved
3
PH3DDR
0
W
• Modes 1*3, 2*3, 4 and 7 (when EXPE = 1)
2
PH2DDR
0
W
1
PH1DDR
0
W
0
PH0DDR
0
W
When the OE output enable bit (OEE) and OE output select bit (OES) are
set to 1, pin PH3 functions as the OE output pin. Otherwise, when bit
CS7E is set to 1, pin PH3 functions as a CS output pin when the
corresponding PH3DDR bit is set to 1, and as an input port when the bit is
cleared to 0. When bit CS7E is cleared to 0, pin PH3 is an I/O port, and its
function can be switched with PH3DDR. When areas 2 to 5 are specified
1
as continuous synchronous DRAM space* , OE output is CKE output.
When bit CS6E is set to 1, setting bit PH2DDR makes pin PH2 function as
the CS6 output pin and as an I/O port when the bit is cleared to 0. When
bit CS6E is cleared to 0, pin PH2 is an I/O port, and its function can be
switched with PH2DDR.
1
Pin PH1 functions as the SDRAMφ* output pin when the input level of the
2
*
DCTL pin is high. Pin PH1 functions as the CS5 output pin when the
input level of the DCTL pin*2 is low, area 5 is specified as normal space,
and bit PH1DDR is set to 1; if the bit is cleared to 0, pin PH1 functions as
an I/O port. When bit CS5E is cleared to 0, pin PH1 is an I/O port, and its
function can be switched with PH1DDR. When area 5 is specified as
DRAM space and bit CS5E is set to 1, pin PH1 functions as the RAS5
output pin and as an I/O port when the bit is cleared to 0.
Pin PH0 functions as the CS4 output pin when area 4 is specified as
normal space and bit PH0DDR is set to 1; if the bit is cleared to 0, pin
PH0 functions as an I/O port. When bit CS4E is cleared to 0, pin PH0 is
an I/O port, and its function can be switched with PH0DDR. When area 4
is specified as DRAM space and bit CS5E is set to 1, pin PH0 functions
as the RAS4 output pin and as an I/O port when the bit is cleared to 0.
2
When areas 2 to 5 are specified as continuous synchronous DRAM* , pin
PH0 functions as the WE output pin and as an I/O port when the bit is
cleared to 0.
• Mode 7 (when EXPE = 0)
Pins PH3 to PH0 are I/O ports, and their functions can be switched with
PHDDR.
1
Pin PH1 functions as the SDRAMφ* output pin when the input level of the
2
2
*
DCTL pin is high. When the input level of the DCTL pin* is low, pin
PH1 is an I/O port and its function can be switched with PHDDR.
Notes: 1. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and H8S/2373.
2. When synchronous DRAM interface is not used, input a low-level signal on the DCTL pin.
3. Only modes 1 and 2 are supported on ROM-less versions.
Rev.7.00 Mar. 18, 2009 page 541 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.16.2 Port H Data Register (PHDR)
PHDR stores output data for the port H pins.
Bit
Bit Name
Initial Value
R/W
7
to
4
⎯
All 0
⎯
3
PH3DR
0
R/W
2
PH2DR
0
R/W
1
PH1DR
0
R/W
0
PH0DR
0
R/W
Description
Reserved
These bits are reserved; they are always read as 0
and cannot be modified.
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
10.16.3 Port H Register (PORTH)
PORTH shows port H pin states.
PORTH cannot be modified.
Bit
Bit Name
Initial Value
R/W
7
to
4
⎯
Undefined
⎯
3
PH3
⎯*
R
2
PH2
⎯*
R
1
PH1
⎯*
R
0
PH0
⎯*
R
Note:
Description
Reserved
If these bits are read, they will return an undefined
value.
*
If a port H read is performed while PHDDR bits are
set to 1, the PHDR values are read. If a port H read
is performed while PHDDR bits are cleared to 0, the
pin states are read.
Determined by the states of pins PH3 to PH0.
Rev.7.00 Mar. 18, 2009 page 542 of 1136
REJ09B0109-0700
Section 10 I/O Ports
10.16.4 Pin Functions
Port H pins also function as bus control signal I/Os and interrupt inputs. The correspondence
between the register specification and the pin functions is shown below.
Note: Only modes 1 and 2 are supported on ROM-less versions.
• PH3/CS7/OE/CKE*2/(IRQ7)
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
OEE, bit OES, bit CS7E, and bit PH3DDR.
Operating
mode
1, 2, 4
7
⎯
EXPE
0
OEE
0
OES
⎯
0
Area
2 to 5
⎯
⎯
CS7E
0
PH3DDR
Pin
function
0
1
1
0
0
1
0
0
1
⎯
0
Normal
synspace chronous
or
DRAM
DRAM space*2
space
⎯
⎯
1
1
0
1
⎯
1
1
⎯
⎯
⎯
⎯
⎯
0
CKE*2
output
PH3 PH3 PH3 CS7 PH3 PH3 PH3 CS7
OE
input output input output input output input output output
1
1
⎯
0
1
0
1
1
0
Normal
synspace chronous
or
DRAM
DRAM space*2
space
0
1
0
⎯
1
1
0
1
⎯
⎯
⎯
PH3 PH3 PH3 PH3 PH3 CS7 PH3 PH3 PH3 CS7
OE
input output input output input output input output input output output
CKE*2
output
IRQ7 input*1
Notes: 1. IRQ7 interrupt input pin when bit ITS7 is set to 1 in ITSR
2. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
• PH2/CS6/(IRQ6)
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
CS6E, and bit PH2DDR.
Operating
mode
1, 2, 4
7
⎯
EXPE
CS6E
0
0
PH2DDR
Pin function
1
⎯
1
0
1
0
1
0
1
0
1
0
1
0
1
PH2
input
PH2
output
PH2
input
CS6
output
PH2
input
PH2
output
PH2
input
PH2
output
PH2
input
CS6
output
IRQ6 interrupt input*
Note:
*
IRQ6 interrupt input pin when bit ITS6 is set to 1 in ITSR.
Rev.7.00 Mar. 18, 2009 page 543 of 1136
REJ09B0109-0700
Section 10 I/O Ports
• PH1/CS5/RAS5/SDRAMφ*2
The pin function is switched as shown below according to the operating mode, DCTL pin, bit
EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR.
DCTL*1
0
Operating
mode
1
1, 2, 4
⎯
EXPE
Area 5
⎯
7
0
Normal space
⎯
DRAM space
DCTL
⎯
1
Normal space
⎯
DRAM space
0
CS5E
0
PH1DDR
0
Pin function
1
1
0
0
1
0
1
1
⎯
1
⎯
PH1 PH1 PH1 CS5 PH1 PH1 RAS5
input output input output input output output
0
0
1
0
1
1
0
1
⎯
⎯
⎯
0
1
0
1
PH1 PH1 PH1 PH1 PH1 CS5 PH1 PH1 RAS5 SDRAM*2
input output input output input output input output output φ output
Notes: 1. When SDRAM interface is not used, input a low-level signal on the DCTL pin.
2. Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
• PH0/CS4/RAS4/WE*
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
CS4E, bits RMTS2 to RMTS0, and bit PH0DDR.
Operating
mode
1, 2, 4
7
⎯
EXPE
⎯
Area 4
0
Normal space
DRAM
space
1
⎯
Synchronous
DRAM*
⎯
Normal space
DRAM
space
space
CS4E
0
PH0DDR
Pin function
Note:
*
Synchronous
DRAM*
space
⎯
1
0
1
0
1
0
1
⎯
⎯
0
1
0
1
0
1
⎯
⎯
PH0
input
PH0
output
PH0
input
CS4
output
RAS4
output
WE*
output
PH0
input
PH0
output
PH0
input
PH0
output
PH0
input
CS4
output
RAS4
output
WE*
output
Not used in the H8S/2378 0.18μm F-ZTAT Group, H8S/2377, H8S/2375, and
H8S/2373.
Rev.7.00 Mar. 18, 2009 page 544 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Section 11 16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels.
The function list of the 16-bit timer unit and its block diagram are shown in table 11.1 and figure
11.1, respectively.
11.1
Features
• Maximum 16-pulse input/output
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
⎯ Waveform output at compare match
⎯ Input capture function
⎯ Counter clear operation
⎯ Synchronous operations:
Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare match and input capture possible
Register simultaneous input/output possible by counter synchronous operation
⎯ Maximum of 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 and 3
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
• Cascaded operation
• Fast access via internal 16-bit bus
• 26 interrupt sources
• Automatic transfer of register data
• Programmable pulse generator (PPG) output trigger can be generated
• A/D converter conversion start trigger can be generated
• Module stop mode can be set
TIMTPU0A_010020020400
Rev.7.00 Mar. 18, 2009 page 545 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.1 TPU Functions
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
Count clock
φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
TCLKA
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKC
TCLKD
General registers
(TGR)
TGRA_0
TGRB_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TGRA_5
TGRB_5
General registers/
buffer registers
TGRC_0
TGRD_0
⎯
⎯
TGRC_3
TGRD_3
⎯
⎯
I/O pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Counter clear
function
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
⎯
⎯
Compare 0 output
match
1 output
output
Toggle
output
Input capture
function
Synchronous
operation
PWM mode
Phase counting
mode
Buffer operation
⎯
⎯
⎯
Rev.7.00 Mar. 18, 2009 page 546 of 1136
REJ09B0109-0700
⎯
Section 11 16-Bit Timer Pulse Unit (TPU)
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
DTC
TGR
activation compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
DMAC
TGRA
activation compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
A/D
TGRA
converter compare
trigger
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
PPG
trigger
TGRA/
TGRB
compare
match or
input capture
TGRA/
TGRB
compare
match or
input capture
TGRA/
TGRB
compare
match or
input capture
TGRA/
⎯
TGRB
compare
match or
input capture
⎯
Interrupt
sources
5 sources
4 sources
4 sources
5 sources
4 sources
4 sources
• Compare
• Compare
• Compare
• Compare
• Compare
• Compare
match or
match or
match or
match or
match or
match or
input capture input capture input
input capture input capture input capture
0A
1A
capture 2A
3A
4A
5A
• Compare
• Compare
• Compare
• Compare
• Compare
• Compare
match or
match or
match or
match or
match or
match or
input
input capture input
input capture input capture input capture
capture 0B
1B
capture 2B
3B
4B
5B
• Compare
• Overflow
match or
• Underflow
input capture
0C
• Overflow
• Underflow
• Compare
• Overflow
match or
• Underflow
input capture
3C
• Compare
match or
input capture
0D
• Compare
match or
input capture
3D
• Overflow
• Overflow
• Overflow
• Underflow
Legend:
: Possible
⎯: Not possible
Rev.7.00 Mar. 18, 2009 page 547 of 1136
REJ09B0109-0700
TGRD
TGRB
TGRC
TGRB
A/D conversion start request signal
TGRD
TGRB
TGRB
TGRB
PPG output trigger signal
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Timer interrupt enable register
Timer status register
Timer general registers (A, B, C, D)
Timer counter
Figure 11.1 Block Diagram of TPU
Rev.7.00 Mar. 18, 2009 page 548 of 1136
REJ09B0109-0700
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TCI4V
TCI4U
Channel 5: TGI5A
TGI5B
TCI5V
TCI5U
Internal data bus
TGRC
TCNT
TCNT
TGRA
TCNT
TGRA
TGRA
Bus interface
TGRB
TCNT
TCNT
TGRA
TCNT
Module data bus
TGRA
TSR
TSR
TSR
TIER
TIER
TSR
TIOR
TIORH TIORL
TIER:
TSR:
TGR (A, B, C, D):
TCNT:
TGRA
TSR
TIER
TIER
TSR
TIER
TSTR TSYR
TIOR
Control logic
TIOR
TIER
TMDR
TIORH TIORL
TIOR
TCR
TMDR
Channel 4
TCR
TMDR
Channel 5
Common
TCR
TMDR
TCR
TMDR
Channel 1
TCR
Channel 0
Timer start register
Timer synchronous register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
TMDR
Channel 2
Legend:
TSTR:
TSYR:
TCR:
TMDR:
TIOR (H, L):
Control logic for channels 0 to 2
Input/output pins
TIOCA0
Channel 0:
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Channel 1:
TIOCB1
Channel 2:
TIOCA2
TIOCB2
TCR
Clock input
Internal clock: φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
External clock: TCLKA
TCLKB
TCLKC
TCLKD
Control logic for channels 3 to 5
Input/output pins
TIOCA3
Channel 3:
TIOCB3
TIOCC3
TIOCD3
TIOCA4
Channel 4:
TIOCB4
TIOCA5
Channel 5:
TIOCB5
Channel 3
Section 11 16-Bit Timer Pulse Unit (TPU)
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2
Input/Output Pins
Table 11.2 Pin Configuration
Channel
Symbol
I/O
Function
All
TCLKA
Input
External clock A input pin
(Channel 1 and 5 phase counting mode A phase input)
TCLKB
Input
External clock B input pin
(Channel 1 and 5 phase counting mode B phase input)
TCLKC
Input
External clock C input pin
(Channel 2 and 4 phase counting mode A phase input)
TCLKD
Input
External clock D input pin
(Channel 2 and 4 phase counting mode B phase input)
TIOCA0
I/O
TGRA_0 input capture input/output compare output/PWM output pin
TIOCB0
I/O
TGRB_0 input capture input/output compare output/PWM output pin
TIOCC0
I/O
TGRC_0 input capture input/output compare output/PWM output pin
TIOCD0
I/O
TGRD_0 input capture input/output compare output/PWM output pin
TIOCA1
I/O
TGRA_1 input capture input/output compare output/PWM output pin
TIOCB1
I/O
TGRB_1 input capture input/output compare output/PWM output pin
TIOCA2
I/O
TGRA_2 input capture input/output compare output/PWM output pin
TIOCB2
I/O
TGRB_2 input capture input/output compare output/PWM output pin
TIOCA3
I/O
TGRA_3 input capture input/output compare output/PWM output pin
TIOCB3
I/O
TGRB_3 input capture input/output compare output/PWM output pin
TIOCC3
I/O
TGRC_3 input capture input/output compare output/PWM output pin
TIOCD3
I/O
TGRD_3 input capture input/output compare output/PWM output pin
TIOCA4
I/O
TGRA_4 input capture input/output compare output/PWM output pin
TIOCB4
I/O
TGRB_4 input capture input/output compare output/PWM output pin
TIOCA5
I/O
TGRA_5 input capture input/output compare output/PWM output pin
TIOCB5
I/O
TGRB_5 input capture input/output compare output/PWM output pin
0
1
2
3
4
5
Rev.7.00 Mar. 18, 2009 page 549 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
11.3
Register Descriptions
The TPU has the following registers in each channel.
• Timer control register_0 (TCR_0)
• Timer mode register_0 (TMDR_0)
• Timer I/O control register H_0 (TIORH_0)
• Timer I/O control register L_0 (TIORL_0)
• Timer interrupt enable register_0 (TIER_0)
• Timer status register_0 (TSR_0)
• Timer counter_0 (TCNT_0)
• Timer general register A_0 (TGRA_0)
• Timer general register B_0 (TGRB_0)
• Timer general register C_0 (TGRC_0)
• Timer general register D_0 (TGRD_0)
• Timer control register_1 (TCR_1)
• Timer mode register_1 (TMDR_1)
• Timer I/O control register _1 (TIOR_1)
• Timer interrupt enable register_1 (TIER_1)
• Timer status register_1 (TSR_1)
• Timer counter_1 (TCNT_1)
• Timer general register A_1 (TGRA_1)
• Timer general register B_1 (TGRB_1)
• Timer control register_2 (TCR_2)
• Timer mode register_2 (TMDR_2)
• Timer I/O control register_2 (TIOR_2)
• Timer interrupt enable register_2 (TIER_2)
• Timer status register_2 (TSR_2)
• Timer counter_2 (TCNT_2)
• Timer general register A_2 (TGRA_2)
• Timer general register B_2 (TGRB_2)
• Timer control register_3 (TCR_3)
• Timer mode register_3 (TMDR_3)
• Timer I/O control register H_3 (TIORH_3)
• Timer I/O control register L_3 (TIORL_3)
Rev.7.00 Mar. 18, 2009 page 550 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
• Timer interrupt enable register_3 (TIER_3)
• Timer status register_3 (TSR_3)
• Timer counter_3 (TCNT_3)
• Timer general register A_3 (TGRA_3)
• Timer general register B_3 (TGRB_3)
• Timer general register C_3 (TGRC_3)
• Timer general register D_3 (TGRD_3)
• Timer control register_4 (TCR_4)
• Timer mode register_4 (TMDR_4)
• Timer I/O control register _4 (TIOR_4)
• Timer interrupt enable register_4 (TIER_4)
• Timer status register_4 (TSR_4)
• Timer counter_4 (TCNT_4)
• Timer general register A_4 (TGRA_4)
• Timer general register B_4 (TGRB_4)
• Timer control register_5 (TCR_5)
• Timer mode register_5 (TMDR_5)
• Timer I/O control register_5 (TIOR_5)
• Timer interrupt enable register_5 (TIER_5)
• Timer status register_5 (TSR_5)
• Timer counter_5 (TCNT_5)
• Timer general register A_5 (TGRA_5)
• Timer general register B_5 (TGRB_5)
Common Registers
• Timer start register (TSTR)
• Timer synchronous register (TSYR)
Rev.7.00 Mar. 18, 2009 page 551 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.1
Timer Control Register (TCR)
The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR
registers, one for each channel. TCR register settings should be made only when TCNT operation
is stopped.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 2 to 0
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
These bits select the TCNT counter clearing
source. See tables 11.3 and 11.4 for details.
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g. φ/4 both edges = φ/2
rising edge). If phase counting mode is used on
channels 1, 2, 4, and 5, this setting is ignored and
the phase counting mode setting has priority.
Internal clock edge selection is valid when the input
clock is φ/4 or slower. This setting is ignored if the
input clock is φ/1, or when overflow/underflow of
another channel is selected.
00: Count at rising edge
01: Count at falling edge
1×: Count at both edges
Legend: ×: Don’t care
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Rev.7.00 Mar. 18, 2009 page 552 of 1136
REJ09B0109-0700
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The
clock source can be selected independently for
each channel. See tables 11.5 to 11.10 for details.
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.3 CCLR2 to CCLR0 (Channels 0 and 3)
Channel
Bit 7
CCLR2
Bit 6
CCLR1
Bit 5
CCLR0
Description
0, 3
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input
2
capture*
0
TCNT cleared by TGRD compare match/input
2
capture*
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
1
1
0
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 11.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Channel
Bit 7
2
Reserved*
Bit 6
CCLR1
Bit 5
CCLR0
Description
1, 2, 4, 5
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Rev.7.00 Mar. 18, 2009 page 553 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.5 TPSC2 to TPSC0 (Channel 0)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
0
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
External clock: counts on TCLKC pin input
1
External clock: counts on TCLKD pin input
1
1
0
1
Table 11.6 TPSC2 to TPSC0 (Channel 1)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
1
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
1
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
Internal clock: counts on φ/256
1
Counts on TCNT2 overflow/underflow
1
1
Note: This setting is ignored when channel 1 is in phase counting mode.
Rev.7.00 Mar. 18, 2009 page 554 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.7 TPSC2 to TPSC0 (Channel 2)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
2
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
External clock: counts on TCLKC pin input
1
Internal clock: counts on φ/1024
1
1
0
1
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 11.8 TPSC2 to TPSC0 (Channel 3)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
3
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
0
External clock: counts on TCLKA pin input
1
Internal clock: counts on φ/1024
1
0
Internal clock: counts on φ/256
1
Internal clock: counts on φ/4096
1
1
Rev.7.00 Mar. 18, 2009 page 555 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.9 TPSC2 to TPSC0 (Channel 4)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
4
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
0
Internal clock: counts on φ/1024
1
Counts on TCNT5 overflow/underflow
1
1
0
1
Note: This setting is ignored when channel 4 is in phase counting mode.
Table 11.10 TPSC2 to TPSC0 (Channel 5)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
5
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
1
0
Internal clock: counts on φ/256
1
External clock: counts on TCLKD pin input
1
1
Note: This setting is ignored when channel 5 is in phase counting mode.
Rev.7.00 Mar. 18, 2009 page 556 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.2
Timer Mode Register (TMDR)
TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR
registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
—
All 1
—
Reserved
These bits are always read as 1 and cannot be
modified.
5
BFB
0
R/W
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together
for buffer operation. When TGRD is used as a
buffer register, TGRD input capture/output compare
is not generated.
In channels 1, 2, 4, and 5, which have no TGRD,
bit 5 is reserved. It is always read as 0 and cannot
be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer
operation
4
BFA
0
R/W
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together
for buffer operation. When TGRC is used as a
buffer register, TGRC input capture/output compare
is not generated.
In channels 1, 2, 4, and 5, which have no TGRC,
bit 4 is reserved. It is always read as 0 and cannot
be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer
operation
3
2
1
0
MD3
MD2
MD1
MD0
0
0
0
0
R/W
R/W
R/W
R/W
Modes 3 to 0
These bits are used to set the timer operating
mode.
MD3 is a reserved bit. The write value should
always be 0. See table 11.11 for details.
Rev.7.00 Mar. 18, 2009 page 557 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.11 MD3 to MD0
Bit 3
1
MD3*
Bit 2
2
MD2*
Bit 1
MD1
Bit 0
MD0
Description
0
0
0
0
Normal operation
1
Reserved
0
PWM mode 1
1
PWM mode 2
0
Phase counting mode 1
1
Phase counting mode 2
0
Phase counting mode 3
1
Phase counting mode 4
×
⎯
1
1
0
1
1
×
×
Legend: ×: Don’t care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
11.3.3
Timer I/O Control Register (TIOR)
TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected
by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
Rev.7.00 Mar. 18, 2009 page 558 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
IOB3
IOB2
IOB1
IOB0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control B3 to B0
3
2
1
0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control A3 to A0
Specify the function of TGRB.
For details, see tables 11.12, 11.14, 11.15, 11.16,
11.18, and 11.19.
Specify the function of TGRA.
For details, see tables 11.20, 11.22, 11.23, 11.24,
11.26, and 11.27.
TIORL_0, TIORL_3
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
IOD3
IOD2
IOD1
IOD0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control D3 to D0
3
2
1
0
IOC3
IOC2
IOC1
IOC0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control C3 to C0
Specify the function of TGRD.
For details, see tables 11.13 and 11.17.
Specify the function of TGRC.
For details, see tables 11.21 and 11.25
Rev.7.00 Mar. 18, 2009 page 559 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.12 TIORH_0
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_0
Function
0
0
0
0
Output
compare
register
1
TIOCB0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
Initial output is 0 output
0
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCB0 pin
Input capture at rising edge
Capture input source is TIOCB0 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCB0 pin
Input capture at both edges
1
Capture input source is channel 1/count clock
Input capture at TCNT_1 count- up/count-down*
Legend: ×: Don’t care
Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
Rev.7.00 Mar. 18, 2009 page 560 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.13 TIORL_0
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_0
Function
0
0
0
0
Output
compare
2
register*
1
TIOCD0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
2
register*
Capture input source is TIOCD0 pin
Input capture at rising edge
Capture input source is TIOCD0 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCD0 pin
Input capture at both edges
1
Capture input source is channel 1/count clock
1
Input capture at TCNT_1 count-up/count-down*
Legend: ×: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.7.00 Mar. 18, 2009 page 561 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.14 TIOR_1
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_1
Function
0
0
0
0
Output
compare
register
1
TIOCB1 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCB1 pin
Input capture at rising edge
Capture input source is TIOCB1 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCB1 pin
Input capture at both edges
1
TGRC_0 compare match/input capture
Input capture at generation of TGRC_0 compare
match/input capture
Legend: ×: Don’t care
Rev.7.00 Mar. 18, 2009 page 562 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.15 TIOR_2
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_2
Function
0
0
0
0
Output
compare
register
1
TIOCB2 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
×
0
0
1
Input
capture
register
Capture input source is TIOCB2 pin
Input capture at rising edge
Capture input source is TIOCB2 pin
Input capture at falling edge
1
×
Capture input source is TIOCB2 pin
Input capture at both edges
Legend: ×: Don’t care
Rev.7.00 Mar. 18, 2009 page 563 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.16 TIORH_3
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_3
Function
0
0
0
0
Output
compare
register
1
TIOCB3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCB3 pin
Input capture at rising edge
Capture input source is TIOCB3 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCB3 pin
Input capture at both edges
1
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down*
Legend: ×: Don’t care
Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
Rev.7.00 Mar. 18, 2009 page 564 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.17 TIORL_3
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_3
Function
0
0
0
0
Output
compare
2
register*
1
TIOCD3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
2
register*
Capture input source is TIOCD3 pin
Input capture at rising edge
Capture input source is TIOCD3 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCD3 pin
Input capture at both edges
1
Capture input source is channel 4/count clock
1
Input capture at TCNT_4 count-up/count-down*
Legend: ×: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.7.00 Mar. 18, 2009 page 565 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.18 TIOR_4
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_4
Function
0
0
0
0
Output
compare
register
1
TIOCB4 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCB4 pin
Input capture at rising edge
Capture input source is TIOCB4 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCB4 pin
Input capture at both edges
1
Capture input source is TGRC_3 compare
match/input capture
Input capture at generation of TGRC_3 compare
match/input capture
Legend: ×: Don’t care
Rev.7.00 Mar. 18, 2009 page 566 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.19 TIOR_5
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_5
Function
0
0
0
0
Output
compare
register
1
TIOCB5 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
×
0
0
1
Input
capture
register
Capture input source is TIOCB5 pin
Input capture at rising edge
Capture input source is TIOCB5 pin
Input capture at falling edge
1
×
Capture input source is TIOCB5 pin
Input capture at both edges
Legend: ×: Don’t care
Rev.7.00 Mar. 18, 2009 page 567 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.20 TIORH_0
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_0
Function
0
0
0
0
Output
compare
register
1
TIOCA0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCA0 pin
Input capture at rising edge
Capture input source is TIOCA0 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCA0 pin
Input capture at both edges
1
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Legend: ×: Don’t care
Rev.7.00 Mar. 18, 2009 page 568 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.21 TIORL_0
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_0
Function
0
0
0
0
Output
compare
register*
1
TIOCC0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register*
Capture input source is TIOCC0 pin
Input capture at rising edge
Capture input source is TIOCC0 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCC0 pin
Input capture at both edges
1
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Legend: ×: Don’t care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.7.00 Mar. 18, 2009 page 569 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.22 TIOR_1
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_1
Function
0
0
0
0
Output
compare
register
1
TIOCA1 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCA1 pin
Input capture at rising edge
Capture input source is TIOCA1 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCA1 pin
Input capture at both edges
1
Capture input source is TGRA_0 compare
match/input capture
Input capture at generation of channel 0/TGRA_0
compare match/input capture
Legend: ×: Don’t care
Rev.7.00 Mar. 18, 2009 page 570 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.23 TIOR_2
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_2
Function
0
0
0
0
Output
compare
register
1
TIOCA2 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
×
0
0
1
Input
capture
register
Capture input source is TIOCA2 pin
Input capture at rising edge
Capture input source is TIOCA2 pin
Input capture at falling edge
1
×
Capture input source is TIOCA2 pin
Input capture at both edges
Legend: ×: Don’t care
Rev.7.00 Mar. 18, 2009 page 571 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.24 TIORH_3
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_3
Function
0
0
0
0
Output
compare
register
1
TIOCA3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCA3 pin
Input capture at rising edge
Capture input source is TIOCA3 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCA3 pin
Input capture at both edges
1
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down
Legend: ×: Don’t care
Rev.7.00 Mar. 18, 2009 page 572 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.25 TIORL_3
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_3
Function
0
0
0
0
Output
compare
register*
1
TIOCC3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register*
Capture input source is TIOCC3 pin
Input capture at rising edge
Capture input source is TIOCC3 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCC3 pin
Input capture at both edges
1
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down
Legend: ×: Don’t care
Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.7.00 Mar. 18, 2009 page 573 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.26 TIOR_4
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_4
Function
0
0
0
0
Output
compare
register
1
TIOCA4 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCA4 pin
Input capture at rising edge
Capture input source is TIOCA4 pin
Input capture at falling edge
1
×
×
×
Capture input source is TIOCA4 pin
Input capture at both edges
1
Capture input source is TGRA_3 compare
match/input capture
Input capture at generation of TGRA_3 compare
match/input capture
Legend: ×: Don’t care
Rev.7.00 Mar. 18, 2009 page 574 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.27 TIOR_5
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_5
Function
0
0
0
0
Output
compare
register
1
TIOCA5 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
×
0
0
1
Input
capture
register
Input capture source is TIOCA5 pin
Input capture at rising edge
Input capture source is TIOCA5 pin
Input capture at falling edge
1
×
Input capture source is TIOCA5 pin
Input capture at both edges
Legend: ×: Don’t care
Rev.7.00 Mar. 18, 2009 page 575 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.4
Timer Interrupt Enable Register (TIER)
TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has
six TIER registers, one for each channel.
Bit
Bit Name
Initial value
R/W
Description
7
TTGE
0
R/W
A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion
start requests by TGRA input capture/compare
match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
6
—
1
—
Reserved
This bit is always read as 1 and cannot be
modified.
5
TCIEU
0
R/W
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by
the TCFU flag when the TCFU flag in TSR is set to
1 in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
4
TCIEV
0
R/W
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by
the TCFV flag when the TCFV flag in TSR is set to
1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
3
TGIED
0
R/W
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by
the TGFD bit when the TGFD bit in TSR is set to 1
in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
Rev.7.00 Mar. 18, 2009 page 576 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial value
R/W
Description
2
TGIEC
0
R/W
TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by
the TGFC bit when the TGFC bit in TSR is set to 1
in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by
the TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by
the TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Rev.7.00 Mar. 18, 2009 page 577 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.5
Timer Status Register (TSR)
TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each
channel.
Bit
Bit Name
Initial value
R/W
Description
7
TCFD
1
R
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is always
read as 1 and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6
—
1
—
Reserved
This bit is always read as 1 and cannot be
modified.
5
TCFU
0
R/(W)*
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1, 2, 4, and 5 are set to
phase counting mode.
In channels 0 and 3, bit 5 is reserved. It is always
read as 0 and cannot be modified.
[Setting condition]
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
4
TCFV
0
R/(W)*
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred.
[Setting condition]
When the TCNT value overflows (changes from
H'FFFF to H'0000)
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
Rev.7.00 Mar. 18, 2009 page 578 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial value
R/W
Description
3
TGFD
0
R/(W)*
Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD
input capture or compare match in channels 0 and
3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is
always read as 0 and cannot be modified.
[Setting conditions]
•
When TCNT = TGRD while TGRD is
functioning as output compare register
•
When TCNT value is transferred to TGRD by
input capture signal while TGRD is functioning
as input capture register
[Clearing conditions]
2
TGFC
0
R/(W)*
•
When DTC is activated by TGID interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFD after reading TGFD
=1
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC
input capture or compare match in channels 0 and
3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is
always read as 0 and cannot be modified.
[Setting conditions]
•
When TCNT = TGRC while TGRC is
functioning as output compare register
•
When TCNT value is transferred to TGRC by
input capture signal while TGRC is functioning
as input capture register
[Clearing conditions]
•
When DTC is activated by TGIC interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFC after reading TGFC
=1
Rev.7.00 Mar. 18, 2009 page 579 of 1136
REJ09B0109-0700
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial value
R/W
Description
1
TGFB
0
R/(W)*
Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB
input capture or compare match.
[Setting conditions]
•
When TCNT = TGRB while TGRB is functioning
as output compare register
•
When TCNT value is transferred to TGRB by
input capture signal while TGRB is functioning
as input capture register
[Clearing conditions]
0
TGFA
0
R/(W)*
•
When DTC is activated by TGIB interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFB after reading TGFB
=1
Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA
input capture or compare match.
[Setting conditions]
When TCNT = TGRA while TGRA is functioning as
output compare register
When TCNT value is transferred to TGRA by input
capture signal while TGRA is functioning as input
capture register
[Clearing conditions]
Note:
*
•
When DTC is activated by TGIA interrupt while
DISEL bit of MRB in DTC is 0
•
When DMAC is activated by TGIA interrupt
while DTE bit of DMABCR in DTC is 0
•
When 0 is written to TGFA after reading TGFA
=1
Only 0 can be written, for flag clearing.
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.6
Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
11.3.7
Timer General Register (TGR)
The TGR registers are 16-bit readable/writable registers with a dual function as output compare
and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two
each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for
operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must
always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA–TGRC and
TGRB–TGRD.
11.3.8
Timer Start Register (TSTR)
TSTR selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR
or setting the count clock in TCR, first stop the TCNT counter.
Bit
Bit Name
Initial value
R/W
Description
7, 6
—
All 0
—
Reserved
The write value should always be 0.
5
4
3
2
1
0
CST5
CST4
CST3
CST2
CST1
CST0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Counter Start 5 to 0
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained.
If TIOR is written to when the CST bit is cleared to 0,
the pin output level will be changed to the set initial
output value.
0: TCNT_5 to TCNT_0 count operation is stopped
1: TCNT_5 to TCNT_0 performs count operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.9
Timer Synchronous Register (TSYR)
TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit
Bit Name
Initial value
R/W
Description
7, 6
—
—
R/W
Reserved
5
4
3
2
1
0
SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
The write value should always be 0.
Timer Synchronization 5 to 0
These bits select whether operation is independent of
or synchronized with other channels.
When synchronous operation is selected,
synchronous presetting of multiple channels, and
synchronous clearing through counter clearing on
another channel are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit, the
TCNT clearing source must also be set by means of
bits CCLR2 to CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operates independently
(TCNT presetting /clearing is unrelated to
other channels)
1: TCNT_5 to TCNT_0 performs synchronous
operation (TCNT synchronous presetting/
synchronous clearing is possible)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.4
Operation
11.4.1
Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, periodic counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for
the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic
counter, and so on.
1. Example of count operation setting procedure
Figure 11.2 shows an example of the count operation setting procedure.
[1] Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
Operation selection
Select counter clock
[1]
Periodic counter
Select counter clearing source
[2]
Select output compare register
[3]
Set period
[4]
Start count
[5]
<Periodic counter>
[2] For periodic counter
operation, select the
TGR to be used as
the TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
Free-running counter
[3] Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
[4] Set the periodic
counter cycle in the
TGR selected in [2].
Start count
<Free-running counter>
[5]
[5] Set the CST bit in
TSTR to 1 to start
the counter
operation.
Figure 11.2 Example of Counter Operation Setting Procedure
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Section 11 16-Bit Timer Pulse Unit (TPU)
2. Free-running count operation and periodic count operation
Immediately after a reset, the TPU’s TCNT counters are all designated as free-running
counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to
H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER
is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again
from H'0000.
Figure 11.3 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
CST bit
TCFV
Figure 11.3 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the
relevant channel performs periodic count operation. The TGR register for setting the period is
designated as an output compare register, and counter clearing by compare match is selected
by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts
count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When
the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared
to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an
interrupt. After a compare match, TCNT starts counting up again from H'0000.
Figure 11.4 illustrates periodic counter operation.
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Section 11 16-Bit Timer Pulse Unit (TPU)
TCNT value
TGR
Counter cleared by TGR
compare match
H'0000
Time
CST bit
Flag cleared by software or
DTC activation
TGF
Figure 11.4 Periodic Counter Operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the
corresponding output pin using a compare match.
1. Example of setting procedure for waveform output by compare match
Figure 11.5 shows an example of the setting procedure for waveform output by a compare
match.
Output selection
Select waveform output mode
[1]
[1] Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TIOC pin until the
first compare match occurs.
[2] Set the timing for compare match generation in
TGR.
Set output timing
[2]
Start count
[3]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
<Waveform output>
Figure 11.5 Example of Setting Procedure for Waveform Output by Compare Match
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Section 11 16-Bit Timer Pulse Unit (TPU)
2. Examples of waveform output operation
Figure 11.6 shows an example of 0 output/1 output.
In this example, TCNT has been designated as a free-running counter, and settings have been
made so that 1 is output by compare match A, and 0 is output by compare match B. When the
set level and the pin level match, the pin level does not change.
TCNT value
H'FFFF
TGRA
TGRB
Time
H'0000
No change
No change
1 output
TIOCA
TIOCB
No change
No change
0 output
Figure 11.6 Example of 0 Output/1 Output Operation
Figure 11.7 shows an example of toggle output.
In this example TCNT has been designated as a periodic counter (with counter clearing
performed by compare match B), and settings have been made so that output is toggled by both
compare match A and compare match B.
TCNT value
Counter cleared by TGRB compare match
H'FFFF
TGRB
TGRA
Time
H'0000
Toggle output
TIOCB
Toggle output
TIOCA
Figure 11.7 Example of Toggle Output Operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC
pin input edge.
Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3,
and 4, it is also possible to specify another channel’s counter input clock or compare match signal
as the input capture source.
Note: When another channel’s counter input clock is used as the input capture input for channels
0 and 3, φ/1 should not be selected as the counter input clock used for input capture input.
Input capture will not be generated if φ/1 is selected.
1. Example of setting procedure for input capture operation
Figure 11.8 shows an example of the setting procedure for input capture operation.
[1] Designate TGR as an input capture register by
means of TIOR, and select the input capture
source and input signal edge (rising edge, falling
edge, or both edges).
Input selection
Select input capture input
[1]
Start count
[2]
[2] Set the CST bit in TSTR to 1 to start the count
operation.
<Input capture operation>
Figure 11.8 Example of Setting Procedure for Input Capture Operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
2. Example of input capture operation
Figure 11.9 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input
capture input edge, falling edge has been selected as the TIOCB pin input capture input edge,
and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB
input (falling edge)
TCNT value
H'0180
H'0160
H'0010
H'0005
Time
H'0000
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB
TGRB
H'0180
Figure 11.9 Example of Input Capture Operation
11.4.2
Synchronous Operation
In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously
(synchronous presetting). Also, multiple of TCNT counters can be cleared simultaneously
(synchronous clearing) by making the appropriate setting in TCR.
Synchronous operation enables TGR to be incremented with respect to a single time base.
Channels 0 to 5 can all be designated for synchronous operation.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation Setting Procedure: Figure 11.10 shows an example of the
synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous presetting
Set TCNT
Synchronous clearing
[2]
Clearing
source generation
channel?
No
Yes
<Synchronous presetting>
Select counter
clearing source
[3]
Set synchronous
counter clearing
[4]
Start count
[5]
Start count
[5]
<Counter clearing>
<Synchronous clearing>
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation.
[2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the
same value is simultaneously written to the other TCNT counters.
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 11.10 Example of Synchronous Operation Setting Procedure
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Section 11 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation: Figure 11.11 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed
for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle.
For details on PWM modes, see section 11.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match
TCNT0 to TCNT2 values
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
Time
H'0000
TIOCA_0
TIOCA_1
TIOCA_2
Figure 11.11 Example of Synchronous Operation
11.4.3
Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 11.28 shows the register combinations used in buffer operation.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.28 Register Combinations in Buffer Operation
Channel
Timer General Register
Buffer Register
0
TGRA_0
TGRC_0
TGRB_0
TGRD_0
TGRA_3
TGRC_3
TGRB_3
TGRD_3
3
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 11.12.
Compare match signal
Buffer register
Timer general
register
Comparator
TCNT
Figure 11.12 Compare Match Buffer Operation
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 11.13.
Input capture
signal
Buffer register
Timer general
register
Figure 11.13 Input Capture Buffer Operation
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TCNT
Section 11 16-Bit Timer Pulse Unit (TPU)
Example of Buffer Operation Setting Procedure: Figure 11.14 shows an example of the buffer
operation setting procedure.
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
Buffer operation
[1]
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
Set buffer operation
[2]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
Start count
[3]
Select TGR function
<Buffer operation>
Figure 11.14 Example of Buffer Operation Setting Procedure
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Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of Buffer Operation:
1. When TGR is an output compare register
Figure 11.15 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details on PWM modes, see section 11.4.5, PWM Modes.
TCNT value
TGRB_0
H'0520
H'0450
H'0200
TGRA_0
Time
H'0000
TGRC_0 H'0200
H'0450
H'0520
Transfer
TGRA_0
H'0200
H'0450
TIOCA
Figure 11.15 Example of Buffer Operation (1)
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Section 11 16-Bit Timer Pulse Unit (TPU)
2. When TGR is an input capture register
Figure 11.16 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
Time
TIOCA
TGRA
TGRC
H'0532
H'0F07
H'09FB
H'0532
H'0F07
Figure 11.16 Example of Buffer Operation (2)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of
TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 11.29 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counter operates independently in phase counting mode.
Table 11.29 Cascaded Combinations
Combination
Upper 16 Bits
Lower 16 Bits
Channels 1 and 2
TCNT_1
TCNT_2
Channels 4 and 5
TCNT_4
TCNT_5
Example of Cascaded Operation Setting Procedure: Figure 11.17 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
Start count
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
[2] Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
<Cascaded operation>
Figure 11.17 Cascaded Operation Setting Procedure
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Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of Cascaded Operation: Figure 11.18 illustrates the operation when counting upon
TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been
designated as input capture registers, and the TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
TCNT_1
clock
TCNT_1
H'03A1
H'03A2
TCNT_2
clock
TCNT_2
H'FFFF
H'0000
H'0001
TIOCA1,
TIOCA2
TGRA_1
H'03A2
TGRA_2
H'0000
Figure 11.18 Example of Cascaded Operation (1)
Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
TCNT_1
FFFD
FFFE
0000
FFFF
0000
0001
0002
0001
0000
0001
FFFF
0000
Figure 11.19 Example of Cascaded Operation (2)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be
selected as the output level in response to compare match of each TGR.
Settings of TGR registers can output a PWM waveform in the range of 0–% to 100–% duty cycle.
Designating TGR compare match as the counter clearing source enables the cycle to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR
are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The
outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare
matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If
the set values of paired TGRs are identical, the output value does not change when a compare
match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty cycle
registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a synchronization register compare match, the output value of each pin is
the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical,
the output value does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 11.30.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.30 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
PWM Mode 1
PWM Mode 2
0
TGRA_0
TIOCA0
TIOCA0
TGRB_0
TGRC_0
TIOCB0
TIOCC0
TGRD_0
1
TGRA_1
TIOCD0
TIOCA1
TGRB_1
2
TGRA_2
TGRA_3
TIOCA2
TIOCA3
TGRA_4
TIOCC3
TGRA_5
TGRB_5
TIOCC3
TIOCD3
TIOCA4
TGRB_4
5
TIOCA3
TIOCB3
TGRD_3
4
TIOCA2
TIOCB2
TGRB_3
TGRC_3
TIOCA1
TIOCB1
TGRB_2
3
TIOCC0
TIOCA4
TIOCB4
TIOCA5
TIOCA5
TIOCB5
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Example of PWM Mode Setting Procedure: Figure 11.20 shows an example of the PWM mode
setting procedure.
PWM mode
Select counter clock
[1]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
[2] Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Select counter clearing source
Select waveform output level
Set TGR
[2]
[3]
[4]
[3] Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
[4] Set the cycle in the TGR selected in [2], and
set the duty in the other TGRs.
[5] Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set PWM mode
[5]
Start count
[6]
[6] Set the CST bit in TSTR to 1 to start the count
operation.
<PWM mode>
Figure 11.20 Example of PWM Mode Setting Procedure
Examples of PWM Mode Operation: Figure 11.21 shows an example of PWM mode 1
operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as
the duty cycle.
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Section 11 16-Bit Timer Pulse Unit (TPU)
TCNT value
TGRA
Counter cleared by
TGRA compare match
TGRB
H'0000
Time
TIOCA
Figure 11.21 Example of PWM Mode Operation (1)
Figure 11.22 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as
the duty cycle.
TCNT value
Counter cleared by
TGRB_1 compare match
TGRB_1
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
H'0000
Time
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 11.22 Example of PWM Mode Operation (2)
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Section 11 16-Bit Timer Pulse Unit (TPU)
Figure 11.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle
in PWM mode.
TCNT value
TGRB rewritten
TGRA
TGRB
TGRB rewritten
TGRB
rewritten
H'0000
Time
0% duty
TIOCA
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB rewritten
TGRB
H'0000
Time
100% duty
TIOCA
Output does not change when cycle register and duty
register compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB
TGRB rewritten
Time
H'0000
100% duty
TIOCA
0% duty
Figure 11.23 Example of PWM Mode Operation (3)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 11.31 shows the correspondence between external clock pins and channels.
Table 11.31 Clock Input Pins in Phase Counting Mode
External Clock Pins
Channels
A-Phase
B-Phase
When channel 1 or 5 is set to phase counting mode
TCLKA
TCLKB
When channel 2 or 4 is set to phase counting mode
TCLKC
TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 11.24 shows an example of the
phase counting mode setting procedure.
[1] Select phase counting mode with bits MD3 to
MD0 in TMDR.
[2] Set the CST bit in TSTR to 1 to start the count
operation.
Phase counting mode
Select phase counting mode
[1]
Start count
[2]
<Phase counting mode>
Figure 11.24 Example of Phase Counting Mode Setting Procedure
Rev.7.00 Mar. 18, 2009 page 603 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or
down according to the phase difference between two external clocks. There are four modes,
according to the count conditions.
1. Phase counting mode 1
Figure 11.25 shows an example of phase counting mode 1 operation, and table 11.32
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 11.25 Example of Phase Counting Mode 1 Operation
Table 11.32 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Up-count
Low level
Low level
High level
High level
Down-count
Low level
High level
Low level
Legend:
: Rising edge
: Falling edge
Rev.7.00 Mar. 18, 2009 page 604 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
2. Phase counting mode 2
Figure 11.26 shows an example of phase counting mode 2 operation, and table 11.33
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 11.26 Example of Phase Counting Mode 2 Operation
Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
Operation
High level
Don’t care
Low level
Don’t care
Low level
Don’t care
High level
Up-count
High level
Don’t care
Low level
Don’t care
High level
Don’t care
Low level
Down-count
Legend:
: Rising edge
: Falling edge
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Section 11 16-Bit Timer Pulse Unit (TPU)
3. Phase counting mode 3
Figure 11.27 shows an example of phase counting mode 3 operation, and table 11.34
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 11.27 Example of Phase Counting Mode 3 Operation
Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
Operation
High level
Don’t care
Low level
Don’t care
Low level
Don’t care
High level
Up-count
High level
Down-count
Low level
Don’t care
High level
Don’t care
Low level
Don’t care
Legend:
: Rising edge
: Falling edge
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Section 11 16-Bit Timer Pulse Unit (TPU)
4. Phase counting mode 4
Figure 11.28 shows an example of phase counting mode 4 operation, and table 11.35
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 11.28 Example of Phase Counting Mode 4 Operation
Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Up-count
Low level
Low level
Don’t care
High level
High level
Down-count
Low level
High level
Don’t care
Low level
Legend:
: Rising edge
: Falling edge
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Section 11 16-Bit Timer Pulse Unit (TPU)
Phase Counting Mode Application Example: Figure 11.29 shows an example in which phase
counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo
motor 2-phase encoder pulses in order to detect the position or speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and
TGRC_0 are used for the compare match function, and are set with the speed control cycle and
position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating
in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture
source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed.
TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and
TGRC_0 compare matches are selected as the input capture source, and the up/down-counter
values for the control cycles are stored.
This procedure enables accurate position/speed detection to be achieved.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Channel 1
TCLKA
TCLKB
Edge
detection
circuit
TCNT_1
TGRA_1
(speed cycle capture)
TGRB_1
(position cycle capture)
TCNT_0
TGRA_0
(speed control cycle)
+
-
TGRC_0
(position control cycle)
+
-
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation)
Channel 0
Figure 11.29 Phase Counting Mode Application Example
11.5
Interrupt Sources
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
Table 11.36 lists the TPU interrupt sources.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.36 TPU Interrupts
Channel
Name
Interrupt Source
Interrupt
Flag
DTC
Activation
DMAC
Activation
0
TGI0A
TGRA_0 input capture/compare match
TGFA_0
Possible
Possible
TGI0B
TGRB_0 input capture/compare match
TGFB_0
Possible
Not possible
TGI0C
TGRC_0 input capture/compare match
TGFC_0
Possible
Not possible
TGI0D
TGRD_0 input capture/compare match
TGFD_0
Possible
Not possible
TGI0E
TCNT_0 overflow
TCFV_0
Not possible
Not possible
TGI1A
TGRA_1 input capture/compare match
TGFA_1
Possible
Possible
TGI1B
TGRB_1 input capture/compare match
TGFB_1
Possible
Not possible
TCI1V
TCNT_1 overflow
TCFV_1
Not possible
Not possible
TCI1U
TCNT_1 underflow
TCFU_1
Not possible
Not possible
TGI2A
TGRA_2 input capture/compare match
TGFA_2
Possible
Possible
TGI2B
TGRB_2 input capture/compare match
TGFB_2
Possible
Not possible
TCI2V
TCNT_2 overflow
TCFV_2
Not possible
Not possible
TCI2U
TCNT_2 underflow
TCFU_2
Not possible
Not possible
TGI3A
TGRA_3 input capture/compare match
TGFA_3
Possible
Possible
TGI3B
TGRB_3 input capture/compare match
TGFB_3
Possible
Not possible
TGI3C
TGRC_3 input capture/compare match
TGFC_3
Possible
Not possible
TGI3D
TGRD_3 input capture/compare match
TGFD_3
Possible
Not possible
TCI3V
TCNT_3 overflow
TCFV_3
Not possible
Not possible
TGI4A
TGRA_4 input capture/compare match
TGFA_4
Possible
Possible
TGI4B
TGRB_4 input capture/compare match
TGFB_4
Possible
Not possible
1
2
3
4
5
Note:
TCI4V
TCNT_4 overflow
TCFV_4
Not possible
Not possible
TCI4U
TCNT_4 underflow
TCFU_4
Not possible
Not possible
TGI5A
TGRA_5 input capture/compare match
TGFA_5
Possible
Possible
TGI5B
TGRB_5 input capture/compare match
TGFB_5
Possible
Not possible
TCI5V
TCNT_5 overflow
TCFV_5
Not possible
Not possible
TCI5U
TCNT_5 underflow
TCFU_5
Not possible
Not possible
This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each
for channels 1, 2, 4, and 5.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one
each for channels 1, 2, 4, and 5.
11.6
DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For
details, see section 9, Data Transfer Controller (DTC).
A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources,
four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
11.7
DMAC Activation
The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel.
For details, see section 7, DMA Controller (DMAC).
In the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC
activation sources, one for each channel.
11.8
A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to start A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is started.
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Section 11 16-Bit Timer Pulse Unit (TPU)
In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
11.9
Operation Timing
11.9.1
Input/Output Timing
TCNT Count Timing: Figure 11.30 shows TCNT count timing in internal clock operation, and
figure 11.31 shows TCNT count timing in external clock operation.
φ
Internal clock
Rising edge
Falling edge
TCNT
input clock
TCNT
N–1
N
N+1
N+2
Figure 11.30 Count Timing in Internal Clock Operation
φ
External clock
Rising edge
Falling edge
Falling edge
TCNT
input clock
TCNT
N–1
N
N+1
Figure 11.31 Count Timing in External Clock Operation
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N+2
Section 11 16-Bit Timer Pulse Unit (TPU)
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the (TIOC pin) TCNT input clock is generated.
Figure 11.32 shows output compare output timing.
φ
TCNT
input clock
N
TCNT
N+1
N
TGR
Compare
match signal
TIOC pin
Figure 11.32 Output Compare Output Timing
Input Capture Signal Timing: Figure 11.33 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
TCNT
TGR
N
N+1
N+2
N
N+2
Figure 11.33 Input Capture Input Signal Timing
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Section 11 16-Bit Timer Pulse Unit (TPU)
Timing for Counter Clearing by Compare Match/Input Capture: Figure 11.34 shows the
timing when counter clearing by compare match occurrence is specified, and figure 11.35 shows
the timing when counter clearing by input capture occurrence is specified.
φ
Compare
match signal
Counter
clear signal
TCNT
N
TGR
N
H'0000
Figure 11.34 Counter Clear Timing (Compare Match)
φ
Input capture
signal
Counter clear
signal
TCNT
N
H'0000
N
TGR
Figure 11.35 Counter Clear Timing (Input Capture)
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Section 11 16-Bit Timer Pulse Unit (TPU)
Buffer Operation Timing: Figures 11.36 and 11.37 show the timings in buffer operation.
φ
TCNT
n
n+1
Compare
match signal
TGRA,
TGRB
n
TGRC,
TGRD
N
N
Figure 11.36 Buffer Operation Timing (Compare Match)
φ
Input capture
signal
TCNT
N
TGRA,
TGRB
n
TGRC,
TGRD
N+1
N
N+1
n
N
Figure 11.37 Buffer Operation Timing (Input Capture)
11.9.2
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 11.38 shows the timing for
setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal
timing.
Rev.7.00 Mar. 18, 2009 page 615 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
φ
TCNT input
clock
TCNT
N
TGR
N
N+1
Compare
match signal
TGF flag
TGI interrupt
Figure 11.38 TGI Interrupt Timing (Compare Match)
TGF Flag Setting Timing in Case of Input Capture: Figure 11.39 shows the timing for setting
of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing.
φ
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 11.39 TGI Interrupt Timing (Input Capture)
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Section 11 16-Bit Timer Pulse Unit (TPU)
TCFV Flag/TCFU Flag Setting Timing: Figure 11.40 shows the timing for setting of the TCFV
flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing.
Figure 11.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
the TCIU interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
H'FFFF
H'0000
Overflow
signal
TCFV flag
TCIV interrupt
Figure 11.40 TCIV Interrupt Setting Timing
φ
TCNT
input clock
TCNT
(underflow)
H'0000
H'FFFF
Underflow
signal
TCFU flag
TCIU interrupt
Figure 11.41 TCIU Interrupt Setting Timing
Rev.7.00 Mar. 18, 2009 page 617 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.42
shows the timing for status flag clearing by the CPU, and figure 11.43 shows the timing for status
flag clearing by the DTC or DMAC.
TSR write cycle
T2
T1
φ
TSR address
Address
Write signal
Status flag
Interrupt
request
signal
Figure 11.42 Timing for Status Flag Clearing by CPU
DTC/DMAC
read cycle
T1
T2
DTC/DMAC
write cycle
T1
T2
φ
Address
Source address
Destination
address
Status flag
Interrupt
request
signal
Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation
Rev.7.00 Mar. 18, 2009 page 618 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10
Usage Notes
11.10.1 Module Stop Mode Setting
TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 24, Power-Down Modes.
11.10.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.44 shows the input clock
conditions in phase counting mode.
Overlap
Phase
Phase
diffediffeOverlap
rence
rence
Pulse width
Pulse width
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 11.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev.7.00 Mar. 18, 2009 page 619 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.3 Caution on Cycle Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
φ
f=
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value
11.10.4 Contention between TCNT Write and Clear Operations
If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed. Figure 11.45 shows the timing in this
case.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
Counter clearing
signal
TCNT
N
H'0000
Figure 11.45 Contention between TCNT Write and Clear Operations
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 11.46 shows the timing in this case.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 11.46 Contention between TCNT Write and Increment Operations
Rev.7.00 Mar. 18, 2009 page 621 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 11.47 shows the timing in this case.
TGR write cycle
T2
T1
φ
TGR address
Address
Write signal
Compare
match signal
Disabled
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 11.47 Contention between TGR Write and Compare Match
Rev.7.00 Mar. 18, 2009 page 622 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 11.48 shows the timing in this case.
TGR write cycle
T2
T1
φ
Buffer register
address
Address
Write signal
Compare
match signal
Buffer register write data
Buffer
register
TGR
N
M
N
Figure 11.48 Contention between Buffer Register Write and Compare Match
Rev.7.00 Mar. 18, 2009 page 623 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.8 Contention between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data after input capture transfer.
Figure 11.49 shows the timing in this case.
TGR read cycle
T2
T1
φ
TGR address
Address
Read signal
Input capture
signal
TGR
X
Internal
data bus
M
M
Figure 11.49 Contention between TGR Read and Input Capture
Rev.7.00 Mar. 18, 2009 page 624 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.9 Contention between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 11.50 shows the timing in this case.
TGR write cycle
T2
T1
φ
Address
TGR address
Write signal
Input capture
signal
TCNT
TGR
M
M
Figure 11.50 Contention between TGR Write and Input Capture
Rev.7.00 Mar. 18, 2009 page 625 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.10 Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 11.51 shows the timing in this case.
Buffer register write cycle
T2
T1
φ
Buffer register
address
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
N
M
N
M
Figure 11.51 Contention between Buffer Register Write and Input Capture
Rev.7.00 Mar. 18, 2009 page 626 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.11 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 11.52 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter
clearing signal
TGF
Disabled
TCFV
Figure 11.52 Contention between Overflow and Counter Clearing
Rev.7.00 Mar. 18, 2009 page 627 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, when
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 11.53 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
TCNT
TCNT write data
H'FFFF
M
TCFV flag
Figure 11.53 Contention between TCNT Write and Overflow
Rev.7.00 Mar. 18, 2009 page 628 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
11.10.14 Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore
be disabled before entering module stop mode.
Rev.7.00 Mar. 18, 2009 page 629 of 1136
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Section 11 16-Bit Timer Pulse Unit (TPU)
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Section 12 Programmable Pulse Generator (PPG)
Section 12 Programmable Pulse Generator (PPG)
The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse
unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that
can operate both simultaneously and independently. The block diagram of PPG is shown in figure
12.1.
12.1
Features
• 16-bit output data
• Four output groups
• Selectable output trigger signals
• Non-overlap mode
• Can operate together with the data transfer controller (DTC) and the DMA controller (DMAC)
• Settable inverted output
• Module stop mode can be set
PPG0001A_000020020400
Rev.7.00 Mar. 18, 2009 page 631 of 1136
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Section 12 Programmable Pulse Generator (PPG)
Compare match signals
Control logic
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
PO7
PO6
PO5
PO4
PO3
PO2
PO1
PO0
Legend:
PMR
PCR
NDERH
NDERL
NDRH
NDRL
PODRH
PODRL
NDERH
NDERL
PMR
PCR
Pulse output
pins, group 3
PODRH
NDRH
PODRL
NDRL
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
: PPG output mode register
: PPG output control register
: Next data enable register H
: Next data enable register L
: Next data register H
: Next data register L
: Output data register H
: Output data register L
Figure 12.1 Block Diagram of PPG
Rev.7.00 Mar. 18, 2009 page 632 of 1136
REJ09B0109-0700
Internal
data bus
Section 12 Programmable Pulse Generator (PPG)
12.2
Input/Output Pins
Table 12.1 shows the PPG pin configuration.
Table 12.1 Pin Configuration
Pin Name
I/O
Function
PO15
Output
Group 3 pulse output
PO14
Output
PO13
Output
PO12
Output
PO11
Output
PO10
Output
PO9
Output
PO8
Output
PO7
Output
PO6
Output
PO5
Output
PO4
Output
PO3
Output
PO2
Output
PO1
Output
PO0
Output
12.3
Group 2 pulse output
Group 1 pulse output
Group 0 pulse output
Register Descriptions
The PPG has the following registers.
• Next data enable register H (NDERH)
• Next data enable register L (NDERL)
• Output data register H (PODRH)
• Output data register L (PODRL)
• Next data register H (NDRH)
• Next data register L (NDRL)
• PPG output control register (PCR)
• PPG output mode register (PMR)
Rev.7.00 Mar. 18, 2009 page 633 of 1136
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Section 12 Programmable Pulse Generator (PPG)
12.3.1
Next Data Enable Registers H, L (NDERH, NDERL)
NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the
PPG, set the corresponding DDR to 1.
NDERH
Bit
Bit Name
Initial Value
R/W
Description
7
NDER15
0
R/W
Next Data Enable 15 to 8
6
NDER14
0
R/W
5
NDER13
0
R/W
4
NDER12
0
R/W
3
NDER11
0
R/W
When a bit is set to 1, the value in the
corresponding NDRH bit is transferred to the
PODRH bit by the selected output trigger. Values
are not transferred from NDRH to PODRH for
cleared bits.
2
NDER10
0
R/W
1
NDER9
0
R/W
0
NDER8
0
R/W
NDERL
Bit
Bit Name
Initial Value
R/W
Description
7
NDER7
0
R/W
Next Data Enable 7 to 0
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
When a bit is set to 1, the value in the
corresponding NDRL bit is transferred to the
PODRL bit by the selected output trigger. Values
are not transferred from NDRL to PODRL for
cleared bits.
2
NDER2
0
R/W
1
NDER1
0
R/W
0
NDER0
0
R/W
Rev.7.00 Mar. 18, 2009 page 634 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
12.3.2
Output Data Registers H, L (PODRH, PODRL)
PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse
output by NDER is read-only and cannot be modified.
PODRH
Bit
Bit Name
Initial Value
R/W
Description
7
POD15
0
R/W
Output Data Register 15 to 8
6
POD14
0
R/W
5
POD13
0
R/W
4
POD12
0
R/W
3
POD11
0
R/W
2
POD10
0
R/W
For bits which have been set to pulse output by
NDERH, the output trigger transfers NDRH values
to this register during PPG operation. While
NDERH is set to 1, the CPU cannot write to this
register. While NDERH is cleared, the initial output
value of the pulse can be set.
1
POD9
0
R/W
0
POD8
0
R/W
PODRL
Bit
Bit Name
Initial Value
R/W
Description
7
POD7
0
R/W
Output Data Register 7 to 0
6
POD6
0
R/W
5
POD5
0
R/W
4
POD4
0
R/W
3
POD3
0
R/W
2
POD2
0
R/W
For bits which have been set to pulse output by
NDERL, the output trigger transfers NDRL values
to this register during PPG operation. While
NDERL is set to 1, the CPU cannot write to this
register. While NDERL is cleared, the initial output
value of the pulse can be set.
1
POD1
0
R/W
0
POD0
0
R/W
12.3.3
Next Data Registers H, L (NDRH, NDRL)
NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on
whether pulse output groups have the same output trigger or different output triggers.
Rev.7.00 Mar. 18, 2009 page 635 of 1136
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Section 12 Programmable Pulse Generator (PPG)
NDRH
If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR15
0
R/W
Next Data Register 15 to 8
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
If pulse output groups 2 and 3 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR15
0
R/W
Next Data Register 15 to 12
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
3
to
0
—
All 1
—
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 1
—
Reserved
3
NDR11
0
R/W
Next Data Register 11 to 8
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
Reserved
1 is always read and write is disabled.
1 is always read and write is disabled.
Rev.7.00 Mar. 18, 2009 page 636 of 1136
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Section 12 Programmable Pulse Generator (PPG)
NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR7
0
R/W
Next Data Register 7 to 0
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR7
0
R/W
Next Data Register 7 to 4
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
3
to
0
—
All 1
—
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 1
—
Reserved
3
NDR3
0
R/W
Next Data Register 3 to 0
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Reserved
1 is always read and write is disabled.
1 is always read and write is disabled.
Rev.7.00 Mar. 18, 2009 page 637 of 1136
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Section 12 Programmable Pulse Generator (PPG)
12.3.4
PPG Output Control Register (PCR)
PCR selects output trigger signals on a group-by-group basis. For details on output trigger
selection, refer to section 12.3.5, PPG Output Mode Register (PMR).
Bit
Bit Name
Initial Value
R/W
Description
7
G3CMS1
1
R/W
Group 3 Compare Match Select 1 and 0
6
G3CMS0
1
R/W
Select output trigger of pulse output group 3.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
5
4
G2CMS1
1
R/W
Group 2 Compare Match Select 1 and 0
G2CMS0
1
R/W
Select output trigger of pulse output group 2.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
3
G1CMS1
1
R/W
Group 1 Compare Match Select 1 and 0
2
G1CMS0
1
R/W
Select output trigger of pulse output group 1.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
1
G0CMS1
1
R/W
Group 0 Compare Match Select 1 and 0
0
G0CMS0
1
R/W
Select output trigger of pulse output group 0.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
Rev.7.00 Mar. 18, 2009 page 638 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
12.3.5
PPG Output Mode Register (PMR)
PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a
low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If
non-overlapping operation is selected, PPG updates its output values at compare match A or B of
the TPU that becomes the output trigger. For details, refer to section 12.4.4, Non-Overlapping
Pulse Output.
Bit
Bit Name
Initial Value
R/W
7
G3INV
1
R/W
Description
Group 3 Inversion
Selects direct output or inverted output for pulse
output group 3.
0: Inverted output
1: Direct output
6
G2INV
1
R/W
Group 2 Inversion
Selects direct output or inverted output for pulse
output group 2.
0: Inverted output
1: Direct output
5
G1INV
1
R/W
Group 1 Inversion
Selects direct output or inverted output for pulse
output group 1.
0: Inverted output
1: Direct output
4
G0INV
1
R/W
Group 0 Inversion
Selects direct output or inverted output for pulse
output group 0.
0: Inverted output
1: Direct output
Rev.7.00 Mar. 18, 2009 page 639 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
Bit
Bit Name
Initial Value
R/W
Description
3
G3NOV
0
R/W
Group 3 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 3.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the selected
TPU channel)
2
G2NOV
0
R/W
Group 2 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 2.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the selected
TPU channel)
1
G1NOV
0
R/W
Group 1 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 1.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the selected
TPU channel)
0
G0NOV
0
R/W
Group 0 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 0.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the selected
TPU channel)
Rev.7.00 Mar. 18, 2009 page 640 of 1136
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Section 12 Programmable Pulse Generator (PPG)
12.4
Operation
Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is
determined by its corresponding PODR initial setting. When the compare match event specified
by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output
values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR
before the next compare match.
DDR
NDER
Q
Output trigger signal
C
Q PODR D
Q NDR D
Internal data bus
Pulse output pin
Normal output/inverted output
Figure 12.2 Overview Diagram of PPG
Rev.7.00 Mar. 18, 2009 page 641 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
12.4.1
Output Timing
If pulse output is enabled, NDR contents are transferred to PODR and output when the specified
compare match event occurs. Figure 12.3 shows the timing of these operations for the case of
normal output in groups 2 and 3, triggered by compare match A.
φ
N
TCNT
TGRA
N+1
N
Compare match
A signal
n
NDRH
PODRH
PO8 to PO15
m
n
m
n
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example)
Rev.7.00 Mar. 18, 2009 page 642 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
12.4.2
Sample Setup Procedure for Normal Pulse Output
Figure 12.4 shows a sample procedure for setting up normal pulse output.
Normal PPG output
Select TGR functions
[1]
Set TGRA value
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
Enable pulse output
[6]
Select output trigger
[7]
[1] Set TIOR to make TGRA an output
compare register (with output
disabled).
[2] Set the PPG output trigger period.
TPU setup
Port and
PPG setup
TPU setup
Set next pulse
output data
[8]
Start counter
[9]
Compare match?
No
[3] Select the counter clock source with
bits TPSC2 to TPSC0 in TCR.
Select the counter clear source with
bits CCLR2 to CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC or DMAC can also be set
up to transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to 1.
[7] Select the TPU compare match
event to be used as the output
trigger in PCR.
[8] Set the next pulse output values in
NDR.
Yes
Set next pulse
output data
[10]
[9] Set the CST bit in TSTR to 1 to start
the TCNT counter.
[10] At each TGIA interrupt, set the next
output values in NDR.
Figure 12.4 Setup Procedure for Normal Pulse Output (Example)
Rev.7.00 Mar. 18, 2009 page 643 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
12.4.3
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output.
TCNT value
Compare match
TCNT
TGRA
H'0000
Time
80
NDRH
PODRH
00
C0
80
40
C0
60
40
20
60
30
20
10
30
18
10
08
18
88
08
80
88
C0
80
40
C0
PO15
PO14
PO13
PO12
PO11
Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output)
1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set
a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in
TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.
2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Write output data H'80 in NDRH.
3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH
contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the
next output data (H'C0) in NDRH.
4. Five-phase pulse output (one or two phases active at a time) can be obtained subsequently by
writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts.
If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained
without imposing a load on the CPU.
Rev.7.00 Mar. 18, 2009 page 644 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
12.4.4
Non-Overlapping Pulse Output
During non-overlapping operation, transfer from NDR to PODR is performed as follows:
• NDR bits are always transferred to PODR bits at compare match A.
• At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 12.6 illustrates the non-overlapping pulse output operation.
DDR
NDER
Q
Compare match A
Compare match B
Pulse
output
pin
C
Q PODR D
Q NDR D
Internal data bus
Normal output/inverted output
Figure 12.6 Non-Overlapping Pulse Output
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A.
The NDR contents should not be altered during the interval from compare match B to compare
match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next
data must be written before the next compare match B occurs.
Figure 12.7 shows the timing of this operation.
Rev.7.00 Mar. 18, 2009 page 645 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
Compare match A
Compare match B
Write to NDR
Write to NDR
NDR
PODR
0 output
0/1 output
Write to NDR
Do not write here
to NDR here
0 output 0/1 output
Do not write
to NDR here
Write to NDR
here
Figure 12.7 Non-Overlapping Operation and NDR Write Timing
Rev.7.00 Mar. 18, 2009 page 646 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
12.4.5
Sample Setup Procedure for Non-Overlapping Pulse Output
Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output.
Non-overlapping
pulse output
Select TGR functions
[1]
Set TGR values
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
Enable pulse output
[6]
Select output trigger
[7]
Set non-overlapping groups
[8]
Set next pulse
output data
[9]
Start counter
[10]
TPU setup
PPG setup
TPU setup
Compare match A?
[2] Set the pulse output trigger period
in TGRB and the non-overlap
period in TGRA.
[3] Select the counter clock source
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR2 to CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC or DMAC can also be set
up to transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to
1.
[7] Select the TPU compare match
event to be used as the pulse
output trigger in PCR.
No
[8] In PMR, select the groups that will
operate in non-overlap mode.
Yes
Set next pulse
output data
[1] Set TIOR to make TGRA and
TGRB an output compare registers
(with output disabled).
[11]
[9] Set the next pulse output values in
NDR.
[10] Set the CST bit in TSTR to 1 to
start the TCNT counter.
[11] At each TGIA interrupt, set the next
output values in NDR.
Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
Rev.7.00 Mar. 18, 2009 page 647 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
12.4.6
Example of Non-Overlapping Pulse Output (Example of Four-Phase
Complementary Non-Overlapping Output)
Figure 12.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRH
Time
95
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
Non-overlap margin
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
Rev.7.00 Mar. 18, 2009 page 648 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are
output compare registers. Set the trigger period in TGRB and the non-overlap margin in
TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1
to enable the TGIA interrupt.
2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.
Write output data H'95 in NDRH.
3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs,
outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0
to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt
handling routine writes the next output data (H'65) in NDRH.
4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by
writing H'59, H'56, H'95... at successive TGIA interrupts.
If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained
without imposing a load on the CPU.
Rev.7.00 Mar. 18, 2009 page 649 of 1136
REJ09B0109-0700
Section 12 Programmable Pulse Generator (PPG)
12.4.7
Inverted Pulse Output
If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the
inverse of the PODR contents can be output.
Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the
settings of figure 12.9.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRL
Time
95
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 12.10 Inverted Pulse Output (Example)
Rev.7.00 Mar. 18, 2009 page 650 of 1136
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65
Section 12 Programmable Pulse Generator (PPG)
12.4.8
Pulse Output Triggered by Input Capture
Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA
functions as an input capture register in the TPU channel selected by PCR, pulse output will be
triggered by the input capture signal.
Figure 12.11 shows the timing of this output.
φ
TIOC pin
Input capture
signal
NDR
N
PODR
M
PO
M
N
N
Figure 12.11 Pulse Output Triggered by Input Capture (Example)
12.5
Usage Notes
12.5.1
Module Stop Mode Setting
PPG operation can be disabled or enabled using the module stop control register. The initial value
is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 24, Power-Down Modes.
12.5.2
Operation of Pulse Output Pins
Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by
another peripheral function is enabled, the corresponding pins cannot be used for pulse output.
Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage
of the pins.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
Rev.7.00 Mar. 18, 2009 page 651 of 1136
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Section 12 Programmable Pulse Generator (PPG)
Rev.7.00 Mar. 18, 2009 page 652 of 1136
REJ09B0109-0700
Section 13 8-Bit Timers (TMR)
Section 13 8-Bit Timers (TMR)
This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit
counter. The 8-bit timer module can be used to count external events and be used as a
multifunction timer in a variety of applications, such as generation of counter reset, interrupt
requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two
registers.
13.1
Features
• Selection of four clock sources
The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an
external clock input
• Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or by an external reset signal
• Timer output control by a combination of two compare match signals
The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to generate output waveforms with an arbitrary duty
cycle or PWM output
• Provision for cascading of two channels (TMR_0 and TMR_1)
Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the
lower 8 bits (16-bit count mode)
TMR_1 can be used to count TMR_0 compare matches (compare match count mode)
• Three independent interrupts
Compare match A and B and overflow interrupts can be requested independently
• A/D converter conversion start trigger can be generated
TIMH260A_000020020400
Rev.7.00 Mar. 18, 2009 page 653 of 1136
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Section 13 8-Bit Timers (TMR)
Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
External clock source
TMCI0
TMCI1
Internal clock sources
TMR_0 TMR_1
φ/8
φ/8
φ/64
φ/64
φ/8192
φ/8192
Clock 1
Clock 0
Clock select
TCORA_0
Compare match A1
Compare match A0 Comparator A_0
Overflow 1
Overflow 0
TMO0
TMRI0
TCNT_0
TCORA_1
Comparator A_1
TCNT_1
Clear 1
TMO1
TMRI1
Control logic
Compare match B1
Compare match B0 Comparator B_0
A/D
conversion
start request
signal
Comparator B_1
TCORB_0
TCORB_1
TCSR_0
TCSR_1
TCR_0
TCR_1
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals
Legend:
TCORA_0
TCORB_0
TCNT_0
TCSR_0
TCR_0
: Time constant register A_0
: Time constant register B_0
: Timer counter_0
: Timer control/status register_0
: Timer control register_0
TCORA_1
TCORB_1
TCNT_1
TCSR_1
TCR_1
: Time constant register A_1
: Time constant register B_1
: Timer counter_1
: Timer control/status register_1
: Timer control register_1
Figure 13.1 Block Diagram of 8-Bit Timer Module
Rev.7.00 Mar. 18, 2009 page 654 of 1136
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Internal bus
Clear 0
Section 13 8-Bit Timers (TMR)
13.2
Input/Output Pins
Table 13.1 shows the pin configuration of the 8-bit timer module.
Table 13.1 Pin Configuration
Channel
Name
Symbol
I/O
Function
0
Timer output pin
TMO0
Output
Outputs at compare match
Timer clock input pin
TMCI0
Input
Inputs external clock for counter
Timer reset input pin
TMRI0
Input
Inputs external reset to counter
Timer output pin
TMO1
Output
Outputs at compare match
Timer clock input pin
TMCI1
Input
Inputs external clock for counter
Timer reset input pin
TMRI1
Input
Inputs external reset to counter
1
13.3
Register Descriptions
The 8-bit timer module has the following registers. For details on the module stop control register,
refer to section 24.1.2, Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).
• Timer counter_0 (TCNT_0)
• Time constant register A_0 (TCORA_0)
• Time constant register B_0 (TCORB_0)
• Timer control register_0 (TCR_0)
• Timer control/status register_0 (TCSR_0)
• Timer counter_1 (TCNT_1)
• Time constant register A_1 (TCORA_1)
• Time constant register B_1 (TCORB_1)
• Timer control register_1 (TCR_1)
• Timer control/status register_1 (TCSR_1)
Rev.7.00 Mar. 18, 2009 page 655 of 1136
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Section 13 8-Bit Timers (TMR)
13.3.1
Timer Counter (TCNT)
TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be
accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a
clock. TCNT can be cleared by an external reset input or by a compare match signal A or B.
Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When
TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00.
13.3.2
Time Constant Register A (TCORA)
TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction.
The value in TCORA is continually compared with the value in TCNT. When a match is detected,
the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled
during the T2 state of a TCORA write cycle.
The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match A) and the settings of bits OS1 and OS0 in TCSR.
TCORA is initialized to H'FF.
13.3.3
Time Constant Register B (TCORB)
TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag in TCSR is set to 1. Note, however, that comparison is disabled during
the T2 state of a TCOBR write cycle.
The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match B) and the settings of bits OS3 and OS2 in TCSR.
TCORB is initialized to H'FF.
Rev.7.00 Mar. 18, 2009 page 656 of 1136
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Section 13 8-Bit Timers (TMR)
13.3.4
Timer Control Register (TCR)
TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts.
Bit
Bit Name
Initial Value
R/W
7
CMIEB
0
R/W
Description
Compare Match Interrupt Enable B
Selects whether CMFB interrupt requests
(CMIB) are enabled or disabled when the CMFB
flag in TCSR is set to 1.
0: CMFB interrupt requests (CMIB) are disabled
1: CMFB interrupt requests (CMIB) are enabled
6
CMIEA
0
R/W
Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests
(CMIA) are enabled or disabled when the CMFA
flag in TCSR is set to 1.
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
5
OVIE
0
R/W
Timer Overflow Interrupt Enable
Selects whether OVF interrupt requests (OVI)
are enabled or disabled when the OVF flag in
TCSR is set to 1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
4
3
CCLR1
CCLR0
0
0
R/W
R/W
Counter Clear 1 and 0
These bits select the method by which TCNT is
cleared.
00: Clearing is disabled
01: Clear by compare match A
10: Clear by compare match B
11: Clear by rising edge of external reset input
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
These bits select the clock input to TCNT and
count condition. See table 13.2.
Rev.7.00 Mar. 18, 2009 page 657 of 1136
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Section 13 8-Bit Timers (TMR)
Table 13.2 Clock Input to TCNT and Count Condition
TCR
Channel
TMR_0
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
0
Clock input disabled
1
Internal clock, counted at falling edge of φ/8
0
Internal clock, counted at falling edge of φ/64
1
Internal clock, counted at falling edge of φ/8192
1
TMR_1
1
0
0
Count at TCNT_1 overflow signal*
0
0
0
Clock input disabled
1
Internal clock, counted at falling edge of φ/8
0
Internal clock, counted at falling edge of φ/64
1
1
All
Note:
*
1
0
0
Internal clock, counted at falling edge of φ/8192
Count at TCNT_0 compare match A*
1
0
1
External clock, counted at rising edge
1
0
External clock, counted at falling edge
1
1
External clock, counted at both rising and falling edges
If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this
setting.
Rev.7.00 Mar. 18, 2009 page 658 of 1136
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Section 13 8-Bit Timers (TMR)
13.3.5
Timer Control/Status Register (TCSR)
TCSR displays status flags, and controls compare match output.
TCSR_0
Bit
7
Bit Name
CMFB
Initial Value
R/W
Description
0
R/(W)*
Compare Match Flag B
[Setting condition]
•
Set when TCNT matches TCORB
[Clearing conditions]
6
CMFA
0
R/(W)*
•
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt while
DISEL bit of MRB in DTC is 0
Compare Match Flag A
[Setting condition]
•
Set when TCNT matches TCORA
[Clearing conditions]
5
OVF
0
R/(W)*
•
Cleared by reading CMFA when CMFA = 1,
then writing 0 to CMFA
•
When DTC is activated by CMIA interrupt while
DISEL bit of MRB in DTC is 0
Timer Overflow Flag
[Setting condition]
Set when TCNT overflows from H'FF to H'00
[Clearing condition]
Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
4
ADTE
0
R/W
A/D Trigger Enable
Selects enabling or disabling of A/D converter start
requests by compare match A.
0: A/D converter start requests by compare match
A are disabled
1: A/D converter start requests by compare match
A are enabled
Rev.7.00 Mar. 18, 2009 page 659 of 1136
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Section 13 8-Bit Timers (TMR)
Bit
Bit Name
Initial Value
R/W
Description
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3 and 2
These bits select a method of TMO pin output
when compare match B of TCORB and TCNT
occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B
occurs (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1 and 0
These bits select a method of TMO pin output
when compare match A of TCORA and TCNT
occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A
occurs (toggle output)
Note:
*
Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.7.00 Mar. 18, 2009 page 660 of 1136
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Section 13 8-Bit Timers (TMR)
TCSR_1
Bit
7
Bit Name
CMFB
Initial Value
R/W
Description
0
R/(W)*
Compare Match Flag B
[Setting condition]
•
Set when TCNT matches TCORB
[Clearing conditions]
6
CMFA
0
R/(W)*
•
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt while
DISEL bit of MRB in DTC is 0
Compare Match Flag A
[Setting condition]
•
Set when TCNT matches TCORA
[Clearing conditions]
5
OVF
0
R/(W)*
•
Cleared by reading CMFA when CMFA = 1,
then writing 0 to CMFA
•
When DTC is activated by CMIA interrupt while
DISEL bit of MRB in DTC is 0
Timer Overflow Flag
[Setting condition]
•
Set when TCNT overflows from H'FF to H'00
[Clearing condition]
•
4
—
1
R
Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
Reserved
This bit is always read as 1 and cannot be
modified.
Rev.7.00 Mar. 18, 2009 page 661 of 1136
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Section 13 8-Bit Timers (TMR)
Bit
Bit Name
Initial Value
R/W
Description
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3 and 2
These bits select a method of TMO pin output
when compare match B of TCORB and TCNT
occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B
occurs (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1 and 0
These bits select a method of TMO pin output
when compare match A of TCORA and TCNT
occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A
occurs (toggle output)
Note:
*
Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.7.00 Mar. 18, 2009 page 662 of 1136
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Section 13 8-Bit Timers (TMR)
13.4
Operation
13.4.1
Pulse Output
Figure 13.2 shows an example that the 8-bit timer is used to generate a pulse output with a
selected duty cycle. The control bits are set as follows:
[1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is
cleared at a TCORA compare match.
[2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA
compare match and to 0 at a TCORB compare match.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with
a pulse width determined by TCORB. No software intervention is required.
TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 13.2 Example of Pulse Output
Rev.7.00 Mar. 18, 2009 page 663 of 1136
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Section 13 8-Bit Timers (TMR)
13.5
Operation Timing
13.5.1
TCNT Incrementation Timing
Figure 13.3 shows the count timing for internal clock input. Figure 13.4 shows the count timing
for external clock signal. Note that the external clock pulse width must be at least 1.5 states for
incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The
counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
Clock input
to TCNT
TCNT
N–1
N
N+1
Figure 13.3 Count Timing for Internal Clock Input
φ
External clock
input pin
Clock input
to TCNT
TCNT
N–1
N
Figure 13.4 Count Timing for External Clock Input
Rev.7.00 Mar. 18, 2009 page 664 of 1136
REJ09B0109-0700
N+1
Section 13 8-Bit Timers (TMR)
13.5.2
Timing of CMFA and CMFB Setting when Compare-Match Occurs
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT
match, the compare match signal is not generated until the next incrementation clock input.
Figure 13.5 shows this timing.
φ
TCNT
N
TCOR
N
N+1
Compare match
signal
CMF
Figure 13.5 Timing of CMF Setting
Rev.7.00 Mar. 18, 2009 page 665 of 1136
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Section 13 8-Bit Timers (TMR)
13.5.3
Timing of Timer Output when Compare-Match Occurs
When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR.
Figure 13.6 shows the timing when the output is set to toggle at compare match A.
φ
Compare match A
signal
Timer output pin
Figure 13.6 Timing of Timer Output
13.5.4
Timing of Compare Match Clear
TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and
CCLR0 bits in TCR. Figure 13.7 shows the timing of this operation.
φ
Compare match
signal
TCNT
N
Figure 13.7 Timing of Compare Match Clear
Rev.7.00 Mar. 18, 2009 page 666 of 1136
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H'00
Section 13 8-Bit Timers (TMR)
13.5.5
Timing of TCNT External Reset
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 13.8
shows the timing of this operation.
φ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 13.8 Timing of Clearance by External Reset
13.5.6
Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.9
shows the timing of this operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 13.9 Timing of OVF Setting
Rev.7.00 Mar. 18, 2009 page 667 of 1136
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Section 13 8-Bit Timers (TMR)
13.6
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match count mode). In this case, the timer operates as below.
13.6.1
16-Bit Counter Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
[1] Setting of compare match flags
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.
[2] Counter clear specification
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the
16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match
event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter
clear by the TMRI0 pin has also been set.
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
cleared independently.
[3] Pin output
• Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the
16-bit compare match conditions.
• Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the
lower 8-bit compare match conditions.
13.6.2
Compare Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A’s for channel
0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clear are in accordance with the
settings for each channel.
Rev.7.00 Mar. 18, 2009 page 668 of 1136
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Section 13 8-Bit Timers (TMR)
13.7
Interrupt Sources
13.7.1
Interrupt Sources and DTC Activation
There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are
shown in table 13.3. Each interrupt source is set as enabled or disabled by the corresponding
interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the
interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB
interrupts.
Table 13.3 8-Bit Timer Interrupt Sources
Name
Interrupt Source
Interrupt Flag
DTC Activation
Priority
CMIA0
TCORA_0 compare match
CMFA
Possible
High
CMIB0
TCORB_0 compare match
CMFB
Possible
OVI0
TCNT_0 overflow
OVF
Not possible
Low
CMIA1
TCORA_1 compare match
CMFA
Possible
High
CMIB1
TCORB_1 compare match
CMFB
Possible
OVI1
TCNT_1 overflow
OVF
Not possible
13.7.2
Low
A/D Converter Activation
The A/D converter can be activated only by TMR_0 compare match A.
If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of TMR_0
compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer
conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is
started.
Rev.7.00 Mar. 18, 2009 page 669 of 1136
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Section 13 8-Bit Timers (TMR)
13.8
Usage Notes
13.8.1
Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 13.10 shows this operation.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 13.10 Contention between TCNT Write and Clear
Rev.7.00 Mar. 18, 2009 page 670 of 1136
REJ09B0109-0700
Section 13 8-Bit Timers (TMR)
13.8.2
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 13.11 shows this operation.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 13.11 Contention between TCNT Write and Increment
Rev.7.00 Mar. 18, 2009 page 671 of 1136
REJ09B0109-0700
Section 13 8-Bit Timers (TMR)
13.8.3
Contention between TCOR Write and Compare Match
During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs as shown in figure 13.12.
When using the TMR, ICR input capture is in contention with compare match in the same way as
writes to the TCOR. In such cases input capture has precedence and the compare match signal is
inhibited.
TCOR write cycle by CPU
T1
T2
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data
Compare match signal
Inhibited
Figure 13.12 Contention between TCOR Write and Compare Match
Rev.7.00 Mar. 18, 2009 page 672 of 1136
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Section 13 8-Bit Timers (TMR)
13.8.4
Contention between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 13.4.
Table 13.4 Timer Output Priorities
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
13.8.5
Low
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 13.5 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in
table 13.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge. This increments TCNT.
The erroneous incrementation can also happen when switching between internal and external
clocks.
Rev.7.00 Mar. 18, 2009 page 673 of 1136
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Section 13 8-Bit Timers (TMR)
Table 13.5 Switching of Internal Clock and TCNT Operation
No.
1
Timing of Switchover
by Means of CKS1
TCNT Clock Operation
and CKS0 Bits
Switching from
1
low to low*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
CKS bit write
2
Switching from
2
low to high*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit write
3
Switching from
3
high to low*
Clock before
swichover
Clock after
swichover
*4
TCNT clock
TCNT
N
N+1
CKS bit write
Rev.7.00 Mar. 18, 2009 page 674 of 1136
REJ09B0109-0700
N+2
Section 13 8-Bit Timers (TMR)
No.
4
Timing of Switchover
by Means of CKS1
TCNT Clock Operation
and CKS0 Bits
Switching from high
to high
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit write
Notes: 1.
2.
3.
4.
13.8.6
Includes switching from low to stop, and from stop to low.
Includes switching from stop to high.
Includes switching from high to stop.
Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
Mode Setting with Cascaded Connection
If 16-bit counter mode and compare match count mode are specified at the same time, input clocks
for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter
and compare match count modes simultaneously.
13.8.7
Interrupts in Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC and DMAC activation source. Interrupts should
therefore be disabled before entering module stop mode.
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Section 13 8-Bit Timers (TMR)
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Section 14 Watchdog Timer (WDT)
Section 14 Watchdog Timer (WDT)
The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
At the same time, the WDT can also generate an internal reset signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagram of the WDT is shown in figure 14.1.
14.1
Features
• Selectable from eight counter input clocks
• Switchable between watchdog timer mode and interval timer mode
In watchdog timer mode
• If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not
the entire chip is reset at the same time.
In interval timer mode
• If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
WDT0101A_010020020400
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Section 14 Watchdog Timer (WDT)
Clock
WDTOVF
Internal reset signal*
Clock
select
Reset
control
RSTCSR
TCNT
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
sources
TSCR
Module bus
Bus
interface
Internal bus
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
WDT
Legend:
: Timer control/status register
TCSR
: Timer counter
TCNT
RSTCSR : Reset control/status register
Note: * An internal reset signal can be generated by the register setting.
Figure 14.1 Block Diagram of WDT
14.2
Input/Output Pin
Table 14.1 shows the WDT pin configuration.
Table 14.1 Pin Configuration
Name
Symbol
I/O
Function
Watchdog timer overflow
WDTOVF
Output
Outputs counter overflow signal in watchdog
timer mode
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Section 14 Watchdog Timer (WDT)
14.3
Register Descriptions
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR have to be written to in a method different from normal registers. For details, refer to
section 14.6.1, Notes on Register Access.
• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)
14.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
TCSR is cleared to 0.
14.3.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
Bit
7
Bit Name
OVF
Initial Value
R/W
0
R/(W)*
Description
Overflow Flag
Indicates that TCNT has overflowed in interval
timer mode. Only a write of 0 is permitted, to clear
the flag.
[Setting condition]
When TCNT overflows in interval timer mode
(changes from H'FF to H'00)
When internal reset request generation is selected
in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
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Section 14 Watchdog Timer (WDT)
Bit
Bit Name
Initial Value
R/W
Description
6
WT/IT
0
R/W
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: Interval timer mode
When TCNT overflows, an interval timer interrupt
(WOVI) is requested.
1: Watchdog timer mode
When TCNT overflows, the WDTOVF signal is
output.
5
TME
0
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and
is initialized to H'00.
4, 3
—
All 1
—
Reserved
These bits are always read as 1 and cannot be
modified.
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
Selects the clock source to be input to TCNT. The
overflow frequency for φ = 20 MHz is enclosed in
parentheses.
000: Clock φ/2 (frequency: 25.6 μs)
001: Clock φ/64 (frequency: 819.2 μs)
010: Clock φ/128 (frequency: 1.6 ms)
011: Clock φ/512 (frequency: 6.6 ms)
100: Clock φ/2048 (frequency: 26.2 ms)
101: Clock φ/8192 (frequency: 104.9 ms)
110: Clock φ/32768 (frequency: 419.4 ms)
111: Clock φ/131072 (frequency: 1.68 s)
Note:
*
Only a write of 0 is permitted, to clear the flag.
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Section 14 Watchdog Timer (WDT)
14.3.3
Reset Control/Status Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by overflows.
Bit
7
Bit Name
WOVF
Initial Value
R/W
Description
0
R/(W)*
Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be written.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, and
then writing 0 to WOVF
6
RSTE
0
R/W
Reset Enable
Specifies whether or not a reset signal is generated
in the chip if TCNT overflows during watchdog
timer operation.
0: Reset signal is not generated even if TCNT
overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
1: Reset signal is generated if TCNT overflows
5
—
0
R/W
Reserved
Can be read and written, but does not affect
operation.
4
to
0
—
Note:
*
All 1
—
Reserved
These bits are always read as 1 and cannot be
modified.
Only a write of 0 is permitted, to clear the flag.
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Section 14 Watchdog Timer (WDT)
14.4
Operation
14.4.1
Watchdog Timer Mode
To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1.
If TCNT overflows without being rewritten because of a system crash or other error, the
WDTOVF signal is output.
This ensures that TCNT does not overflow while the system is operating normally. Software must
prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before
overflow occurs. This WDTOVF signal can be used to reset the chip internally in watchdog timer
mode.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets this LSI
internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input
to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset
has priority and the WOVF bit in RSTCSR is cleared to 0.
The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0.
The internal reset signal is output for 518 states.
When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT
overflows when 1 is set in the RSTE bit in RSTCSR, an internal reset signal is generated to the
entire chip.
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Section 14 Watchdog Timer (WDT)
TCNT count
Overflow
H'FF
Time
H'00
WT/IT=1
TME=1
H'00 written
to TCNT
WOVF=1
WDTOVF and
internal reset are
generated
WT/IT=1
TME=1
H'00 written
to TCNT
WDTOVF signal
132 states*2
Internal reset signal*1
518 states
Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated.
2. 130 states when the RSTE bit is cleared to 0.
Figure 14.2 Operation in Watchdog Timer Mode
14.4.2
Interval Timer Mode
To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1.
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows. Therefore, an interrupt can be generated at intervals.
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested
at the same time the OVF bit in the TCSR is set to 1.
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Section 14 Watchdog Timer (WDT)
TCNT count
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WOVI
WT/IT=0
TME=1
WOVI
WOVI
WOVI
Legend:
WOVI: Interval timer interrupt request generation
Figure 14.3 Operation in Interval Timer Mode
14.5
Interrupt Source
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 14.2 WDT Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
WOVI
TCNT overflow
OVF
Impossible
14.6
Usage Notes
14.6.1
Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT, TCSR, and RSTCSR
TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
Rev.7.00 Mar. 18, 2009 page 684 of 1136
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Section 14 Watchdog Timer (WDT)
TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition
shown in figure 14.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte
data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer
instruction cannot perform writing to RSTCSR.
The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0
to the WOVF bit, satisfy the lower condition shown in figure 14.4.
If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit.
To write to the RSTE bit, satisfy the above condition shown in figure 14.4. If satisfied, the transfer
instruction writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the
WOVF bit.
TCNT write or
Writing to RSTE bit in RSTCSR
15
Address: H'FFBC (TCNT)
H'FFBE (RSTCSR)
8
7
H'5A
0
Write data
TCSR write
Address: H'FFBC (TCSR)
15
8
7
H'A5
0
Write data
Writing 0 to WOVF bit in RSTCSR
Address: H'FFBE (RSTCSR)
15
8
7
H'A5
0
H'00
Writing to RSTE bit in RSTCSR
Address: H'FFBE (RSTCSR)
15
8
H'5A
7
0
Write data
Figure 14.4 Writing to TCNT, TCSR, and RSTCSR
Reading TCNT, TCSR, and RSTCSR
These registers are read in the same way as other registers. The read addresses are H'FFBC for
TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR.
Rev.7.00 Mar. 18, 2009 page 685 of 1136
REJ09B0109-0700
Section 14 Watchdog Timer (WDT)
14.6.2
Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write
cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this
operation.
TCNT write cycle
T1
T2
Next cycle
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 14.5 Contention between TCNT Write and Increment
14.6.3
Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
14.6.4
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.
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Section 14 Watchdog Timer (WDT)
14.6.5
Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer mode operation, but TCNT and TCSR of the WDT are reset.
TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that
a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,
read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.
14.6.6
System Reset by WDTOVF Signal
If the WDTOVF output signal is input to the RES pin, the chip will not be initialized correctly.
Make sure that the WDTOVF signal is not input logically to the RES pin.
To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 14.6.
This LSI
Reset input
Reset signal to entire system
RES
WDTOVF
Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example)
Rev.7.00 Mar. 18, 2009 page 687 of 1136
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Section 14 Watchdog Timer (WDT)
Rev.7.00 Mar. 18, 2009 page 688 of 1136
REJ09B0109-0700
Section 15 Serial Communication Interface (SCI, IrDA)
Section 15 Serial Communication Interface (SCI, IrDA)
This LSI has five independent serial communication interface (SCI) channels. The SCI can handle
both asynchronous and clocked synchronous serial communication. Serial data communication
can be carried out with standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA). A function is also provided for serial communication between processors (multiprocessor
communication function) in asynchronous mode. The SCI also supports an IC card (Smart Card)
interface conforming to ISO/IEC 7816-3 (Identification Card) as an asynchronous serial
communication interface extension function. One of the five SCI channels (SCI_0) can generate
an IrDA communication waveform conforming to IrDA specification version 1.0.
Figure 15.1 shows a block diagram of the SCI.
15.1
Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
External clock can be selected as a transfer clock source (except for in Smart Card interface
mode).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Four interrupt sources ⎯ transmit-end, transmit-data-empty, receive-data-full, and receive
error ⎯ that can issue requests. The transmit-data-empty interrupt and receive data full
interrupts can activate the data transfer controller (DTC) or DMA controller (DMAC).
• Module stop mode can be set
Asynchronous mode
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
SCI0021A_000020020400
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Section 15 Serial Communication Interface (SCI, IrDA)
• Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
• Average transfer rate generator (only for H8S/2378R Group): The following transfer rate can
be selected (SCI_2 only)
115.152 or 460.606 kbps at 10.667-MHz operation
115.196, 460.784, or 720 kbps at 16-MHz operation
720 kbps at 32-MHz operation
Clocked Synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart Card Interface
• Automatic transmission of error signal (parity error) in receive mode
• Error signal detection and automatic data retransmission in transmit mode
• Direct convention and inverse convention both supported
Rev.7.00 Mar. 18, 2009 page 690 of 1136
REJ09B0109-0700
Bus interface
Section 15 Serial Communication Interface (SCI, IrDA)
Module data bus
RDR
RxD
RSR
SCMR
SSR
SCR
SMR
SEMR
TDR
TSR
BRR
φ
Baud rate
generator
Transmission/
reception control
TxD
Parity generation
φ/4
φ/16
φ/64
Clock
Parity check
External clock
SCK
Legend:
RSR
RDR
TSR
TDR
SMR
SCR
SSR
SCMR
BRR
SEMR
Internal
data bus
TEI
TXI
RXI
ERI
: Receive shift register
: Receive data register
: Transmit shift register
: Transmit data register
: Serial mode register
: Serial control register
: Serial status register
: Smart card mode register
: Bit rate register
: Serial extension mode register (only in SCI_2)
Average transfer
rate generator
(SCI_2)
10.667-MHz operation
• 115.152 kbps
• 460.606 kbps
16-MHz operation
• 115.196 kbps
• 460.784 kbps
• 720 kbps
32-MHz operation
• 720 kbps
Figure 15.1 Block Diagram of SCI
Rev.7.00 Mar. 18, 2009 page 691 of 1136
REJ09B0109-0700
Section 15 Serial Communication Interface (SCI, IrDA)
15.2
Input/Output Pins
Table 15.1 shows the pin configuration of the serial communication interface.
Table 15.1 Pin Configuration
Channel
Pin Name*
I/O
Function
0
SCK0
I/O
Channel 0 clock input/output
RxD0/IrRxD
Input
Channel 0 receive data input (normal/IrDA)
TxD0/IrTxD
Output
Channel 0 transmit data output (normal/IrDA)
SCK1
I/O
Channel 1 clock input/output
RxD1
Input
Channel 1 receive data input
TxD1
Output
Channel 1 transmit data output
SCK2
I/O
Channel 2 clock input/output
RxD2
Input
Channel 2 receive data input
TxD2
Output
Channel 2 transmit data output
SCK3
I/O
Channel 3 clock input/output
RxD3
Input
Channel 3 receive data input
TxD3
Output
Channel 3 transmit data output
SCK4
I/O
Channel 4 clock input/output
RxD4
Input
Channel 4 receive data input
TxD4
Output
Channel 4 transmit data output
1
2
3
4
Note:
*
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
Rev.7.00 Mar. 18, 2009 page 692 of 1136
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3
Register Descriptions
The SCI has the following registers. The serial mode register (SMR), serial status register (SSR),
and serial control register (SCR) are described separately for normal serial communication
interface mode and Smart Card interface mode because their bit functions partially differ.
• Receive shift register_0 (RSR_0)
• Transmit shift register_0 (TSR_0)
• Receive data register_0 (RDR_0)
• Transmit data register_0 (TDR_0)
• Serial mode register_0 (SMR_0)
• Serial control register_0 (SCR_0)
• Serial status register_0 (SSR_0)
• Smart card mode register_0 (SCMR_0)
• Bit rate register_0 (BRR_0)
• IrDA control register_0 (IrCR_0)
• Receive shift register_1 (RSR_1)
• Transmit shift register_1 (TSR_1)
• Receive data register_1 (RDR_1)
• Transmit data register_1 (TDR_1)
• Serial mode register_1 (SMR_1)
• Serial control register_1 (SCR_1)
• Serial status register_1 (SSR_1)
• Smart card mode regis