MP38875 15A, 16V, 800kHz Step-Down Converter with Synchronous Gate Driver The Future of Analog IC Technology DESCRIPTION FEATURES The MP38875 is a monolithic step-down switch mode converter with a built in internal power MOSFET. It achieves 15A continuous output current over a wide input supply range with excellent load and line regulation. • • • • • Current mode operation provides fast transient response and eases loop stabilization. • Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. The MP38875 requires a minimum number of readily available standard external components and is available in a 20-pin 3mm x 4mm QFN package. The MP38875 is ideal for a wide range of applications including distributed power systems, pre-regulator for linear regulators, compact DCDC regulators for PCB space limited platforms. Wide 4.5V to 16V Operating Input Range 15A Output Current 25mΩ Internal Power MOSFET Switch Synchronous Gate Driver Synch from 300KHz to > 1MHz External Clock or 800KHz Fixed Switching Frequency Synch Output to Drive Another Regulator in Phase-Shift Operation Feedback Voltage Accuracy: 2% Programmable Soft-Start Startup Tracking EN and Power Good for Power Sequencing Cycle-by-Cycle Over Current Protection Thermal Shutdown Output Adjustable from 0.8V to 12V Stable with Low ESR Output Ceramic Capacitors Available in a 3mm x 4mm QFN Package • • • • • • • • • APPLICATIONS • • • Distributed Power Systems Pre-Regulator for Linear Regulators Compact DC-DC Regulator for PCB Space Limited Platforms “MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VCC Efficiency vs. Output Current VIN=12V,VO=1.8V System IN PG C1 22uF 25V CB 1uF SW COMP R3 C6 C3 VCC SS/TRK MP38875 EN 90 VOUT 1.8V/15A SYNCOUT C2 100uF 6.3V 80 70 60 50 40 30 SYNCIN MP38875 Rev. 0.9 11/20/2009 L1 0.72uH BG FB OFF ON 100 BST EFFICIENCY (%) VIN GND 20 0 2 4 6 8 10 12 14 16 IOUT (A) www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 1 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER ABSOLUTE MAXIMUM RATINGS (1) PACKAGE REFERENCE Supply Voltage VIN ....................................... 18V VSW....................... –0.3V (-5V for < 10ns) to 19V VBS ....................................................... VSW + 6V All Other Pins................................. –0.3V to +6V Junction Temperature...............................150°C Lead Temperature ....................................260°C Storage Temperature ..............–65°C to +150°C TOP VIEW PIN 1 ID GND GATE VIN 20 19 18 VCC 1 17 SYNCOUT 2 16 SYNCIN 3 15 EN 4 SS/TRK 5 13 FB 6 12 COMP 7 VIN 14 SW Recommended Operating Conditions Supply Voltage VIN ........................... 4.5V to 16V Output Voltage VOUT ................... 0.8V to VIN -4V Operating Temperature .............–40°C to +85°C 11 8 9 Thermal Resistance 10 (3) θJA θJC QFN (3mm x 4mm) ................. 48 ...... 11... °C/W PG BST VIN * (2) Part Number* Package MP38875DL 3mm x 4mm QFN Temperature Top Marking –40°C to +85°C 3887 Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on JESD51-7 4-layer board. For Tape & Reel, add suffix –Z (e.g. MP38875DL–Z) For RoHS compliant packaging, add suffix –LF (e.g. MP38875DL–LF–Z) ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25°C, unless otherwise noted. Parameters Symbol Feedback Voltage VFB Feedback Current Switch On Resistance (4) Switch Leakage Current Limit (4) Oscillator Frequency Fold-back Frequency Maximum Duty Cycle Minimum On Time(4) Soft-Start Charging Current Maximum COMP Level Gain of Error Amplifier Error Amplifier Sink Current Error Amplifier Source Current Power Good Ramp Up Threshold Power Good Ramp Down Threshold IFB MP38875 Rev. 0.9 11/20/2009 Condition 4.5V ≤ VIN ≤ 16V VFB = 0.8V Min Typ Max 0.794 0.810 0.826 RDS(ON) VEN = 0V, VSW = 0V fSW tON ISS VCOMP_MAX GEA VFB = 0.6V, SYNCIN = 0V VFB = 0V VFB = 0.6V VSS = 0V VFB = 0.6V VCOMP = 1.5V VCOMP = 1.5V VCOMP = 1.5V www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 10 25 0.1 21 800 200 90 100 8 4.4 2 –270 +270 90 85 10 Units V nA mΩ µA A KHz KHz % ns µA V mA/V µA µA % % 2 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25°C, unless otherwise noted. Parameters Power Good Delay Power Good Sink Current Capability Power Good Leakage Current VCC Tolerance VCC Regulation Sync Frequency SYNCIN Bias Current SYNCIN Logic High Voltage SYNCIN Logic Low Voltage Symbol Condition VPG IPG_LEAK VCC Min Sink 4mA VPG = 3.3V ICC = 0mA ICC = 0~20mA FSYNC ISYNCIN Typ 20 Max 0.4 10 5.3 5 0.3 1 10 2 0.4 VCC = 5V, Source 5mA VCC = 5V, Sink 5mA SYNCHOUT High Level SYNCHOUT Low Level Under Voltage Lockout Threshold Rising Under Voltage Lockout Threshold Hysteresis EN Input Low Voltage En Input High Voltage 3.85 4.6 V 0.4 4.1 900 V V mV V V 4.35 0.4 2 VEN = 2V VEN = 0V VEN = 0V VEN = 2V, VFB = 1V EN Input Current Supply Current (Shutdown) Supply Current (Quiescent) Thermal Shutdown Gate Driver Sink Impedance Gate Driver Source Impedance Gate Drive Current Sense Trip Threshold RSINK RSOURCE Td1 Gate Drive Non-Overlap Time (see Figure 1) (4) Td2 From BG low to SW high From SW low to BG high Units µs V nA V % MHz nA V V 2 0.1 0.1 1.0 150 1 4 20 µA mA °C Ω Ω mV 10 ns 10 ns µA . 1V VBG 1V VSW Td1 1V 1V Td2 Figure 1—Gate Drive Non-Overlap Time Diagram MP38875 Rev. 0.9 11/20/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 3 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER PIN FUNCTIONS Pin # Name 1 VCC Description BG Driver Bias Supply. Decouple with a 1µF ceramic capacitor. Timing output to drive another MP38875 (or similar device) SYNCIN for phase-shift 2 SYNCOUT operation. 3 SYNCIN External Frequency Synchronization. Connect to GND if not used. 4 EN On/Off Control. 5 SS/TRK Soft-Start/Track Input. Connect a capacitor to ground. Feedback. An external resistor divider from the output to GND, tapped to the FB pin, sets the output voltage. To prevent current limit run away during a short circuit fault 6 FB condition the frequency foldback comparator lowers the oscillator frequency when the FB voltage is below 400mV. 7 COMP Compensation. Connect R/C network to ground. Power Good Indicator. Connect this pin to VCC or VOUT by a 100kΩ pull-up resistor. The output of this pin is an open drain if the output voltage is within 10% of the 8 PG nominal voltage, otherwise it is LOW. If PG is initially at open drain, there is a 20µs delay to pull PG if the output voltage is less than 10% regulation window. Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply 9 BST voltage. It is connected between SW and BS pins to form a floating supply across the power switch driver. 10, 18, Supply Voltage. The MP38875 operates from a +4.5V to +16V unregulated input. C1 VIN Exposed Pad is needed to prevent large voltage spikes from appearing at the input. 11-17 SW Switch Output. These pins are fused together. 19 GATE Gate Driver Output. Connect this pin to the synchronous MOSFET. 20 GND Ground. MP38875 Rev. 0.9 11/20/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 4 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS EFFICIENCY (%) 90 80 70 60 50 40 30 20 0 2 4 6 8 10 12 14 16 IOUT (A) 100 99 98 97 96 95 94 93 92 91 90 0 2 4 6 8 10 12 14 16 18 20 22 24 LOAD CURRENT(A) NORMALIZED OUTPUT VOLTAGE (%) 100 NORMALIZED OUTPUT VOLTAGE (%) VIN=12V, VOUT=1.8V, L=0.72uF, TA = +25ºC, unless otherwise noted. 100.10 100.05 100.00 99.95 99.90 4 5 6 7 8 9 1011121314151617 INPUT VOLTAGE (V) 25 5.4 23 5.2 21 5 Vcc(V) PEAK CURRENT (A) Peak Current vs. Duty Cycle 19 17 Vo/AC 20mV/div 4.6 15 4.4 13 11 4.8 IOUT 10A/div 4.2 0 10 20 30 40 50 60 4 5 6 7 8 9 1011121314151617 70 DUTY CYCLE (%) INPUT VOLTAGE(V) VIN 10V/div VEN 5V/div VEN 5V/div VSW 10V/div VSW 10V/div VSW 10V/div VOUT 2V/div I_inductor 5A/div VOUT 2V/div I_inductor 5A/div VOUT 1V/div MP38875 Rev. 0.9 11/20/2009 I_inductor 10A/div www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 5 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) VIN=12V, VOUT=1.8V, L=0.72uF, TA = +25ºC, unless otherwise noted. Case Temperature Rise vs. Output Current IOUT=3A - 15A 78 Vo=3.3V 68 58 48 Vo=1.8V 38 28 18 8 3 4 5 6 7 8 9 10 11 1213 1415 16 OUTPUT CURRENT(A) 1085 1075 1065 1055 1045 1035 1025 1015 1005 995 985 975 5 6 7 8 9 10 11 12 13 14 15 16 17 INPUT VOLTAGE(V) 0.3 VOUT=1.2V, IOUT=0A 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 4 5 6 7 8 9 10 11121314151617 INPUT VOLTAGE(V) Output Short Circuit Output Ripple Input Ripple IOUT=0A VIN=12V, VOUT=1.8V, IOUT=15A VIN=12V, VOUT=1.8V, IOUT=15A Vo 1V/div Vsw 10V/div Vsw 10V/div Vsw 10V/div Vo/AC 50mV/div Vin/AC 500mV/div I_inductor 10A/div I_inductor 10A/div I_inductor 10A/div 1us/div 1us/div 400us/div Two Phase Steady State Waveform Two Phase Transient Response IOUT=30A IOUT=1A - 20A, 1A/us 17 15 Vsw 10V/div IOUT_MAX(A) 88 Disabled Supply Current vs. Input Voltage Enabled Supply Current vs. Input Voltage Vo/AC 50mV/div Vsw 10V/div I_inductor 10A/div 13 11 V IN=5V 9 7 I_inductor 5A/div I_inductor 10A/div V IN=12V 5 1us/div 100us/div 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VOUT (V) MP38875 Rev. 0.9 11/20/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 6 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER FUNCTION BLOCK DIAGRAM SYNCIN SYNCOUT IN CURRENT SENSE AMPLIFIER D + -VCC REGULATOR BST EN REGULATOR OSCILLATOR 800KHz S + -- SS/TRK REFERENCE VFB FB DRIVER R CURRENT LIMIT COMPARATOR ISS Q R SW Q VCC VCC VBC DRIVER BG + -- + -- PWM COMPARATOR ERROR AMPLIFIER GND PG VFB VBG Power Good COMP Figure 2—Functional Block Diagram OPERATION The MP38875 is a fixed frequency, synchronous, step-down switching regulator with an integrated high-side power MOSFET and a gate driver for a low-side external MOSFET. It achieves 15A continuous output current over a wide input supply range with excellent load and line regulation. It provides a single highly efficient solution with current mode control for fast loop response and easy compensation. The MP38875 operates in a fixed frequency, peak current control mode to regulate the output voltage. A PWM cycle is initiated by the internal clock. The integrated high-side power MOSFET is turned on and remains on until its current reaches the value set by the COMP voltage. When the power switch is off, it remains off until the next clock cycle starts. If, in 90% of one PWM period, the current in the power MOSFET does MP38875 Rev. 0.9 11/20/2009 not reach the COMP set current value, the power MOSFET will be forced to turn off. Error Amplifier The error amplifier compares the FB pin voltage with the internal 0.8V reference (REF) and outputs a current proportional to the difference between the two. This output current is then used to charge or discharge the external compensation network to form the COMP voltage, which is used to control the power MOSFET current. The optimized external compensation network minimizes the external component counts and simplifies the control loop design. See Application Information for compensation network design. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 7 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER Internal Regulator Most of the internal circuitries are powered from the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5.0V, the output of the regulator is in full regulation. When VIN is lower than 5.0V, the output decreases. Since this internal regulator provides the bias current for the bottom gate driver that requires significant amount of current depending upon the external MOSFET selection, a 1µF ceramic capacitor for decoupling purpose is required. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the chip from operating at insufficient supply voltage. The MP38875 UVLO comparator monitors the output voltage of the internal regulator, VCC. The UVLO rising threshold is about 4.0V while its falling threshold is a consistent 3.2V. Soft-Start The soft-start is implemented to prevent the converter output voltage from overshooting during startup. When the chip starts, the internal current source (10µA) charges up an external soft start capacitor CSS from 0V t o 1.2V. When it is lower than the internal reference (REF), SS overrides REF so the error amplifier uses SS as the reference. When SS is higher than REF, REF regains control. Over-Current-Protection and Latch off The MP38875 has cycle-by-cycle over current limit. If the soft start Voltage is greater than 1.2V, and inductor current exceeds the current limit threshold, and FB voltage drops below 50% of reference Voltage, then the MP38875 goes into latch off until En or IN is recycled. This protection mode is especially useful when the output is dead-short to ground. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. When the silicon die temperature is higher than 150°C, it shuts down the whole chip. When the temperature is lower than its lower threshold, typically 140°C, the chip is enabled again. Floating Driver and Bootstrap Charging MP38875 Rev. 0.9 11/20/2009 The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally by VIN through D1, M3, C4, L1 and C2 (Figure 3). If (VIN-VSW) is more than 5V, U2 will regulate M3 to maintain a 5V BST voltage across C4. D1 VIN M3 + 5V + -- BST U2 -- C4 VOUT SW L1 C2 Figure 3—Internal Bootstrap Charging Circuit Startup and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts. The reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. The regulator provides stable supply for the remaining circuitries. Three events can shut down the chip: EN low, VIN low and thermal shutdown. In the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. The COMP voltage and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. Synchin/Synchout Control The MP38875 has a dedicated synchin control pin (SYNCIN) that allows MP38875 be synchronized to external clock ranging from 300KHz up to 1 MHz. the MP38875 also has a synchout pin (SYNCOUT) generating a 50% duty cycle, 180° out of phase logic signal. The Synchout signal can be used to synchronize a slave phase by connecting the SYNCOUT pin of the master MP38875 with the SYNCIN pin of the slave MP38875. The 180° interleaving operation greatly reduces the requirement of the input decoupling capacitors. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 8 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER APPLICATION INFORMATION Setting the Output Voltage The external resistor divider is used to set the output voltage (see the Typical Application Circuit on the front page). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation capacitor (see Figure 1). Choose R1 to be around 40.2kΩ for optimal transient response. R2 is then given by: R2 = R1 VOUT −1 0 .8 V Table 1—Resistor Selection for Common Output Voltages VOUT (V) R1 (kΩ) R2 (kΩ) 1.8 2.5 3.3 5 40.2 (1%) 40.2 (1%) 40.2 (1%) 40.2 (1%) 32.4 (1%) 19.1 (1%) 13 (1%) 7.68 (1%) Selecting the Inductor A 1µH to 10µH inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most applications. For highest efficiency, the inductor DC resistance should be less than 7mΩ. For most designs, the inductance value can be derived from the following equation. L= VOUT × ( VIN − VOUT ) VIN × ∆IL × f OSC Where ∆IL is the inductor ripple current. Choose inductor current to be approximately 30% of the maximum load current, 15A. The maximum inductor peak current is: IL(MAX ) = ILOAD + ∆I L 2 Under light load conditions below 200mA, larger inductance is recommended for improved efficiency Synchronous MOSFET The external synchronous MOSFET is used to supply current to the inductor when the internal high-side switch is off. It reduces the power loss significantly when compared against a Schottky rectifier. MP38875 Rev. 0.9 11/20/2009 Table 2 lists example synchronous MOSFETs and manufacturers. Table 2—Synchronous MOSFETSelection Guide Manufacture Part No. Siliconix IR si7336ADP 1RFH7932P6F Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors are preferred, but tantalum or low-ESR electrolytic capacitors may also suffice. Since the input capacitor (C1) absorbs the input switching current it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: I C1 = ILOAD × VOUT ⎛⎜ VOUT × 1− VIN ⎜⎝ VIN ⎞ ⎟ ⎟ ⎠ The worse case condition occurs at VIN = 2VOUT, where: IC1 = ILOAD For simplification, choose the input 2 capacitor whose RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1µF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: ∆VIN = ⎛ ILOAD V V × OUT × ⎜1 − OUT fS × C1 VIN ⎜⎝ VIN ⎞ ⎟⎟ ⎠ Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 9 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER The output voltage ripple can be estimated by: ∆VOUT = VOUT ⎛ V × ⎜⎜1 − OUT fS × L ⎝ VIN ⎞ ⎞ ⎛ 1 ⎟ ⎟⎟ × ⎜ R ESR + ⎜ 8 × f S × C2 ⎟⎠ ⎠ ⎝ Where L is the inductor value and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ∆VOUT = ⎞ ⎛ V × ⎜⎜1 − OUT ⎟⎟ V × L × C2 ⎝ IN ⎠ VOUT 8 × fS 2 In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ∆VOUT = VOUT ⎛ V × ⎜⎜1 − OUT fS × L ⎝ VIN ⎞ ⎟⎟ × R ESR ⎠ The characteristics of the output capacitor also affect the stability of the regulation system. The MP38875 can be optimized for a wide range of capacitance and ESR values. Compensation Components MP38875 employs current mode control for easy compensation and fast transient response. The system stability and transient response are controlled through the COMP pin. COMP pin is the output of the internal error amplifier. A series capacitor-resistor combination sets a pole-zero combination to control the characteristics of the control system. The DC gain of the voltage feedback loop is given by: A VDC = R LOAD × G CS × A VEA × VFB VOUT Where AVEA is the error amplifier voltage gain, the current sense 9600V/V; GCS is transconductance, 12.8A/V; RLOAD is the load resistor value. The system has two poles of importance. One is due to the compensation capacitor (C3), the output resistor of error amplifier. The other is MP38875 Rev. 0.9 11/20/2009 due to the output capacitor and the load resistor. These poles are located at: fP1 = GEA 2π × C3 × A VEA fP2 = 1 2π × C2 × R LOAD Where, GEA is the transconductance, 2.4mA/V. error amplifier The system has one zero of importance, due to the compensation capacitor (C3) and the compensation resistor (R3). This zero is located at: f Z1 = 1 2π × C3 × R3 The system may have another zero of importance, if the output capacitor has a large capacitance and/or a high ESR value. The zero, due to the ESR and capacitance of the output capacitor, is located at: fESR = 1 2π × C2 × R ESR In this case (as shown in Figure 3), a third pole set by the compensation capacitor (C6) and the compensation resistor (R3) is used to compensate the effect of the ESR zero on the loop gain. This pole is located at: f P3 = 1 2π × C6 × R3 The goal of compensation design is to shape the converter transfer function to get a desired loop gain. The system crossover frequency where the feedback loop has the unity gain is important. Lower crossover frequencies result in slower line and load transient responses, while higher crossover frequencies could cause system unstable. A good rule of thumb is to set the crossover frequency to approximately onetenth of the switching frequency. The Table 3 lists the typical values of compensation components for some standard output voltages with various output capacitors and inductors. The values of the compensation components have been optimized for fast transient. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 10 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER Table 3—Compensation Values for Typical Output Voltage / Capacitor VOUT (V) L1 (µH) 1.2 1.2 1.8 2.5 3.3 5 0.82 0.82 0.82 1.2 1.3 1.8 C2, Ceramic (µF) 100X2 47 47 47 47 47 C2, Poscap (µF)/ESR(mΩ) R3 (kΩ) C3 (nF) C6 (pF) None 330/ 9/ 6.3V 330/ 9/ 6.3V 330/ 9/ 6.3V 220/ 18/ 6.3V 220/ 18/ 6.3V 2.2 5.49 8.25 11.5 8.06 16 10 3.3 2.2 1.5 2.7 1 100 560 390 270 680 100 To optimize the compensation components ， the following procedure can be used. 1. Choose the compensation resistor (R3) to set the desired crossover frequency. Determine the R3 value by the following equation: R3 = 2π × C2 × f C VOUT × G EA × G CS VFB PCB Layout Guide PCB layout is very important to achieve stable operation. Please follow these guidelines and take Figure 4 for references. 1) Keep the path of switching current short and minimize the loop area formed by Input cap, high-side and low-side MOSFETs. 2) Keep the connection of low-side MOSFET between SW pin and input power ground as short and wide as possible. 3) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 4) Route SW away from sensitive analog areas such as FB. 5) Connect IN, SW, and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. Where fC is the desired crossover frequency. 2. Choose the compensation capacitor (C3) to achieve the desired phase margin. For applications with typical inductor values, setting the compensation zero, fZ1, below one forth of the crossover frequency provides sufficient phase margin. Determine the C3 value by the following equation: C3 > 4 2π × R3 × f C 3. Determine if the second compensation capacitor (C6) is required. It is required if the ESR zero of the output capacitor is located at less than half of the switching frequency, or the following relationship is valid: f 1 < S 2π × C2 × R ESR 2 If this is the case, then add the second compensation capacitor (C6) to set the pole fP3 at the location of the ESR zero. Determine the C6 value by the equation: C6 = C2 × R ESR R3 Top Layer MP38875 Rev. 0.9 11/20/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 11 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER In these cases, an external BST diode is recommended from the output of the voltage regulator to BST pin, as shown in Figure.5 External BST Diode IN4148 BST MP38875 CBST SW L + COUT 5V or 3.3V Figure 5—Add Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the BST cap is 0.1~1µF. Bottom Layer Output Voltage Tracking and Sequencing The MP38875 allows the user to program how its output voltage ramps during startup by means of the SS pin. Through this pin, the output voltage can be set to either coincidentally or rationally track another output voltage, as shown below. Figure 4—PCB Layout External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator. The applicable conditions of external BST diode are: z VOUT=5V or 3.3V; and z Duty cycle is high: D= VOUT >65% VIN OUTPUT VOLTAGE VOUT2 VOUT2 VOUT1 VOUT1 L1 SW VOUT2 R1 R1 MP38875 FB R2 R2 SS L1 VOUT1 SW MP38875 FB COUT1 R2 SS L2 SW R3 MP38875 FB R4 SS VOUT1 COUT1 L2 VOUT2 SW MP38875 R3 FB COUT2 R4 SS R2 = R4 R2 = R4 R3 > R1 R3 > R1 (a) Coincidentally Tracking R1 VOUT2 COUT2 (a) Rationally Tracking Figure 6—Output Voltage Tracking MP38875 Rev. 0.9 11/20/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 12 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER Two Phase Operation The MP38875 can be configured as a two-phase interleaving regulator to provide up to 30A load current. The current balance is automatically achieved by connecting the two COMP pins together. See Figure 7 for detail configurations. U1 VIN + 18 10 1 R3 100k VIN VIN VCC 4 R8 100k 3 SYNCIN TRACK BST SW SW SW SW SW SW SW EN 2 R4 9 17 16 15 14 13 12 11 10 VOUT WE-744325072 M1 Si7336A N-CH 30V 27A BG 19 COMP 7 CSS/TRK FB GND R10 51 R5 6.8k R1 6.19k 6 GND C9 10nF + C7 2.2nF C6 150pF SYNCOUT 5 PG PG 8 MP38875 R2 12.7k 20 C8 R13 150pF 51 U2 18 VIN 10 1 VIN VCC PG MP38875 SW SW SW SW SW SW SW BG 4 EN 3 BST SYNCIN COMP 2 5 8 9 R19 10 17 16 15 14 13 12 11 19 WE-744325072 M2 Si7336A N-CH 30V 27A + 7 SYNCOUT CSS/TRK FB 6 GND 20 Figure 7—Two Phase Operation MP38875 Rev. 0.9 11/20/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 13 MP38875 – 15A, 16V, 800kHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER PACKAGE INFORMATION QFN20 (3mm X 4mm) 0.65 0.85 2.90 3.10 0.25 REF PIN 1 ID MARKING 0.65 0.85 18 20 PIN 1 ID SEE DETAIL A 17 1 0.50 BSC 3.90 4.10 PIN 1 ID INDEX AREA 0.50 BSC 3.00 BSC 0.18 0.30 0.18 0.30 7 11 8 10 TOP VIEW 2.40 2.60 0.30 0.50 BOTTOM VIEW 0.80 1.00 0.20 REF PIN 1 ID OPTION A 0.20x45º TYP. PIN 1 ID OPTION B R0.20 TYP. 0.00 0.05 SIDE VIEW 0.70 1.10 DETAIL A 0.75 0.50 0.55 NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) JEDEC REFERENCE IS MO-220, VARIATION VGED. 5) DRAWING IS NOT TO SCALE. 0.75 0.25 0.25 3.90 2.50 0.50 0.50 RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP38875 Rev. 0.9 11/20/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 14