IK Semicon IN74HC299A 8-bit bidirectional universal shift register with parallel i/o high-performance silicon-gate cmo Datasheet

TECHNICAL DATA
IN74HC299A
8-Bit Bidirectional Universal
Shift Register with Parallel I/O
High-Performance Silicon-Gate CMOS
The IN74HC299A is identical in pinout to the LS/ALS299. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC299A features a multiplexed parallel input/output data
port to achieve full 8-bit handling in a 20 pin package. Due to the large
output drive capability and the 3-state feature, this device is ideally suited
for interface with bus lines in a bus-oriented system.
Two Mode-Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table.
Synchronous parallel loading is accomplished by taking both ModeSelect lines, S1 and S2, high. This places the outputs in the highimpedance state, which permits data applied to the data port to be clocked
into the register. Reading out of the register can be accomplished when
the outputs are enabled. The active-low asynchronous Reset overrides all
other inputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC299AN Plastic
IN74HC299ADW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
Rev. 00
IN74HC299A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
Rev. 00
IN74HC299A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Test Conditions
Guaranteed Limit
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VIH
Minimum HighLevel Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum HighLevel Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 6.0 mA (P/Q)
⎢IOUT⎢ ≤ 7.8 mA (P/Q)
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA (Q’)
⎢IOUT⎢ ≤ 5.2 mA (Q’)
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN=VIH or VIL
⎢IOUT⎢ ≤ 6.0 mA (P/Q)
⎢IOUT⎢ ≤ 7.8 mA (P/Q)
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA (Q’)
⎢IOUT⎢ ≤ 5.2 mA (Q’)
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VOL
Maximum LowLevel Output Voltage
VIN= VIL or VIH
⎢IOUT⎢ ≤ 20 µA
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
IOZ
Maximum ThreeState Leakage
Current
(QA thru QH)
Output in High-Impedance
State
VIN= VIL or VIH
VOUT=VCC or GND
6.0
±0.5
±5.0
±10
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
8.0
80
160
µA
Rev. 00
IN74HC299A
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C
to
-55°C
≤85°C
≤125°C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
5.0
25
29
4.0
20
24
3.4
17
20
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to QA’ or
QH’ (Figures 1 and 5)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
tPLH, tPHL
Maximum Propagation Delay, Clock to QA thru
QH (Figures 1 and 5)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
tPHL
Maximum Propagation Delay, Reset to QA’ or
QH’ (Figures 2 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPHL
Maximum Propagation Delay, Reset to QA thru
QH (Figures 2 and 5)
2.0
4.5
6.0
190
38
32
240
48
41
285
57
48
ns
tPLZ, tPHZ
Maximum Propagation Delay , OE1, OE2, S1, or
S2 to QA thru QH (Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZL, tPZH
Maximum Propagation Delay , OE1, OE2, S1, or
S2 to QA thru QH (Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH, tTHL
Maximum Output Transition Time, QA thru QH
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tTLH, tTHL
Maximum Output Transition Time, QA’ thru QH’
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance)
-
10
10
10
pF
Maximum Three-State I/O Capacitance
(I/O in High-Impedance State), QA thru QH
-
15
15
15
pF
CIN
COUT
CPD
Power Dissipation Capacitance (Per Package),
Output Enable
Typical @25°C,VCC=5.0 V
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
240
pF
Rev. 00
IN74HC299A
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C to-55°C
≤85°C
≤125°C
Unit
tsu
Minimum Setup Time, Mode Select
S1 or S2 to Clock (Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Data Inputs
SA, SH, PA thru PH to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Clock to Mode
Select S1 or S2 (Figure 4)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
th
Minimum Hold Time, Clock to Data
Inputs, SA, SH, PA thru PH (Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
trec
Minimum Recovery Time, Reset
Inactive to Clock (Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset (Figure
2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Rev. 00
IN74HC299A
FUNCTION TABLE
Inputs
Mode
Reset
Mode
Select
Response
Output
Enables
Clock
Serial
Inputs
PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA’ QH’
QA QB QC QD QE QF QG QH
S2
S1
OE1
OE2
L
X
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
QA through QH=Z
L
L
H
L
H
H
X
D
X
Shift Right: QA through QH=Z;
F A; F A
FB; etc
DA
D
QG
H
L
H
X
H
D
X
Shift Right: QA through QH=Z;
FA; FA FB; etc
DA
D
QG
H
L
H
L
L
D
X
Shift Right: DA FA =QA;
FB =QB; etc
FA
D
QG
H
H
L
H
X
X
D
Shift Left: QA through QH=Z;
F H; F H
FG; etc
DH
QB
D
H
H
L
X
H
X
D
Shift Left: QA through QH=Z;
F H; F H
FG; etc
DH
QB
D
H
H
L
L
L
X
D
Shift Left: DH
FH =QH;
FG =QG; etc
FH
QB
D
Parallel
Load
H
H
H
X
X
X
X
PA
PH
Hold
H
L
L
H
X
X
X
X
Hold: QA through QH=Z; FN=FN
PA
PH
H
L
L
X
H
X
X
X
Hold: QA through QH=Z; FN=FN
PA
PH
H
L
L
L
L
X
X
X
Hold: QN =QH
PA
PH
Reset
Shift
Right
Shift
Left
DA D H
Parallel Load:PN
FN
Z = high impedance
D = data on serial input
F = flip-flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the highimpedance state; however, sequential operation or clearing of the register is not affected.
Rev. 00
IN74HC299A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3a. Switching Waveforms
Figure 3b. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
Rev. 00
IN74HC299A
EXPANDED LOGIC DIAGRAM
Rev. 00
IN74HC299A
N SUFFIX PLASTIC DIP
(MS - 001AD)
A
Dimension, mm
11
20
B
1
10
Symbol
MIN
MAX
A
24.89
26.92
B
6.1
7.11
5.33
C
F
L
C
-T- SEATING
PLANE
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
N
G
K
M
J
H
D
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 013AC)
A
20
11
H
Dimension, mm
B
1
P
10
G
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
12.6
13
B
7.4
7.6
C
2.35
2.65
D
0.33
0.51
F
0.4
1.27
G
1.27
H
9.53
J
0°
8°
K
0.1
0.3
M
0.23
0.32
P
10
10.65
R
0.25
0.75
Rev. 00
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