MOTOROLA MCM6706BJ10R 32k x 8 bit static random access memory Datasheet

MOTOROLA
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by MCM6706B/D
SEMICONDUCTOR TECHNICAL DATA
MCM6706B
Product Preview
32K x 8 Bit Static Random
Access Memory
28
The MCM6706B is a 262,144 bit static random access memory organized as
32,768 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706B is available in a 300 mil, 28–lead surface–mount SOJ
package.
•
•
•
•
•
Single 5.0 V ± 10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: MCM6706B–8 = 8 ns
MCM6706B–10 = 10 ns
MCM6706B–12 = 12 ns
BLOCK DIAGRAM
J PACKAGE
300 MIL SOJ
CASE 810B–03
1
PIN ASSIGNMENT
A
1
28
VCC
A
2
27
W
A
3
26
A
A
4
25
A
A
5
24
A
A
6
23
A
A
7
22
G
A
8
21
A
A
9
20
E
A
A
10
19
DQ
A
DQ
11
18
DQ
DQ
12
17
DQ
DQ
13
16
DQ
VSS
14
15
DQ
A
A
A
ROW
DECODER
MEMORY MATRIX
(256 ROWS
128 x 8 COLUMNS)
A
A
A
PIN NAMES
DQ
COLUMN I/O
COLUMN DECODER
INPUT
DATA
CONTROL
DQ
A
A
A
A
A
A
A
A . . . . . . . . . . . . . . . . . . . . Address Input
W . . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ . . . . . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . + 5.0 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
E
W
G
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
10/9/96
 Motorola, Inc. 1996
MOTOROLA
FAST SRAM
MCM6706B
1
TRUTH TABLE (X = Don’t Care)
E
G
W
Mode
I/O Pin
Cycle
H
L
L
L
X
H
L
X
X
H
H
L
Not Selected
Read
Read
Write
High–Z
High–Z
Dout
Din
—
—
Read Cycle
Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Symbol
Value
Unit
VCC
– 0.5 to + 7.0
V
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current
Iout
± 30
mA
Power Dissipation
PD
2.0
W
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to + 70
°C
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
Storage Temperature — Plastic
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.2
—
VCC + 0.3*
V
Input Low Voltage
VIL
– 0.5**
—
0.8
V
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)
Ilkg(O)
—
± 1.0
µA
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
—
V
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
* VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
DC CHARACTERISTICS
Parameter
POWER SUPPLY CURRENTS
Parameter
Symbol
6706B–8
6706B–10
6706B–12
Unit
Notes
AC Active Supply Current
(Iout = 0 mA, VCC = max, f = fmax)
ICCA
195
185
175
mA
1, 2, 3
AC Standby Current (E = VIH, VCC = max, f = fmax)
ISB1
75
70
65
mA
1, 2, 3
CMOS Standby Current (VCC = max, f = 0 MHz,
E ≥ VCC – 0.2 V, Vin ≤ VSS, or ≥ VCC – 0.2 V)
ISB2
20
20
20
mA
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3 V, VIH = 3 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
MCM6706B
2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol
Max
Unit
Address Input Capacitance
Cin
5
pF
Control Pin Input Capacitance (E, G, W)
Cin
6
pF
Cout
6
pF
Parameter
I/O Capacitance
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a
READ CYCLE (See Notes 1 and 2)
MCM6706B–8
Parameter
MCM6706B–10
MCM6706B–12
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
8
—
10
—
12
—
ns
3
Address Access Time
tAVQV
—
8
—
10
—
12
ns
Chip Enable Access Time
tELQV
—
8
—
10
—
12
ns
Output Enable Access Time
tGLQV
—
4
—
5
—
6
ns
Output Hold from Address Change
tAXQX
3
—
3
—
3
—
ns
Chip Enable Low to Output Active
tELQX
1
—
1
—
1
—
ns
4 ,5, 6
Chip Enable High to Output High–Z
tEHQZ
—
4.5
—
5
—
6
ns
4, 5, 6
Output Enable Low to Output Active
tGLQX
0
—
0
—
0
—
ns
4, 5, 6
Output Enable High to Output High–Z
tGHQZ
—
4
—
5
—
6
ns
4, 5, 6
NOTES:
1. W is high for read cycle.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from
device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIL).
8. Addresses valid prior to or coincident with E going low.
TIMING LIMITS
+5 V
480 Ω
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
OUTPUT
255 Ω
5 pF
VL = 1.5 V
(a)
(b)
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the device point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
Figure 1. AC Test Loads
MOTOROLA FAST SRAM
MCM6706B
3
READ CYCLE 1 (See Note 7)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
DATA VALID
PREVIOUS DATA VALID
tAVQV
READ CYCLE 2 (See Note 8)
tAVAV
A (ADDRESS)
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
G (OUTPUT ENABLE)
tGHQZ
tGLQV
tGLQX
Q (DATA OUT)
DATA VALID
tAVQV
MCM6706B
4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6706B–8
Parameter
MCM6706B–10
MCM6706B–12
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
tAVAV
8
—
10
—
12
—
ns
3
Address Setup Time
tAVWL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVWH
8
—
9
—
10
—
ns
Write Pulse Width
tWLWH,
tWLEH
8
—
9
—
10
—
ns
Data Valid to End of Write
tDVWH
4
—
5
—
6
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
—
4
—
5
—
6
ns
4, 5, 6
Wirte High to Output Active
tWHQX
3
—
3
—
3
—
ns
4, 5, 6
Write Recovery Time
tWHAX
0
—
0
—
0
—
ns
Write Cycle Time
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
5. Parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
tAVAV
A (ADDRESS)
tAVWH
tWHAX
E (CHIP ENABLE)
tWLEH
tWLWH
W (WRITE ENABLE)
tAVWL
tDVWH
D (DATA IN)
tWHDX
DATA VALID
tWLQZ
Q (DATA OUT)
HIGH–Z
HIGH–Z
tWHQX
MOTOROLA FAST SRAM
MCM6706B
5
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6706B–8
Parameter
MCM6706B–10
MCM6706B–12
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
tAVAV
8
—
10
—
12
—
ns
3
Address Setup Time
tAVEL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVEH
8
—
9
—
10
—
ns
Chip Enable to End of Write
tELWH,
tELEH
7
—
8
—
9
—
ns
Data Valid to End of Write
tDVEH
4
—
5
—
6
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
ns
Write Cycle Time
4,5
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
tAVAV
A (ADDRESS)
tAVEH
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
tEHAX
W (WRITE ENABLE)
tDVEH
D (DATA IN)
Q (DATA OUT)
MCM6706B
6
tEHDX
DATA VALID
HIGH–Z
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
J PACKAGE
300 MIL SOJ
CASE 810B–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
3. CONTROLLING DIMENSION: INCH.
4. DIM R TO BE DETERMINED AT DATUM -T-.
F
DETAIL Z
28
15
N
1
D 24 PL
14
0.18 (0.007)
-A-
M
T A
0.18 (0.007)
H BRK
S
S
T B
S
P
-B-
L
G
M
M
E
C
0.10 (0.004)
K
DETAIL Z
-T-
SEATING PLANE
S RAD
R
0.25 (0.010)
S
T B
S
DIM
A
B
C
D
E
F
G
H
K
L
M
N
P
R
S
MILLIMETERS
MIN
MAX
18.29 18.54
7.50
7.74
3.26
3.75
0.39
0.50
2.24
2.48
0.67
0.81
1.27 BSC
—
0.50
0.89
1.14
0.64 BSC
10°
0°
0.76
1.14
8.38
8.64
6.60
6.86
0.77
1.01
INCHES
MIN
MAX
0.720 0.730
0.295 0.305
0.128 0.148
0.015 0.020
0.088 0.098
0.026 0.032
0.050 BSC
0.020
—
0.035 0.045
0.025 BSC
10°
0°
0.030 0.045
0.330 0.340
0.260 0.270
0.030 0.040
ORDERING INFORMATION
(Order by Full Part Number)
MCM
6706B X
XX
X
Motorola Memory Prefix
Shipping Method (R = Tape and Reel, Blank = Rails)
Part Number
Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns)
Package (J = 300 mil SOJ)
Full Part Numbers — MCM6706BJ8
MCM6706BJ10
MCM6706BJ12
MCM6706BJ8R
MCM6706BJ10R
MCM6706BJ12R
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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MOTOROLA FAST SRAM
◊
MCM6706B/D
MCM6706B
7