ATMEL AT24C256B Two-wire serial eeprom 256k (32,768 x 8) Datasheet

Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 3.6V)
Internally Organized as 32,768 x 8
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (3.6V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 40 Years
• Lead-free/Halogen-free Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead MAP, 8-lead Ultra Thin
Small Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
•
•
•
•
•
•
•
•
•
Two-wire Serial
EEPROM
256K (32,768 x 8)
Description
The AT24C256B provides 262,144 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits each. The
device’s cascadable feature allows up to eight devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead Ultra
Thin SAP, 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is
available in a 1.8V (1.8V to 3.6V) version.
Table 1. Pin Configurations
Pin Name
Function
A0–A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
NC
No Connect
GND
Ground
8-lead PDIP
AT24C256B
8-lead SOIC
A0
1
8
VCC
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP
A2
3
6
SCL
A2
3
6
SCL
GND
4
5
SDA
GND
4
5
SDA
8-lead dBGA2
8-lead TSSOP
VCC
8
1
A0
WP
7
2
A1
SCL
6
3
A2
SDA
5
4
GND
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
Bottom View
8-lead Ultra Thin SAP
8-lead MAP
VCC
8
1
A0
VCC
8
1
A0
WP
7
2
A1
WP
7
2
A1
SCL
6
3
A2
SCL
6
3
A2
SDA
5
4
GND
SDA
5
4
GND
Bottom View
Bottom View
Rev. 5080B–SEEPR–1/07
1
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground ........................................ −1.0V to +5.0V
Maximum Operating Voltage ............................................ 4.3V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Figure 1. Block Diagram
2
AT24C256B
5080B–SEEPR–1/07
AT24C256B
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each
EEPROM device and negative-edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address
inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx
devices. When the pins are hardwired, as many as eight 256K devices may be addressed on
a single bus system. (Device addressing is discussed in detail under “Device Addressing,”
page 8.) A device is selected when a corresponding hardware and software match is true. If
these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel
recommends always connecting the address pins to a known state. When using a pull-up
resistor, Atmel recommends using 10kΩ or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal
write operations. When WP is connected directly to Vcc, all write operations to the memory are
inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However,
due to capacitive coupling that may appear during customer applications, Atmel recommends
always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.
Memory
Organization
AT24C256B, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64
bytes each. Random word addressing requires a 15-bit data word address.
3
5080B–SEEPR–1/07
Table 1. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol
Test Condition
CI/O
CIN
Note:
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, SCL)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
Table 2. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +3.6V (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
VCC1
Supply Voltage
3.6
V
ICC1
Supply Current
VCC = 3.6V
READ at 400 kHz
1.0
2.0
mA
ICC2
Supply Current
VCC = 3.6V
WRITE at 400 kHz
2.0
3.0
mA
ISB1
Standby Current
(1.8V option)
VCC = 1.8V
1.0
µA
ILI
Input Leakage Current
VIN = VCC or VSS
0.10
3.0
µA
ILO
Output Leakage
Current
VOUT = VCC or VSS
0.05
3.0
µA
VIL
Input Low Level(1)
−0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
1.8
VCC = 3.6V
VIN = VCC or VSS
(1)
3.0
VIH
Input High Level
VOL2
Output Low Level
VCC = 3.0V
IOL = 2.1 mA
0.4
V
VOL1
Output Low Level
VCC = 1.8V
IOL = 0.15 mA
0.2
V
Notes:
4
1. VIL min and VIH max are reference only and are not tested.
AT24C256B
5080B–SEEPR–1/07
AT24C256B
Table 3. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.
1.8-volt
Min
2.5, 3.6-volt
Symbol
Parameter
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
1.3
0.4
µs
tHIGH
Clock Pulse Width High
0.6
0.4
µs
ti
Noise Suppression Time(1)
tAA
Clock Low to Data Out Valid
0.05
tBUF
Time the bus must be free before a
new transmission can start(1)
1.3
0.5
µs
tHD.STA
Start Hold Time
0.6
0.25
µs
tSU.STA
Start Set-up Time
0.6
0.25
µs
tHD.DAT
Data In Hold Time
0
0
µs
tSU.DAT
Data In Set-up Time
Min
100
100
ns
400
100
(1)
Inputs Rise Time
tR
Max
(1)
0.9
0.05
Max
Units
1000
kHz
50
ns
0.55
µs
0.3
0.3
µs
300
100
ns
tF
Inputs Fall Time
tSU.STO
Stop Set-up Time
0.6
0.25
µs
tDH
Data Out Hold Time
50
50
ns
tWR
Write Cycle Time
Endurance(1)
25°C, Page Mode, 3.3V
Notes:
5
5
1,000,000
ms
Write
Cycles
1. This parameter is ensured by characterization and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 3.6V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC
5
5080B–SEEPR–1/07
Device
Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 2).
Data changes during SCL high periods will indicate a start or stop condition as defined below.
Figure 2. Data Validity
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that
must precede any other command (see Figure 3).
Figure 3. Start and Stop Definition
SDA
SCL
START
STOP
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The AT24C256B features a low-power standby mode that is enabled upon
power-up and after the receipt of the stop bit and the completion of any internal operations.
6
AT24C256B
5080B–SEEPR–1/07
AT24C256B
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
Start Bit
1
SCL
Start Bit
Dummy Clock Cycles
2
3
8
Stop Bit
9
SDA
Figure 4. Bus Timing
Figure 5. Write Cycle Timing
SCL
SDA
8th BIT
ACK
WORDn
(1)
twr
STOP
CONDITION
Note:
START
CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end
of the internal clear/write cycle.
7
5080B–SEEPR–1/07
Figure 6. Output Acknowledge
Device
Addressing
The 256K EEPROM requires an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see Figure 7). The device address word consists of a
mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to
all two-wire EEPROM devices.
Figure 7. Device Address
1
MSB
0
1
0
A2
A1
A0
R/W
LSB
The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices
on the same bus. These bits must compare to their corresponding hardwired input pins. The
A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition
if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not
made, the device will return to a standby state.
DATA SECURITY: The AT24C256B has a hardware data protection scheme that allows the
user to write protect the whole memory when the WP pin is at VCC.
8
AT24C256B
5080B–SEEPR–1/07
AT24C256B
Write
Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a “0”. The addressing device, such as a microcontroller, must
then terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle and the EEPROM will not respond until the write is complete (see Figure 8).
Figure 8. Byte Write
Note:
* = DON’T CARE bit
PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 63 more data words. The
EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9).
Figure 9. Page Write
Note:
* = DON’T CARE bit
The data word address lower six bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 64 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “roll over” during write is from the last byte of the current page to the
first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a “0”, allowing the read or write sequence to continue.
9
5080B–SEEPR–1/07
Read
Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to “1”. There are three read operations:
current address read, random address read, and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll
over” during read is from the last byte of the last memory page, to the first byte of the first
page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input “0” but does generate a following stop condition
(see Figure 10).
Figure 10. Current Address Read
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 11).
Figure 11. Random Read
Note:
10
* = DON’T CARE bit
AT24C256B
5080B–SEEPR–1/07
AT24C256B
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond
with a “0” but does generate a following stop condition (see Figure 12).
Figure 12. Sequential Read
11
5080B–SEEPR–1/07
AT24C256B Ordering Information
Ordering Code
Package
Operation Range
8P3
8S1
8U2-1
8S2
8A2
8Y1
8Y7
Lead-free/Halogen-free
Industrial Temperature
(−40°C to 85°C)
Die Sale
Industrial Temperature
(−40°C to 85°C)
AT24C256B-10PU-1.8
AT24C256BN-10SU-1.8
AT24C256BU2-10UU-1.8
AT24C256BW-10SU-1.8
AT24C256B-10TU-1.8
AT24C256BY1-10YU-1.8
AT24C256BY7-10YH-1.8 (NiPdAu Lead Finish)
AT24C256B-W1.8-11(1)
Notes:
1. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon
request. Please contact Serial Interface Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2
8-lead, 0.200” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8U2-1
8-ball, die Ball Grid Array Package (dBGA2)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8Y7
8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
−1.8
12
Low-voltage (1.8V to 3.6V)
AT24C256B
5080B–SEEPR–1/07
AT24C256B
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
NOM
MAX
NOTE
–
–
0.210
2
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
3
D1
0.005
–
–
3
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
e
0.100 BSC
eA
L
Notes:
MIN
0.300 BSC
0.115
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
13
5080B–SEEPR–1/07
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
∅
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
R
14
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
B
AT24C256B
5080B–SEEPR–1/07
AT24C256B
8S2 - EIAJ SOIC
C
1
E
E1
L
N
θ
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
SIDE VIEW
NOM
MAX
NOTE
A
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
5
C
0.15
0.35
5
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
θ
0˚
8˚
e
Notes: 1.
2.
3.
4.
5.
MIN
1.27 BSC
2, 3
4
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs aren't included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/7/06
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
D
15
5080B–SEEPR–1/07
8U2-1 – dBGA2
D
A1 BALL PAD CORNER
1.
b
E
A1
A2
Top View
A
A1 BALL PAD CORNER
2
Side View
1
A
B
e
C
D
(e1)
d
(d1)
COMMON DIMENSIONS
(Unit of Measure = mm)
Bottom View
SYMBOL
MIN
NOM
MAX
8 Solder Balls
A
0.81
0.91
1.00
A1
0.15
0.20
0.25
A2
0.40
0.45
0.50
b
0.25
0.30
0.35
D
2.35 BSC
1. Dimension 'b' is measured at the maximum solder ball diameter.
E
3.73 BSC
This drawing is for general information only.
e
0.75 BSC
e1
0.74 REF
d
0.75 BSC
d1
0.80 REF
NOTE
1
6/24/03
R
16
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
DRAWING NO.
PO8U2-1
REV.
A
AT24C256B
5080B–SEEPR–1/07
AT24C256B
8Y1 – MAP
PIN 1 INDEX AREA
A
1
3
2
4
PIN 1 INDEX AREA
E1
D1
D
L
8
Bottom View
COMMON DIMENSIONS
(Unit of Measure = mm)
A
Side View
5
e
End View
Top View
6
b
A1
E
7
SYMBOL
MIN
NOM
MAX
A
–
–
0.90
A1
0.00
–
0.05
D
4.70
4.90
5.10
E
2.80
3.00
3.20
D1
0.85
1.00
1.15
E1
0.85
1.00
1.15
b
0.25
0.30
0.35
e
L
NOTE
0.65 TYP
0.50
0.60
0.70
2/28/03
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
DRAWING NO.
REV.
8Y1
C
17
5080B–SEEPR–1/07
8Y7 – UT SAP
PIN 1 INDEX AREA
A
D1
PIN 1 ID
D
E1
L
A1
E
e
b
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
A
–
–
0.60
A1
0.00
–
0.05
D
5.80
6.00
6.20
E
4.70
4.90
5.10
D1
3.30
3.40
3.50
E1
3.90
4.00
4.10
b
0.35
0.40
0.45
SYMBOL
e
1.27 TYP
e1
L
NOTE
3.81 REF
0.50
0.60
0.70
10/13/05
R
18
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array
Package (UTSAP) Y7
DRAWING NO.
REV.
8Y7
B
AT24C256B
5080B–SEEPR–1/07
AT24C256B
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
4.40
4.50
3, 5
E
E1
e
D
A2
6.40 BSC
4.30
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.65 BSC
0.45
L1
Notes:
4
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
19
5080B–SEEPR–1/07
Revision History
20
Doc.
Rev.
Date
Comments
5080B
12/2006
Pg. 12 ordering information
- Changed part number from AT24C256BW-10SH1.8 to AT24C256BW-10SU-1.8
Pg. 19
- Added 8A2 package drawing
Pg. 1
- Added 8-lead Ultra Thin SAP in Features and
Descriptions
- Added 8-lead Ultra Thin SAP package drawing
Pg. 12 ordering information
-Added new part number AT24C256BY7-10YH-1.8
-Add note regarding die sale options
-Add 8Y7 package type description
-Add 8Y7 package drawing
5080A
9/2004
Initial document release
AT24C256B
5080B–SEEPR–1/07
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5080B–SEEPR–1/07