CY2292 Three-PLL General-Purpose EPROM Programmable Clock Generator Features Benefits • Three integrated phase-locked loops • EPROM programmability • Generates up to three custom frequencies from external sources • Factory-programmable (CY2292) or field-programmable (CY2292F) device options • Easy customization and fast turnaround • Programming support available for all opportunities • Low-skew, low-jitter, high-accuracy outputs • Meets critical industry standard timing requirements • Power-management options (Shutdown, OE, Suspend) • Supports low-power applications • Frequency select option • Eight user-selectable frequencies on CPU PLL • Smooth slewing on CPUCLK • Allows downstream PLLs to stay locked on CPUCLK output • Configurable 3.3V or 5V operation • Enables application compatibility • 16-pin SOIC Package (TSSOP: F only) • Industry-standard packaging saves on board space Selector Guide Part Number Outputs Input Frequency Range Output Frequency Range Specifics CY2292 6 10 MHz–25 MHz (external crystal) 76.923 kHz–100 MHz (5V) 1 MHz–30 MHz (reference clock) 76.923 kHz–80 MHz (3.3V) Factory Programmable Commercial Temperature CY2292I 6 10 MHz–25 MHz (external crystal) 76.923 kHz–90 MHz (5V) 1 MHz–30 MHz (reference clock) 76.923 kHz–66.6 MHz (3.3V) Factory Programmable Industrial Temperature CY2292F 6 10 MHz–25 MHz (external crystal) 76.923 kHz–90 MHz (5V) 1 MHz–30 MHz (reference clock) 76.923 kHz–66.6 MHz (3.3V) Field Programmable Commercial Temperature CY2292FI 6 10 MHz–25 MHz (external crystal) 76.923 kHz–80 MHz (5V) 1 MHz–30 MHz (reference clock) 76.923 kHz–60.0 MHz (3.3V) Field Programmable Industrial Temperature CY2292FZ 6 10 MHz–25 MHz (external crystal) 76.923 kHz–90 MHz (5V) 1 MHz–30 MHz (reference clock) 76.923 kHz–66.6 MHz (3.3V) Field Programmable Commercial Temperature Logic Block Diagram . XTALIN OSC. XTALOUT XBUF CPLL (8 BIT) /1,2,4 CPUCLK S0 CLKA S1 UPLL (10 BIT) SPLL (8 BIT) CLKB /1,2,4,8 /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40 /48,52,96,104 CLKC CLKD CONFIG EPROM SHUTDOWN/ OE Cypress Semiconductor Corporation Document #: 38-07449 Rev. *C MUX S2/SUSPEND • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised Sept. 07, 2005 CY2292 Pin Configurations CY2292 16-pin SOIC CLKC 1 16 VDD GND 2 15 SHUTDOWN/OE S2/SUSPEND 3 14 XTALIN 4 13 VDD S1 XTALOUT XBUF 5 12 6 11 S0 GND CLKD 7 10 CLKA CPUCLK 8 9 CLKB Pin Summary Name CLKC Pin Number CY2292 1 Description Configurable clock output C. VDD 2, 14 Voltage supply. GND 3, 11 Ground. XTALIN[1] 4 Reference crystal input or external reference clock input. XTALOUT[1, 2] 5 Reference crystal feedback. XBUF 6 Buffered reference clock output. CLKD 7 Configurable clock output D. CPUCLK 8 CPU frequency clock output. CLKB 9 Configurable clock output B. CLKA 10 Configurable clock output A. S0 12 CPU clock select input, bit 0. S1 13 CPU clock select input, bit 1. S2/SUSPEND 15 CPU clock select input, bit 2. Optionally enables suspend feature when LOW.[3] SHUTDOWN/OE 16 Places outputs in three-state[4] condition and shuts down chip when LOW. Optionally, only places outputs in three-state[4] condition and does not shut down chip when LOW. Operation The CY2292 is a third-generation family of clock generators. The CY2292 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems. All parts provide a highly configurable set of clocks for PC motherboard applications. Each of the four configurable clock outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies will have low (≤ 500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. The CY2292 can be configured for either 5V or 3.3V operation. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator has been designed for 10-MHz to 25-MHz crystals, providing additional flexibility. No external components are required with this crystal. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. Output Configuration The CY2292 has four independent frequency sources on-chip. These are the reference oscillator, and three Phase-Locked Loops (PLLs). Each PLL has a specific function. The System PLL (SPLL) provides fixed output frequencies on the configurable outputs. The SPLL offers the most output frequency divider options. The CPU PLL (CPLL) is controlled by the select inputs (S0–S2) to provide eight user-selectable frequencies with smooth slewing between frequencies. The Utility PLL (UPLL) provides the most accurate clock. It is often used for miscellaneous frequencies not provided by the other frequency sources. All configurations are EPROM programmable, providing short sample and production lead times. Please refer to the application note Understanding the CY2291, CY2292, and CY2295 for information on configuring the part. Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD ≈ 17 pF or 18 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal). 3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information. 4. The CY2292 has weak pull-downs on all outputs. Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW. Document #: 38-07449 Rev. *C Page 2 of 11 CY2292 Power-Saving Features The SHUTDOWN/OE input three-states the outputs when pulled LOW. If system shutdown is enabled, a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins will be less than 50 µA (for commercial temperature or 100 µA for industrial temperature). After leaving shutdown mode, the PLLs will have to relock. All outputs have a weak pull-down so that the outputs do not float when three-stated.[4] The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a three-state condition.[3] The CPUCLK can slew (transition) smoothly between 20 MHz and the maximum output frequency (100 MHz at 5V/80 MHz at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz at 3.3V for Industrial Temp. and for field-programmed parts). This feature is extremely useful in “Green” PC and laptop applications, where reducing the frequency of operation can result in considerable power savings. This feature meets all 486 and Pentium® processor slewing requirements. CyClocks Software CyClocks is an easy-to-use application that allows you to configure any one of the EPROM-programmable clocks offered by Cypress. You may specify the input frequency, PLL and output frequencies, and different functional options. Please note the output frequency ranges in this data sheet when specifying them in CyClocks to ensure that you stay within the limits. CyClocks also has a power calculation feature that allows you to see the power consumption of your specific Document #: 38-07449 Rev. *C configuration. You can download a copy of CyClocks for free on Cypress’s web site at www.cypress.com. Cypress FTG Programmer The Cypress Frequency Timing Generator (FTG) Programmer is a portable programmer designed to custom program our family of EPROM Field Programmable Clock Devices. The FTG programmers connect to a PC serial port and allow users of CyClocks software to quickly and easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670. Custom Configuration Request Procedure The CY229x are EPROM-programmable devices that may be configured in the factory or in the field by a Cypress Field Application Engineer (FAE). The output frequencies requested will be matched as closely as the internal PLL divider and multiplier options allow. All custom requests must be submitted to your local Cypress FAE or sales representative. The method to use to request custom configurations is: Use CyClocks software. This software automatically calculates the output frequencies that can be generated by the CY229x devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. The CyClocks software is available free of charge from the Cypress web site (http://www.cypress.com) or from your local sales representative. Once the custom request has been processed you will receive a part number with a 3-digit extension (e.g., CY2292SC-128) specific to the frequencies and pinout of your device. This will be the part number used for samples requests and production orders. Page 3 of 11 CY2292 Maximum Ratings Storage Temperature ................................. –65°C to +150°C Max. Soldering Temperature (10 sec) ......................... 260°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature .................................................. 150°C Supply Voltage ............................................... –0.5V to +7.0V Package Power Dissipation...................................... 750 mW DC Input Voltage............................................ –0.5V to +7.0V Static Discharge Voltage.............................................≤ 2000V (per MIL-STD-883, Method 3015) Operating Conditions[5] Parameter Description Min. Max. Unit All 4.5 5.5 V Supply Voltage, 3.3V operation All 3.0 3.6 V Commercial Operating Temperature, Ambient CY2292/CY2292F 0 +70 °C −40 +85 °C 25 pF VDD Supply Voltage, 5.0V operation VDD TA Part Numbers Industrial Operating Temperature, Ambient CY2292I/CY2292FI CLOAD Max. Load Capacitance 5.0V Operation All CLOAD Max. Load Capacitance 3.3V Operation All 15 pF fREF External Reference Crystal All 10.0 25.0 MHz External Reference Clock[6, 7, 8] All 1 30 MHz Electrical Characteristics, Commercial 5.0V Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = 4.0 mA Min. Typ. Max. 2.4 V VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[9] Except crystal pins VIL LOW-Level Input Voltage[9] Except crystal pins IIH Input HIGH Current VIN = VDD – 0.5V <1 IIL Input LOW Current VIN = +0.5V <1 IOZ Output Leakage Current Three-state outputs Current[10] Commercial IDD VDD Supply IDDS VDD Power Supply Current in Shutdown Mode[10] Shutdown active CY2292/CY2292F 0.4 2.0 VDD = VDD max., 5V operation Unit V V 0.8 V 10 µA 10 µA 250 µA 75 100 mA 10 50 µA Max. Unit Electrical Characteristics, Commercial 3.3V Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = 4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[9] Except crystal pins [9] Min. Typ. 2.4 V 0.4 2.0 V VIL LOW-Level Input Voltage IIH Input HIGH Current VIN = VDD – 0.5V <1 <1 Except crystal pins IIL Input LOW Current VIN = +0.5V IOZ Output Leakage Current Three-state outputs IDD VDD Supply Current[10] Commercial VDD = VDD Max., 3.3V operation IDDS VDD Power Supply Current in Shutdown Mode[10] Shutdown active CY2292/CY2292F V 0.8 V 10 µA 10 µA 250 µA 50 65 mA 10 50 µA Notes: 5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted. 6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 7. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock. 8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended that a 150Ω pull-up resistor to VDD be connected to the Xout pin. 9. Xtal inputs have CMOS thresholds. 10. Load = Max., VIN = 0V or VDD, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations will vary. Power can be approximated by the following formula (multiply by 0.65 for 3V operation): IDD=10+0.06•(FCPLL+FUPLL+2•FSPLL)+0.27•(FCLKA+FCLKB+FCLKC+FCLKD+FCPUCLK+FXBUF). Document #: 38-07449 Rev. *C Page 4 of 11 CY2292 Electrical Characteristics, Industrial 5.0V Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = 4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[9] Except crystal pins VIL LOW-Level Input Voltage[9] Except crystal pins Min. Typ. Max. Unit 0.4 V 2.4 V 2.0 V 0.8 V IIH Input HIGH Current VIN = VDD – 0.5V <1 10 µA IIL Input LOW Current VIN = +0.5V <1 10 µA IOZ Output Leakage Current Three-state outputs 250 µA IDD VDD Supply Current[10] Industrial VDD = VDD Max., 5V operation 75 110 mA IDDS VDD Power Supply Current in Shutdown Mode[10] Shutdown active CY2292I/CY2292FI 10 100 µA Typ. Max. Unit Electrical Characteristics, Industrial 3.3V Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = 4.0 mA Min. 2.4 V VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[9] Except crystal pins VIL LOW-Level Input Voltage[9] Except crystal pins IIH Input HIGH Current VIN = VDD – 0.5V <1 IIL Input LOW Current VIN = +0.5V <1 IOZ Output Leakage Current Three-state outputs IDD VDD Supply Current[10] Industrial VDD = VDD Max., 3.3V operation IDDS VDD Power Supply Current in Shutdown Mode[10] Shutdown active 0.4 2.0 V V CY2292I/CY2292FI 0.8 V 10 µA 10 µA 250 µA 50 70 mA 10 100 µA Switching Characteristics, Commercial 5.0V Parameter t1 Name Output Period Output Duty Cycle[11] Description Clock output range, 5V operation Min. Typ. Max. Unit CY2292 10 (100 MHz) 13000 (76.923 kHz) ns CY2292F 11.1 (90 MHz) 13000 (76.923 kHz) ns Duty cycle for outputs, defined as t2 ÷ t1[12] fOUT > 66 MHz 40% 50% 60% Duty cycle for outputs, defined as t2 ÷ t1[12] fOUT < 66 MHz 45% 50% 55% t3 Rise Time Output clock rise time[13] 3 5 ns t4 Fall Time Output clock fall time[13] 2.5 4 ns t5 Output Disable Time Time for output to enter three-state mode after SHUTDOWN/OE goes LOW 10 15 ns t6 Output Enable Time Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH 10 15 ns t7 Skew Skew delay between any identical or related outputs[3, 12, 14] < 0.25 0.5 ns CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/ms t8 Notes: 11. XBUF duty cycle depends on XTALIN duty cycle. 12. Measured at 1.4V. 13. Measured between 0.4V and 2.4V. 14. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application note: Jitter in PLL-Based Systems. Document #: 38-07449 Rev. *C Page 5 of 11 CY2292 Switching Characteristics, Commercial 5.0V (continued) Typ. Max. Unit t9A Parameter Clock Jitter[14] Name Peak-to-peak period jitter (t9A max. – t9A min.), % of clock period (fOUT < 4 MHz) <0.5 1 % t9B Clock Jitter[14] Peak-to-peak period jitter (t9B max. – t9B min.) (4 MHz < fOUT < 16 MHz) <0.7 1 ns t9C Clock Jitter[14] Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) <400 500 ps t9D Clock Jitter[14] Peak-to-peak period jitter (fOUT > 50 MHz) <250 350 ps t10A Lock Time for CPLL Lock Time from Power-up <25 50 ms t10B Lock Time for UPLL and Lock Time from Power-up SPLL <0.25 1 ms Slew Limits Description CPU PLL Slew Limits Min. CY2292 20 100 MHz CY2292F 20 90 MHz Switching Characteristics, Commercial 3.3V Parameter t1 Name Output Period Description Clock output range, 3.3V operation CY2292 CY2292F Output Duty Cycle[11] t3 Rise Time Min. Max. Unit 12.5 (80 MHz) Typ. 13000 (76.923 kHz) ns 15 (66.6 MHz) 13000 (76.923 kHz) ns Duty cycle for outputs, defined as t2 ÷ t1[12] fOUT > 66 MHz 40% 50% 60% Duty cycle for outputs, defined as t2 ÷ t1[12] fOUT < 66 MHz 45% 50% 55% 3 5 Output clock rise time[13] time[13] ns t4 Fall Time Output clock fall 2.5 4 ns t5 Output Disable Time Time for output to enter three-state mode after SHUTDOWN/OE goes LOW 10 15 ns t6 Output Enable Time Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH 10 15 ns t7 Skew Skew delay between any identical or related outputs[3, 12, 14] < 0.25 0.5 ns t8 CPUCLK Slew Frequency transition rate 20.0 MHz/ ms t9A Clock Jitter[14] Peak-to-peak period jitter (t9A max. – t9A min.), % of clock period (fOUT < 4 MHz) < 0.5 1 % t9B Clock Jitter[14] Peak-to-peak period jitter (t9B max. – t9B min.) (4 MHz < fOUT < 16 MHz) < 0.7 1 ns t9C Clock Jitter[14] Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) < 400 500 ps Jitter[14] Peak-to-peak period jitter (fOUT > 50 MHz) < 250 350 ps < 25 50 ms < 0.25 1 ms t9D Clock t10A Lock Time for CPLL Lock Time from Power-up t10B Lock Time for UPLL and SPLL Lock Time from Power-up Slew Limits CPU PLL Slew Limits Document #: 38-07449 Rev. *C 1.0 CY2292 20 80 MHz CY2292F 20 66.6 MHz Page 6 of 11 CY2292 Switching Characteristics, Industrial 5.0V Parameter t1 Name Output Period Output Duty Cycle[11] Description Clock output range, 5V operation Min. Typ. Max. Unit CY2292I 11.1 (90 MHz) 13000 (76.923 kHz) ns CY2292FI 12.5 (80 MHz) 13000 (76.923 kHz) ns Duty cycle for outputs, defined as t2 ÷ t1[12] fOUT > 66 MHz 40% 50% 60% Duty cycle for outputs, defined as t2 ÷ t1[12] fOUT < 66 MHz 45% 50% 55% t3 Rise Time Output clock rise time[13] 3 5 ns t4 Fall Time Output clock fall time[13] 2.5 4 ns t5 Output Disable Time Time for output to enter three-state mode after SHUTDOWN/OE goes LOW 10 15 ns t6 Output Enable Time Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH 10 15 ns t7 Skew Skew delay between any identical or related outputs[3, 12, 14] < 0.25 0.5 ns t8 CPUCLK Slew Frequency transition rate 20.0 MHz/ ms t9A Clock Jitter[14] Peak-to-peak period jitter (t9A max. – t9A min.), % of clock period (fOUT < 4 MHz) < 0.5 1 % t9B Clock Jitter[14] Peak-to-peak period jitter (t9B max. – t9B min.) (4 MHz < fOUT < 16 MHz) < 0.7 1 ns t9C Clock Jitter[14] Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) < 400 500 ps t9D Clock Jitter[14] Peak-to-peak period jitter (fOUT > 50 MHz) < 250 350 ps t10A Lock Time for CPLL Lock Time from Power-up <25 50 ms t10B Lock Time for UPLL and SPLL Lock Time from Power-up <0.25 1 ms Slew Limits CPU PLL Slew Limits 1.0 CY2292I 20 90 MHz CY2292FI 20 80 MHz Switching Characteristics, Industrial 3.3V Parameter t1 Name Output Period Description Clock output range, 3.3V CY2292I operation CY2292FI Output Duty Cycle[11] Min. Typ. Max. Unit 15 (66.6 MHz) 13000 (76.923 kHz) ns 16.66 (60 MHz) 13000 (76.923 kHz) ns Duty cycle for outputs, defined as t2 ÷ t1[12] fOUT > 66 MHz 40% 50% 60% Duty cycle for outputs, defined as t2 ÷ t1[12] fOUT < 66 MHz 45% 50% 55% t3 Rise Time Output clock rise time[13] 3 5 ns t4 Fall Time Output clock fall time[13] 2.5 4 ns t5 Output Disable Time Time for output to enter three-state mode after SHUTDOWN/OE goes LOW 10 15 ns t6 Output Enable Time Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH 10 15 ns t7 Skew Skew delay between any identical or related outputs[3, 12, 14] < 0.25 0.5 ns t8 CPUCLK Slew Frequency transition rate 20.0 MHz/ms Document #: 38-07449 Rev. *C 1.0 Page 7 of 11 CY2292 Switching Characteristics, Industrial 3.3V (continued) Typ. Max. Unit t9A Parameter Clock Jitter[14] Name Peak-to-peak period jitter (t9A max. – t9A min.), % of clock period (fOUT < 4 MHz) Description Min. < 0.5 1 % t9B Clock Jitter[14] Peak-to-peak period jitter (t9B max. – t9B min.) (4 MHz < fOUT < 16 MHz) < 0.7 1 ns t9C Clock Jitter[14] Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) < 400 500 ps t9D Clock Jitter[14] Peak-to-peak period jitter (fOUT > 50 MHz) < 250 350 ps t10A Lock Time for CPLL Lock Time from Power-up < 25 50 ms t10B Lock Time for UPLL and SPLL Lock Time from Power-up < 0.25 1 ms Slew Limits CPU PLL Slew Limits CY2292I 20 66.6 MHz CY2292FI 20 60 MHz Switching Waveforms All Outputs, Duty Cycle and Rise/Fall Time t1 t2 OUTPUT t3 t4 Output Three-State Timing[4] OE t5 t6 ALL THREE-STATE OUTPUTS CLK Outputs Jitter and Skew t9A CLK OUTPUT t7 RELATED CLK CPU Frequency Change SELECT OLD SELECT Fold NEW SELECT STABLE t8 & t10 Fnew CPU Document #: 38-07449 Rev. *C Page 8 of 11 CY2292 Test Circuit VDD CLK out 0.1 µF CLOAD OUTPUTS VDD 0.1 µF GND Package Characteristics Package θJA (C/W) θJC (C/W) Transistor Count 16-pin SOIC 83 19 9271 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY2292SC–XXX 16-Pin SOIC Commercial 5.0V CY2292SC–XXXT 16-Pin SOIC – Tape and Reel Commercial 5.0V CY2292SL–XXX 16-Pin SOIC Commercial 3.3V CY2292SL–XXXT 16-Pin SOIC – Tape and Reel Commercial 3.3V CY2292F 16-Pin SOIC Commercial 3.3V or 5.0V CY2292FT 16-Pin SOIC – Tape and Reel Commercial 3.3V or 5.0V CY2292SI–XXX 16-Pin SOIC Industrial 3.3V or 5.0V CY2292SI–XXXT 16-Pin SOIC – Tape and Reel Industrial 3.3V or 5.0V CY2292FI 16-Pin SOIC Industrial 3.3V or 5.0V CY2292FIT 16-Pin SOIC – Tape and Reel Industrial 3.3V or 5.0V CY2292FZ 16-Pin TSSOP Commercial 3.3V or 5.0V CY2292FZT 16-Pin TSSOP – Tape and Reel Commercial 3.3V or 5.0V 16-Pin SOIC Commercial 5.0V Lead-Free CY2292SXC–XXX CY2292SXC–XXXT 16-Pin SOIC – Tape and Reel Commercial 5.0V CY2292SXL–XXX 16-Pin SOIC Commercial 3.3V CY2292SXL–XXXT 16-Pin SOIC – Tape and Reel Commercial 3.3V CY2292FXC 16-Pin SOIC Commercial 3.3V or 5.0V CY2292FXCT 16-Pin SOIC – Tape and Reel Commercial 3.3V or 5.0V CY2292SXI–XXX 16-Pin SOIC Industrial 3.3V or 5.0V CY2292SXI–XXXT 16-Pin SOIC – Tape and Reel Industrial 3.3V or 5.0V CY2292FXI 16-Pin SOIC Industrial 3.3V or 5.0V CY2292FXIT 16-Pin SOIC – Tape and Reel Industrial 3.3V or 5.0V CY2292FZX 16-Pin TSSOP Commercial 3.3V or 5.0V CY2292FZXT 16-Pin TSSOP – Tape and Reel Commercial 3.3V or 5.0V Document #: 38-07449 Rev. *C Page 9 of 11 CY2292 Package Diagrams 16 Lead (150 Mil) SOIC 16-Lead (150-Mil) SOIC S16.15 PIN 1 ID 8 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.15gms 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] PART # S16.15 STANDARD PKG. 9 SZ16.15 LEAD FREE PKG. 16 0.386[9.804] 0.393[9.982] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.016[0.406] 0.035[0.889] 0°~8° 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249] 0.0075[0.190] 0.0098[0.249] 51-85068-*B 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A CyClocks is a trademark of Cypress Semiconductor Corporation.Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07449 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2292 Document History Page Document Title: CY2292 Three-PLL General-Purpose EPROM Programmable Clock Generator Document Number: 38-07449 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 116993 07/01/02 DSG Changed from Spec number: 38-00946 to 38-07449 *A 119639 12/05/02 CKN Changed 8 MHz to 20 MHz in Power-saving Features *B 277130 See ECN RGL Added Lead-free Devices *C 395808 See ECN RGL Minor Change: fixed the typo in the ordering code Document #: 38-07449 Rev. *C Page 11 of 11