AD FDVE1040-1R5M 20 v, 4 a, synchronous, step-down dc-to-dc regulator Datasheet

FEATURES
Input voltage: 4.5 V to 20 V
Integrated MOSFET: 44 mΩ/11.6 mΩ
Reference voltage: 0.6 V ± 1%
Continuous output current: 4 A
Programmable switching frequency: 200 kHz to 1.4 MHz
Synchronizes to external clock: 200 kHz to 1.4 MHz
180° out-of-phase clock synchronization
Precision enable and power good
External compensation
Internal soft start with external adjustable option
Startup into a precharged output
Supported by ADIsimPower design tool
TYPICAL APPLICATIONS CIRCUIT
ADP2384
VIN
CIN
CBST
EN
VOUT
FB
RT
COMP
VREG
CVREG
COUT
RTOP
SYNC
RT
L
SW
PGOOD
SS
GND
PGND
RC
CSS
RBOT
CC
Figure 1.
APPLICATIONS
100
95
90
85
EFFICIENCY (%)
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point-of-load applications
BST
PVIN
10725-001
Data Sheet
20 V, 4 A, Synchronous, Step-Down
DC-to-DC Regulator
ADP2384
80
75
70
65
60
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
10725-002
VOUT = 1.2V
VOUT = 3.3V
VOUT = 5V
55
Figure 2. Efficiency vs. Output Current, VIN = 12 V, fSW = 300 kHz
GENERAL DESCRIPTION
The ADP2384 is a synchronous, step-down dc-to-dc regulator
with an integrated 44 mΩ, high-side power MOSFET and
an 11.6 mΩ, synchronous rectifier MOSFET to provide a high
efficiency solution in a compact 4 mm × 4 mm LFCSP package.
This device uses a peak current mode, constant frequency pulsewidth modulation (PWM) control scheme for excellent stability
and transient response. The switching frequency of the ADP2384
can be programmed from 200 kHz to 1.4 MHz. To minimize
system noise, the synchronization function allows the switching
frequency to be synchronized to an external clock.
The ADP2384 requires minimal external components and operates
from an input voltage of 4.5 V to 20 V. The output voltage can be
adjusted from 0.6 V to 90% of the input voltage and delivers up to
4 A of continuous current. Each IC draws less than 120 μA current
from the input source when it is disabled.
This regulator targets high performance applications that require
high efficiency and design flexibility. External compensation and an
adjustable soft start function provide design flexibility. The powergood output and precision enable input provide simple and reliable
power sequencing.
Other key features include undervoltage lockout (UVLO),
overvoltage protection (OVP), overcurrent protection (OCP),
short-circuit protection (SCP), and thermal shutdown (TSD).
The ADP2384 operates over the −40°C to +125°C junction
temperature range and is available in a 24-lead, 4 mm × 4 mm
LFCSP package.
Rev. 0
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©2012 Analog Devices, Inc. All rights reserved.
ADP2384
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Shutdown .................................................................... 14
Applications ....................................................................................... 1
Applications Information .............................................................. 15
Typical Applications Circuit............................................................ 1
Input Capacitor Selection .......................................................... 15
General Description ......................................................................... 1
Output Voltage Setting .............................................................. 15
Revision History ............................................................................... 2
Voltage Conversion Limitations ............................................... 15
Specifications..................................................................................... 3
Inductor Selection ...................................................................... 15
Absolute Maximum Ratings............................................................ 5
Output Capacitor Selection....................................................... 16
Thermal Resistance ...................................................................... 5
Programming the Input Voltage UVLO .................................. 17
ESD Caution .................................................................................. 5
Compensation Design ............................................................... 17
Pin Configuration and Function Descriptions ............................. 6
ADIsimPower Design Tool ....................................................... 17
Typical Performance Characteristics ............................................. 7
Design Example .............................................................................. 18
Functional Block Diagram ............................................................ 11
Output Voltage Setting .............................................................. 18
Theory of Operation ...................................................................... 12
Frequency Setting ....................................................................... 18
Control Scheme .......................................................................... 12
Inductor Selection ...................................................................... 18
Precision Enable/Shutdown ...................................................... 12
Output Capacitor Selection....................................................... 19
Internal Regulator (VREG) ....................................................... 12
Compensation Components ..................................................... 19
Bootstrap Circuitry .................................................................... 12
Soft Start Time Program ........................................................... 19
Oscillator ..................................................................................... 12
Input Capacitor Selection .......................................................... 19
Synchronization .......................................................................... 12
Recommended External Components .................................... 20
Soft Start ...................................................................................... 13
Circuit Board Layout Recommendations ................................... 21
Power Good................................................................................. 13
Typical Applications Circuits ........................................................ 22
Peak Current-Limit and Short-Circuit Protection................. 13
Outline Dimensions ....................................................................... 23
Overvoltage Protection (OVP) ................................................. 14
Ordering Guide .......................................................................... 23
Undervoltage Lockout (UVLO) ............................................... 14
REVISION HISTORY
8/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
ADP2384
SPECIFICATIONS
VPVIN = 12 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
PVIN
PVIN Voltage Range
Quiescent Current
Shutdown Current
PVIN Undervoltage Lockout Threshold
Symbol
VPVIN
IQ
ISHDN
UVLO
Test Conditions/Comments
No switching
EN = GND
PVIN rising
PVIN falling
Min
4.5
2.1
45
3.5
Typ
2.9
80
4.3
3.8
Max
Unit
20
3.6
120
4.5
V
mA
µA
V
V
FB
FB Regulation Voltage
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
EA Sink Current
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
Regulator Current Limit
SW
High-Side On Resistance 1
Low-Side On Resistance1
High-Side Peak Current Limit
Low-Side Negative Current-Limit
Threshold Voltage 2
SW Minimum On Time
SW Minimum Off Time
BST
Bootstrap Voltage
OSCILLATOR (RT PIN)
Switching Frequency
Switching Frequency Range
SYNC
Synchronization Range
SYNC Minimum Pulse Width
SYNC Minimum Off Time
SYNC Input High Voltage
SYNC Input Low Voltage
SS
Internal Soft Start
SS Pin Pull-Up Current
PGOOD
Power-Good Range
FB Rising Threshold
FB Rising Hysteresis
FB Falling Threshold
FB Falling Hysteresis
VFB
0°C < TJ < 85°C
−40°C < TJ < 125°C
0.594
0.591
0.6
0.6
0.01
0.606
0.609
0.1
V
V
µA
340
40
40
470
60
60
600
80
80
µS
µA
µA
7.6
8
340
100
8.4
135
V
mV
mA
44
11.6
70
20
mΩ
mΩ
6.1
20
7.4
A
mV
125
200
168
260
ns
ns
4.5
5
5.5
V
530
200
600
670
1400
kHz
kHz
1400
0.4
kHz
ns
ns
V
V
3.9
Clock cycles
µA
IFB
gm
ISOURCE
ISINK
VVREG
VPVIN = 12 V, IVREG = 50 mA
VPVIN = 12 V, IVREG = 50 mA
65
VBST − VSW = 5 V
VVREG = 8 V
4.8
tMIN_ON
tMIN_OFF
VBOOT
fSW
fSW
RT = 100 kΩ
200
100
100
1.3
ISS_UP
2.5
PGOOD from low to high
PGOOD from high to low
PGOOD from low to high
PGOOD from high to low
Rev. 0 | Page 3 of 24
1600
3.2
95
5
105
11.7
%
%
%
%
ADP2384
Parameter
Power-Good Deglitch Time
Power-Good Leakage Current
Power-Good Output Low Voltage
EN
EN Rising Threshold
EN Falling Threshold
EN Source Current
Data Sheet
Symbol
Test Conditions/Comments
PGOOD from low to high
PGOOD from high to low
VPGOOD = 5 V
IPGOOD = 1 mA
0.97
EN voltage below falling threshold
EN voltage above rising threshold
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
2
Min
Typ
1024
16
0.01
125
Max
1.17
1.07
5
1
1.28
150
25
Pin-to-pin measurement.
Guaranteed by design.
Rev. 0 | Page 4 of 24
0.1
200
Unit
Clock cycle
Clock cycle
µA
mV
V
V
µA
µA
°C
°C
Data Sheet
ADP2384
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
PVIN, EN, PGOOD
SW
BST
FB, SS, COMP, SYNC, RT
VREG
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +22 V
−1 V to +22 V
VSW + 6 V
−0.3 V to +6 V
−0.3 V to +12 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
θJA is specified for the worst-case conditions, that is, a device
soldered in a 4-layer, JEDEC standard circuit board for surfacemount packages.
Table 3. Thermal Resistance
Package Type
24-Lead LFCSP_WQ
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 24
θJA
42.6
Unit
°C/W
ADP2384
Data Sheet
20 EN
19 PVIN
22 RT
21 PGOOD
24 SS
23 SYNC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 PVIN
COMP 1
FB 2
17 PVIN
25
GND
VREG 3
16 PVIN
15 BST
GND 4
26
SW
SW 5
14 SW
SW 6
PGND 11
PGND 12
PGND 9
PGND 10
SW 7
PGND 8
13 PGND
10725-003
ADP2384
TOP VIEW
NOTES
1. THE EXPOSED GND PAD MUST BE SOLDERED
TO A LARGE, EXTERNAL, COPPER GND PLANE
TO REDUCE THERMAL RESISTANCE.
2. THE EXPOSED SW PAD MUST BE CONNECTED
TO THE SW PINS OF THE ADP2384 BY USING
SHORT, WIDE TRACES, OR ELSE SOLDERED
TO A LARGE, EXTERNAL, COPPER SW PLANE
TO REDUCE THERMAL RESISTANCE.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
COMP
FB
VREG
4
5, 6, 7, 14
8, 9, 10, 11, 12, 13
15
16,17,18,19
20
GND
SW
PGND
BST
PVIN
EN
21
22
PGOOD
RT
23
SYNC
24
SS
25
26
EP, GND
EP, SW
Description
Error Amplifier Output. Connect an RC network from COMP to GND.
Feedback Voltage Sense Input. Connect to a resistor divider from the output voltage, VOUT.
Output of the Internal 8 V Regulator. The control circuits are powered from this voltage. Place a 1 µF, X7R
or X5R ceramic capacitor between this pin and GND.
Analog Ground. Return of internal control circuit.
Switch Node Output. Connect to the output inductor.
Power Ground. Return of low-side power MOSFET.
Supply Rail for the High-Side Gate Drive. Place a 0.1 µF, X7R or X5R capacitor between SW and BST.
Power Input. Connect to the input power source and connect a bypass capacitor between this pin and PGND.
Precision Enable Pin. An external resistor divider can be used to set the turn-on threshold. To enable the
part automatically, connect the EN pin to the PVIN pin.
Power-Good Output (Open Drain). A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
Frequency Setting. Connect a resistor between RT and GND to program the switching frequency from 200 kHz
to 1.4 MHz.
Synchronization Input. Connect this pin to an external clock to synchronize the switching frequency from
200 kHz and 1.4 MHz. See the Oscillator section and Synchronization section for more information.
Soft Start Control. Connect a capacitor from SS to GND to program the soft start time. If this pin is open,
the regulator uses the internal soft start time.
The exposed GND pad must be soldered to a large, external, copper GND plane to reduce thermal resistance.
The exposed SW pad must be connected to the SW pins of the ADP2384, using short, wide traces, or else
soldered to a large, external, copper SW plane to reduce thermal resistance.
Rev. 0 | Page 6 of 24
Data Sheet
ADP2384
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
95
95
90
90
85
85
EFFICIENCY (%)
80
75
70
65
80
75
70
65
INDUCTOR: FDVE1040-3R3M
55
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
INDUCTOR: FDVE1040-6R8M
50
10725-004
55
0
0.5
1.0
1.5
2.0
2.5
3.0
95
95
90
90
85
85
EFFICIENCY (%)
100
80
75
70
65
80
75
70
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
65
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
INDUCTOR: FDVE1040-3R3M
60
55
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
INDUCTOR: FDVE1040-1R5M
50
10725-005
55
4.0
Figure 7. Efficiency at VIN = 12 V, fSW = 300 kHz
100
60
3.5
OUTPUT CURRENT (A)
Figure 4. Efficiency at VIN = 12 V, fSW = 600 kHz
EFFICIENCY (%)
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
60
10725-007
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
60
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
10725-008
EFFICIENCY (%)
TA = 25°C, VIN = 12 V, VOUT = 3.3 V, L = 3.3 µH, COUT = 47 µF × 2, fSW = 600 kHz, unless otherwise noted.
Figure 8. Efficiency at VIN = 5 V, fSW = 600 kHz
Figure 5. Efficiency at VIN = 18 V, fSW = 600 kHz
100
3.2
3.0
70
60
TJ = –40°C
TJ = +25°C
TJ = +125°C
6
8
10
12
14
16
INPUT VOLTAGE (V)
18
2.6
2.4
2.2
TJ = –40°C
TJ = +25°C
TJ = +125°C
2.0
50
4
2.8
20
1.8
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
Figure 6. Shutdown Current vs. VIN
Figure 9. Quiescent Current vs. VIN
Rev. 0 | Page 7 of 24
18
20
10725-009
QUIESCENT CURRENT (mA)
80
10725-006
SHUTDOWN CURRENT (µA)
90
ADP2384
Data Sheet
4.5
1.25
4.4
1.20
EN THRESHOLD (V)
PVIN UVLO THRESHOLD (V)
RISING
RISING
4.3
4.2
4.1
4.0
3.9
1.15
1.10
FALLING
1.05
FALLING
3.8
1.00
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
0.95
–40
10725-010
3.6
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 10. UVLO Threshold vs. Temperature
10725-013
3.7
Figure 13. EN Threshold vs. Temperature
3.30
606
3.25
FEEDBACK VOLTAGE (mV)
SS PULL-UP CURRENT (µA)
604
3.20
3.15
3.10
3.05
3.00
602
600
598
596
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
594
–40
10725-011
20
40
60
80
100
120
100
120
Figure 14. FB Voltage vs. Temperature
8.4
630
8.3
VREG VOLTAGE (V)
620
610
RT = 100kΩ
600
590
580
8.2
8.1
8.0
7.9
7.8
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
7.7
–40
10725-012
FREQUENCY (kHz)
0
TEMPERATURE (°C)
Figure 11. SS Pin Pull-Up Current vs. Temperature
570
–40
–20
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 15. VREG Voltage vs. Temperature
Figure 12. Frequency vs. Temperature
Rev. 0 | Page 8 of 24
10725-015
2.90
–40
10725-014
2.95
Data Sheet
ADP2384
65
PEAK CURRENT LIMIT THRESHOLD (A)
7.0
MOSFET RESISTOR (mΩ)
HIGH-SIDE RDSON
45
35
25
5
–40
–20
0
20
40
60
80
100
6.0
5.5
5.0
4.5
4.0
–40
10725-016
LOW-SIDE RDSON
15
6.5
120
TEMPERATURE (°C)
–20
0
20
40
60
80
100
10725-019
55
120
TEMPERATURE (°C)
Figure 16. MOSFET RDSON vs. Temperature
Figure 19. Current-Limit Threshold vs. Temperature
VOUT (AC)
EN
3
1
IL
VOUT
1
2
SW
PGOOD
4
IOUT
W
CH2 10.0V
CH4 2.00A Ω
M2.00µs
T 50.00%
A CH2
5.00V
10725-017
B
CH1 10mV
CH1 2.00V
CH3 10.0V
Figure 17. Working Mode Waveform
B
W
CH2 5.00V
CH4 5.00A Ω
M2.00ms
T 27.00%
A CH3
8.60V
10725-020
4
2
Figure 20. Soft Start with Full Load
SYNC
EN
3
VOUT
2
1
SW
PGOOD
2
4
IL
B
W
CH2 5.00V
CH4 2.00A Ω
M2.00ms
T 50.20%
A CH2
3.90V
CH2 5.00V
CH4 10.0V
Figure 18. Voltage Precharged Output
M1.00µs
T 50.00%
A CH2
Figure 21. External Synchronization
Rev. 0 | Page 9 of 24
3.40V
10725-021
CH1 2.00V
CH3 10.0V
10725-018
4
ADP2384
Data Sheet
VOUT (AC)
VOUT (AC)
1
1
VIN
SW
3
IOUT
IL
4
B
W
CH4 2.00A Ω
M200µs
T 70.40%
A CH4
2.52A
B
CH1 20.0mV
CH3 5.00V BW
Figure 22. Load Transient Response, 1 A to 4 A
W
CH2 10.0V
B
W
M1.00ms
A CH3
T 30.00%
Figure 25. Line Transient Response, VIN from 8 V to 14 V, IOUT = 4 A
VOUT
VOUT
1
1
SW
SW
2
2
IL
IL
4
A CH1
1.48V
CH1 2.00V
Figure 23. Output Short Entry
4
4
LOAD CURRENT (A)
5
3
2
1
65
75
85
M4.00ms
T 78.80%
A CH1
1.72V
2
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
55
CH2 10.0V
CH4 5.00A Ω
3
95
105
AMBIENT TEMPERATURE (°C)
Figure 24. Output Current vs. Ambient Temperature at VIN = 12 V,
fSW = 600 kHz
0
45
10725-024
0
45
W
Figure 26. Output Short Recovery
5
1
B
10725-026
M4.00ms
T 30.40%
VOUT = 1V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
55
65
75
85
95
105
AMBIENT TEMPERATURE (°C)
Figure 27. Output Current vs. Ambient Temperature at VIN = 12 V,
fSW = 300 kHz
Rev. 0 | Page 10 of 24
10725-027
CH2 10.0V
CH4 5.00A Ω
10725-023
4
CH1 2.00V BW
LOAD CURRENT (A)
12.0V
10725-025
CH1 100mV
10725-022
2
Data Sheet
ADP2384
FUNCTIONAL BLOCK DIAGRAM
VREG
CLK
RT
OSC
BIAS AND DRIVER
REGULATOR
PVIN
SLOPE RAMP
SYNC
UVLO
EN
EN_BUF
BOOST
REGULATOR
1.17V
1µA
4µA
ACS
SLOPE RAMP
Σ
VI_MAX
+
OCP
–
HICCUP
MODE
BST
COMP
0.6V
+
SS
+ AMP
FB
–
DRIVER
SW
CONTROL
LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
OVP
0.7V
NFET
+
CMP
–
ISS
NFET
DRIVER
CLK
PGND
–
NEG CURRENT
–
CMP
+
+
–
0.54V
VREG
VI_NEG
+
PGOOD
DEGLITCH
10725-028
GND
Figure 28. Functional Block Diagram
Rev. 0 | Page 11 of 24
ADP2384
Data Sheet
THEORY OF OPERATION
The ADP2384 operates from an input voltage that ranges from
4.5 V to 20 V and regulates the output voltage from 0.6 V to 90%
of the input voltage. Additional features that maximize design
flexibility include the following: programmable switching
frequency, programmable soft start, external compensation,
precision enable, and a power-good output.
BOOTSTRAP CIRCUITRY
The ADP2384 includes a regulator to provide the gate drive
voltage for the high-side N-MOSFET. It uses differential sensing to
generate a 5 V bootstrap voltage between the BST and SW pins.
It is recommended that a 0.1 µF, X7R or X5R ceramic capacitor
be placed between the BST pin and the SW pin.
OSCILLATOR
The ADP2384 switching frequency is controlled by the RT pin.
A resistor from RT to GND can program the switching frequency
according to the following equation:
CONTROL SCHEME
fSW (kHz) =
PRECISION ENABLE/SHUTDOWN
The EN input pin has a precision analog threshold of 1.17 V
(typical) with 100 mV of hysteresis. When the enable voltage
exceeds 1.17 V, the regulator turns on; when it falls below 1.07 V
(typical), the regulator turns off. To force the regulator to automatically start when input power is applied, connect EN to PVIN.
A 100 kΩ resistor sets the frequency to 600 kHz, and a 42.2 kΩ
resistor sets the frequency to 1.2 MHz. Figure 29 shows the
typical relationship between fSW and RT.
1400
1200
1000
FREQUENCY (kHz)
The ADP2384 uses a fixed frequency, peak current mode PWM
control architecture. At the start of each oscillator cycle, the
high-side N-MOSFET is turned on, putting a positive voltage
across the inductor. When the inductor current crosses the peak
inductor current threshold, the high-side N-MOSFET is turned
off and the low-side N-MOSFET is turned on. This puts a negative
voltage across the inductor, causing the inductor current to
decrease. The low-side N-MOSFET stays on for the rest of the
cycle (see Figure 17).
INTERNAL REGULATOR (VREG)
The on-board regulator provides a stable supply for the internal
circuits. It is recommended that a 1 µF ceramic capacitor be placed
between the VREG pin and GND. The internal regulator includes
a current-limit circuit to protect the output if the maximum
external load current is exceeded.
800
600
400
200
The precision EN pin has an internal pull-down current source
(5 µA) that provides a default turn-off when the EN pin is open.
When the EN pin voltage exceeds 1.17 V (typical), the ADP2384
is enabled and the internal pull-down current source at the EN
pin decreases to 1 µA, which allows users to program the PVIN
UVLO and hysteresis.
69,120
RT (k Ω) + 15
0
20
60
100
140
180
220
RT (kΩ)
260
300
10725-029
The ADP2384 is a synchronous step-down, dc-to-dc regulator
that uses a current mode architecture with an integrated highside power switch and a low-side synchronous rectifier. The
regulator targets high performance applications that require
high efficiency and design flexibility.
Figure 29. Switching Frequency vs. RT
SYNCHRONIZATION
To synchronize the ADP2384, connect an external clock to the
SYNC pin. The frequency of the external clock can be in the range
of 200 kHz to 1.4 MHz. During synchronization, the regulator
operates in continuous conduction mode (CCM), and the rising
edge of the switching waveform runs 180° out of phase to the rising
edge of the external clock.
When the ADP2384 operates in synchronization mode,
a resistor must be connected from the RT pin to GND to
program the internal oscillator to run at 90% to 110% of the
external synchronization clock.
Rev. 0 | Page 12 of 24
Data Sheet
ADP2384
SOFT START
VOUT RISING
1600
(ms)
f SW (kHz)
105%
100%
95%
90%
PGOOD
A slower soft start time can be programmed by using the SS pin.
When a capacitor is connected between the SS pin and GND, an
internal current charges the capacitor to establish the soft start
ramp. The soft start time is calculated using the following equation:
tSS_EXT = 0.6 V × C SS
I SS _ UP
where:
CSS is the soft start capacitance.
ISS_UP is the soft start pull-up current (3.2 µA).
The internal error amplifier includes three positive inputs: the
internal reference voltage, the internal digital soft start voltage,
and the SS pin voltage. The error amplifier regulates the FB
voltage to the lowest of the three voltages.
If the output voltage is charged prior to turn-on, the ADP2384
prevents reverse inductor current that would discharge the output
capacitor. This function remains active until the soft start
voltage exceeds the voltage on the FB pin.
POWER GOOD
The power-good pin (PGOOD) is an active high, open-drain
output that requires an external resistor to pull it up to a voltage.
A logic high on the PGOOD pin indicates that the voltage on
the FB pin (and, therefore, the output voltage) is within regulation.
The power-good circuitry monitors the output voltage on the
FB pin and compares it to the rising and falling thresholds that
are specified in Table 1. If the rising output voltage exceeds the
target value, the PGOOD pin is held low. The PGOOD pin
continues to be held low until the falling output voltage returns
to the target value.
If the output voltage falls below the target output voltage, the
PGOOD pin is held low. The PGOOD pin continues to be held
low until the rising output voltage returns to the target value.
The power-good rising and falling thresholds are shown in
Figure 30. There is a 1024-cycle waiting period before the PGOOD
pin is pulled from low to high, and there is a 16-cycle waiting
period before the PGOOD pin is pulled from high to low.
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
10725-130
tSS_INT =
116.7%
VOUT (%)
The ADP2384 has integrated soft start circuitry to limit the
output voltage rising time and reduce inrush current at startup.
The internal soft start time is calculated using the following
equation:
VOUT FALLING
Figure 30. PGOOD Rising and Falling Thresholds
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2384 has a peak current-limit protection circuit to
prevent current runaway. During the initial soft start, the
ADP2384 uses frequency foldback to prevent output current
runaway. The switching frequency is reduced according to the
voltage on the FB pin, which allows more time for the inductor
to discharge. The correlation between the switching frequency
and the FB pin voltage is shown in Table 5.
Table 5. FB Pin Voltage and Switching Frequency
FB Pin Voltage
VFB ≥ 0.4 V
0.4 V > VFB ≥ 0.2 V
VFB < 0.2 V
Switching Frequency
fSW
fSW/2
fSW/4
For protection against heavy loads, the ADP2384 uses a hiccup
mode for overcurrent protection. When the inductor peak current
reaches the current-limit value, the high-side MOSFET turns off
and the low-side MOSFET turns on until the next cycle. The overcurrent counter increments during this process. If the overcurrent
counter reaches 10 or the FB pin voltage falls to 0.4 V after the
soft start, the regulator enters hiccup mode. The high-side and
low-side MOSFETs are both turned off. The regulator remains
in hiccup mode for 4096 clock cycles and then attempts to restart.
If the current-limit fault has cleared, the regulator resumes normal
operation. Otherwise, it reenters hiccup mode.
The ADP2384 also provides a sink current limit to prevent the
low-side MOSFET from sinking a lot of current from the load.
When the voltage across the low-side MOSFET exceeds the sink
current-limit threshold, which is typically 20 mV, the low-side
MOSFET turns off immediately for the rest of the cycle. Both highside and low-side MOSFETs turn off until the next clock cycle.
In some cases, the input voltage (VPVIN) ramp rate is too slow or
the output capacitor is too large for the output to reach regulation
during the soft start process, which causes the regulator to enter
the hiccup mode. To avoid such occurrences, use a resistor
divider at the EN pin to program the input voltage UVLO,
or use a longer soft start time.
Rev. 0 | Page 13 of 24
ADP2384
Data Sheet
OVERVOLTAGE PROTECTION (OVP)
THERMAL SHUTDOWN
The ADP2384 includes an overvoltage protection feature
to protect the regulator against an output short to a higher
voltage supply or when a strong load disconnect transient
occurs. If the feedback voltage increases to 0.7 V, the internal
high-side and low-side MOSFETs are turned off until the
voltage at the FB pin decreases to 0.63 V. At that time, the
ADP2384 resumes normal operation.
If the ADP2384 junction temperatures rises above 150°C, the
internal thermal shutdown circuit turns off the regulator for selfprotection. Extreme junction temperatures can be the result of
high current operation, poor circuit board thermal design,
and/or high ambient temperature. A 25°C hysteresis is included
in the thermal shutdown circuit so that, if an overtemperature
event occurs, the ADP2384 does not return to normal operation
until the on-chip temperature falls below 125°C. Upon recovery, a
soft start is initiated before normal operation begins.
UNDERVOLTAGE LOCKOUT (UVLO)
Undervoltage lockout circuitry is integrated in the ADP2384 to
prevent the occurrence of power-on glitches. If the VPVIN voltage
falls below 3.8 V typical, the part shuts down and both the
power switch and synchronous rectifier turn off. When the
VPVIN voltage rises above 4.3 V typical, the soft start period
is initiated and the part is enabled.
Rev. 0 | Page 14 of 24
Data Sheet
ADP2384
APPLICATIONS INFORMATION
INPUT CAPACITOR SELECTION
The input capacitor reduces the input voltage ripple caused by
the switch current on PVIN. Place the input capacitor as close
as possible to the PVIN pin. A ceramic capacitor in the 10 μF to
47 μF range is recommended. The loop that is composed of this
input capacitor, the high-side N-MOSFET, and the low-side
N-MOSFET must be kept as small as possible.
The voltage rating of the input capacitor must be greater than
the maximum input voltage. The rms current rating of the input
capacitor should be larger than the value calculated from the
following equation:
ICIN_RMS = IOUT ×
D × (1 − D )
OUTPUT VOLTAGE SETTING
The output voltage of the ADP2384 is set by an external
resistive divider. The resistor values are calculated using
VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) ×
IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT_MAX (2)
where:
VOUT_MAX is the maximum output voltage.
tMIN_OFF is the minimum off time.
IOUT_MAX is the maximum output current.
RBOT 
VOUT_MAX = DMAX × VIN
To limit output voltage accuracy degradation due to FB bias
current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT < 30 kΩ.
As shown in Equation 1 to Equation 3, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.
INDUCTOR SELECTION
Table 6. Resistor Divider Values for Various Output Voltages
RTOP ± 1% (kΩ)
10
10
15
20
47.5
10
22
RBOT ± 1% (kΩ)
15
10
10
10
15
2.21
3
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2384 is typically 125 ns. The
minimum output voltage for a given input voltage and switching
frequency can be calculated using the following equation:
where:
VOUT_MIN is the minimum output voltage.
tMIN_ON is the minimum on time.
fSW is the switching frequency.
RDSON_HS is the high-side MOSFET on resistance.
RDSON_LS is the low-side MOSFET on resistance.
IOUT_MIN is the minimum output current.
RL is the series resistance of the output inductor.
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor value leads to a faster transient response but
degrades efficiency, due to a larger inductor ripple current;
using a large inductor value leads to smaller ripple current
and better efficiency but results in a slower transient response.
As a guideline, the inductor ripple current, ΔIL, is typically set
to one-third of the maximum load current. The inductor value
is calculated using the following equation:
VOLTAGE CONVERSION LIMITATIONS
VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) ×
IOUT_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT_MIN
(3)
where DMAX is the maximum duty cycle.
Table 6 lists the recommended resistor divider values for
various output voltages.
VOUT (V)
1.0
1.2
1.5
1.8
2.5
3.3
5.0
The maximum output voltage, limited by the minimum off time
at a given input voltage and frequency, can be calculated using
the following equation:
The maximum output voltage, limited by the maximum duty
cycle at a given input voltage, can be calculated by using the
following equation:
VOUT = 0.6 × 1 + RTOP 



The maximum output voltage for a given input voltage and
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is typically
200 ns, and the maximum duty cycle of the ADP2384 is
typically 90%.
(1)
L = (VIN − VOUT ) × D
∆I L × f SW
where:
VIN is the input voltage.
VOUT is the output voltage.
D is the duty cycle (D = VOUT/VIN).
ΔIL is the inductor current ripple.
fSW is the switching frequency.
The ADP2384 uses adaptive slope compensation in the current
loop to prevent subharmonic oscillations when the duty cycle is
larger than 50%. The internal slope compensation limits the
minimum inductor value.
Rev. 0 | Page 15 of 24
ADP2384
Data Sheet
For a duty cycle that is larger than 50%, the minimum inductor
value is determined using the following equation:
L (Minimum) = VOUT × (1 − D )
2 × f SW
COUT_UV =
IPEAK = IOUT + ∆I L
2
The saturation current of the inductor must be larger than the peak
inductor current. For ferrite core inductors with a quick saturation
characteristic, the saturation current rating of the inductor should
be higher than the current-limit threshold of the switch. This
prevents the inductor from reaching saturation.
Another example occurs when a load is suddenly removed from
the output, and the energy stored in the inductor rushes into
the output capacitor, causing the output to overshoot.
The output capacitance that is required to meet the overshoot
requirement can be calculated using the following equation:
2
∆I L
12
K OV × ∆I STEP × L
COUT_OV =
2
(VOUT + ∆VOUT _ OV ) 2 − VOUT
The rms current of the inductor is calculated as follows:
I OUT +
2
where:
KUV is a factor, with a typical setting of KUV = 2.
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
The peak inductor current is calculated by
IRMS =
KUV × ∆I STEP × L
2 × (VIN − VOUT ) × ∆VOUT _ UV
2
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 7 lists some recommended inductors.
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects the output ripple voltage
load step transient and the loop stability of the regulator.
For example, during a load step transient where the load is
suddenly increased, the output capacitor supplies the load until
the control loop can ramp up the inductor current. The delay
caused by the control loop causes output undershoot. The
output capacitance that is required to satisfy the voltage droop
requirement can be calculated using the following equation:
2
where:
ΔVOUT_OV is the allowable overshoot on the output voltage.
KOV is a factor, with a typical setting of KOV = 2.
The output ripple is determined by the ESR and the value of the
capacitance. Use the following equation to select a capacitor
that can meet the output ripple requirements:
COUT_RIPPLE =
8 × f SW
∆I L
× ∆VOUT _ RIPPLE
RESR = ∆VOUT _ RIPPLE
∆I L
where:
ΔVOUT_RIPPLE is the allowable output ripple voltage.
RESR is the equivalent series resistance of the output capacitor
in ohms (Ω).
Table 7. Recommended Inductors
Vendor
Toko
Vishay
Wurth Elektronik
Part No.
FDVE1040-1R5M
FDVE1040-2R2M
FDVE1040-3R3M
FDVE1040-4R7M
FDVE1040-6R8M
FDVE1040-100M
IHLP4040DZ-1R0M-01
IHLP4040DZ-1R5M-01
IHLP4040DZ-2R2M-01
IHLP4040DZ-3R3M-01
IHLP4040DZ-4R7M-01
IHLP4040DZ-6R8M-01
IHLP4040DZ-100M-01
744325120
744325180
744325240
744325330
744325420
744325550
Value (µH)
1.5
2.2
3.3
4.7
6.8
10
1.0
1.5
2.2
3.3
4.7
6.8
10
1.2
1.8
2.4
3.3
4.2
5.5
Rev. 0 | Page 16 of 24
ISAT (A)
13.7
11.4
9.8
8.2
7.1
6.1
36
27.5
25.6
18.6
17
13.5
12
25
18
17
15
14
12
IRMS (A)
14.6
11.6
9.0
8.0
7.1
5.2
17.5
15
12
10
9.5
8.0
6.8
20
16
14
12
11
10
DCR (mΩ)
4.6
6.8
10.1
13.8
20.2
34.1
4.1
5.8
9
14.4
16.5
23.3
36.5
1.8
3.5
4.75
5.9
7.1
10.3
Data Sheet
ADP2384
Select the largest output capacitance given by COUT_UV, COUT_OV,
and COUT_RIPPLE to meet both load transient and output ripple
performance.
The selected output capacitor voltage rating should be greater than
the output voltage. The rms current rating of the output capacitor
must be larger than the value that is calculated by
The ADP2384 uses a transconductance amplifier for the error
amplifier and to compensate the system. Figure 32 shows the
simplified, peak current mode control, small signal circuit.
VOUT
RTOP
VCOMP
–
gm
+
ICOUT_RMS = ∆I L
12
VOUT
RBOT
AVI
COUT
R
RC
PROGRAMMING THE INPUT VOLTAGE UVLO
+
CCP
–
RESR
CC
10725-031
The ADP2384 has a precision enable input that can be used to
program the UVLO threshold of the input voltage (see Figure 31).
Figure 32. Simplified Peak Current Mode Control, Small Signal Circuit
PVIN
ADP2384
The compensation components, RC and CC, contribute a zero,
and RC and the optional CCP contribute an optional pole.
RTOP_EN
The closed-loop transfer equation is as follows:
EN CMP
EN
TV (s) =
1.17V
RBOT_EN
4µA
1 + RC × CC × s
× GVD ( s )


R × CC × CCP
× s 
s × 1 + C
CC + CCP


10725-030
1µA
Figure 31. Programming the Input Voltage UVLO
The following design guideline shows how to select the RC, CC,
and CCP compensation components for ceramic output capacitor
applications:
Use the following equation to calculate RTOP_EN and RBOT_EN:
RTOP_EN = 1.07 V × V IN _ RISING − 1.17 V × V IN _ FALLING
1.07 V × 5 μA − 1.17 V × 1 μA
RBOT_EN =
1.
1.17 V × RTOP _ EN
VIN _ RISING − RTOP _ EN × 5 μA − 1.17 V
2.
where:
VIN_RISING is the VIN rising threshold.
VIN_FALLING is the VIN falling threshold.
0.6 V × g m × AVI
3.
For peak current mode control, the power stage can be simplified
as a voltage controlled current source supplying current to the
output capacitor and load resistor. It is composed of one domain
pole and a zero that is contributed by the output capacitor ESR.
The control-to-output transfer function is based on the following:

s
4.

1
2 × π × ( R + RESR ) × COUT
CCP is optional. It can be used to cancel the zero caused by
the ESR of the output capacitor.
CCP = RESR × COUT
RC


s
1 + 2 × π × f 
P 

fP =
Place the compensation zero at the domain pole, fP; then
determine CC by using the following equation:
CC = ( R + RESR ) × COUT
RC
GVD (s) = VOUT ( s ) = AVI × R ×  1 + 2 × π × f 
Z 

VCOMP ( s )
1
2 × π × RESR × COUT
Determine the cross frequency, fC. Generally, fC is between
fSW/12 and fSW/6.
Calculate RC using the following equation:
RC = 2 × π × VOUT × COUT × f C
COMPENSATION DESIGN
fZ =
− gm
RBOT
×
×
RBOT + RTOP CC + CCP
ADIsimPower DESIGN TOOL
where:
AVI = 8.7 A/V.
R is the load resistance.
COUT is the output capacitance.
RESR is the equivalent series resistance of the output capacitor.
The ADP2384 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs that are optimized for a specific design goal. The
tools enable the user to generate a full schematic and bill of
materials and calculate performance in minutes. ADIsimPower
can optimize designs for cost, area, efficiency, and part count,
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For more
information about theADIsimPower design tools, refer to
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can request an unpopulated board.
Rev. 0 | Page 17 of 24
ADP2384
Data Sheet
DESIGN EXAMPLE
ADP2384
PVIN
CIN
10µF
25V
BST
CBST L1
0.1µF 3.3µH
EN
RT
100kΩ
CVREG
1µF
CSS
22nF
VOUT = 3.3V
SW
PGOOD
RTOP
10kΩ
1%
SYNC
COUT2
47µF
6.3V
COUT1
47µF
6.3V
FB
RT
COMP
VREG
SS
GND PGND
CCP
3.9pF
RC
31.6kΩ
CC
1500pF
RBOT
2.21kΩ
1%
10725-032
VIN = 12V
Figure 33. Schematic for Design Example
This section describes the procedures for selecting the external
components, based on the example specifications that are listed
in Table 8. See Figure 33 for the schematic of this design example.
Table 8. Step-Down DC-to-DC Regulator Requirements
Parameter
Input Voltage
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
Switching Frequency
This calculation results in L = 3.323 μH. Choose the standard
inductor value of 3.3 μH.
The peak-to-peak inductor ripple current can be calculated
using the following equation:
ΔIL = (VIN − VOUT ) × D
L × f SW
Specification
VIN = 12.0 V ± 10%
VOUT = 3.3 V
IOUT = 4 A
∆VOUT_RIPPLE = 33 mV
±5%, 1 A to 4 A, 2 A/μs
fSW = 600 kHz
This calculation results in ∆IL = 1.21 A.
Use the following equation to calculate the peak inductor
current:
IPEAK = IOUT + ∆I L
2
OUTPUT VOLTAGE SETTING
Choose a 10 kΩ resistor as the top feedback resistor (RTOP),
and calculate the bottom feedback resistor (RBOT) by using the
following equation:

0.6
RBOT = RTOP × 

V
 OUT − 0.6 
This calculation results in IPEAK = 4.605 A.
Use the following equation to calculate the rms current flowing
through the inductor:
IRMS =
I OUT +
2
∆I L
12
2
This calculation results in IRMS = 4.015 A.
To set the output voltage to 3.3 V, the resistors values are as
follows: RTOP = 10 kΩ, and RBOT = 2.21 kΩ.
FREQUENCY SETTING
Connect a 100 kΩ resistor from the RT pin to GND to set the
switching frequency to 600 kHz.
Based on the calculated current value, select an inductor with
a minimum rms current rating of 4.02 A and a minimum
saturation current rating of 4.61 A.
INDUCTOR SELECTION
However, to protect the inductor from reaching its saturation
point under the current-limit condition, the inductor should be
rated for at least a 6 A saturation current for reliable operation.
The peak-to-peak inductor ripple current, ∆IL, is set to 30% of
the maximum output current. Use the following equation to
estimate the inductor value:
Based on the requirements described previously, select a 3.3 μH
inductor, such as the FDVE1040-3R3M from Toko, which has
a 10.1 mΩ DCR and a 9.8 A saturation current.
L = (VIN − VOUT ) × D
∆I L × f SW
where:
VIN = 12 V.
VOUT = 3.3 V.
D = 0.275.
∆IL = 1.2 A.
fSW = 600 kHz.
Rev. 0 | Page 18 of 24
Data Sheet
ADP2384
The 47 µF ceramic output capacitor has a derated value of 32 µF.
OUTPUT CAPACITOR SELECTION
The output capacitor is required to meet both the output voltage
ripple and load transient response requirements.
RC = 2 × π × 3.3 V × 2 × 32 μF × 60 kHz = 32.5 kΩ
0.6 V × 470 μs × 8.7 A/V
To meet the output voltage ripple requirement, use the following
equation to calculate the ESR and capacitance value of the output
capacitor:
CC = (0.825 Ω + 0.002 Ω) × 2 × 32 μF = 1629 pF
CCP = 0.002 Ω × 2 × 32 μF = 3.9 pF
32.5 k Ω
Choose standard components, as follows: RC = 31.6 kΩ,
CC = 1500 pF, and CCP = 3.9 pF.
∆VOUT _ RIPPLE
∆I L
This calculation results in COUT_RIPPLE = 7.6 μF, and RESR = 27 mΩ.
Figure 34 shows the bode plot at 4 A. The cross frequency is
59 kHz, and the phase margin is 55°.
To meet the ±5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
COUT_UV =
K OV × ∆I STEP × L
2
(VOUT + ∆VOUT _ OV ) 2 − VOUT
MAGNITUDE (dB)
COUT_OV =
2
KUV × ∆I STEP × L
2 × (VIN − VOUT ) × ∆VOUT _ UV
2
where:
KOV = KUV = 2 are the coefficients for estimation purposes.
∆ISTEP = 3 A is the load transient step.
∆VOUT_OV = 5%VOUT is the overshoot voltage.
∆VOUT_UV = 5%VOUT is the undershoot voltage.
60
180
48
144
36
108
24
72
12
36
0
0
–12
–36
–24
–72
–36
–108
–48
–144
–60
1k
PHASE (Degrees)
RESR =
∆I L
8 × f S × ∆VOUT _ RIPPLE
–180
10k
100k
1M
FREEQUENCY (Hz)
This calculation results in COUT_OV = 53.2 μF, and COUT_UV = 20.7 μF.
According to the calculation, the output capacitance must be
greater than 53 μF, and the ESR of the output capacitor must be
smaller than 27 mΩ. It is recommended that two pieces of 47
μF/X5R/6.3 V ceramic capacitors be used, such as the
GRM32ER60J476ME20 from Murata, with an ESR of 2 mΩ.
COMPENSATION COMPONENTS
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this case, fSW is running at 600 kHz;
therefore, the fC is set to 60 kHz.
10725-040
COUT_RIPPLE =
32.5 k Ω
Figure 34. Bode Plot at 4 A
SOFT START TIME PROGRAM
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
CSS = TSS _ EXT × I SS _UP = 4 ms × 3.2 μA = 21.3 nF
0.6
0.6 V
Choose a standard component value, as follows: CSS = 22 nF.
INPUT CAPACITOR SELECTION
A minimum 10 μF ceramic capacitor must be placed near the
PVIN pin. In this application, it is recommended that one 10 μF,
X5R, 25 V ceramic capacitor be used.
Rev. 0 | Page 19 of 24
ADP2384
Data Sheet
RECOMMENDED EXTERNAL COMPONENTS
Table 9. Recommended External Components for Typical Applications with 4 A Output Current
fSW (kHz)
300
600
1000
1
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
12
5
5
5
5
5
5
12
12
12
5
5
5
5
5
5
VOUT (V)
1
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
L (µH)
2.2
3.3
3.3
4.7
4.7
6.8
10
2.2
2.2
3.3
3.3
3.3
3.3
2.2
2.2
2.2
3.3
4.7
1
1
1.5
1.5
1.5
1.5
1.5
2.2
2.2
1
1
1
1
1
1
COUT (µF) 1
680
680
470
470
2 × 100
2 × 100
100 + 47
680
470
470
3 × 100
2 × 100
2 × 100
3 × 100
2 × 100
2 × 47
2 × 47
100
3 × 100
2 × 100
2 × 100
100 + 47
100
100
100
100
100
3 × 100
2 × 100
100 + 47
2 × 47
100
100
RTOP (kΩ)
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
15
20
47.5
10
22
10
10
15
20
47.5
10
47.5
10
22
10
10
15
20
47.5
10
RBOT (kΩ)
15
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
10
15
2.21
3
15
10
10
10
15
2.21
15
2.21
3
15
10
10
10
15
2.21
RC (kΩ)
47
59
47
60.4
22
29.4
34
47
39
47
24
22
29.4
39
31.6
24
31.6
44.2
26.7
21
26.7
24
22
28
37.4
47
69
43.2
33
33
30
37.4
47
CC (pF)
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
1000
1000
1000
1000
1000
1000
1000
1000
1000
CCP (pF)
150
100
100
68
10
8.2
4.7
150
100
100
15
10
8.2
10
8.2
4.7
4.7
2.2
10
10
10
8.2
4.7
4.7
3.3
2.2
1
8.2
6.8
4.7
4.7
3.3
2.2
680 μF: 4 V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. 0 | Page 20 of 24
Data Sheet
ADP2384
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good printed circuit board (PCB) layout is essential for obtaining
the best performance from the ADP2384. Poor PCB layout can
degrade the output regulation, as well as the electromagnetic
interference (EMI) and electromagnetic compatibility (EMC)
performance. Figure 36 shows an example of a good PCB layout
for the ADP2384. For optimum layout, refer to the following
guidelines:
•
•
•
ADP2384
VIN
PVIN
CIN
BST
CBST
EN
RTOP
SYNC
VREG
CVREG
GND PGND
PULL UP
PVIN
PVIN
PGOOD
SYNC
RT
EN
RT
CSS
SS
CSS
CC
Figure 35. High Current Path in the PCB Circuit
COMP
PVIN
FB
GND
PVIN
VREG
PVIN
BST
CVREG
GND
SW
SW
SW
SW
INPUT INPUT
BYPASS BULK
CAP
CAP
CBST
+
PGND
PGND
PGND
PGND
PGND
PGND
SW
SW
RC
SS
INDUCTOR
POWER GROUND PLANE
OUTPUT
CAPACITOR
10725-034
VOUT
VIA
BOTTOM LAYER TRACE
COPPER PLANE
Figure 36. Recommended PCB Layout
Rev. 0 | Page 21 of 24
10725-033
RT
RBOT
COMP
RT
ANALOG GROUND PLANE
RTOP
COUT
FB
In addition, ensure that the high current path from the power
ground plane through the inductor and output capacitor
back to the power ground plane is as short as possible by
tying the PGND pins of the ADP2384 to the PGND plane
as close as possible to the input and output capacitors.
RBOT
VOUT
L
SW
PGOOD
CC
•
RC
•
CCP
•
Use separate analog ground planes and power ground
planes. Connect the ground reference of sensitive analog
circuitry, such as output voltage divider components, to
analog ground. In addition, connect the ground reference
of power components, such as input and output capacitors,
to power ground. Connect both ground planes to the exposed
GND pad of the ADP2384.
Place the input capacitor, inductor, and output capacitor as
close as possible to the IC, and use short traces.
Ensure that the high current loop traces are as short and as
wide as possible. Make the high current path from the input
capacitor through the inductor, the output capacitor, and the
power ground plane back to the input capacitor as short as
possible. To accomplish this, ensure that the input and output
capacitors share a common power ground plane.
Connect the exposed GND pad of the ADP2384 to a large,
external copper ground plane to maximize its power
dissipation capability and minimize junction temperature.
In addition, connect the exposed SW pad to the SW pins
of the ADP2384 using short, wide traces; or connect the
exposed SW pad to a large copper plane of the switching
node for high current flow.
Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Minimize
the length of the trace that connects the top of the feedback
resistor divider to the output while keeping the trace away
from the high current traces and the switching node to
avoid noise pickup. To further reduce noise pickup, place
an analog ground plane on either side of the FB trace and
ensure that the trace is as short as possible to reduce the
parasitic capacitance pickup.
ADP2384
Data Sheet
TYPICAL APPLICATIONS CIRCUITS
ADP2384
BST
PVIN
CIN
10µF
25V
CBST L1
0.1µF 1.5µH
EN
PGOOD
RT
124kΩ
CVREG
1µF
VOUT = 1.2V
SW
COUT1
100µF
6.3V
RTOP
10kΩ
1%
SYNC
COUT2
100µF
6.3V
COUT3
100µF
6.3V
FB
RT
SS
CCP
10pF
GND PGND
CSS
22nF
RBOT
10kΩ
1%
COMP
VREG
RC
27.4kΩ
CC
2.2nF
10725-036
VIN = 12V
Figure 37. Typical Applications Circuit, VIN = 12 V, VOUT = 1.2 V, IOUT = 4 A, fSW = 500 kHz
ADP2384
BST
PVIN
CIN
10µF
25V
CBST L1
0.1µF 2.2µH
EN
SW
PGOOD
RT
100kΩ
CVREG
1µF
RTOP
20kΩ
1%
SYNC
VOUT = 1.8V
COUT1
100µF
6.3V
COUT2
100µF
6.3V
FB
RT
COMP
VREG
SS
CCP
8.2pF
GND PGND
RC
31.6kΩ
CC
1.5nF
RBOT
10kΩ
1%
10725-035
VIN = 12V
Figure 38. Typical Applications Circuit Using Internal Soft Start, VIN = 12 V, VOUT = 1.8 V, IOUT = 4 A, fSW = 600 kHz
ADP2384
BST
PVIN
CIN
10µF
25V
CBST L1
0.1µF 4.7µH
EN
SW
PGOOD
RT
124kΩ
RTOP
22kΩ
1%
SYNC
CSS
22nF
VOUT = 5V
FB
RT
COMP
VREG
CVREG
1µF
COUT
100µF
6.3V
SS
GND PGND
CCP
2.2pF
RC
44.2kΩ
CC
1.5nF
RBOT
3kΩ
1%
10725-037
VIN = 12V
Figure 39. Typical Applications Circuit with Programming Switching Frequency at 500 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 4 A, fSW = 500 kHz
Rev. 0 | Page 22 of 24
Data Sheet
ADP2384
OUTLINE DIMENSIONS
PIN 1
INDICATOR
2.80
2.70
2.60
0.50
BSC
24
19
18
EXPOSED
PAD
TOP VIEW
0.80
0.75
0.70
SEATING
PLANE
12
6
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.25
0.20
0.15
1
EXPOSED
PAD
13
0.50
0.40
0.30
PIN 1
INDICATOR
1.50
1.40
1.30
0.45
0.35
0.25
1.05
0.95
0.85
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD .
06-24-2010-A
4.10
4.00 SQ
3.90
Figure 40. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP2384ACPZN-R7
ADP2384-EVALZ
1
Temperature Range
−40°C to +125°C
Package Description
24-Lead LFCSP_WQ
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
Package Option
CP-24-12
Packing
7” Tape and Reel
ADP2384
Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10725-0-8/12(0)
Rev. 0 | Page 24 of 24