AT49(H)BV/(H)LV01 Features • • • • • • • • • • Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Fast Read Access Time - 55 ns Internal Program Control and Timer 8K bytes Boot Block With Lockout Fast Erase Cycle Time - 10 seconds Byte By Byte Programming - 30 µs/Byte typical Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation – 25 mA Active Current – 50 µA CMOS Standby Current • Typical 10,000 Write Cycles Description The AT49(H)BV010 and the AT49(H)LV010 are 3-volt-only, 1-megabit Flash memories organized as 131,072 words of 8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 55 ns with power dissipation of just 90 mW over the commercial temperature range. When the devices are deselected, the CMOS standby current is less than 50 µA. To allow for simple in-system reprogrammability, the AT49(H)BV/(H)LV010 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49(H)BV/(H)LV010 is performed by erasing the entire 1 megabit of memory and then programming on a byte by byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. (continued) 1-Megabit (128K x 8) Single 2.7-volt Battery-Voltage™ Flash Memory AT49BV010 AT49HBV010 AT49LV010 AT49HLV010 Pin Configurations Pin Name Function A0 - A16 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 4 3 2 1 32 31 30 A12 A15 A16 NC VCC WE A17 PLCC Top View A14 A13 A8 A9 A11 OE A10 CE I/O7 TSOP Top View Type 1 A11 A9 A8 A13 A14 NC WE VCC NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 0677B-A–9/97 1 The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. Block Diagram DATA INPUTS/OUTPUTS I/O0 - I/O7 VCC GND OE WE CE ADDRESS INPUTS OE, CE AND WE LOGIC DATA LATCH INPUT/OUTPUT BUFFERS Y DECODER Y-GATING X DECODER MAIN MEMORY (120K BYTES) OPTIONAL BOOT BLOCK (8K BYTES) 01FFF 00000 Device Operation READ: The AT49(H)BV/(H)LV010 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. ERASURE: Before a byte can be reprogrammed, the 128K bytes memory array (or 120K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified t BP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. 2 AT49(H)BV/(H)LV010 BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 00000H to 01FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. AT49(H)BV/(H)LV010 For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49(H)BV/(H)LV010 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49(H)BV/(H)LV010 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49(H)BV/(H)LV010 in the following ways: (a) V CC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V. Command Definition (in Hex) Command Sequence Bus Cycles 1st Bus Cycle Addr Data 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data 2AAA 55 5555 10 2AAA 55 5555 40 Read 1 Addr DOUT Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr DIN Boot Block Lockout(1) 6 5555 AA 2AAA 55 5555 80 5555 AA Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit(2) 3 5555 AA 2AAA 55 5555 F0 Product ID Exit(2) 1 XXXX F0 Notes: 5th Bus Cycle 1. The 8K byte boot sector has the address range 00000H to 01FFFH. 2. Either one of the Product ID exit commands can be used. Absolute Maximum Ratings* Temperature Under Bias ......................-55°C to +125°C Storage Temperature............................-65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground......................... -0.6V to +6.25V All Output Voltages with Respect to Ground................... -0.6V to VCC + 0.6V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on OE with Respect to Ground......................... -0.6V to +13.5V 3 DC and AC Operating Range Operating Temperature (Case) VCC Power Supply AT49HLV 010-55 AT49HBV/ HLV010-70 AT49HBV/ HLV010-90 AT49BV/ LV010-12 AT49BV010-15 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C AT49LV010 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V N/A AT49BV010 N/A 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V Com. Operating Modes Mode CE OE WE Ai I/O Read VIL VIL VIH Ai DOUT Program(2) VIL VIH VIL Ai DIN Standby/Write Inhibit VIH X(1) X X High Z Program Inhibit X X VIH Program Inhibit X VIL X Output Disable X VIH X VIL VIL VIH High Z Product Identification Hardware A1 - A16 = VIL, A9 = VH,(3) A0 = VIL Manufacturer Code(4) A1 - A16 = VIL, A9 = VH,(3) A0 = VIH Device Code(4) Software(5) Notes: A0 = VIL, A1 - A16 = VIL Manufacturer Code(4) A0 = VIH, A1 - A16 = VIL Device Code(4) 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V ± 0.5V. 4. Manufacturer Code: 1FH, Device Code: 17H. 5. See details under Software Product Identification Entry/Exit. DC Characteristics Symbol Parameter Condition ILI Input Load Current ILO Max Units VIN = 0V to VCC 10 µA Output Leakage Current VI/O = 0V to VCC 10 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC 50 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC 1 mA ICC(1) VCC Active Current f = 5 MHz; IOUT = 0 mA 25 mA VIL Input Low Voltage 0.6 V VIH Input High Voltage VOL Output Low Voltage IOL = 2.1 mA Output High Voltage IOH = -100 µA; VCC = 3.0V VOH Note: 4 1. In the erase mode, ICC is 50 mA. AT49(H)BV/(H)LV010 Min 2.0 V 0.45 2.4 V V AT49(H)BV/(H)LV010 AC Read Characteristics AT49HLV 010-55 AT49HBV/ HLV010-70 AT49HBV/ HLV010-90 Min Min Symbol Parameter tACC Address to Output Delay 55 70 90 tCE (1) CE to Output Delay 55 70 tOE (2) OE to Output Delay 30 35 tDF (3, 4) tOH Min CE or OE to Output Float 0 Output Hold from OE, CE or Address, whichever occurred first 0 Max 25 Max 0 25 AT49BV01015 Max Units 120 150 ns 90 120 150 ns 40 50 0 70 ns 30 0 40 ns Max 0 0 AT49BV/ LV010-12 Min 25 Max 0 0 0 Min 0 ns AC Read Waveforms(1)(2)(3)(4) ADDRESS ADDRESS VALID CE tCE OE tDF tACC HIGH Z OUTPUT Notes: tOH OUTPUT VALID 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impace on tACC. 3. tDF is specified from OE or CE whichever occurs frist (CL - 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level AC DRIVING LEVELS 2.4V Output Test Load 55/70 ns AC MEASUREMENT LEVEL 1.5V 0.4V 90/120/150 ns 3.0V 3.0V 1.8K 1.8K OUTPUT PIN tR, tF < 5 ns 1.3K OUTPUT PIN 30 pF 1.3K 100 pF Pin Capacitance (f = 1 MHz, T = 25°C)(1) Typ Max Units Conditions CIN 4 6 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note: 1. This parameter is characterized and is not 100% tested. 5 AC Byte Load Characteristics Symbol Parameter Min tAS, tOES Address, OE Set-up Time tAH Address Hold Time tCS Units 0 ns 100 ns Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 200 ns tDS Data Set-up Time 100 ns tDH, tOEH Data, OE Hold Time 0 ns tWPH Write Pulse Width High 200 ns AC Byte Load Waveforms WE Controlled OE tOES tOEH ADDRESS tAS tAH tCH CE tCS WE tWP tDS tWPH tDH DATA IN CE Controlled OE tOES tOEH ADDRESS tAS tAH tCH WE tCS CE tWP tDS DATA IN 6 Max AT49(H)BV/(H)LV010 tWPH tDH AT49(H)BV/(H)LV010 Program Cycle Characteristics Symbol Parameter Min tBP Byte Programming Time tAS Address Set-up Time tAH Typ Max Units µs 30 0 ns Address Hold Time 100 ns tDS Data Set-up Time 100 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 200 ns tWPH Write Pulse Width High 200 ns tEC Erase Cycle Time 10 seconds Program Cycle Waveforms PROGRAM CYCLE OE CE tWP tWPH tBP WE tAH tAS A0-A16 5555 tDH 2AAA 5555 ADDRESS tDS AA DATA 55 A0 INPUT DATA Chip Erase Cycle Waveforms OE CE tWP tWPH WE tAS A0-A16 tDH tAH 5555 2AAA 5555 5555 2AAA 5555 tDS DATA Note: tEC AA 55 80 AA 55 10 BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 OE must be high only when WE and CE are both low. 7 Data Polling Characteristics(1) Symbol Parameter tDH Data Hold Time 0 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) tWR Write Recovery Time Notes: Min Typ Max Units ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. Data Polling Waveforms WE CE tOEH OE tDH tOE tWR I/O7 A0-A17 An An An An An Toggle Bit Characteristics(1) Symbol Parameter tDH Data Hold Time 0 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) tOEHP OE High Pulse tWR Write Recovery Time Notes: Min Typ Max Units ns 150 ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. Toggle Bit Waveforms(1)(2)(3) WE CE tOEH tOEHP OE tDH I/O6 Notes: tOE tWR HIGH Z 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 8 AT49(H)BV/(H)LV010 AT49(H)BV/(H)LV010 Software Product Identification Entry(1) Boot Block Lockout Feature Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 LOAD DATA 80 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) LOAD DATA AA TO ADDRESS 5555 Software Product Identification Exit(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ANY ADDRESS OR LOAD DATA 40 TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE(4) PAUSE 1 second(2) LOAD DATA F0 TO ADDRESS 5555 Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled. EXIT PRODUCT IDENTIFICATION MODE(4) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A16 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does note remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturers Code: 1FH Device Code: 17H. 9 Ordering Information(1) ICC (mA) tACC (ns) Active Standby 70 25 90 120 150 Note: Ordering Code Package 0.05 AT49HBV010-70JC AT49HBV010-70TC 32J 32T Commercial (0°C - 70°C) 25 0.05 AT49HBV010-70JI AT49HBV010-70TI 32J 32T Industrial (-40°C - 85°C) 25 0.05 AT49HBV010-90JC AT49HBV010-90TC 32J 32T Commercial (0°C - 70°C) 25 0.05 AT49HBV010-90JI AT49HBV010-90TI 32J 32T Industrial (-40°C - 85°C) 25 0.05 AT49BV010-12JC AT49BV010-12TC 32J 32T Commercial (0°C - 70°C) 25 0.05 AT49BV010-12JI AT49BV010-12TI 32J 32T Industrial (-40°C - 85°C) 25 0.05 AT49BV010-15JC AT49BV010-15TC 32J 32T Commercial (0°C - 70°C) 25 0.05 AT49BV010-15JI AT49BV010-15TI 32J 32T Industrial (-40°C - 85°C) 1. The 49(H)BV/(H)LV010 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher address range should contact Atmel. Package Type 32J 32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC) 32T 32-Lead, Thin Small Outline Package (TSOP) 10 Operation Range AT49(H)BV/(H)LV010 AT49(H)BV/(H)LV010 Ordering Information (Continued) ICC (mA) tACC (ns) Active Standby 55 25 70 90 120 Ordering Code Package Operation Range 0.05 AT49HLV010-55JC AT49HLV010-55TC 32J 32T Commercial (0°C - 70°C) 25 0.05 AT49HLV010-55JI AT49HLV010-55TI 32J 32T Industrial (-40°C - 85°C) 25 0.05 AT49HLV010-70JC AT49HLV010-70TC 32J 32T Commercial (0°C - 70°C) 25 0.05 AT49HLV010-70JI AT49HLV010-70TI 32J 32T Industrial (-40°C - 85°C) 25 0.05 AT49HLV010-90JC AT49HLV010-90TC 32J 32T Commercial (0°C - 70°C) 25 0.05 AT49HLV010-90JI AT49HLV010-90TI 32J 32T Industrial (-40°C - 85°C) 25 0.05 AT49LV010-12JC AT49LV010-12TC 32J 32T Commercial (0°C - 70°C) 25 0.05 AT49LV010-12JI AT49LV010-12TI 32J 32T Industrial (-40°C - 85°C) Package Type 32J 32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC) 32T 32-Lead, Thin Small Outline Package (TSOP) 11