APT42F50B
APT42F50S
600V, 42A, 0.14Ω Max, trr, ≤250ns
N-Channel FREDFET
Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET.
This 'FREDFET' version has a drain-source (body) diode that has been optimized for
high reliability in ZVS phase shifted bridge and other circuits through reduced trr, soft
recovery, and high recovery dv/dt capability. Low gate charge, high gain, and a greatly
reduced ratio of Crss/Ciss result in excellent niose immunity and low switching loss. The
intrinsic gate resistance and capacitance of the poly-silicon gate structure help control
di/dt during switching, resulting in low EMI and reliable paralleling, even when switching
at very high frequency.
TO
-2
47
D3PAK
APT42F50B
APT42F50S
Single die FREDFET
D
G
S
TYPICAL APPLICATIONS
FEATURES
• Fast switching with low EMI
• ZVS phase shifted and other full full bridge
• Low trr for high reliability
• Half bridge
• Ultra low Crss for improved noise immunity
• PFC and other boost converter
• Low gate charge
• Buck converter
• Avalanche energy rated
• Single and two switch forward
• RoHS compliant
• Flyback
Absolute Maximum Ratings
Symbol
ID
Parameter
Unit
Ratings
Continuous Drain Current @ TC = 25°C
42
Continuous Drain Current @ TC = 100°C
27
A
IDM
Pulsed Drain Current
VGS
Gate-Source Voltage
±30
V
EAS
Single Pulse Avalanche Energy 2
930
mJ
IAR
Avalanche Current, Repetitive or Non-Repetitive
21
A
1
135
Thermal and Mechanical Characteristics
Max
Unit
W
PD
Total Power Dissipation @ TC = 25°C
624
RθJC
Junction to Case Thermal Resistance
0.20
RθCS
Case to Sink Thermal Resistance, Flat, Greased Surface
TJ,TSTG
Operating and Storage Junction Temperature Range
TL
Soldering Temperature for 10 Seconds (1.6mm from case)
WT
Package Weight
Torque
Mounting Torque ( TO-247 Package), 6-32 or M3 screw
Microsemi Website - http://www.microsemi.com
0.15
-55
150
300
°C/W
°C
0.22
oz
6.2
g
10
in·lbf
1.1
N·m
9-2006
Typ
Rev A
Min
Characteristic
050-8084
Symbol
Static Characteristics
TJ = 25°C unless otherwise specified
Symbol
Parameter
Test Conditions
Min
VBR(DSS)
Drain-Source Breakdown Voltage
VGS = 0V, ID = 250µA
500
∆VBR(DSS)/∆TJ
Drain-Source On Resistance
VGS(th)
Gate-Source Threshold Voltage
∆VGS(th)/∆TJ
VGS = 10V, ID = 21A
3
Zero Gate Voltage Drain Current
IGSS
Gate-Source Leakage Current
Dynamic Characteristics
Forward Transconductance
Ciss
Input Capacitance
Crss
Reverse Transfer Capacitance
Coss
Output Capacitance
TJ = 125°C
0.60
0.11
4
-10
0.14
5
100
500
±100
Min
f = 1MHz
Co(er)
5
Effective Output Capacitance, Energy Related
Typ
Max
32
6810
90
735
VGS = 0V, VDS = 25V
Effective Output Capacitance, Charge Related
Unit
V
V/°C
Ω
V
mV/°C
µA
nA
Unit
S
pF
425
VGS = 0V, VDS = 0V to 333V
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
td(on)
Turn-On Delay Time
tf
VGS = 0V
Test Conditions
VDS = 50V, ID = 21A
4
td(off)
TJ = 25°C
Max
TJ = 25°C unless otherwise specified
Co(cr)
tr
VDS = 500V
Typ
VGS = ±30V
Parameter
gfs
3
VGS = VDS, ID = 1mA
Threshold Voltage Temperature Coefficient
IDSS
Symbol
Reference to 25°C, ID = 250µA
Breakdown Voltage Temperature Coefficient
RDS(on)
AP42F50B_S
Current Rise Time
Turn-Off Delay Time
215
170
38
80
29
35
80
26
VGS = 0 to 10V, ID = 21A,
VDS = 250V
Resistive Switching
VDD = 333V, ID = 21A
RG = 4.7Ω 6 , VGG = 15V
Current Fall Time
nC
ns
Source-Drain Diode Characteristics
Symbol
IS
ISM
VSD
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 1
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Irrm
Reverse Recovery Current
dv/dt
Peak Recovery dv/dt
Test Conditions
Min
Typ
D
MOSFET symbol
showing the
integral reverse p-n
junction diode
(body diode)
Max
42
A
G
135
S
ISD = 21A, TJ = 25°C, VGS = 0V
1.0
250
525
TJ = 25°C
TJ = 125°C
ISD = 21A 3
TJ = 25°C
diSD/dt = 100A/µs
TJ = 125°C
Unit
TJ = 25°C
TJ = 125°C
ISD ≤ 21A, di/dt ≤1000A/µs, VDD = 400V,
TJ = 125°C
10
25
9
12
V
ns
µC
A
20
V/ns
1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature.
2 Starting at TJ = 25°C, L = 4.22mH, RG = 4.7Ω, IAS = 21A.
050-8084
Rev A
9-2006
3 Pulse test: Pulse Width < 380µs, duty cycle < 2%.
4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS.
5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(cr) for any value of
VDS less than V(BR)DSS, use this equation: Co(er) = -1.84E-7/VDS^2 + 3.75E-8/VDS + 1.05E-10.
6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452)
Microsemi reserves the right to change, without notice, the specifications and information contained herein.
160
V
GS
= 10V
ID, DRIAN CURRENT (A)
TJ = 25°C
60
40
60
6V
50
40
30
20
5V
TJ = 150°C
10
TJ = 125°C
0
25
20
15
10
5
0
VDS(ON), DRAIN-TO-SOURCE VOLTAGE (V)
4.5V
0
NORMALIZED TO
VGS = 10V @ 21A
VDS> ID(ON) x RDS(ON) MAX.
250µSEC. PULSE TEST
@ <0.5 % DUTY CYCLE
120
2.0
ID, DRAIN CURRENT (A)
1.0
0.5
100
TJ = -55°C
80
TJ = 25°C
60
TJ = 125°C
40
20
0
0
25 50 75 100 125 150
0
-55 -25
TJ, JUNCTION TEMPERATURE (°C)
Figure 3, RDS(ON) vs Junction Temperature
60
0
8
7
6
5
4
3
2
1
VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 4, Transfer Characteristics
20,000
10,000
C, CAPACITANCE (pF)
40
TJ = 125°C
30
20
1000
Coss
100
Crss
10
0
16
40
30
20
10
ID, DRAIN CURRENT (A)
Figure 5, Gain vs Drain Current
500
400
300
200
100
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 6, Capacitance vs Drain-to-Source Voltage
12
VDS = 100V
10
VDS = 250V
8
6
VDS = 400V
4
2
250
200
150
100
50
Qg, TOTAL GATE CHARGE (nC)
Figure 7, Gate Charge vs Gate-to-Source Voltage
0
0
140
ID = 21A
14
0
10
50
120
100
80
TJ = 25°C
60
TJ = 150°C
40
20
0
1.5
1.2
0.9
0.6
0.3
VSD, SOURCE-TO-DRAIN VOLTAGE (V)
Figure 8, Drain Current vs Source-to-Drain Voltage
0
9-2006
0
VGS, GATE-TO-SOURCE VOLTAGE (V)
Ciss
TJ = -55°C
TJ = 25°C
ISD, REVERSE DRAIN CURRENT(A)
gfs, TRANSCONDUCTANCE
50
Rev A
RDS(ON), DRAIN-TO-SOURCE ON RESISTANCE
140
1.5
30
25
20
15
10
5
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 2, Output Characteristics
Figure 1, Output Characteristics
2.5
= 7, 8 &10V
GS
050-8084
ID, DRAIN CURRENT (A)
100
20
V
70
120
80
T = 125°C
J
TJ = -55°C
140
0
APT42F50B_S
80
APT42F50B_S
200
200
100
100
I
I
DM
ID, DRAIN CURRENT (A)
10
13µs
Rds(on)
100µs
1ms
1
0.1
10ms
Rds(on)
100µs
1ms
10ms
100ms
Scaling for Different Case & Junction
Temperatures:
ID = ID(T = 25 C)*(TJ - TC)/125
DC line
0.1
13µs
TJ = 150°C
TC = 25°C
1
100ms
TJ = 125°C
TC = 75°C
1
10
C
DC line
°
800
100
10
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 10, Maximum Forward Safe Operating Area
800
100
10
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 9, Forward Safe Operating Area
TJ (°C)
1
TC (°C)
0.0846
0.116
Dissipated Power
(Watts)
0.0122
ZEXT are the external thermal
impedances: Case to sink,
sink to ambient, etc. Set to
zero when modeling only
the case to junction.
ZEXT
ID, DRAIN CURRENT (A)
DM
0.249
Figure 11, Transient Thermal Impedance Model
0.20
D = 0.9
0.15
0.7
Note:
0.5
0.10
PDM
ZθJC, THERMAL IMPEDANCE (°C/W)
0.25
t1
0.3
t2
0.05
SINGLE PULSE
0.1
0
t1 = Pulse Duration
t
Duty Factor D = 1/t2
Peak TJ = PDM x ZθJC + TC
0.05
1.0
10-1
10-2
10-3
RECTANGULAR PULSE DURATION (seconds)
Figure 12. Maximum Effective Transient Thermal Impedance Junction-to-Case vs Pulse Duration
10-4
10-5
D3PAK Package Outline
TO-247 (B) Package Outline
15.49 (.610)
16.26 (.640)
6.15 (.242) BSC
5.38 (.212)
6.20 (.244)
Drain
(Heat Sink)
e3 100% Sn Plated
4.69 (.185)
5.31 (.209)
1.49 (.059)
2.49 (.098)
4.98 (.196)
5.08 (.200)
1.47 (.058)
1.57 (.062)
15.95 (.628)
16.05(.632)
Drain
13.79 (.543)
13.99(.551)
Revised
4/18/95
20.80 (.819)
21.46 (.845)
1.04 (.041)
1.15(.045)
9-2006
4.50 (.177) Max.
Rev A
Revised
8/29/97
11.51 (.453)
11.61 (.457)
3.50 (.138)
3.81 (.150)
0.46 (.018)
0.56 (.022) {3 Plcs}
050-8084
13.41 (.528)
13.51(.532)
0.40 (.016)
0.79 (.031)
19.81 (.780)
20.32 (.800)
2.87 (.113)
3.12 (.123)
1.65 (.065)
2.13 (.084)
1.01 (.040)
1.40 (.055)
Gate
Drain
0.020 (.001)
0.178 (.007)
2.67 (.105)
2.84 (.112)
1.27 (.050)
1.40 (.055)
1.22 (.048)
1.32 (.052)
1.98 (.078)
2.08 (.082)
5.45 (.215) BSC
{2 Plcs.}
Source
2.21 (.087)
2.59 (.102)
5.45 (.215) BSC
2-Plcs.
Dimensions in Millimeters and (Inches)
Source
Drain
Gate
Dimensions in Millimeters (Inches)
Microsemi's products are covered by one or more of U.S.patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786
5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 and foreign patents. US and Foreign patents pending. All Rights Reserved.
3.81 (.150)
4.06 (.160)
(Base of Lead)
Heat Sink (Drain)
and Leads
are Plated