AD AD8351-EVAL Low distortion differential rf/if amplifier Datasheet

Low Distortion
Differential RF/IF Amplifier
AD8351
FEATURES
–3 dB Bandwidth of 2.2 GHz for AV = 12 dB
Single Resistor Programmable Gain
0 dB ≤ AV ≤ 26 dB
Differential Interface
Low Noise Input Stage 2.7 nV/√Hz @ AV = 10 dB
Low Harmonic Distortion
–79 dBc Second @ 70 MHz
–81 dBc Third @ 70 MHz
OIP3 of 31 dBm @ 70 MHz
Single-Supply Operation: 3 V to 5.5 V
Low Power Dissipation: 28 mA @ 5 V
Adjustable Output Common-Mode Voltage
Fast Settling and Overdrive Recovery
Slew Rate of 13,000 V/␮s
Power-Down Capability
10-Lead MSOP Package
APPLICATIONS
Differential ADC Drivers
Single-Ended-to-Differential Conversion
IF Sampling Receivers
RF/IF Gain Blocks
SAW Filter Interfacing
FUNCTIONAL BLOCK DIAGRAM
AD8351
VOCM
BIAS CELL
PWUP
VPOS
RGP1
OPHI
INHI
OPLO
INLO
COMM
RGP2
0
AD8351 WITH 10 dB OF
GAIN DRIVING THE
AD6645 (RL = 1k⍀)
ANALOG INPUT: 70MHz
ENCODE : 80MHz
SNR :
69.1dB
FUND : –1.1dBFS
HD2 : –78.5dBc
HD3 : –80.7dBc
THD : –75.9dBc
SFDR : 78.2dBc
–10
–20
–30
–40
–50
100nF 25⍀
INHI
RG
200⍀
AD6645
14-BIT ADC
AD8351
AD8351
INLO
100nF 25⍀
–60
–70
2
–80
3
+
–90
–100
–110
–120
–130
GENERAL DESCRIPTION
The AD8351 is a low cost differential amplifier useful in RF and
IF applications up to 2.2 GHz. The voltage gain can be set from
unity to 26 dB using a single external gain resistor. The AD8351
provides a nominal 150 Ω differential output impedance. The
excellent distortion performance and low noise characteristics of
this device allow for a wide range of applications.
The AD8351 is designed to satisfy the demanding performance
requirements of communications transceiver applications. The
device can be used as a general-purpose gain block, an ADC driver,
0
5
10
15
20
25
30
35
and a high speed data interface driver, among other functions. The
AD8351 can also be used as a single-ended-to-differential
amplifier with similar distortion products as in the differential
configuration. The exceptionally good distortion performance
makes the AD8351 an ideal solution for 12-bit and 14-bit IF
sampling receiver designs.
Fabricated in ADI’s high speed XFCB process, the AD8351
has high bandwidth that provides high frequency performance
and low distortion. The quiescent current of the AD8351 is 28 mA
typically. The AD8351 amplifier comes in a compact 10-lead
MSOP package and will operate over the temperature range
of –40°C to +85°C.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
(V = 5 V, R = 150 , R = 110 (A = 10 dB), f = 70 MHz, T = 25C, parameters
differentially, unless otherwise noted .)
AD8351–SPECIFICATIONS specified
S
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Bandwidth for 0.2 dB Flatness
Gain Accuracy
Gain Supply Sensitivity
Gain Temperature Sensitivity
Slew Rate
Settling Time
Overdrive Recovery Time
Reverse Isolation (S12)
L
G
Conditions
V
Min
GAIN = 6 dB, VOUT ≤ 1.0 V p-p
GAIN = 12 dB, VOUT ≤ 1.0 V p-p
GAIN = 18 dB, VOUT ≤ 1.0 V p-p
0 dB ≤ GAIN ≤ 20 dB, VOUT ≤ 1.0 V p-p
0 dB ≤ GAIN ≤ 20 dB, VOUT ≤ 1.0 V p-p
Using 1% Resistor for RG, 0 dB ≤ AV ≤ 20 dB
VS ± 5%
–40°C to +85°C
RL = 1 kΩ, VOUT = 2 V Step
RL = 150 Ω, VS = 2 V Step
1 V Step to 1%
VIN = 4 V to 0 V Step, VOUT ≤ ± 10 mV
INPUT/OUTPUT CHARACTERISTICS
Input Common-Mode
Voltage Adjustment Range
Max Output Voltage Swing
1 dB Compressed
Output Common-Mode Offset
Output Common-Mode Drift
–40°C to +85°C
Output Differential Offset Voltage
Output Differential Offset Drift –40°C to +85°C
Input Bias Current
Input Resistance1
Input Capacitance1
CMRR
Output Resistance1
Output Capacitance1
POWER INTERFACE
Supply Voltage
PWUP Threshold
PWUP Input Bias Current
Typ
MHz
MHz
MHz
MHz
MHz
dB
dB/V
mdB/°C
V/␮s
V/␮s
ns
ns
dB
1.2 to 3.8
4.75
40
0.24
20
0.13
± 15
5
0.8
43
150
0.8
V
V p-p
mV
mV/°C
mV
mV/°C
␮A
kΩ
pF
dB
Ω
pF
5.5
1.3
100
25
28
Quiescent Current
–2–
Unit
3,000
2,200
600
200
400
±1
0.08
3.9
13,000
7,500
<3
<2
–67
3
PWUP at 5 V
PWUP at 0 V
Max
32
V
V
␮A
␮A
mA
REV. B
AD8351
Parameter
NOISE/DISTORTION
10 MHz
Second/Third Harmonic
Distortion2
Third-Order IMD
Output Third-Order Intercept
Noise Spectral Density (RTI)
1 dB Compression Point
70 MHz
Second/Third Harmonic
Distortion2
Third-Order IMD
Output Third-Order Intercept
Noise Spectral Density (RTI)
1 dB Compression Point
140 MHz
Second/Third Harmonic
Distortion2
Third-Order IMD
Output Third-Order Intercept
Noise Spectral Density (RTI)
1 dB Compression Point
240 MHz
Second/Third Harmonic
Distortion2
Third-Order IMD
Output Third-Order Intercept
Noise Spectral Density (RTI)
1 dB Compression Point
Conditions
Min
RL = 1 kΩ, VOUT = 2 V p-p
RL = 150 Ω, VOUT = 2 V p-p
RL = 1 kΩ, f1 = 9.5 MHz, f2 = 10.5 MHz,
VOUT = 2 V p-p Composite
RL = 150 Ω, f1 = 9.5 MHz, f2 = 10.5 MHz,
VOUT = 2 V p-p Composite
f1 = 9.5 MHz, f2 = 10.5 MHz
RL = 1 kΩ, VOUT = 2 V p-p
RL = 150 Ω, VOUT = 2 V p-p
RL = 1 kΩ, f1 = 69.5 MHz, f2 = 70.5 MHz,
VOUT = 2 V p-p Composite
RL = 150 Ω, f1 = 69.5 MHz, f2 = 70.5 MHz,
VOUT = 2 V p-p Composite
f1 = 69.5 MHz, f2 = 70.5 MHz
RL = 1 kΩ, VOUT = 2 V p-p
RL = 150 Ω, VOUT = 2 V p-p
RL = 1 kΩ, f1 = 139.5 MHz, f2 = 140.5 MHz,
VOUT = 2 V p-p Composite
RL = 150 Ω, f1 = 139.5 MHz, f2 = 140.5 MHz,
VOUT = 2 V p-p Composite
f1 = 139.5 MHz, f2 = 140.5 MHz
RL = 1 kΩ, VOUT = 2 V p-p
RL = 150 Ω, VOUT = 2 V p-p
RL = 1 kΩ, f1 = 239.5 MHz, f2 = 240.5 MHz,
VOUT = 2 V p-p Composite
RL = 150 Ω, f1 = 239.5 MHz, f2 = 240.5 MHz,
VOUT = 2 V p-p Composite
f1 = 239.5 MHz, f2 = 240.5 MHz
NOTES
1
Values are specified differentially.
2
See Applications section for single-ended-to-differential performance.
Specifications subject to change without notice.
REV. B
–3–
Typ
Max
Unit
–95/–93
–86/–71
dBc
dBc
–90
dBc
–70
33
2.65
13.5
dBc
dBm
nV/√Hz
dBm
–79/–81
–65/–66
dBc
dBc
–85
dBc
–69
31
2.70
13.3
dBc
dBm
nV/√Hz
dBm
–69/–69
–54/–53
dBc
dBc
–79
dBc
–67
29
2.75
13
dBc
dBm
nV/√Hz
dBm
–60/–66
–46/–50
dBc
dBc
–76
dBc
–62
27
2.90
13
dBc
dBm
nV/√Hz
dBm
AD8351
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
PWUP Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPOS
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 320 mW
␪JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
10 VOCM
PWUP 1
RGP1 2
AD8351
9
VPOS
8 OPHI
TOP VIEW
INLO 4 (Not to Scale) 7 OPLO
INHI 3
RGP2 5
6
COMM
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temp. Range
Package Description
Package Option
Branding
AD8351ARM
AD8351ARM-R2
AD8351ARM-REEL7
AD8351-EVAL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
10-Lead MSOP, 7" Tape and Reel
10-Lead MSOP, 7" Tape and Reel
10-Lead MSOP, 7" Tape and Reel
Evaluation Board
RM-10
RM-10
RM-10
JDA
JDA
JDA
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Function
1
2
3
4
5
6
7
8
9
10
PWUP
RGP1
INHI
INLO
RGP2
COMM
OPLO
OPHI
VPOS
VOCM
Apply a positive voltage (1.3 V ≤ VPWUP ≤ VPOS ) to activate device.
Gain Resistor Input 1.
Balanced Differential Input. Biased to midsupply, typically ac-coupled
Balanced Differential Input. Biased to midsupply, typically ac-coupled.
Gain Resistor Input 2.
Device Common. Connect to low impedance ground.
Balanced Differential Output. Biased to VOCM, typically ac-coupled.
Balanced Differential Output. Biased to VOCM, typically ac-coupled.
Positive Supply Voltage. 3 V to 5.5 V.
Voltage applied to this pin sets the common-mode voltage at both the input and output.
Typically decoupled to ground with a 0.1 µF capacitor.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8351 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. B
Typical Performance Characteristics– AD8351
(VS = 5 V, T = 25ⴗC, unless otherwise noted.)
30
20
RG = 20⍀
RG = 10⍀
25
15
RG = 80⍀
GAIN (dB)
GAIN (dB)
20
10
RG = 200⍀
5
RG = 50⍀
15
RG = 200⍀
10
0
5
–5
10
1
100
FREQUENCY (MHz)
1000
0
10000
35
30
GAIN FLATNESS (dB)
25
GAIN (dB)
20
15
RL = OPEN
5
RL = 150⍀
0
–5
RL = 1k⍀
–10
10
100
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
1000
10000
RL = 1k⍀
RL = 150⍀
RL = 150⍀
RL = 1k⍀
10
100
FREQUENCY (MHz)
1
10k
1k
100
FREQUENCY (MHz)
TPC 4. Gain vs. Frequency for a 1 kΩ Differential Load
(AV = 10 dB, 18 dB, and 26 dB)
TPC 1. Gain vs. Frequency for a 150 Ω Differential Load
(AV = 6 dB, 12 dB, and 18 dB)
10
10
1
RG (⍀)
1000
TPC 5. Gain Flatness vs. Frequency
(RL = 150 Ω and 1 kΩ, AV =10 dB)
TPC 2. Gain vs. Gain Resistor, RG (f = 100 MHz,
RL = 150 Ω, 1 kΩ, and Open)
0
10.75
10.50
10.25
10.25
10.00
10.00
9.75
9.75
9.50
9.50
–20
ISOLATION (dB)
10.50
GAIN (RL = 150⍀) (dB)
GAIN (RL = 1k⍀) (dB)
–10
–30
–40
–50
–60
–70
9.25
–80
–90
9.25
–50
–30
–10
10
30
50
TEMPERATURE (ⴗC)
70
90
9.00
110
0
200
300
400 500 600 700
FREQUENCY (MHz)
800
900
TPC 6. Isolation vs. Frequency (AV = 10 dB)
TPC 3. Gain vs. Temperature at 100 MHz (AV = 10 dB)
REV. B
100
–5–
1000
AD8351
–45
–55
HD2
–50
–65
HD2
–60
–75
–85
–70
HD3
–95
–80
DIFFERENTIAL INPUT
–105
–90
–100
0
25
50
75
100 125 150 175
FREQUENCY (MHz)
200
225
–55
HARMONIC DISTORTION (dBc)
HD3
–40
–50
HARMONIC DISTORTION (VPOS = 3V) (dBc)
HARMONIC DISTORTION (VPOS = 5V) (dBc)
–30
–115
250
–40
–30
–50
HD2
–40
–60
–50
–70
HD3
–80
–70
–90
DIFFERENTIAL INPUT
–100
HD2
–90
50
75
100 125 150 175
FREQUENCY (MHz)
20
30
40
50
60
70
80
90
100
200
225
–55
SINGLE-ENDED INPUT
–60
–65
HD3
–70
–75
–80
–85
HD2
–90
–95
–100
–110
250
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (MHz)
TPC 11. Harmonic Distortion vs. Frequency for 2 V p-p
into RL = 150 Ω Using Single-Ended Input (AV = 10 dB)
3.00
3.00
2.95
2.95
NOISE SPECTRAL DENSITY (nV/ Hz)
NOISE SPECTRAL DENSITY (nV/ Hz)
10
–50
TPC 8. Harmonic Distortion vs. Frequency for 2 V p-p into
RL = 150 Ω (AV = 10 dB, at 3 V and 5 V Supplies)
2.90
2.85
2.80
2.75
2.70
2.65
2.60
2.90
2.85
2.80
2.75
2.70
2.65
2.60
2.55
2.55
2.50
HD3
–90
TPC 10. Harmonic Distortion vs. Frequency for 2 V p-p
into RL = 1 kΩ Using Single-Ended Input (AV = 10 dB)
HARMONIC DISTORTION (dBc)
–30
–20
25
–85
0
HARMONIC DISTORTION (VPOS = 3V) (dBc)
HARMONIC DISTORTION (VPOS = 5V) (dBc)
HD3
0
HD2
–80
–100
–20
–80
HD3
–75
FREQUENCY (MHz)
0
–60
–65
–70
–95
TPC 7. Harmonic Distortion vs. Frequency for 2 V p-p
into RL = 1 kΩ (AV = 10 dB, at 3 V and 5 V Supplies)
–10
SINGLE-ENDED INPUT
–60
2.50
0
50
100
150
FREQUENCY (MHz)
200
250
0
50
100
150
FREQUENCY (MHz)
200
250
TPC 12. Noise Spectral Density (RTI) vs. Frequency
(RL = 150 Ω, 3 V Supply, AV = 10 dB)
TPC 9. Noise Spectral Density (RTI) vs. Frequency
(RL = 150 Ω, 5 V Supply, AV = 10 dB)
–6–
REV. B
AD8351
16
–70
–75
RL = 150
VPOS = 5V
RL = 1k
12
THIRD-ORDER IMD (dBc)
OUTPUT 1dB COMPRESSION (dBm)
14
10
8
RL = 150
VPOS = 3V
RL = 1k
6
4
–80
–85
–90
2
0
0
25
50
75
100
125
150
175
200
225
–95
250
0
25
50
75
FREQUENCY (MHz)
100
125
150
175
200
225
250
FREQUENCY (MHz)
TPC 13. Output Compression Point, P1 dB, vs. Frequency
(RL = 150 Ω and 1 kΩ, AV = 10 dB, at 3 V and 5 V Supplies)
TPC 16. Third-Order Intermodulation Distortion vs.
Frequency for a 2 V p-p Composite Signal into RL = 1 kΩ
(AV = 10 dB, at 5 V Supplies)
16
–50
14
–55
12
THIRD-ORDER IMD (dBc)
OUTPUT 1dB COMPRESSION (dBm)
VPOS = 5V
VPOS = 3V
10
8
6
4
–60
–65
–70
2
0
0
100
GAIN RESISTOR ()
–75
1000
50
75
100
125
150
175
200
225
250
TPC 17. Third-Order Intermodulation Distortion
vs. Frequency for a 2 V p-p Composite Signal into
RL = 150 Ω (AV = 10 dB, at 5 V Supplies)
13.41
13.40
13.39
13.38
13.37
13.36
13.35
13.34
13.33
13.32
13.31
13.30
25
FREQUENCY (MHz)
TPC 14. Output Compression Point, P1 dB, vs. RG (f =
100 MHz, RL = 150 Ω, AV = 10 dB, at 3 V and 5 V Supplies)
13.29
0
–68.0 –68.2 –68.4 –68.6 –68.6 –68.8 –69.0 –69.2 –69.4 –69.6 –69.8
THIRD-ORDER INTERMODULATION DISTORTION (dBc)
OUTPUT 1dB COMPRESSION (dB)
TPC 15. Output Compression Point Distribution
(f = 70 MHz, RL = 150 Ω, AV = 10 dB)
REV. B
TPC 18. Third-Order Intermodulation Distortion
Distribution (f = 70 MHz, RL = 150 Ω, AV = 10 dB)
–7–
AD8351
0
4000
–25
3000
2500
–50
2000
1500
PHASE (deg)
IMPEDANCE MAGNITUDE ()
3500
3GHz
10MHz
10MHz
WITH
500MHz
500MHz
50
3GHz
TERMINATIONS
–75
1000
WITHOUT
TERMINATIONS
500
0
10
–100
1000
100
FREQUENCY (MHz)
TPC 22. Input Reflection Coefficient vs. Frequency
(RS = RL = 100 Ω with and without 50 Ω Terminations)
160
30
150
25
140
20
130
15
120
10
110
5
IMPEDANCE PHASE (deg)
IMPEDANCE MAGNITUDE ()
TPC 19. Input Impedance vs. Frequency
500MHz
10MHz
3GHz
0
1000
100
0
100
FREQUENCY (MHz)
TPC 23. Output Reflection Coefficient vs.
Frequency (RS = RL = 100 Ω)
TPC 20. Output Impedance vs. Frequency
–4
PHASE (deg)
–6
–8
–10
–12
–14
–16
–18
0
25
50
75
100
125
150
175
200
225
80
70
RL = 150
60
CMRR (dB)
–2
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
250
GROUP DELAY (ps)
0
RL = 1k
50
40
30
20
0
FREQUENCY (MHz)
10
100
FREQUENCY (MHz)
1000
TPC 24. Common-Mode Rejection Ratio,
CMRR (RS = 100 Ω)
TPC 21. Phase and Group Delay (AV = 10 dB, at 5 V Supplies)
–8–
REV. B
AD8351
1.00
0.6
0pF
0.75
0.4
5pF
2pF
0.50
10pF
VOLTAGE (V)
VOLTAGE (V)
0.2
0
0.25
0
–0.25
–0.2
–0.50
–0.4
–0.75
–1.00
–0.6
15
16
17
18
19
20
21
22
23
24
25
0
0.5
1.0
1.5
TIME (ns)
5
4.5
4
4.0
3
3.5
2
SETTLING (%)
OUTPUT (V)
5.0
3.0
2.5
2.0
3.5
4.0
0
–1
–2
1.0
–3
0.5
–4
–5
0
5
10
15
20
25
TIME (ns)
30
35
0
40
VOUT
2
1
VIN
0
–1
–2
–3
10
15
20
25
30
TIME (ns)
6
9
12
15
TPC 29. 1% Settling Time for a 2 V p-p Step
(AV = 10 dB, RL = 150 Ω)
3
5
3
TIME (ns)
TPC 26. 2⫻ Output Overdrive Recovery (RL = 150 Ω, AV = 10 dB)
VOLTAGE (V)
3.0
1
1.5
0
35
40
45
50
TPC 27. Overdrive Recovery Using Sinusoidal Input
Waveform RL = 150 Ω (AV = 10 dB, at 5 V Supplies)
REV. B
2.5
TPC 28. Large Signal Transient Response for a
1 V p-p Output Step (AV = 10 dB, RIP = 25 Ω)
TPC 25. Transient Response under Capacitive
Loading (RL = 150 Ω, CL = 0 pF, 2 pF, 5 pF, 10 pF)
0
2.0
TIME (ns)
–9–
AD8351
BASIC CONCEPTS
COMMON-MODE ADJUSTMENT
Differential signaling is used in high performance signal chains,
where distortion performance, signal-to-noise ratio, and low power
consumption is critical. Differential circuits inherently provide
improved common-mode rejection and harmonic distortion performance as well as better immunity to interference and ground noise.
The output common-mode voltage level is the dc offset voltage
present at each of the differential outputs. The ac signals are of
equal amplitude with a 180° phase difference but are centered
at the same common-mode voltage level. The common-mode
output voltage level can be adjusted from 1.2 V to 3.8 V by
driving the desired voltage level into the VOCM pin, as illustrated in Figure 2.
1
2
PWUP
RGP1
VOCM 10
VPOS 9
0.1F
3
BALANCED
SOURCE
RG
4
OPHI
INLO
OPLO
8
RL
1
2A
7
2
A
5
RGP2
COMM 6
3
BALANCED
SOURCE
Figure 1. Differential Circuit Representation
GAIN ADJUSTMENT
The differential gain of the AD8351 is set using a single external
resistor, RG, which is connected between Pins 2 and 5. The gain
can be set to any value between 0 dB and 26 dB using the resistor
values specified in TPC 2, with common gain values provided in
Table I. The board traces used to connect the external gain resistor should be balanced and as short as possible to help prevent
noise pickup and to ensure balanced gain and stability. The low
frequency voltage gain of the AD8351 can be modeled as
RL × RG (5.6) + 9.2 × RF × RL
RG × RL × 4.6 + 19.5 × RG + ( RL + RF ) × (39 + RG )
=
RG
4
Figure 1 illustrates the expected input and output waveforms for
a typical application. Usually the applied input waveform will be
a balanced differential drive, where the signal applied to the INHI
and INLO pins are equal in amplitude and differ in phase by 180°.
In some applications, baluns may be used to transform a singleended drive signal to a differential signal. The AD8351 may also be
used to transform a single-ended signal to a differential signal.
AV =
VS
A
INHI
VOUT
VIN
where: RF is 350 Ω (internal).
RG is the gain setting resistor.
Table I. Gain Resistor Selection for Common Gain Values
(Load Resistance Is Specified as Single-Ended)
RG (RL = 75 )
RG (RL = 500 )
0 dB
6 dB
10 dB
20 dB
680 Ω
200 Ω
100 Ω
22 Ω
2 kΩ
470 Ω
200 Ω
43 Ω
RGP1
INHI
INLO
RGP2
VOCM
CDECL 1.2V
0.1F TO
3.8V
VOCM 10
VPOS 9
OPHI 8
RL
OPLO
7
COMM 6
Figure 2. Common-Mode Adjustment
INPUT AND OUTPUT MATCHING
The AD8351 provides a moderately high differential input
impedance of 5 kΩ. In practical applications, the input of the
AD8351 will be terminated to a lower impedance to provide an
impedance match to the driving source, as depicted in Figure 3.
The terminating resistor, RT, should be as close as possible to
the input pins in order to minimize reflections due to impedance mismatch. The 150 Ω output impedance may need to be
transformed to provide the desired output match to a given
load. Matching components can be calculated using a Smith
Chart or by using a resonant approach to determine the matching network that results in a complex conjugate match. The
input and output impedances and reflection coefficients are
provided in TPCs 19, 20, 22, and 23. For additional information on reactive matching to differential sources and loads, refer
to the Applications section of the AD8350 data sheet.
Figure 3 illustrates a SAW (surface acoustic wave) filter interface. Many SAW filters are inherently differential, allowing for a
low loss output match. In this example, the SAW filter requires
a 50 Ω source impedance in order to provide the desired center
frequency and Q. The series L shunt C output network provides
a 150 Ω to 50 Ω impedance transformation at the desired frequency
of operation. The impedance transformation is illustrated on a Smith
Chart in Figure 4.
RL is the single-ended load resistance.
Gain, AV
5
PWUP
It is possible to drive a single-ended SAW filter simply by connecting the unused output to ground using the appropriate
terminating resistance. The overall gain of the system will be
reduced by 6 dB due to the fact that only half of the signal will
be available to the input of the SAW filter.
VPOS
RS
BALANCED
SOURCE
RT
0.1F
RS = RT 0.1F RG
RS
0.1F
AD8351
150
0.1F
RT
LS
27nF
CP
8pF
190MHz SAW
50
LS
27nF
Figure 3. Example of Differential SAW Filter Interface (fC = 190 MHz)
–10–
REV. B
AD8351
50
7
100
25
6
5
10
RF (k)
200
500
50
150
4
RL = 1000
3
RL = 500
0
500
SHUNT C
2
200
RL = 150
SERIES L
100
1
50
0
0
25
1000
100
RG ()
10
Figure 6b. Feedback Resistor Selection
Figure 4. Smith Chart Representation of SAW
Filter Output Matching Network
0.1F
50
50
RG
ADC DRIVING
0.1F
AD8351
0.1F
RL
0.1F
25
RF
Figure 5. Single-Ended Application
SINGLE-ENDED-TO-DIFFERENTIAL OPERATION
The AD8351 can easily be configured as a single-ended-todifferential gain block, as illustrated in Figure 5. The input signal
is ac-coupled and applied to the INHI input. The unused input is
ac-coupled to ground. The values of C1 through C4 should be
selected such that their reactances are negligible at the desired
frequency of operation. To balance the outputs, an external feedback resistor, RF, is required. To select the gain resistor and the
feedback resistor, refer to Figures 6a and 6b. From Figure 6a,
select an RG for the required dB gain at a given load. Next, select
from Figure 6b an RF resistor for the selected RG and load.
The circuit in Figure 7 represents a simplified front end of the
AD8351 driving the AD6645, which is a 14-bit, 105 MSPS A/D
converter. For optimum performance, the AD6645 and the
AD8351 are driven differentially. The resistors R1 and R2 present
a 50 Ω differential input impedance to the source with R3 and R4
providing isolation from the A/D input. The gain setting resistor
for the AD8351 is RG. The AD6645 presents a 1 kΩ differential
load to the AD8351 and requires a 2.2 V p-p differential signal
between AIN and AIN for a full-scale output. This AD8351
circuit then provides the gain, isolation, and source matching for
the AD6645. The AD8351 also provides a balanced input, not
provided by the balun, to the AD6645, which is essential for
second-order cancellation. The signal generator is bipolar,
centered around ground. Connecting the VOCM pin (10) of the
AD8351 to the VREF pin of the AD6645 sets the common-mode
output voltage of the AD8351 at 2.4 V. This voltage is bypassed
with a 0.1 µF capacitor. Increasing the gain of the AD8351 will
increase the system noise and thus decrease the SNR but will
not significantly affect the distortion. The circuit in Figure 7 can
provide SFDR performance of better than –90 dBc with a 10 MHz
input and –80 dBc with a 70 MHz input at a gain of 10 dB.
Even though the differential balance is not perfect under these
conditions, the distortion performance is still impressive. TPCs 10
and 11 show the second and third harmonic distortion performance when driving the input of the AD8351 using a single-ended
50 Ω source.
100nF
INHI
OPHI
25
25
BALANCE
50
SOURCE
RG
100nF
35
25
AIN
AD6645
AD8351
OPLO 25
INLO
AIN VREF
DIGITAL
OUT
VOCM
30
RL = 1000
25
GAIN (dB)
Figure 7. ADC Driving Application Using Differential Input
20
RL = 150
15
10
5
RL = 500
0
0
100
RG ()
1000
The circuit of Figure 8 represents a single-ended input to differential output configuration of the AD8351 driving the AD6645.
In this case, R1 provides the input impedance. RG is the gain
setting resistor. The resistor RF is required to balance the output
voltages required for second-order cancellation by the AD6645
and can be selected using a chart. (See the Single-Ended-toDifferential Operation section.) The circuit depicted in Figure 8
can provide SFDR performance of better than –90 dBc with a
10 MHz input and –77 dBc with a 70 MHz input.
Figure 6a. Gain Selection
REV. B
–11–
AD8351
RF
I/O CAPACITIVE LOADING
INHI
R1
50
SINGLEENDED
50
SOURCE
OPHI
25
AIN
100nF
RG
AD6645
AD8351
OPLO 25
AIN VREF
INLO
DIGITAL
OUT
VOCM
25 100nF
100nF
Figure 8. ADC Driving Application Using Single-Ended Input
ANALOG MULTIPLEXING
The AD8351 can be used as an analog multiplexer in applications
where it is desirable to select multiple high speed signals. The
isolation of each device when in a disabled state (PWUP pin pulled
low) is about 60 dBc for the maximum input level of 0.5 V p-p out
to 100 MHz. The low output noise spectral density allows for a
simple implementation as depicted in Figure 9. The PWUP interface can be easily driven using most standard logic interfaces. By
using an N-bit digital interface, up to N devices can be controlled.
Output loading effects and noise need to be considered when using
a large number of input signal paths. Each disabled AD8351 presents approximately a 700 Ω load in parallel with the 150 Ω output
source impedance of the enabled device. As the load increases due
to the addition of N devices, the distortion performance will degrade
due to the heavier loading. Distortion better than –70 dBc can be
achieved with four devices muxed into a 1 kΩ load for signal frequencies up to 70 MHz.
BIT 1
INHI
N-BIT
DIGITAL
INTERFACE
PWUP
OPHI
RGP1
SIGNAL
INPUT 1
AD8351
RG
Input or output direct capacitive loading greater than a few picofarads can result in excessive peaking and/or oscillation outside
the pass band. This results from the package and bond wire inductance resonating in parallel with the input/output capacitance of
the device and the associated coupling that results internally
through the ground inductance. For low resistive load or source
resistance, the effective Q is lower, and higher relative capacitance termination(s) can be allowed before oscillation or excessive
peaking occurs. These effects can be eliminated by adding series
input resistors (RIP) for high source capacitance, or series output
resistors (ROP) for high load capacitance. Generally less than
25 Ω is all that is required for I/O capacitive loading greater than
~2 pF. The higher the C, the smaller the R parasitic suppression
resistor required. In addition, RIP also helps to reduce low gain
in-band peaking, especially for light resistive loads.
CSTRAY
RIP
RG
CSTRAY
RIP
ROP
CL
RL
1k
AD8351
ROP
CL
Figure 10. Input and Output Parasitic Suppression
Resistors, RIP and ROP, Used to Suppress
Capacitive Loading Effects
Due to package parasitic capacitance on the RG ports, high RG
values (low gain) cause high ac-peaking inside the pass band,
resulting in poor settling in the time domain. As an example,
when driving a 1 kΩ load, using 25 Ω for RIP reduces the peaking
by ~7 dB for RG equal to 200 Ω (AV = 10 dB) (see Figure 11).
RGP2
INLO
OPLO
BIT 2
INHI
PWUP
OPHI
RGP1
SIGNAL
INPUT 2
AD8351
RG
RGP2
INLO
MUX
OUTPUT
LOAD
OPLO
BIT N
INHI
PWUP
OPHI
RGP1
SIGNAL
INPUT N
AD8351
RG
RGP2
INLO
Figure 11. Reducing Gain Peaking with Parasitic
Suppressing Resistors (RIP = 25 Ω, RL = 1 kΩ)
OPLO
Figure 9. Using Several AD8351s to Form an
N-Channel Analog MUX
–12–
REV. B
AD8351
(“de-Q”) the resonant effects of the device bond wires and
surrounding parasitic board capacitance. Typically, 25 Ω series
resistors (size 0402) adequately de-Q the input system without a
significant decrease in ac performance.
It is important to ensure that all I/O, ground, and RG port traces
be kept as short as possible. In addition, it is required that the
ground plane be removed from under the package. Due to the
inverse relationship between the gain of the device and the value
of the RG resistor, any parasitic capacitance on the RG ports can
result in gain-peaking at high frequencies. Following the precautions outlined in Figure 12 will help to reduce parasitic board
capacitance, thus extending the device’s bandwidth and reducing
potential peaking or oscillation.
Figure 13 illustrates the value of adding input and output series
resistors to help desensitize the resonant effects of board parasitics.
Overshoot and undershoot can be significantly reduced with the
simple addition of RIP and ROP.
1.5
NO RIP OR ROP
1.0
AGND
10
2
9
ROP = 25
0.5
RIP
COPLANAR
WAVEGUIDE
OR STRIP
ROP
3
8
4
7
5
6
VOLTAGE (V)
RT
1
Hi-Z
RT
RIP
ROP
RIP = ROP = 25
0
–0.5
RG
–1.0
AGND
–1.5
0
Figure 12. General Description of Recommended
Board Layout for High-Z Load Conditions
2
TIME (ns)
3
4
Figure 13. Step Response Characteristics with and
without Input and Output Parasitic Suppression Resistors
TRANSMISSION LINE EFFECTS
As noted, stray transmission line capacitance, in combination with
package parasitics, can potentially form a resonant circuit at high
frequencies, resulting in excessive gain peaking. RF transmission
lines connecting the input and output networks should be designed
such that stray capacitance is minimized. The output single-ended
source impedance of the AD8351 is dynamically set to a nominal
value of 75 Ω. Therefore, for a matched load termination, the
characteristic impedance of the output transmission lines should be
designed to be 75 Ω. In many situations, the final load impedance
may be relatively high, greater than 1 kΩ. It is suggested that the
board be designed as shown in Figure 12 for high impedance load
conditions. In most practical board designs, this requires that
the printed-circuit board traces be dimensioned to a small width
(~5 mils) and that the underlying and adjacent ground planes are
far enough away to minimize capacitance.
CHARACTERIZATION SETUP
The test circuit used for 150 Ω and 1 kΩ load testing is provided
in Figure 14. The evaluation board uses balun transformers to
simplify interfacing to single-ended test equipment. Balun effects
need to be removed from the measurements in order to accurately characterize the performance of the device at frequencies
exceeding 1 GHz.
The output L-pad matching networks provide a broadband
impedance match with minimum insertion loss. The input
lines are terminated with 50 Ω resistors for input impedance
matching. The power loss associated with these networks needs
to be accounted for when attempting to measure the gain of the
device. The required resistor values and the appropriate insertion loss and correction factors used to assess the voltage gain
are provided in Table II.
Typically the driving source impedance into the device will be
low and terminating resistors will be used to prevent input reflections. The transmission line should be designed to have the
appropriate characteristic impedance in the low-Z region. The
high impedance environment between the terminating resistors
and device input pins should not have ground planes underneath or near the signal traces. Small parasitic suppressing
resistors may be necessary at the device input pins to help desensitize
RS
50
RT
50
0.1nF
Table II. Load Conditions Specified Differentially
Load
Condition
R1
R2
Total
Insertion
Loss
150 Ω
1 kΩ
43.2 Ω
475 Ω
86.6 Ω
52.3 Ω
5.8 dB
15.9 dB
100nF
R1
50 CABLE
50 CABLE
AD8351
DUT
0.1nF
BALANCED
SOURCE
RS
50
RT
50
50
R2
RLOAD
50 TEST
EQUIPMENT
50 CABLE
50 CABLE
100nF
R1
Figure 14. Test Circuit
REV. B
1
–13–
R2
50
Conversion
Factor
20 log (S21)
to 20 log (AV)
7.6 dB
25.9 dB
AD8351
EVALUATION BOARD
An evaluation board is available for experimentation. Various
parameters such as gain, common-mode level, and input and
output network configurations can be modified through minor
resistor changes. The schematic and evaluation board artwork
are presented in Figures 15, 16, and 17.
ACOM
VPOS
ENBL
VCOM
P1
R17
0
W1
AGND
R6
OPEN
R18
0
C3
0.1F
R2
24.9
R3
OPEN
J1
RF_IN+
T1
C4
R5
100nF 0
1:1
ETC1-1-13
(MACOM)
R12
0
1 PWUP
VOCM 10
2 RGP1
VPOS 9
C2
100nF
R15
R1
100
J2
RF_IN–
VPOS
AD8351
R7
0
R8
C5
100nF 0
R4
24.9
3 INHI
OPHI 8
4 INLO
OPLO 7
5 RGP2
COMM 6
C6
R13
OPEN
R11
0
100nF 61.9
R16
0
R9
C7
100nF 61.9
R10
61.9
R14
0
C10
100nF
T3
1:1
ETC1-1-13
(MACOM)
J6
TEST OUT2
T4
C9
100nF
J4
RF_OUT–
1:1
ETC1-1-13
(MACOM)
10 PIN mSOIC
J5
TEST IN2
J3
RF_OUT+
T2
1:1
ETC1-1-13
(MACOM)
Figure 15. Evaluation Board Schematic
Figure 17. Component Side Silkscreen
Figure 16. Component Side Layout
–14–
REV. B
AD8351
Table III. Evaluation Board Configuration Options
Component
Function
Default Condition
P1-1, P1-2,
VPOS, AGND
Supply and Ground Pins.
Not Applicable
P1-3
Common-Mode Offset Pin. Allows for monitoring or adjustment of the
output common-mode voltage.
Not Applicable
W1, R7, P1-4, R17, R18
Device Enable. Configured such that switch W1 disables the device when
Pin 1 is set to ground. Device can be disabled remotely using Pin 4 of
header P1.
W1 = Installed
R7 = 0 Ω (Size 0603)
R17 = R18 = 0 Ω (Size 0603)
R2, R3, R4, R5, R8, R12,
T1, C4, C5
Input Interface. R3 and R12 are used to ground one side of the differential
drive interface for single-ended applications. T1 is a 1-to-1 impedance ratio
balun used to transform a single-ended input into a balanced differential
signal. R2 and R4 are used to provide a differential 50 Ω input termination.
R5 and R8 can be increased to reduce gain peaking when driving from a high
source impedance. The 50 Ω termination provides an insertion loss of 6 dB.
C4 and C5 are used to provide ac coupling.
R2 = R4 = 24.9 Ω (Size 0805)
R3 = Open (Size 0603)
R5 = R8 = R12 = 0 Ω
(Size 0603)
C4 = C5 = 10 0 nF (Size 0603)
T1 = MacomTM ETC1-1-13
R9, R10, R11, R13, R14,
R15, R16, T2, C4, C5,
C6, C7
Output Interface. R13 and R14 are used to ground one side of the differential
output interface for single-ended applications. T2 is a 1-to-1 impedance ratio
balun used to transform a balanced differential signal into a single-ended
signal. R9, R10, and R11 are provided for generic placement of matching
components. R15 and R16 allow additional output series resistance when
driving capacitive loads. The evaluation board is configured to provide a
150 Ω to 50 Ω impedance transformation with an insertion loss of 9.9 dB.
C4 through C7 are used to provide ac coupling.
R9 = R10 = 61.9 Ω (Size 0603)
R11 = 61.9 Ω (Size 0603)
R13 = Open (Size 0603)
R14 = 0 Ω (Size 0603)
R15 = R16 = 0 Ω (Size 0402)
C4 = C5 = 100 nF (Size 0603)
C6 = C7 = 100 nF (Size 0603)
T2 = Macom ETC1-1-13
R1
Gain Setting Resistor. Resistor R1 is used to set the gain of the device.
Refer to TPC 2 when selecting gain resistor. When R1 is 100 Ω, the
overall system gain of the evaluation board will be approximately –6 dB.
R1 = 100 Ω (Size 0603)
C2
Power Supply Decoupling. The supply decoupling consists of a 100 nF
capacitor to ground.
C2 = 100 nF (Size 0805)
R6, C3, P1-3
Common-Mode Offset Adjustment. Used to trim common-mode output
level. By applying a voltage to Pin 3 of header P1, the output commonmode voltage can be directly adjusted. Typically decoupled to ground
using a 0.1 µF capacitor.
R6 = 0 Ω (Size 0603)
C3 = 0.1 µF (Size 0805)
T3, T4, C9, C10
Calibration Networks. Calibration path provided to allow for compensation
of the insertion loss of the baluns and the reactance of the coupling capacitors.
T3 = T4 = Macom
ETC1-1-13
C9 = C10 = 100 nF
(Size 0603)
REV. B
–15–
AD8351
OUTLINE DIMENSIONS
10-Lead Mini Small Outline Package [MSOP]
(RM-10)
C03145–0–2/04(B)
Dimensions shown in millimeters
3.00 BSC
10
6
4.90 BSC
3.00 BSC
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.27
0.17
SEATING
PLANE
0.23
0.08
8
0
0.80
0.60
0.40
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Revision History
Location
Page
2/04—Data Sheet changed from REV. A to REV. B.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3/03—Data Sheet changed from REV. 0 to REV. A.
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Change to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–16–
REV. B