EP9302 Data Sheet
FEATURES
•
•
•
•
•
Linux®, Microsoft® Windows® CE-enabled MMU
100-MHz System Bus
MaverickCrunch™ Math Engine
• Floating point, Integer and Signal Processing
Instructions
• Optimized for digital music compression and
decompression algorithms.
• Hardware interlocks allow in-line coding.
MaverickKey™ IDs
• 32-bit unique ID can be used for DRM-compliant,
128-bit random ID.
Integrated Peripheral Interfaces
• 16-bit SDRAM Interface (up to 4 banks)
• 16-bit SRAM / FLASH / ROM
• Serial EEPROM Interface
• 1/10/100 Mbps Ethernet MAC
• Two UARTs
• Two-port USB 2.0 Full-speed Host (OHCI)
(12 Mbits per second)
• IrDA Interface
• ADC
• Serial Peripheral Interface (SPI) Port
Serial
Audio
Interface
•
•
• 6-channel Serial Audio Interface (I2S)
• 2-channel, Low-cost Serial Audio Interface (AC'97)
Internal Peripherals
• 12 Direct Memory Access (DMA) Channels
• Real-time Clock with Software Trim
• Dual PLL controls all clock domains.
• Watchdog Timer
• Two General-purpose 16-bit Timers
• One General-purpose 32-bit Timer
• One 40-bit Debug Timer
• Interrupt Controller
• Boot ROM
Package
• 208-pin LQFP
Peripheral Bus
MaverickCrunch
(2) UARTs
w/
IrDA
12 Channel DMA
MaverickKeyTM
(2) USB
Hosts
Clocks &
Timers
TM
ARM920T
D-Cache
16KB
Interrupts
& GPIO
I-Cache
16KB
MMU
Bus Bridge
USER INTERFACE
COMMUNICATIONS PORTS
•
High-speed ARM9
System-on-chip Processor
with MaverickCrunch
200-MHz ARM920T Processor
• 16-kbyte Instruction Cache
• 16-kbyte Data Cache
Processor Bus
Ethernet
MAC
Boot
ROM
SRAM &
Flash I/F
Unified
SDRAM I/F
MEMORY AND STORAGE
©Copyright 2005 Cirrus Logic (All Rights Reserved)
http://www.cirrus.com
MAR ‘05
DS653PP3
1
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
OVERVIEW
The EP9302 is an ARM920T-based system-on-a-chip
design with a large peripheral set targeted to a variety of
applications:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The ARM920T microprocessor core with separate
16 kbyte, 64-way set-associative instruction and data
caches is augmented by the MaverickCrunch™ coprocessor enabling faster than real-time compression of
audio CDs.
The MaverickKey™ unique hardware programmed IDs
are a solution to the growing concern over secure web
content and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Industrial controls
Digital media servers
Integrated home media gateways
Digital audio jukeboxes
Streaming audio players
Set-top boxes
Point-of-sale terminals
Thin clients
Biometric security systems
GPS & fleet management systems
Educational toys
Industrial computers
Industrial hand-held devices
Voting machines
Medical equipment
A high-performance 1/10/100 Mbps Ethernet media
access controller (EMAC) is included along with external
interfaces to SPI, AC’97, and I2S audio. A two-port USB
2.0 Full-speed Host (OHCI) (12 Mbits per second), two
UARTs, and a analog voltage measurement analog-todigital converter (ADC) are included as well.
The EP9302 is one of a series of ARM920T-based
devices. Other members of the family have different
peripheral
sets,
coprocessors
and
package
configurations.
The EP9302 is a high-performance, low-power RISCbased, single-chip computer built around an ARM920T
microprocessor core with a maximum operating clock
rate of 200 MHz (184 MHz for industrial conditions). The
ARM core operates from a 1.8 V supply, while the I/O
operates at 3.3 V with power usage between 100 mW
and 750 mW (dependent on speed).
Table A. Change History
2
Revision
Date
Changes
PP1
June 2004
Initial Release.
PP2
July 2004
Update AC data.
Add ADC data.
PP3
March 2005
Update electrical specs with most-current characterization data.
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Table of Contents
Processor Core - ARM920T ......................................................................................... 6
MaverickCrunch™ Math Engine .................................................................................. 6
MaverickKey™ Unique ID ............................................................................................ 6
General Purpose Memory Interface (SDRAM, SRAM, ROM, Flash) ........................... 6
Ethernet Media Access Controller (MAC) .................................................................... 7
Serial Interfaces (SPI, I2S, and AC ’97) ....................................................................... 7
12-bit Analog-to-digital Converter (ADC) ..................................................................... 7
Universal Asynchronous Receiver/Transmitters (UARTs) ............................................ 8
Dual-port USB Host ..................................................................................................... 8
Two-wire Interface ........................................................................................................ 8
Real-Time Clock with Software Trim ............................................................................ 8
PLL and Clocking ......................................................................................................... 9
Timers .......................................................................................................................... 9
Interrupt Controller ....................................................................................................... 9
Dual LED Drivers ......................................................................................................... 9
General Purpose Input/Output (GPIO) ......................................................................... 9
Reset and Power Management ................................................................................. 10
Hardware Debug Interface ......................................................................................... 10
12-Channel DMA Controller ....................................................................................... 10
Internal Boot ROM ..................................................................................................... 10
Electrical Specifications ................................................................................. 11
Absolute Maximum Ratings ........................................................................................11
Recommended Operating Conditions .......................................................................11
DC Characteristics ..................................................................................................... 12
Timings .............................................................................................................13
Memory Interface ....................................................................................................... 14
Ethernet MAC Interface ............................................................................................ 27
Audio Interface ........................................................................................................... 29
AC’97 ........................................................................................................................ 33
ADC ........................................................................................................................... 34
JTAG .......................................................................................................................... 35
208 Pin LQFP Package Outline .....................................................................36
208 Pin LQFP Pinout ................................................................................................. 37
Acronyms and Abbreviations ........................................................................41
Units of Measurement .....................................................................................41
Ordering Information ......................................................................................42
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
List of Figures
Figure 1. Timing Diagram Drawing Key ................................................................................. 13
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 14
Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 15
Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 16
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 17
Figure 6. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement .................... 18
Figure 7. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement .................... 19
Figure 8. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement .................. 20
Figure 9. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement .................. 21
Figure 10. Static Memory Burst Read Cycle Timing Measurement ....................................... 22
Figure 11. Static Memory Burst Write Cycle Timing Measurement ....................................... 23
Figure 12. Static Memory Single Read Wait Cycle Timing Measurement ............................. 24
Figure 13. Static Memory Single Write Wait Cycle Timing Measurement .............................. 25
Figure 14. Static Memory Turnaround Cycle Timing Measurement ....................................... 26
Figure 15. Ethernet MAC Timing Measurement ..................................................................... 28
Figure 16. TI Single Transfer Timing Measurement ............................................................... 30
Figure 17. Microwire Frame Format, Single Transfer ............................................................ 30
Figure 18. SPI Format with SPH=1 Timing Measurement ..................................................... 31
Figure 19. Inter-IC Sound (I2S) Timing Measurement ........................................................... 32
Figure 20. AC ‘97 Configuration Timing Measurement .......................................................... 33
Figure 21. ADC Transfer Function ......................................................................................... 34
Figure 22. JTAG Timing Measurement .................................................................................. 35
4
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
List of Tables
Table A. Change History .......................................................................................................... 2
Table B. General Purpose Memory Interface Pin Assignments .............................................. 6
Table C. Ethernet Media Access Controller Pin Assignments ................................................. 7
Table D. Audio Interfaces Pin Assignment .............................................................................. 7
Table E. 12-bit Analog-to-Digital Converter Pin Assignments ................................................. 7
Table F. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 8
Table G. Dual Port USB Host Pin Assignments ....................................................................... 8
Table H. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 8
Table I. Real-Time Clock with Pin Assignments ..................................................................... 8
Table J. PLL and Clocking Pin Assignments .......................................................................... 9
Table K. Interrupt Controller Pin Assignment .......................................................................... 9
Table L. Dual LED Pin Assignments ....................................................................................... 9
Table M.General Purpose Input/Output Pin Assignment ........................................................ 9
Table N. Reset and Power Management Pin Assignments ................................................... 10
Table O. Hardware Debug Interface ...................................................................................... 10
Table P. Pin List in Numerical Order by Pin Number ............................................................. 37
Table Q. Pin Descriptions ..................................................................................................... 39
Table R. Pin Multiplex Usage Information .............................................................................. 40
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
5
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Processor Core - ARM920T
The ARM920T is a Harvard architecture processor with
separate 16-kbyte instruction and data caches with an 8word line length but a unified memory. The processor
utilizes a five-stage pipeline consisting of fetch, decode,
execute, memory, and write stages. Key features include:
•
•
•
•
•
•
•
•
ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
32-bit Advanced Micro-Controller Bus Architecture
(AMBA)
16 kbyte Instruction Cache with lockdown
16 kbyte Data Cache (programmable write-through or
write-back) with lockdown
MMU for Linux®, Microsoft® Windows® CE and other
operating systems
Translation Look Aside Buffers with 64 Data and 64
Instruction Entries
Programmable Page Sizes of 1 Mbyte, 64 kbyte,
4 kbyte, and 1 kbyte
Independent lockdown of TLB Entries
MaverickCrunch™ Math Engine
The MaverickCrunch Engine is a mixed-mode
coprocessor designed primarily to accelerate the math
processing required to rapidly encode digital audio
formats. It accelerates single and double precision
integer and floating point operations plus an integer
multiply-accumulate
(MAC)
instruction
that
is
considerably faster than the ARM920T's native MAC
instruction. The ARM920T coprocessor interface is
utilized thereby sharing its memory interface and
instruction stream. Hardware forwarding and interlock
allows the ARM to handle looping and addressing while
MaverickCrunch handles computation. Features include:
•
•
•
•
•
•
•
•
IEEE-754 single and double precision floating point
32 / 64-bit integer
Add / multiply / compare
Integer MAC 32-bit input with 72-bit accumulate
Integer Shifts
Floating point to/from integer conversion
Sixteen 64-bit register files
Four 72-bit accumulators
MaverickKey™ Unique ID
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID
are programmed into the EP9302 through the use of
laser probing technology. These IDs can then be used to
match secure copyrighted content with the ID of the
target device the EP9302 is powering, and then deliver
the copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
General Purpose Memory Interface (SDRAM,
SRAM, ROM, Flash)
The EP9302 features a unified memory address model
where all memory devices are accessed over a common
address/data bus. Memory accesses are performed via
the Processor bus. The SRAM memory controller
supports 8 and 16-bit devices and accommodates an
internal boot ROM concurrently with 16-bit SDRAM
memory.
•
•
•
1 to 4 banks of 16-bit ,100-MHz SDRAM
Address and data bus shared between SDRAM,
SRAM, ROM, and FLASH memory
NOR FLASH memory supported
Table B. General Purpose Memory Interface Pin Assignments
Pin Mnemonic
Pin Description
SDCLK
SDRAM Clock
SDCLKEN
SDRAM Clock Enable
SDCSn[3:0]
SDRAM Chip Selects 3-0
RASn
SDRAM RAS
CASn
SDRAM CAS
SDWEn
SDRAM Write Enable
CSn[7:6] and CSn[3:0]
Chip Selects 7, 6, 3, 2, 1, 0
AD[25:0]
Address Bus 25-0
DA[15:0]
Data Bus 15-0
DQMn[1:0]
SDRAM Output Enables / Data Masks
WRn
SRAM Write Strobe
RDn
SRAM Read / OE Strobe
WAITn
SRAM Wait Input
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
6
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Ethernet Media Access Controller (MAC)
Table D. Audio Interfaces Pin Assignment
The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:
•
•
Supports 1/10/100 Mbps transfer rates for home /
small-business / large-business applications
Interfaces to an off-chip PHY through industrystandard Media-independent Interface (MII)
Pin
Name
Normal Mode
I2S on SSP
Mode
I2S on AC'97
Mode
Pin
Description
Pin Description
Pin Description
SCLK1
SPI Bit Clock
SFRM1
SPI Frame Clock I2S Frame Clock
I2S Serial Clock
SSPRX1 SPI Serial Input
SSPTX1
SPI Serial
Output
MDC
Pin Description
Management Data Clock
MDIO
Management Data I / O
RXCLK
Receive Clock
MIIRXD[3:0]
Receive Data
RXDVAL
Receive Data Valid
RXERR
Receive Data Error
TXCLK
Transmit Clock
MIITXD[3:0]
Transmit Data
TXEN
Transmit Enable
TXERR
Transmit Error
CRS
Carrier Sense
CLD
Collision Detect
SPI Serial Input
I2S Serial Output
SPI Serial Output
ARSTn
AC'97 Reset
ABITCLK AC'97 Bit Clock
AC'97 Reset
I2S Master Clock
AC'97 Bit Clock
I2S Serial Clock
ASYNC
AC'97 Frame
Clock
AC'97 Frame
Clock
I2S Frame Clock
ASDI
AC'97 Serial
Input
AC'97 Serial Input
I2S Serial Input
ASDO
AC'97 Serial
Output
AC'97 Serial Output I2S Serial Output
12-bit Analog-to-digital Converter (ADC)
Serial Interfaces (SPI, I2S, and AC ’97)
The Serial Peripheral Interface (SPI) port can be
configured as a master or a slave, supporting the
National Semiconductor®, Motorola®, and Texas
Instruments® signaling protocols.
The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. The I2S port
supports stereo 24-bit audio.
These ports are multiplexed so that the I2S port will take
over either the AC'97 pins or the SPI pins.
•
Normal Mode: One SPI Port and one AC’97 Port
•
I2S on SSP Mode: One AC’97 Port and one I2S Port
•
I2S on AC’97 Mode: One SPI Port and one I2S Port
Note:
I2S Serial Input
(No I2S Master
Clock)
Table C. Ethernet Media Access Controller Pin Assignments
Pin Mnemonic
SPI Bit Clock
SPI Frame Clock
The ADC block consists of a 12-bit analog-to-digital
converter with a analog input multiplexer. The multiplexer
can select to measure battery voltage and other
miscellaneous voltages on the external measurement
pins. Features include:
•
•
•
5 external pins for ADC measurement
Measurement pin input range: 0 to 3.3 V.
ADC-conversion-complete interrupt signal
Table E. 12-bit Analog-to-Digital Converter Pin Assignments
Pin Mnemonic
Pin Description
ADC[0] (Ym, pin 135)
External Analog Measurement Input
ADC[1] (sXp, pin 134)
External Analog Measurement Input
ADC[2] (sXm, pin 133)
External Analog Measurement Input
ADC[3] (sYp, pin 132)
External Analog Measurement Input
ADC[4] (sYm, pin 131)
External Analog Measurement Input
I2S may not be output on AC’97 and SSP ports at the
same time.
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
7
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Universal Asynchronous
Receiver/Transmitters (UARTs)
Two 16550-compatible UARTs are supplied. One
provides asynchronous HDLC (High-level Data Link
Control) protocol support for full duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must assemble the frame in memory before
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. The second
UART provides IrDA® compatibility.
•
•
UART1 supports modem bit rates up to 115.2 kbps,
supports HDLC and includes a 16 byte FIFO for
receive and a 16 byte FIFO for transmit. Interrupts are
generated on Rx, Tx and modem status change.
UART2 contains an IrDA encoder operating at either
the slow (up to 115 kbps), medium (0.576 or 1.152
Mbps), or fast (4 Mbps) IR data rates. It also has a 16
byte FIFO for receive and a 16 byte FIFO for transmit.
Table F. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Pin Mnemonic
•
Supports both low-speed (1.5 Mbps) and full-speed
(12 Mbps) USB device connections
• Root HUB integrated with 2 downstream USB ports
• Transceiver buffers integrated, over-current protection
on ports
• Supports power management
• Operates as a master on the bus
The Open HCI host controller initializes the master DMA
transfer with the AHB bus:
•
•
•
•
Fetches endpoint descriptors and transfer descriptors
Accesses endpoint data from system memory
Accesses the HC communication area
Writes status and retire transfer descriptor
Table G. Dual Port USB Host Pin Assignments
Pin Mnemonic
Pin Name - Description
USBp[2,0]
USB Positive signals
USBm[2,0]
USB Negative Signals
Note:
USBm[1] and USBp[1] are not bonded out.
Two-wire Interface
The two-wire interface provides communication and
control for synchronous-serial-driven devices.
Pin Name - Description
Table H. Two-Wire Port with EEPROM Support Pin Assignments
TXD0
UART1 Transmit
RXD0
UART1 Receive
CTSn
UART1 Clear To
Send / Transmit Enable
DSRn / DCDn
UART1 Data Set
Ready / Data Carrier Detect
DTRn
UART1 Data Terminal Ready
RTSn
UART1 Ready To Send
EGPIO[0] / RI
UART1 Ring Indicator
Real-Time Clock with Software Trim
TXD1 / SIROUT
UART2 Transmit / IrDA
Output
RXD1 / SIRIN
UART2 Receive / IrDA Input
The software trim feature on the real time clock (RTC)
provides software controlled digital compensation of the
32.768 KHz input clock. This compensation is accurate to
± 1.24 sec/month.
Dual-port USB Host
This includes the following feature:
8
Pin Name - Description
Alternative
Usage
EECLK
Two-wire Interface Clock
General
Purpose I/O
EEDATA
Two-Wire Interface Data
General
Purpose I/O
Note:
The USB Open Host Controller Interface (Open HCI)
provides full-speed serial communications ports at a
baud rate of 12 Mbits/sec. Up to 127 USB devices
(printer, mouse, camera, keyboard, etc.) and USB hubs
can be connected to the USB host in the USB “tieredstar” topology.
•
•
Pin Mnemonic
A real time clock must be connected to RTCXTALI or
the EP9302 device will not boot.
Table I. Real-Time Clock with Pin Assignments
Pin Mnemonic
Pin Name - Description
RTCXTALI
Real-Time Clock Oscillator Input
RTCXTALO
Real-Time Clock Oscillator Output
Compliance with the USB 2.0 specification
Compliance with the Open HCI Rev 1.0 specification
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
PLL and Clocking
•
The Processor and the Peripheral Clocks operate from a
single 14.7456 MHz crystal.
Software supported priority mask for all FIQs and
IRQs
Table K. External Interrupt Controller Pin Assignment
The Real Time Clock operates from a 32.768 KHz
external oscillator.
Pin Mnemonic
Pin Name - Description
INT[3] and INT[1:0]
Table J. PLL and Clocking Pin Assignments
Pin Mnemonic
Pin Name - Description
XTALI
Main Oscillator Input
XTALO
Main Oscillator Output
VDD_PLL
Main Oscillator Power
GND_PLL
Main Oscillator Ground
Note:
External Interrupts 2, 1, 0
INT[2] is not bonded out.
Dual LED Drivers
Two pins are assigned specifically to drive external
LEDs.
Table L. Dual LED Pin Assignments
Timers
Pin Mnemonic
Pin Name Description
The Watchdog Timer ensures proper operation by
requiring periodic attention to prevent a reset-on-timeout.
GRLED
Green LED
General Purpose I/O
REDLED
Red LED
General Purpose I/O
Two 16-bit timers operate as free running down-counters
or as periodic timers for fixed interval interrupts and have
a range of 0.03 ms to 4.27 seconds.
One 32-bit timer, plus a 6-bit prescale counter, has a
range of 0.03 µs to 73.3 hours.
One 40-bit debug timer, plus 6-bit prescale counter, has a
range of 1.0 µs to 12.7 days.
Interrupt Controller
The interrupt controller allows up to 54 interrupts to
generate an Interrupt Request (IRQ) or Fast Interrupt
Request (FIQ) signal to the processor core. Thirty-two
hardware priority assignments are provided for assisting
IRQ vectoring, and two levels are provided for FIQ
vectoring. This allows time critical interrupts to be
processed in the shortest time possible. Internal
interrupts may be programmed as active high or active
low level sensitive inputs. GPIO pins programmed as
interrupts may be programmed as active high level
sensitive, active low level sensitive, rising edge triggered,
falling edge triggered, or combined rising/falling edge
triggered.
General Purpose Input/Output (GPIO)
The 16 EGPIO and the 3 FGPIO pins may each be
configured individually as an output, an input, or an
interrupt input.
There are 10 pins that may alternatively be used as input,
output, or open-drain pins, but do not support interrupts.
These pins are:
• Ethernet MDIO
• Both LED Outputs
• EEPROM Clock and Data
• HGPIO[5:2]
• CGPIO[0]
6 pins may alternatively be used as inputs only:
• CTSn, DSRn / DCDn
• 3 Interrupt Lines
2 pins may alternatively be used as outputs only:
• RTSn
• ARSTn
Table M. General Purpose Input/Output Pin Assignment
Pin Mnemonic
•
•
•
•
Supports 54 interrupts from a variety of sources (such
as UARTs, GPIO and ADC)
Routes interrupt sources to either the ARM920T’s
IRQ or FIQ (Fast IRQ) inputs
Three dedicated off-chip interrupt lines operate as
active high level sensitive interrupts
Any of the 19 GPIO lines maybe configured to
generate interrupts
DS653PP3
Alternative Usage
Pin Name - Description
EGPIO[15:0]
Expanded General Purpose Input / Output
Pins with Interrupts
FGPIO[3:1]
Expanded General Purpose Input / Output
Pins with Interrupts
©Copyright 2005 Cirrus Logic (All Rights Reserved)
9
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Reset and Power Management
12-Channel DMA Controller
The chip may be reset through the PRSTn pin or through
the open drain common reset pin, RSTOn.
The DMA module contains 12 separate DMA channels.
Ten of these may be used for peripheral-to-memory or
memory-to-peripheral access. Two of these are
dedicated to memory-to-memory transfers. Each DMA
channel is connected to the 16-bit DMA request bus.
Clocks are managed on a peripheral-by-peripheral basis
and may be turned off to conserve power.
The processor clock is dynamically adjustable from 0 to
200 MHz (184 MHz for industrial conditions).
PRSTn
Power On Reset
The request bus is a collection of requests, Serial Audio
and UARTs. Each DMA channel can be used
independently or dedicated to any request signal. For
each DMA channel, source and destination addressing
can be independently programmed to increment,
decrement, or stay at the same value. All DMA
addresses are physical, not virtual addresses.
RSTOn
User Reset In/Out – Open Drain –
Preserves Real Time Clock value
Internal Boot ROM
Table N. Reset and Power Management Pin Assignments
Pin Mnemonic
Pin Name - Description
Hardware Debug Interface
The JTAG interface allows use of ARM’s Multi-ICE or
other in-circuit emulators.
The Internal 16-kbyte ROM allows booting from FLASH
memory, SPI or UART. Consult the EP9301 User’s Guide
for operational details.
Table O. Hardware Debug Interface
Pin Mnemonic
Pin Name - Description
TCK
JTAG Clock
TDI
JTAG Data In
TDO
JTAG Data Out
TMS
JTAG Test Mode Select
TRSTn
JTAG Port Reset
10
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Electrical Specifications
Absolute Maximum Ratings
(All grounds = 0 V, all voltages with respect to 0 V)
Parameter
Symbol
Min
Max
Unit
RVDD
CVDD
VDD_PLL
VDD_ADC
-
3.96
2.16
2.16
3.96
V
V
V
V
-
2
W
Input Current per Pin, DC (Except supply pins)
-
±10
mA
Output current per pin, DC
-
±50
mA
-0.3
RVDD+0.3
V
-40
+125
°C
Power Supplies
Total Power Dissipation
(Note 1)
Digital Input voltage
(Note 2)
Storage temperature
Note:
1. Includes all power generated by AC and/or DC output loading.
2. The power supply pins are at maximum values listed in “Recommended Operating Conditions”, below.
3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 2.5 Watts.
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Recommended Operating Conditions
(All grounds = 0 V, all voltages with respect to 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
RVDD
CVDD
VDD_PLL
VDD_ADC
3.0
1.65
1.65
3.0
3.3
1.80
1.80
3.3
3.6
1.94
1.94
3.6
V
V
V
V
Operating Ambient Temperature - Commercial
TA
0
+25
+70
°C
Operating Ambient Temperature - Industrial
TA
-40
+25
+85
°C
Power Supplies
Processor Clock Speed - Commercial
FCLK
-
-
200
MHz
Processor Clock Speed - Industrial
FCLK
-
-
184
MHz
System Clock Speed - Commercial
HCLK
-
-
100
MHz
System Clock Speed - Industrial
HCLK
-
-
92
MHz
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
11
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
DC Characteristics
(TA = 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V;
All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)
Parameter
High level output voltage
Iout = -4 mA
Low level output voltage
Iout = 4 mA
(Note 4)
Symbol
Min
Max
Unit
Voh
0.85 × RVDD
-
V
Vol
-
0.15 × RVDD
V
High level input voltage
(Note 5)
Vih
0.65 × RVDD
VDD + 0.3
V
Low level input voltage
(Note 5)
Vil
−0.3
0.35 × RVDD
V
High level leakage current
Vin = 3.3 V
(Note 5)
Iih
-
10
µA
Low level leakage current
Vin = 0
(Note 5)
Iil
-
-10
µA
Min
Typ
Max
Unit
Parameter
Power Supply Pins (Outputs Unloaded)
Power Supply Current:
CVDD / VDD_PLL Total
RVDD
-
180
45
230
80
mA
mA
Low-Power Mode Supply Current
CVDD / VDD_PLL Total
RVDD
-
2
1.0
3.5
2
mA
mA
Note:
12
4. For open drain pins, high level output voltage is dependent on the external load.
5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table Q on
page 39). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not
driven and programmed as an input, it should be tied to power or ground through its own resistor.
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these
diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached
unless specifically stated.
Clock
High to Low
High/Low to High
Bus Change
Bus Valid
Undefined/Invalid
Valid Bus to Tristate
Bus/Signal Omission
Figure 1. Timing Diagram Drawing Key
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements.
• TA = 0 to 70° C
• CVDD = VDD_PLL = 1.8V
• RVDD = 3.3 V
• All grounds = 0 V
• Logic 0 = 0 V, Logic 1 = 3.3 V
• Output loading = 50 pF
• Timing reference levels = 1.5 V
• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between
33 MHz and 100 MHz (92 MHz for industrial conditions).
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
13
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Memory Interface
Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter
Symbol
Min
Typ
Max
Unit
SDCLK high time
tclk_high
-
(tHCLK) / 2
-
ns
SDCLK low time
tclk_low
-
(tHCLK) / 2
-
ns
tclkrf
-
2
4
ns
SDCLK rise/fall time
Signal delay from SDCLK rising edge time
td
-
-
8
ns
Signal hold from SDCLK rising edge time
th
1
-
-
ns
DQMn delay from SDCLK rising edge time
tDQd
-
-
8
ns
DQMn hold from SDCLK rising edge time
tDQh
1
-
-
ns
DA valid setup to SDCLK rising edge time
tDAs
2
-
-
ns
DA valid hold from SDCLK rising edge time
tDAh
3
-
-
ns
SDRAM Load Mode Register Cycle
tclk_low
tclkrf
tclk_high
SDCLK
td
th
SDCSn
RASn
CASn
SDWEn
DQMn
AD
OP-Code
DA
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
14
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
SDRAM Burst Read Cycle
tclk_low
tclk_high
SDCLK
tclkrf
td
th
SDCSn
RASn
CASn
SDWEn
tDQh
tDQd
DQMn
CL = 2
tDQh
DQMn
CL = 3
AD
td
tDAs
DA
tDAh
n
n+1
n+2
n+3
CL = 2
tDAs
DA
CL = 3
tDAh
n
n+1
n+2
n+3
Figure 3. SDRAM Burst Read Cycle Timing Measurement
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
15
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
SDRAM Burst Write Cycle
tclk_high
tclk_low
SDCLK
tclkrf
td
th
th
SDCSn
RASn
CASn
SDWEn
DQMn
AD
DA
n
n +1
n+2
n+3
Figure 4. SDRAM Burst Write Cycle Timing Measurement
16
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
SDRAM Auto Refresh Cycle
tclk_high
tclk_low
SDCLK
tclkrf
td
SDCSn
th
7
b
d
e
RASn
CASn
SDWEn
Note:
Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
17
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory 32-bit Read on 8-bit External Bus
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to CSn assert time
tADs
tHCLK
-
-
ns
CSn assert to Address transition time
tAD1
-
tHCLK × (WST1 + 1)
-
ns
Address assert time
tAD2
-
tHCLK × (WST1 + 1)
-
ns
AD transition to CSn deassert time
tAD3
-
tHCLK × (WST1 + 2)
-
ns
tADh
-
ns
tHCLK
-
tRDpwL
-
tHCLK × (4 × WST1 + 5)
-
ns
tRDd
-
-
3
ns
CSn assert to DQMn assert delay time
tDQMd
-
-
1
ns
DA setup to AD transition time
tDAs1
15
-
-
ns
DA setup to RDn deassert time
tDAs2
tHCLK + 12
-
-
ns
DA hold from AD transition time
tDAh1
0
-
-
ns
DA hold from RDn deassert time
tDAh2
0
-
-
ns
AD hold from CSn deassert time
RDn assert time
CSn to RDn delay time
tADs
tAD1
tAD2
tAD2
tADh
tAD3
AD
CSn
WRn
tRDd
tRDd
RDn
tDQMd
DQMn
tDAh1
tDAh1
tDAh11
tDAh2
DA
tDAs1
tDAs1
tDAs1
tDAs2
WAIT
Figure 6. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement
18
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory 32-bit Write on 8-bit External Bus
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to WRn assert time
tADs
tHCLK − 3
-
-
ns
WRn/DQMn deassert to AD transition time
tADd
-
-
tHCLK + 6
ns
AD hold from WRn deassert time
tADh
tHCLK × 2
-
-
ns
CSn hold from WRn deassert time
tCSh
7
-
-
ns
tWRd
2
ns
CSn to WRn assert delay time
-
-
WRn assert time
tWRpwL
-
tHCLK × (WST1 + 1)
-
ns
WRn deassert time
tWRpwH
-
tHCLK × 2
(tHCLK × 2) + 14
ns
CSn to DQMn assert delay time
tDQMd
-
-
1
ns
DQMn assert time
tDQMpwL
-
tHCLK × (WST1 + 1)
-
ns
DQMn deassert time
tDQMpwH
-
-
(tHCLK × 2) + 7
ns
WRn / DQMn deassert to DA transition time
tDAh
tHCLK
-
-
ns
WRn / DQMn assert to DA valid time
tDAV
-
-
8
ns
tADs
tADd
tADd
tADd
tADh
AD
CSn
tWRd
tWRpwL
tWRpwL
tCSh
tWRpwL
WRn
tWRpwH
tWRpwH
tWRpwH
RDn
tDQMd
tDQMpwL
tDQMpwL
tDQMpwL
DQMn
tDQMpwH
tDAV
tDQMpwH
tDAV
tDQMpwH
tDAV
tDAV
DA
tDAh
tDAh
tDAh
tDAh
WAIT
Figure 7. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
19
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory 32-bit Read on 16-bit External Bus
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to CSn assert time
tADs
tHCLK
-
-
ns
CSn assert to AD transition time
tADd1
-
tHCLK × (WST1 + 1)
-
ns
AD transition to CSn deassert time
tADd2
-
tHCLK × (WST1 + 2)
-
ns
AD hold from CSn deassert time
tADh
tHCLK
-
-
ns
tRDpwL
-
tHCLK × ((2 × WST1) + 3)
-
ns
tRDd
-
-
3
ns
CSn assert to DQMn assert delay time
tDQMd
-
-
1
ns
DA setup to AD transition time
tDAs1
15
-
-
ns
DA to RDn deassert time
tDAs2
tHCLK + 12
-
-
ns
DA hold from AD transition time
tDAh1
0
-
-
ns
DA hold from RDn deassert time
tDAh2
0
-
-
ns
RDn assert time
CSn to RDn delay time
tADs
tADd1
tADd2
tADh
AD
CSn
WRn
tRDd
tRDh
tRDpwl
RDn
DQMn
tDQMh
tDQMd
tDAs1
tDAh1
tDAs2
tDAh2
DA
WAIT
Figure 8. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement
20
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory 32-bit Write on 16-bit External Bus
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to WRn assert time
tADs
tHCLK – 3
-
-
ns
WRn/DQMn deassert to AD transition time
tADd
-
-
tHCLK + 6
ns
AD hold from WRn deassert time
tADh
tHCLK × 2
-
-
ns
CSn hold from WRn deassert time
tCSh
7
-
-
ns
tWRd
CSn to WRn assert delay time
-
-
2
ns
WRn assert time
tWRpwL
-
tHCLK × (WST1 + 1)
-
ns
WRn deassert time
tWRpwH
-
-
(tHCLK × 2) + 14
ns
CSn to DQMn assert delay time
tDQMd
-
-
1
ns
DQMn assert time
tDQMpwL
-
tHCLK × (WST1 + 1)
-
ns
DQMn deassert time
tDQMpwH
-
-
(tHCLK × 2) + 7
ns
WRn / DQMn deassert to DA transition time
tDAh1
tHCLK
-
-
ns
WRn / DQMn assert to DA valid time
tDAV
-
-
8
ns
tADs
tADd
tADh
AD
CSn
tWRd
tWRpwL
WRn
tWRpwL
tCSh
tWRpwH
RDn
tDQMd
tDQpwL
DQMn
tDQpwL
tDQpwH
tDAV
tDAh
tDAV
tDAh
DA
WAIT
Figure 9. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
21
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory Burst Read Cycle
Parameter
Symbol
Min
Typ
Max
Unit
CSn assert to Address 1 transition time
tADd1
-
tHCLK × (WST1 + 1)
-
ns
Address assert time
tADd2
-
tHCLK × (WST2 + 1)
-
ns
AD transition to CSn deassert time
tADd3
-
tHCLK × (WST1 + 2)
-
ns
AD hold from CSn deassert time
tADh
tHCLK
-
-
ns
tRDd
-
-
3
ns
CSn to RDn delay time
CSn to DQMn assert delay time
tDQMd
-
-
1
ns
DA setup to AD transition time
tDAs1
15
-
-
ns
DA setup to CSn deassert time
tDAs2
tHCLK + 12
-
-
ns
DA hold from AD transition time
tDAh1
0
-
-
ns
DA hold from RDn deassert time
tDAh2
0
-
-
ns
Note:
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
tADs
tADd1
tADd2
tADd2
tADh
tADd3
AD
CSn
WRn
tRDd
RDn
DQMn
tDQMd
tDAh1
tDAh1
tDAh1
tDAh2
DA
tDAs1
tDAs1
tDAs1
tDAs2
WAIT
Figure 10. Static Memory Burst Read Cycle Timing Measurement
22
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory Burst Write Cycle
Parameter
Symbol
Min
AD setup to WRn assert time
tADs
tHCLK − 3
ns
AD hold from WRn deassert time
tADh
tHCLK × 2
ns
WRN/DQMn deassert to AD transition time
tADd
CSn hold from WRn deassert time
tCSh
CSn to WRn assert delay time
tWRd
CSn to DQMn assert delay time
tDQMd
DQMn assert time
tDQpwL
DQMn deassert time
tDQpwH
WRn assert time
tWRpwL
WRn deassert time
tWRpwH
WRn/DQMn deassert to DA transition time
tDAh
WRn/DQMn assert to DA valid time
tDAv
Note:
Typ
Max
Unit
tHCLK + 6
ns
7
ns
2
ns
1
ns
tHCLK × (WST1 + 1)
ns
(tHCLK × 2) + 14
ns
tHCLK × (WST1 + 11)
ns
(tHCLK × 2) + 7
ns
tHCLK
ns
8
ns
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
tADs
tADd
tADh
AD
CSn
tWRpwL
WRn
tCSh
tWRpwH
tWRd
RD
tDQMd
tDQpwL
DQMn
tDQpwH
tDAv
tDAh
DA
WAIT
Figure 11. Static Memory Burst Write Cycle Timing Measurement
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
23
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory Single Read Wait Cycle
Parameter
Symbol
Min
Typ
Max
Unit
CSn assert to WAIT time
tWAITd
-
-
tHCLK × (WST1-2)
ns
WAIT assert time
tWAITpw
tHCLK × 2
-
tHCLK × 510
ns
tCSnd
tHCLK × 3
-
tHCLK × 5
ns
WAIT to CSn deassert delay time
AD
CSn
WRn
RDn
DQMn
DA
WAIT
tWAITd
tWAITpw
tCSnd
Figure 12. Static Memory Single Read Wait Cycle Timing Measurement
24
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory Single Write Wait Cycle
Parameter
Symbol
Min
Typ
Max
Unit
tWRd
tHCLK × 2
-
tHCLK × 4
ns
CSn assert to WAIT time
tWAITd
-
-
tHCLK × (WST1-2)
ns
WAIT assert time
tWAITpw
tHCLK × 2
-
tHCLK × 510
ns
tCSnd
tHCLK × 3
-
tHCLK × 5
ns
WAIT to WRn deassert delay time
WAIT to CSn deassert delay time
AD
CSn
tWRd
WRn
RDn
DQMn
DA
tWAITd
WAIT
tWAITpw
tCSnd
Figure 13. Static Memory Single Write Wait Cycle Timing Measurement
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
25
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Static Memory Turnaround Cycle
Parameter
CSnX deassert to CSnY assert time
Symbol
Min
Typ
Max
Unit
tBTcyc
-
tHCLK × (IDCY+1)
-
ns
Notes: 1. X and Y represent any two chip select numbers.
2. IDCY occurs on read-to-write and write-to-read.
3. IDCY is honored when going from a asynchronous device (CSx) to a synchronous device (/SDCSy).
tBTcyc
AD
CSnX
CSnY
WRn
RDn
DQMn
DA
WAIT
Figure 14. Static Memory Turnaround Cycle Timing Measurement
26
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Ethernet MAC Interface
Min
Parameter
Typ
Max
Symbol
10 Mbit
mode
100 Mbit
mode
10 Mbit
mode
100 Mbit
mode
10 Mbit
mode
100 Mbit
mode
Unit
TXCLK cycle time
tTX_per
-
-
400
40
-
-
ns
TXCLK high time
tTX_high
140
14
200
20
260
26
ns
TXCLK low time
tTX_low
140
14
200
20
260
26
ns
TXCLK to signal transition delay time
tTXd
0
0
10
10
25
25
ns
TXCLK rise/fall time
tTXrf
-
-
-
-
5
5
ns
RXCLK cycle time
tRX_per
-
-
400
40
-
-
ns
RXCLK high time
tRX_high
140
14
200
20
260
26
ns
RXCLK low time
tRX_low
140
14
200
20
260
26
ns
tRXs
10
10
-
-
-
-
ns
RXDVAL / RXERR hold time
tRXh
10
10
-
-
-
-
ns
RXCLK rise/fall time
tRXrf
-
-
-
-
5
5
ns
RXDVAL / RXERR setup time
MDC cycle time
tMDC_per
-
-
400
400
-
-
ns
MDC high time
tMDC_high
160
160
-
-
-
-
ns
MDC low time
tMDC_low
160
160
-
-
-
-
ns
MDC rise/fall time
tMDCrf
-
-
-
-
5
5
ns
MDIO setup time (STA sourced)
tMDIOs
10
10
-
-
-
-
ns
MDIO hold time (STA sourced)
tMDIOh
10
10
-
-
-
-
ns
MDC to MDIO signal transition delay time
(PHY sourced)
tMDIOd
-
-
-
-
300
300
ns
STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer
(PHY) interface to the wireless medium.
PHY - Ethernet physical layer interface.
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
27
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
tTX_high
tTX_low
TXCLK
TXD[3:0]/
TXEN/
TXERR
tTXd
tTX_per
tRX_low
tRX_high
RXCLK
tRXh
RXD[3:0]/
RXDVAL/
RXERR
tRX_per
tRXs
MDC
MDIO
(Sourced
by STA)
tMDC_high
tMDC_low
tMDIOs
tMDIOh
tMDC_per
MDC
MDIO
(Sourced
by PHY)
tMDIOd
Figure 15. Ethernet MAC Timing Measurement
28
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Audio Interface
The following table contains the values for the timings of each of the SPI modes.
Parameter
Symbol
Min
Typ
Max
Unit
SCLK cycle time
tclk_per
-
tspix_clk
-
ns
SCLK high time
tclk_high
-
(tspix_clk) / 2
-
ns
SCLK low time
tclk_low
-
(tspix_clk) / 2
-
ns
SCLK rise/fall time
tclkrf
1
-
8
ns
Data from master valid delay time
tDMd
-
-
3
ns
Data from master setup time
tDMs
20
-
-
ns
Data from master hold time
tDMh
40
-
-
ns
Data from slave setup time
tDSs
20
-
-
ns
Data from slave hold time
tDSh
40
-
-
ns
Note:
DS653PP3
The tspix_clk is programmable by the user.
©Copyright 2005 Cirrus Logic (All Rights Reserved)
29
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Texas Instruments’ Synchronous Serial Format
tclk_per
tclk_high
tclkrf
SCLK
tclk_low
SFRM
SSPTXD/
SSPRXD
MSB
LSB
4 to 16 bits
Figure 16. TI Single Transfer Timing Measurement
Microwire
tclk_high
tclk_per
tclkrf
SCLK
tclk_low
SFRM
SSPTXD
LSB
MSB
8-bit control
SSPRXD
0
MSB
LSB
4 to 16 bits output data
Figure 17. Microwire Frame Format, Single Transfer
30
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Motorola SPI
tclk_per
tclk_high
tclkrf
SCLK
(SPO=0)
tclk_low
SCLK
(SPO=1)
tDMs
SSPTXD
(master)
tDMh
MSB
LSB
tDMd
tDSs
SSPRXD
(slave)
tDSh
MSB
LSB
SFRM
Figure 18. SPI Format with SPH=1 Timing Measurement
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
31
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Inter-IC Sound - I2S
Parameter
Symbol
Min
Typ
Max
Unit
SCLK cycle time
tclk_per
-
ti2s_clk
-
ns
SCLK high time
tclk_high
-
(ti2s_clk) / 2
-
ns
SCLK low time
tclk_low
-
(ti2s_clk) / 2
-
ns
SCLK rise/fall time
tclkrf
1
4
8
ns
SCLK to LRCLK assert delay time
tLRd
-
-
3
ns
Hold between SCLK assert then LRCLK deassert
or
Hold between LRCLK deassert then SCLK assert
tLRh
0
-
-
ns
SDI to SCLK deassert setup time
tSDIs
12
-
-
ns
SDI from SCLK deassert hold time
tSDIh
0
-
-
ns
SCLK assert to SDO delay time
tSDOd
-
-
9
ns
SDO from SCLK assert hold time
tSDOh
1
-
-
ns
Note:
ti2s_clk is programmable by the user.
tclk_per
tclk_low
tclk_high
tclkrf
SCLK
tLRd
tLRh
LRCLK
tSDIs
tSDIh
SDI
tSDOd
tSDOh
SDO
Figure 19. Inter-IC Sound (I2S) Timing Measurement
32
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
AC’97
Parameter
Symbol
Min
Typ
Max
Unit
ABITCLK input cycle time
tclk_per
-
81.4
-
ns
ABITCLK input high time
tclk_high
36
-
45
ns
ABITCLK input low time
tclk_low
36
-
45
ns
tclkrf
2
-
6
ns
ts
10
-
-
ns
ABITCLK input rise/fall time
ASDI setup to ABITCLK falling
th
10
-
-
ns
ASDI input rise/fall time
trfin
2
-
6
ns
ABITCLK rising to ASDO / ASYNC valid, CL = 55 pF
tco
2
-
15
ns
trfout
2
-
6
ns
ASDI hold after ABITCLK falling
ASYNC / ASDO rise/fall time, CL = 55 pF
tclk_high
tclk_low
tclk_per
ABITCLK
tclkrf
tclkrf
th
ts
trfin
ASDI
ASDO
trfout
tco
tco
tco
ASYNC
trfout
trfout
Figure 20. AC ‘97 Configuration Timing Measurement
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
33
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
ADC
Parameter
Resolution
Comment
Value
No missing codes
Range of 0 to 3.3 V
50K counts (approximate)
Integral non-linearity
Units
0.01%
Offset error
±15
Full scale error
mV
0.2%
Maximum sample rate
ADIV = 0
ADIV = 1
3750
925
Samples per second
Samples per second
Channel switch settling time
ADIV = 0
ADIV = 1
500
2
µs
ms
120
µV
Noise (RMS) - typical
Note:
ADIV refers to bit 16 in the KeyTchClkDiv register.
ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4.
ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16.
61A8
0000
FFFF
9E58
0
Vref/2
Vref
A/D Converter Transfer Function
(approximately ±25,000 counts)
Figure 21. ADC Transfer Function
Using the ADC:
This ADC has a state-machine based conversion engine that automates the conversion process. The initiator for a
conversion is the read access of the TSXYResult register by the CPU. The data returned from reading this register
contains the result as well as the status bit indicating the state of the ADC. However, this peripheral requires a delay
between each successful conversion and the issue of the next conversion command, or else the returned value of
successive samples may not reflect the analog input. Since the state of the ADC state machine is returned through the
same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion.
Note that reading TSXYResult during a conversion will not affect the result of the ongoing process.
The following is a recommended procedure for safely polling the ADC from software:
1. Read the TSXYResult register into a local variable to initiate a conversion.
2. If the value of bit 31 of the local variable is '0' then repeat step 1.
3. Delay long enough to meet the maximum sample rate as shown above.
4. Mask the local variable with 0xFFFF to remove extraneous data.
5. If signed mode is used, do a sign extend of the lower halfword.
6. Return the sampled value.
34
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
JTAG
Parameter
Symbol
Min
Max
Units
TCK clock period
tclk_per
100
-
ns
TCK clock high time
tclk_high
50
-
ns
TCK clock low time
tclk_low
50
-
ns
TMS / TDI to clock rising setup time
tJPs
20
-
ns
Clock rising to TMS / TDI hold time
tJPh
45
-
ns
JTAG port clock to output
tJPco
-
30
ns
JTAG port high impedance to valid output
tJPzx
-
30
ns
JTAG port valid output to high impedance
tJPxz
-
30
ns
TMS
TDI
tclk_per
tclk_high
tJPs
tJPh
tclk_low
TCK
tJPzx
tJPco
tJPxz
TDO
Figure 22. JTAG Timing Measurement
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
35
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
208 Pin LQFP Package Outline
2.19
208-Pin LQFP (28 × 28 × 1.40-mm Body)
29.60 (1.165)
30.40 (1.197)
27.80 (1.094)
28.20 (1.110)
0.17 (0.007)
0.27 (0.011)
27.80 (1.094)
28.20 (1.110)
29.60 (1.165)
30.40 (1.197)
0.50
(0.0197)
BSC
Pin 1 Indicator
Pin 208
Pin 1
0.45 (0.018)
0.75 (0.030)
1.35 (0.053)
1.45 (0.057)
1.00 (0.039) BSC
0.09 (0.004)
0.20 (0.008)
0° MIN
7° MAX
1.40 (0.055)
1.60 (0.063)
0.05 (0.002)
0.15 (0.006)
NOTES:
1) Dimensions are in millimeters, and controlling dimension is millimeter.
2) Package body dimensions do not include mold protrusion, which is 0.25 mm (0.010 in).
3) Pin 1 identification may be either ink dot or dimple.
4) Package top dimensions can be smaller than bottom dimensions by 0.20 mm (0.008 in).
5) The ‘lead width with plating’ dimension does not include a total allowable dambar protrusion of 0.08 mm
(at maximum material condition).
6) Ejector pin marks in molding are present on every package.
7) Drawing above does not reflect exact package pin count.
36
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
208 Pin LQFP Pinout
The following table shows the 208 pin LQFP pinout.
• VDD_core is CVDD.
• VDD_ring is RVDD.
• NC means that the pin is not connected.
Pin List
The following Low-Profile Quad Flat Pack (LQFP) pin assignment table is sorted in order of pin.
Table P. Pin List in Numerical Order by Pin Number
Pin
Number
Pin
Name
Pin
Number
Pin
Name
Pin
Number
Pin
Name
Pin
Number
Pin
Name
Pin
Number
Pin
Name
Pin
Number
Pin
Name
1
CSn[7]
36
AD[5]
71
AD[9]
106
2
CSn[6]
37
DA[12]
72
DA[1]
107
USBp[0]
141
EGPIO[10]
176
TXEN
ABITCLK
142
EGPIO[9]
177
MIITXD[0]
3
CSn[3]
38
AD[4]
73
AD[8]
108
CTSn
143
EGPIO[8]
178
MIITXD[1]
4
CSn[2]
39
DA[11]
74
DA[0]
109
RXD[0]
144
EGPIO[7]
179
MIITXD[2]
5
CSn[1]
40
AD[3]
75
DSRn
110
RXD[1]
145
EGPIO[6]
180
MIITXD[3]
6
AD[25]
41
vdd_ring
76
DTRn
111
vdd_ring
146
EGPIO[5]
181
TXCLK
7
vdd_ring
42
gnd_ring
77
TCK
112
gnd_ring
147
EGPIO[4]
182
RXERR
8
gnd_ring
43
DA[10]
78
TDI
113
TXD[0]
148
EGPIO[3]
183
RXDVAL
9
AD[24]
44
AD[2]
79
TDO
114
TXD[1]
149
gnd_ring
184
MIIRXD[0]
10
SDCLK
45
DA[9]
80
TMS
115
CGPIO[0]
150
vdd_ring
185
MIIRXD[1]
11
AD[23]
46
AD[1]
81
vdd_ring
116
gnd_core
151
EGPIO[2]
186
MIIRXD[2]
12
vdd_core
47
DA[8]
82
gnd_ring
117
PLL_GND
152
EGPIO[1]
187
gnd_ring
13
gnd_core
48
AD[0]
83
BOOT[1]
118
XTALI
153
EGPIO[0]
188
vdd_ring
14
SDWEn
49
vdd_ring
84
BOOT[0]
119
XTALO
154
ARSTn
189
MIIRXD[3]
15
SDCSn[3]
50
gnd_ring
85
gnd_ring
120
PLL_VDD
155
TRSTn
190
RXCLK
16
SDCSn[2]
51
NC
86
NC
121
vdd_core
156
ASDI
191
MDIO
17
SDCSn[1]
52
NC
87
EECLK
122
gnd_ring
157
USBm[2]
192
MDC
18
SDCSn[0]
53
vdd_ring
88
EEDAT
123
vdd_ring
158
USBp[2]
193
RDn
19
vdd_ring
54
gnd_ring
89
ASYNC
124
RSTOn
159
WAITn
194
WRn
20
gnd_ring
55
AD[15]
90
vdd_core
125
PRSTn
160
EGPIO[15]
195
AD[16]
21
RASn
56
DA[7]
91
gnd_core
126
CSn[0]
161
gnd_ring
196
AD[17]
22
CASn
57
vdd_core
92
ASDO
127
gnd_core
162
vdd_ring
197
gnd_core
23
DQMn[1]
58
gnd_core
93
SCLK1
128
vdd_core
163
EGPIO[14]
198
vdd_core
24
DQMn[0]
59
AD[14]
94
SFRM1
129
gnd_ring
164
EGPIO[13]
199
HGPIO[2]
25
AD[22]
60
DA[6]
95
SSPRX1
130
vdd_ring
165
EGPIO[12]
200
HGPIO[3]
26
AD[21]
61
AD[13]
96
SSPTX1
131
ADC[4]
166
gnd_core
201
HGPIO[4]
27
vdd_ring
62
DA[5]
97
GRLED
132
ADC[3]
167
vdd_core
202
HGPIO[5]
28
gnd_ring
63
AD[12]
98
RDLED
133
ADC[2]
168
FGPIO[3]
203
gnd_ring
29
DA[15]
64
DA[4]
99
vdd_ring
134
ADC[1]
169
FGPIO[2]
204
vdd_ring
30
AD[7]
65
AD[11]
100
gnd_ring
135
ADC[0]
170
FGPIO[1]
205
AD[18]
31
DA[14]
66
vdd_ring
101
INT[3]
136
ADC_VDD
171
gnd_ring
206
AD[19]
32
AD[6]
67
gnd_ring
102
INT[1]
137
RTCXTALI
172
vdd_ring
207
AD[20]
208
SDCLKEN
33
DA[13]
68
DA[3]
103
INT[0]
138
RTCXTALO
173
CLD
34
vdd_core
69
AD[10]
104
RTSn
139
ADC_GND
174
CRS
35
gnd_core
70
DA[2]
105
USBm[0]
140
EGPIO[11]
175
TXERR
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
37
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
The following section focuses on the EP9302 pin signals
from two viewpoints - the pin usage and pad
characteristics, and the pin multiplexing usage. The first
table (Table Q) is a summary of all the EP9302 pin
signals. The second table (Table R) illustrates the pin
signal multiplexing and configuration options.
Table Q is a summary of the EP9302 pin signals, which
illustrates the pad type and pad pull type (if any). The
symbols used in the table are defined as follows. (Note: A
blank box means Not Applicable (NA) or, for Pull Type,
No Pull (NP).)
Under the Pad Type column:
• A - Analog pad
• P - Power pad
• G - Ground pad
• I - Pin is an input only
• I/O - Pin is input/output
• 4mA - Pin is a 4mA output driver
• 8mA - Pin is an 8mA output driver
• 12mA - Pin is an 12mA output driver
See the text description for additional information about
bi-directional pins.
Under the Pull Type Column:
•
•
38
PU - Resistor is a pull up to the RVDD supply
PD - Resistor is a pull down to the RGND supply
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
.
Table Q. Pin Descriptions (Continued)
Table Q. Pin Descriptions
Block
Pad
Type
MDC
EMAC
4ma
JTAG data in
MDIO
EMAC
4ma
PU
Management data input/output
JTAG data out
RXCLK
EMAC
I
PD
Receive clock in
PD
JTAG test mode select
MIIRXD[3:0]
EMAC
I
PD
Receive data in
I
PD
JTAG reset
RXDVAL
EMAC
I
PD
Receive data valid
System
I
PD
Boot mode select in
RXERR
EMAC
I
PD
Receive data error
XTALI
PLL
A
Main oscillator input
TXCLK
EMAC
I
PU
Transmit clock in
XTALO
PLL
A
Main oscillator output
MIITXD[3:0]
EMAC
I
PD
Transmit data out
VDD_PLL
PLL
P
Main oscillator power, 1.8V
TXEN
EMAC
4ma
PD
Transmit enable
GND_PLL
PLL
G
Main oscillator ground
TXERR
EMAC
4ma
PD
Transmit error
RTCXTALI
RTC
A
RTC oscillator input
CRS
EMAC
I
PD
Carrier sense
RTCXTALO
RTC
A
RTC oscillator output
CLD
EMAC
I
PU
Collision detect
WRn
EBUS
4ma
SRAM Write strobe out
GRLED
LED
12ma
Green LED
RDn
EBUS
4ma
SRAM Read / OE strobe out
RDLED
LED
12ma
Red LED
WAITn
EBUS
I
SRAM Wait in
EECLK
EEPROM
4ma
PU
EEPROM / Two-wire Interface clock
AD[25:0]
EBUS
8ma
Shared Address bus out
EEDAT
EEPROM
4ma
PU
EEPROM / Two-wire Interface data
DA[15:0]
EBUS
8ma
PU
Shared Data bus in/out
ABITCLK
AC97
8ma
PD
AC97 bit clock
CSn[3:0]
EBUS
4ma
PU
Chip select out
ASYNC
AC97
8ma
PD
AC97 frame sync
CSn[7:6]
EBUS
4ma
PU
Chip select out
ASDI
AC97
I
PD
AC97 Primary input
DQMn[1:0]
EBUS
8ma
Shared data mask out
ASDO
AC97
8ma
PU
AC97 output
SDCLK
SDRAM
8ma
SDRAM clock out
ARSTn
AC97
8ma
SDCLKEN
SDRAM
8ma
SDRAM clock enable out
SCLK1
SPI1
8ma
PD
SPI bit clock
SDCSn[3:0]
SDRAM
4ma
SDRAM chip selects out
SFRM1
SPI1
8ma
PD
SPI Frame Clock
RASn
SDRAM
8ma
SDRAM RAS out
SSPRX1
SPI1
I
PD
SPI input
CASn
SDRAM
8ma
SDRAM CAS out
SSPTX1
SPI1
8ma
SDWEn
SDRAM
8ma
SDRAM write enable out
INT[3],
INT[1:0]
INT
I
PD
External interrupts
ADC[4:0]
ADC
A
External Analog Measurement Input
PRSTn
Syscon
I
PU
Power on reset
VDD_ADC
ADC
P
ADC power, 3.3V
RSTOn
Syscon
4ma
User Reset in out - open drain
GND_ADC
ADC
G
ADC ground
SLA[1:0]
EEPROM
4ma
Flash programming voltage control
USBp[2, 0]
USB
A
USB positive signals
EGPIO[15:0]
GPIO
I/O, 4ma
PU
Enhanced GPIO
USBm[2, 0]
USB
A
USB negative signals
FGPIO[3:1]
GPIO
I/O, 8ma
PU
GPIO on Port F
TXD0
UART1
4ma
HGPIO[5:2]
GPIO
I/O, 8ma
PU
GPIO on Port H
RXD0
UART1
I
PU
Receive in
CGPIO[0]
GPIO
I/O, 8ma
PU
GPIO on Port C
CTSn
UART1
I
PU
Clear to send / transmit enable
CVDD
Power
P
Digital power, 1.8V
DSRn
UART1
I
PU
Data set ready / Data Carrier Detect
RVDD
Power
P
Digital power, 3.3V
DTRn
UART1
4ma
Data Terminal Ready output
CGND
Ground
G
Digital ground
RTSn
UART1
4ma
Ready to send
RGND
Ground
G
Digital ground
TXD1
UART2
4ma
Transmit / IrDA output
RXD1
UART2
I
Block
Pad
Type
Pull
Type
TCK
JTAG
I
PD
JTAG clock in
TDI
JTAG
I
PD
TDO
JTAG
4ma
TMS
JTAG
I
TRSTn
JTAG
Pin Name
BOOT[1:0]
DS653PP3
PU
Description
Transmit out
PU
Pin Name
Pull
Type
Description
Management data clock
AC97 reset
SPI output
Receive / IrDA input
©Copyright 2005 Cirrus Logic (All Rights Reserved)
39
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Table R illustrates the pin signal multiplexing and configuration options.
Table R. Pin Multiplex Usage Information
40
Physical Pin Name
Description
Multiplex signal name
EGPIO[0]
Ring Indicator Input
RI
EGPIO[1]
1Hz clock monitor
CLK1HZ
EGPIO[3]
HDLC Clock
HDLCCLK1
EGPIO[4]
I2S Transmit Data 1
SDO1
EGPIO[5]
I2S Receive Data 1
SDI1
EGPIO[6]
I2S Transmit Data 2
SDO2
EGPIO[7]
DMA Request 0
DREQ0
EGPIO[8]
DMA Acknowledge 0
DACK0
EGPIO[9]
DMA EOT 0
DEOT0
EGPIO[10]
DMA Request 1
DREQ1
EGPIO[11]
DMA Acknowledge 1
DACK1
EGPIO[12]
DMA EOT 1
DEOT1
EGPIO[13]
I2S Receive Data 2
SDI2
EGPIO[14]
PWM1 Output
PWMOUT1
EGPIO[15]
Device active / present
DASP
ABITCLK
I2S Serial clock
SCLK
ASYNC
I2S Frame Clock
LRCK
ASDO
I2S Transmit Data 0
SDO0
ASDI
I2S Receive Data 0
SDI0
ARSTn
I2S Master clock
MCLK
SCLK1
I2S Serial clock
SCLK
SFRM1
I2S Frame Clock
LRCK
SSPTX1
I2S Transmit Data 0
SDO0
SSPRX1
I2S Receive Data 0
SDI0
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Acronyms and Abbreviations
The following tables list abbreviations and acronyms
used in this data sheet.
Term
Term
Definition
OHCI
Open Host Controller Interface
PHY
Ethernet PHYsical layer interface
PIO
Programmed I/O
RISC
Reduced Instruction Set Computer
SDMI
Secure Digital Music Initiative
SDRAM
Synchronous Dynamic RAM
SPI
Serial Peripheral Interface
SRAM
Static Random Access Memory
STA
Station - Any device that contains an IEEE 802.11
conforming Medium Access Control (MAC) and physical
layer (PHY) interface to the wireless medium
TFT
Thin Film Transistor
TLB
Translation Lookaside Buffer
USB
Universal Serial Bus
Definition
ADC
Analog-to-Digital Converter
ALT
Alternative
AMBA
Advanced Micro-controller Bus Architecture
ATAPI
ATA Packet Interface
CODEC
COder / DECoder
CRC
Cyclic Redundancy Check
DAC
Digital-to-Analog Converter
DMA
Direct-Memory Access
EBUS
External Memory Bus
EEPROM Electronically Erasable Programmable Read Only Memory
EMAC
Ethernet Media Access Controller
FIFO
First In / First Out
FIQ
Fast Interrupt Request
FLASH
Flash memory
GPIO
General Purpose I/O
°C
degree Celsius
HDLC
High-level Data Link Control
Hz
Hertz = cycle per second
I/F
Interface
kbps
kilobits per second
kbyte
kilobyte
I2 S
Inter-IC Sound
kHz
kiloHertz = 1000 Hz
IC
Integrated Circuit
Mbps
Megabits per second
ICE
In-Circuit Emulator
MHz
MegaHertz = 1,000 KiloHertz
IDE
Integrated Drive Electronics
µA
microAmpere = 10-6 Ampere
IEEE
Institute of Electronics and Electrical Engineers
µs
microsecond = 1,000 nanoseconds = 10-6 seconds
IrDA
Infrared Data Association
mA
milliAmpere = 10-3 Ampere
IRQ
Standard Interrupt Request
ms
millisecond = 1,000 microseconds = 10-3 seconds
ISO
International Standards Organization
mW
milliWatt = 10-3 Watts
JTAG
Joint Test Action Group
ns
nanosecond = 10-9 seconds
LFSR
Linear Feedback Shift Register
pF
picoFarad = 10-12 Farads
MII
Media-independent Interface
V
Volt
MMU
Memory Management Unit
W
Watt
DS653PP3
Units of Measurement
Symbol
Unit of Measure
©Copyright 2005 Cirrus Logic (All Rights Reserved)
41
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Ordering Information
The order numbers for the device are:
EP9302-CQ
EP9302-CQZ
EP9302-IQ
EP9302-IQZ
0 °C to +70 °C
0 °C to +70 °C
-40 °C to +85 °C
-40 °C to +85 °C
208-pin LQFP
208-pin LQFP
208-pin LQFP
208-pin LQFP
Lead Free
Lead Free
EP9302 — CQZ
Lead Material:
Z = Lead Free
Part Number
Product Line:
Embedded Processor
Note:
Package Type:
Q = 208 pin, Low Profile Quad Flat Pack (28 mm x 28 mm)
Temperature Range:
C = Commercial
E = Extended Operating Version
I = Industrial Operating Version
Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries
("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS
IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including
those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information
as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing
this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights.
Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization
with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or
promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY
OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE
SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF
THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY
SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY,
INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp.
Texas Instruments is a registered trademark of Texas Instruments, Inc.
Motorola and SPI are registered trademarks of Motorola, Inc.
LINUX is a registered trademark of Linus Torvalds.
42
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3