Renesas HD64F2214 16-bit single-chip microcomputer h8s family/h8s/2200 sery Datasheet

REJ09B0189-0400
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and additions.
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16
H8S/2214 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2200 Series
H8S/2214
Rev. 4.00
Revision Date: Sep. 18, 2008
HD64F2214
HD6432214
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev.4.00 Sep. 18, 2008 Page ii of lx
REJ09B0189-0400
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in
the manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In
operation with an unused pin in the open-circuit state, extra electromagnetic noise is
induced in the vicinity of LSI, an associated shoot-through current flows internally, and
malfunctions may occur due to the false recognition of the pin state as an input signal.
Unused pins should be handled as described under Handling of Unused Pins in the
manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the
states of pins are not guaranteed from the moment when power is supplied until the
reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on
reset function are not guaranteed from the moment when power is supplied until the
power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has
become stable. When switching the clock signal during program execution, wait until the
target clock signal has stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization
of the clock signal. Moreover, when switching to a clock signal produced with an
external resonator (or by an external oscillator) while program execution is in progress,
wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number,
confirm that the change will not lead to problems.
⎯ The characteristics of MPU/MCU in the same group but having different type numbers
may differ because of the differences in internal memory capacity and layout pattern.
When changing to products of different type numbers, implement a system-evaluation
test for each of the products.
Rev.4.00 Sep. 18, 2008 Page iii of lx
REJ09B0189-0400
Configuration of this Manual
This manual comprises the following items:
1. General Precautions in the Handling of MPU/MCU Products
2. Configuration of this Manual
3. Overview
4. Table of Contents
5. Summary
6. Description of Functional Modules
•
CPU and System-Control Modules
•
On-chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Features
ii) I/O pins
iii) Description of Registers
iv) Description of Operation
v) Usage: Points for Caution
When designing an application system that includes this LSI, take the points for caution into
account. Each section includes points for caution in relation to the descriptions given, and points
for caution in usage are given, as required, as the final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
•
Product-type codes and external dimensions
•
Main Revisions for this edition
The history of revisions is a summary of sections that have been revised and sections that have
been added to earlier versions. This does not include all of the revised contents. For details,
confirm by referring to the main description of this manual.
10. Appendix/Appendices
Rev.4.00 Sep. 18, 2008 Page iv of lx
REJ09B0189-0400
Preface
This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit
architecture as its core, and the peripheral functions required to configure a system.
This LSI is equipped with ROM, RAM, a bus controller, data transfer controller (DTC), a DMA
controller (DMAC), two types of timers, a serial communication interface (SCI), a D/A converter,
an A/D converter, and I/O ports as on-chip supporting modules. This LSI is suitable for use as an
embedded processor for high-level control systems. Its on-chip ROM are flash memory (FZTAT™*) and masked ROM that provides flexibility as it can be reprogrammed in no time to
cope with all situations from the early stages of mass production to full-scale mass production.
This is particularly applicable to application devices with specifications that will most probably
change.
Note: * F-ZTAT is a trademark of Renesas Technology, Corp.
Target Users: This manual was written for users who will be using the H8S/2214 Group in the
design of application systems. Members of this audience are expected to understand
the fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2214 Group to the above audience. Refer to the
H8S/2600 Series, H8S/2000 Series Software Manual for a detailed description of
the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU’s functions
Read the H8S/2600 Series, H8S/2000 Series Software Manual.
• In order to understand the details of a register when its name is known
The addresses, bits, and initial values of the registers are summarized in appendix B, Internal
I/O Registers.
Example:
Related Manuals:
Bit order:
The MSB is on the left and the LSB is on the right.
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev.4.00 Sep. 18, 2008 Page v of lx
REJ09B0189-0400
H8S/2214 Group Manuals:
Document Title
Document No.
H8S/2214 Group Hardware Manual
This manual
H8S/2600 Series, H8S/2000 Series Software Manual
REJ09B0139
User’s Manuals for Development Tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage
Editor User’s Manual
REJ10B0058
H8S, H8/300 Series Simulator/Debugger (for Windows) User’s Manual
ADE-702-037
H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial
REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3 User's
Manual
REJ10B0026
Rev.4.00 Sep. 18, 2008 Page vi of lx
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Main Revisions for This Edition
Item
Page
1.3.2 Pin Functions 8 to 11
in Each Operating
Mode
Table 1.2 Pin
Functions in Each
Operating Mode
2.3 Address Space 25
Revisions (See Manual for Details)
Note added
Pin No.
TFP-100B,
TFP-100BV,
TFP-100G,
TFP-100GV
Pin Name
BP-112,
BP-112V,
TBP-112A,
TBP-112AV Mode 4
Mode 5
Mode 6
Mode 7
PROM
Mode*
Note: * NC pins must be left open.
Description added
... The H8S/2000 CPU provides linear access to a maximum 64kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. Note
that the modes and address spaces that can actually be used
differ between individual products. See section 3, MCU Operating
Modes, for details.
Figure 2.6 Memory
Map
Figure amended
H'0000
H'00000000
64 kbyte
H'FFFF
16 Mbyte
H'00FFFFFF
Program area
Data area
Cannot be
used by the
H8S/2214 Group
H'FFFFFFFF
(a) Normal Mode*
(b) Advanced Mode
Note: * Not available in the H8S/2214 Group.
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Item
Page
Revisions (See Manual for Details)
2.6.1 Overview
34
Note added
Table 2.1
Instruction
Classification
Function
Instructions
Size
Types
Data transfer
MOV
1
1
POP* , PUSH*
BWL
5
5
LDM* , STM*
WL
5
MOVFPE, MOVTPE*
L
3
B
Notes : 5. The STM/LDM instructions may only be used with the
ER0 to ER6 registers.
2.6.2 Instructions
and Addressing
Modes
35
Table 2.2
Combinations of
Instructions and
Addressing Modes
Note added
Function
Instruction
Data
transfer
MOV
POP, PUSH
LDM*3, STM*3
MOVFPE*1,
MOVTPE*1
Notes : 3. The STM/LDM instructions may only be used with the
ER0 to ER6 registers.
2.6.3 Table of
Instructions
Classified by
Function
Table 2.3
Instructions
Classified by
Function
38
40
Note added
Type
Instruction
1
Size*
Function
Data transfer
2
LDM*
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
2
STM*
L
Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
1
Size*
Function
B
@ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
Note amended
Type
Arithmetic
operations
46
Instruction
3
TAS*
Note added
Notes : 2. The STM/LDM instructions may only be used with the
ER0 to ER6 registers.
3. This instruction should be used with the ER0, ER1,
ER4, or ER5 general register only.
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Item
Page
2.6.5 Notes on Use 48
of Bit-Manipulation
Instructions
Revisions (See Manual for Details)
Description added
... In this case, the relevant flag need not be read beforehand if it
is clear that it has been set to 1 in an interrupt handling routine,
etc.
See section 2.10.3, Bit Manipulation Instruction Usage Notes, for
details.
2.8.1 Overview
56
Figure 2.15
Processing States
Figure 2.16 State
Transitions
Note added
Note : * The power-down state also includes a medium-speed
mode and module stop mode. See section 17, PowerDown Modes, for details.
57
Figure amended
Sleep mode
Interrupt
request
Software standby mode
STBY = high, RES = low
Hardware standby mode*2
Low Power States
5.1.2 Block
Diagram
Figure 5.1 Block
Diagram of Interrupt
Controller
92
Figure amended
INTM1 INTM0
SYSCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
ISCR
IER
Rev.4.00 Sep. 18, 2008 Page ix of lx
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Item
Page
Revisions (See Manual for Details)
5.3.1 External
Interrupts
100
Note added
Note : n = 7 to 0
Figure 5.3 Timing
of Setting IRQnF
5.5.1 Contention
between Interrupt
Generation and
Disabling
113
Description amended
5.5.5 IRQ
Interrupts
115
Newly added
5.5.6 NMI Interrupt 115
Usage Notes
Newly added
6.1.2 Block
Diagram
Legend added
When an interrupt enable bit is cleared to 0 to disable interrupt
requests, the disabling becomes effective after execution of the
instruction.
120
Legend:
Figure 6.1 Block
Diagram of Bus
Controller
ABWCR : Bus width control register
ASTCR: Access state control register
BCRH: Bus control register H
BCRL: Bus control register L
WCRH: Wait state control register H
WCRL: Wait state control register L
7.3.4 DMA Control 195
Register (DMACR)
Bits 10 to 7—
Reserved
Bit 4—Reserved
196
Description added
Although these bits are readable/writable, only 0 should be written
here.
Description added
Although this bit is readable/writable, only 0 should be written
here.
7.3.5 DMA Band
Control Register
(DMABCR)
200
Bits 10 and 8—
Reserved (DTA1A,
DTA0A)
7.5.4 Repeat Mode 217
Description added
Reserved bits in full address mode. Read and write possible.
Although these bits are readable/writable, only 0 should be written
here.
Description amended
Repeat mode can be specified by setting the RPE bit in DMACR
to 1, and clearing the DTIE bit in DMABCRL to 0.
Rev.4.00 Sep. 18, 2008 Page x of lx
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Item
Page
Revisions (See Manual for Details)
7.5.9 DMAC Bus
Cycles (Dual
Address Mode)
234
Description amended
Either a one-byte or a one-word transfer is performed for each
transfer request, and after the transfer the bus is released.
(2) Full Address
Mode (Cycle Steal
Mode)
8.2.5 DTC Transfer 258
Count Register A
(CRA)
8.3.1 Overview
262
Figure 8.2
Flowchart of DTC
Operation
Description amended
In repeat mode or block transfer mode, CRA is divided into two
parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). In
repeat mode, CRAH holds the transfer count and CRAL functions
as an 8-bit transfer counter (1 to 256). In block transfer mode,
CRAH holds the block size and functions as an 8-bit block size
counter (1 to 256). CRAL is decremented by 1 every time data is
transferred and when the counter value becomes H'00 the
contents of CRAH are transferred. This operation is repeated.
Note added
Transfer Counter = 0
or DISEL = 1
Yes
No
Clear an activation flag
End
Clear DTCER
Interrupt exception *
handling
Note: * See the section on the corresponding peripheral module for details
on the content of the processing required for interrupt handling.
8.3.2 Activation
Sources
264
Description added
... The activation source flag, in the case of RXI0, for example, is
the RDRF flag of SCI0.
Since there are multiple factors that can initiate DTC operation,
the flag that initiated the transfer is not cleared after the last byte
(or word) is transferred. The corresponding interrupt handler must
perform the required processing.
Rev.4.00 Sep. 18, 2008 Page xi of lx
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Item
Page
Revisions (See Manual for Details)
8.3.8 Chain
Transfer
273
Description added
8.5 Usage Notes
280
Figure 8.9 shows the memory map for chain transfer. The DTC
reads the start address for the register information from the DTC
vector address corresponding to the DTC activation factor. After
the data transfer completes, the CHNE bit in this register is tested,
and if it is 1, the next register information allocated sequentially is
read and a transfer is performed. This operation continues until a
data transfer for register information whose CHNE bit is 0
completes.
(1) Module Stop
9.2.2 Register
Configuration
... However, 1 cannot be written in the MSTPA6 bit while the DTC
is operating. See section 17, Power-Down Modes, for details.
286
297
309
(1) Port A Data
Direction Register
(PADDR)
Description added
Setting a P7DDR bit to 1 makes the corresponding port 7 pin an
output pin, while clearing the bit to 0 makes the pin an input pin.
Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section
2.10.4, Access Methods for Registers with Write-Only Bits.
(1) Port 7 Data
Direction Register
(P7DDR)
9.7.2 Register
Configuration
Description added
Setting a P3DDR bit to 1 makes the corresponding port 3 pin an
output pin, while clearing the bit to 0 makes the pin an input pin.
Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section
2.10.4, Access Methods for Registers with Write-Only Bits.
(1) Port 3 Data
Direction Register
(P3DDR)
9.5.2 Register
Configuration
Description added
... P1DDR cannot be read; if it is, an undefined value will be read.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an
output pin, while clearing the bit to 0, makes that pin an input pin.
Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section
2.10.4, Access Methods for Registers with Write-Only Bits.
(1) Port 1 Data
Direction Register
(P1DDR)
9.3.2 Register
Configuration
Description added
316
Description added
Bits 7 to 4 are reserved; these bits cannot be modified and will
return an undefined value if read. Since this register is a write-only
register, do not use bit manipulation instructions to write to this
register. See section 2.10.4, Access Methods for Registers with
Write-Only Bits.
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Item
Page
Revisions (See Manual for Details)
9.8.2 Register
Configuration
323
Description added
... PBDDR cannot be read; if it is, an undefined value will be read.
Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section
2.10.4, Access Methods for Registers with Write-Only Bits.
(1) Port B Data
Direction Register
(PBDDR)
9.9.2 Register
Configuration
331
... PCDDR cannot be read; if it is, an undefined value will be read.
Setting a PCDDR bit to 1 makes the corresponding port C pin an
output pin, while clearing the bit to 0, makes the pin an input pin.
Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section
2.10.4, Access Methods for Registers with Write-Only Bits.
(1) Port C Data
Direction Register
(PCDDR)
9.10.2 Register
Configuration
338
343
349
(1) Port G Data
Direction Register
(PGDDR)
Description added
... PFDDR cannot be read; if it is, an undefined value will be read.
Setting a PFDDR bit to 1 makes the corresponding port C pin an
output pin, while clearing the bit to 0, makes the pin an input pin.
Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section
2.10.4, Access Methods for Registers with Write-Only Bits.
(1) Port F Data
Direction Register
(PFDDR)
9.13.2 Register
Configuration
Description added
... PEDDR cannot be read; if it is, an undefined value will be read.
Setting a PEDDR bit to 1 makes the corresponding port C pin an
output pin, while clearing the bit to 0, makes the pin an input pin.
Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section
2.10.4, Access Methods for Registers with Write-Only Bits.
(1) Port E Data
Direction Register
(PEDDR)
9.12.2 Register
Configuration
Description added
... PDDDR cannot be read; if it is, an undefined value will be read.
Setting a PDDDR bit to 1 makes the corresponding port C pin an
output pin, while clearing the bit to 0, makes the pin an input pin.
Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section
2.10.4, Access Methods for Registers with Write-Only Bits.
(1) Port D Data
Direction Register
(PDDDR)
9.11.2 Register
Configuration
Description added
354
Description added
... Also, bits 7 to 5 are reserved, and will return an undefined value
if read. Setting a PGDDR bit to 1 makes the corresponding port C
pin an output pin, while clearing the bit to 0, makes the pin an
input pin. Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section
2.10.4, Access Methods for Registers with Write-Only Bits.
Rev.4.00 Sep. 18, 2008 Page xiii of lx
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Item
Page
Revisions (See Manual for Details)
9.14 Handling of
Unused Pins
358
Newly added
10.2.1 Timer
Control Register
(TCR)
368
Note amended
Note: Internal clock edge selection is valid when the input clock is
φ/4 or slower. This setting is ignored if the input clock is φ
/1, or when overflow/underflow of another channel is
selected. (Counting occurs on the falling edge of φ when
φ/1 is selected.)
Bits 4 and 3—Clock
Edge 1 and 0
(CKEG1, CKEG0)
10.2.5 Timer
Status Register
(TSR)
383
Description amended
Bit 3
TGFD
Description
Bit 3—Input
Capture/Output
Compare Flag D
(TGFD)
0
[Clearing conditions]
Bit 2—Input
Capture/Output
Compare Flag C
(TGFC)
Description amended
Bit 1—Input
Capture/Output
Compare Flag B
(TGFB)
Bit 0—Input
Capture/Output
Compare Flag A
(TGFA)
(Initial value)
•
When DTC is activated by a TGID interrupt, the DTC module MRB register DISEL
bit is 0, and furthermore the transfer counter is not 0.
•
When 0 is written to TGFD after reading TGFD = 1
Bit 2
384
TGFC
Description
0
[Clearing conditions]
(Initial value)
•
When DTC is activated by a TGIC interrupt, the DTC module MRB register DISEL
bit is 0, and furthermore the transfer counter is not 0.
•
When 0 is written to TGFC after reading TGFC = 1
Description amended
Bit 1
TGFB
Description
0
[Clearing conditions]
(Initial value)
•
When DTC is activated by a TGIB interrupt, the DTC module MRB register DISEL
bit is 0, and furthermore the transfer counter is not 0.
•
When 0 is written to TGFB after reading TGFB = 1
Description amended
Bit 0
TGFA
Description
0
[Clearing conditions]
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REJ09B0189-0400
(Initial value)
•
When DTC is activated by a TGIA interrupt, the DTC module MRB register DISEL
bit is 0, and furthermore the transfer counter is not 0.
•
When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1
•
When 0 is written to TGFA after reading TGFA = 1
Item
Page
10.7 Usage Notes 427
Revisions (See Manual for Details)
Description added
(1) Module Stop
Mode Settings
Figure 10.53
436
Contention between
TCNT Write and
Overflow
Figure amended
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
TCNT write data
TCNT
H'FFFF
M
Prohibited
TCFV flag
451
11.5.5 OVF Flag
Clear Operation in
Interval Timer Mode
12.2.7 Serial
Status Register
(SSR)
Bit 7—Transmit
Data Register
Empty (TDRE)
468
Newly added
Note added
Bit 7
TDRE
Description
0
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR
Note: * This bit is cleared by DTC when DISEL = 0 and
furthermore the transfer counter is not 0.
Bit 6—Receive Data
Register Full
(RDRF)
Note added
Bit 6
RDRF
Description
0
[Clearing conditions]
(Initial value)
•
When 0 is written to RDRF after reading RDRF = 1
•
When the DMAC or DTC* is activated by an RXI interrupt and reads data from
RDR
Note: * This bit is cleared by DTC when DISEL = 0 and
furthermore the transfer counter is not 0.
Rev.4.00 Sep. 18, 2008 Page xv of lx
REJ09B0189-0400
Item
Page
Revisions (See Manual for Details)
12.2.7 Serial
Status Register
(SSR)
470
Note added
Bit 2—Transmit End
(TEND)
Bit 2
TEND
Description
0
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR
Note: * This bit is cleared by DTC when DISEL = 0 and
furthermore the transfer counter is not 0.
12.3.2 Operation in 493
Asynchronous Mode
Figure 12.7
Sample SCI
Initialization
Flowchart
Note added
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if an
external clock is used.
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE* bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
<Transfer completion>
Rev.4.00 Sep. 18, 2008 Page xvi of lx
REJ09B0189-0400
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
[4]
Note: * The RE bit must be set when
the RxD pin is in the 1 state. If
the RE bit is set t 1 with the
RxD pin in the 0 state, this
event may be mistakenly
recognized as a start bit.
Item
Page
12.3.2 Operation in 494
Asynchronous Mode
Figure 12.8
Sample Serial
Transmission
Flowchart
Revisions (See Manual for Details)
Note added
[1]
Initialization
Start transmission
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
No
TDRE = 1
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes
[3]
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
Yes
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
<End>
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[4]
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC or
DTC* is activated by a transmit
data empty interrupt (TXI) request,
and date is written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Note: * The TDRE flag check and clear
operations are performed
automatically
by DTC only when the DTC
DISEL bit is 0 and furthermore
the transfer counter is not 0.
Therefore the CPU must clear
the TDRE flag when either
DISEL is 1 or when DISEL is 0
and furthermore the transfer
counter is 0.
Rev.4.00 Sep. 18, 2008 Page xvii of lx
REJ09B0189-0400
Item
Page
12.3.2 Operation in 497
Asynchronous Mode
Revisions (See Manual for Details)
Note added
Initialization
Figure 12.10
Sample Serial
Reception Data
Flowchart (1)
[1]
Start reception
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error processing and
break detection:
If a receive error occurs, read the
[2]
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
Yes
processing, ensure that the
PER ∨ FER ∨ ORER = 1
ORER, PER, and FER flags are
[3]
all cleared to 0. Reception cannot
No
Error processing
be resumed if any of these flags
(Continued on next page) are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
[4]
Read RDRF flag in SSR
the input port corresponding to
the RxD pin.
Read ORER, PER, and
FER flags in SSR
No
RDRF = 1
[4] SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
[5] Serial reception continuation
procedure:
To continue serial reception,
Yes
before the stop bit for the current
frame is received, read the
Clear RE bit in SCR to 0
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
<End>
flag is cleared automatically
when DMAC or DTC* is
Note: * The RDRF flag is cleared automatically by DTC
activated by an RXI interrupt and
only when the DTC DISEL bit is 0 and
the RDR value is read.
furthermore the transfer counter is not 0.
Therefore the CPU must clear the RDRF flag
when either DISEL is 1 or when DISEL is 0 and
furthermore the transfer counter is 0.
All data received?
Rev.4.00 Sep. 18, 2008 Page xviii of lx
REJ09B0189-0400
[5]
Item
Page
Revisions (See Manual for Details)
12.3.3
Multiprocessor
Communication
Function
503
Note added
Figure 12.14
Sample
Multiprocessor
Serial Transmission
Flowchart
[1] [1] SCI initialization:
Initialization
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
Yes
Read TEND flag in SSR
No
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
[3]
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DMAC or DTC* is activated by a
transmit data empty interrupt
(TXI) request, and data is written
to TDR.
TEND = 1
Yes
No
Break output?
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
[4]
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Yes
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
<End>
Note: * The TDRE flag is cleared
automatically by DTC only
when the DTC DISEL bit is 0
and furthermore the transfer
counter is not 0. Therefore
the CPU must clear the
TDRE flag when either DISEL
is 1 or when DISEL is 0 and
furthermore the transfer
counter is 0.
Rev.4.00 Sep. 18, 2008 Page xix of lx
REJ09B0189-0400
Item
Page
12.3.4 Operation in 512
Clocked
Synchronous Mode
Figure 12.21
Sample Serial
Transmission
Flowchart
Revisions (See Manual for Details)
Note added
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SSR
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC* is activated by a transmit data
empty interrupt (TXI) request, and data
is written to TDR.
No
TEND = 1
Yes
Clear TE bit in SCR to 0
<End>
Rev.4.00 Sep. 18, 2008 Page xx of lx
REJ09B0189-0400
Note: * The TDRE flag is cleared
automatically by DTC only when
the DTC DISEL bit is 0 and
furthermore the transfer counter is
not 0. Therefore the CPU must
clear the TDRE flag when either
DISEL is 1 or when DISEL is 0 and
furthermore the transfer counter is
0.
Item
Page
12.3.4 Operation in 515
Clocked
Synchronous Mode
Revisions (See Manual for Details)
Note added
Initialization
Figure 12.23
Sample Serial
Reception Flowchart
[1]
Start reception
[2]
Read ORER flag in SSR
Yes
[3]
ORER = 1
No
Error processing
(Continued below)
Read RDRF flag in SSR
[4]
No
RDRF = 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[1]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
processing, clear the ORER flag
to 0. Transfer cannot be resumed
if the ORER flag is set to 1.
[4] SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DMAC or
DTC* is activated by a receive
data full interrupt (RXI) request
and the RDR value is read.
<End>
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
<End>
Note: * The RDRF flag is cleared
automatically by DTC only
when the DTC DISEL bit is 0
and furthermore the transfer
counter is not 0. Therefore
the CPU must clear the
RDRF flag when either
DISEL is 1 or when DISEL is
0 and furthermore the
transfer counter is 0.
Rev.4.00 Sep. 18, 2008 Page xxi of lx
REJ09B0189-0400
Item
Page
12.3.4 Operation in 517
Clocked
Synchronous Mode
Figure 12.25
Sample Flowchart of
Simultaneous Serial
Transmit and
Receive Operations
Revisions (See Manual for Details)
Note added
Initialization
[1] SCI initialization:
[1]
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
Start transmission/reception
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0
to 1 can also be identified by a TXI
interrupt.
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
processing, clear the ORER flag to
0. Transmission/reception cannot be
resumed if the ORER flag is set to
1.
Read ORER flag in SSR
ORER = 1
No
Read RDRF flag in SSR
Yes
[3]
Error processing
[4] SCI status check and receive data
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[4]
No
RDRF = 1
Yes
[5] Serial transmission/reception
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
<End>
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to
0, then set both these bits to 1 simultaneously.
* The TDRE flag and RDRF flag clear operations are performed
automatically by DTC only when the corresponding DTC transfer
DISEL bit is 0 and furthermore the transfer counter is not 0.
Therefore the CPU must clear the corresponding flag when
either the corresponding DTC transfer DISEL is 1 or when the
corresponding DTC transfer DISEL is 0 and furthermore the
transfer counter is 0.
Rev.4.00 Sep. 18, 2008 Page xxii of lx
REJ09B0189-0400
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC is activated by a transmit data
empty interrupt (TXI) request and
data is written to TDR. Also, the
RDRF flag is cleared automatically
when the DMAC or DTC* is
activated by a receive data full
interrupt (RXI) request and the RDR
value is read.
Item
Page
12.4 SCI Interrupts 518
Revisions (See Manual for Details)
Note added
... The TDRE flag is cleared to 0 automatically when data transfer
is performed by the DMAC or DTC*. ...
... The RDRF flag is cleared to 0 automatically when data transfer
is performed by the DMAC or DTC*. ...
Note : * The flag is cleared when DISEL is 0 and furthermore the
transfer counter is not 0.
12.5 Usage Notes 520
Description added
(1) Module Stop
Mode Settings
(8) Restrictions on
Use of DMAC or
DTC
523
Description added
(b) When RDR is read by the DMAC or DTC, be sure to set the
activation source to the relevant SCI reception end interrupt
(RXI).
(c) During data transfers, flags are cleared automatically by DTC
only when the DTC DISEL bit is 0 and furthermore the transfer
counter is not 0. Therefore the CPU must clear the flags when
either DISEL is 1 or when DISEL is 0 and furthermore the
transfer counter is 0. In particular, note that during
transmission, data will not be transmitted correctly unless the
CPU clears the TDRE flag.
17.6.3 Setting
Oscillation
Stabilization Time
after Clearing
Software Standby
Mode
630
Table amended
STS2 STS1 STS0 Standby Time 16 MHz 13 MHz 10 MHz 8 MHz
0
0
1
Table 17.4
Oscillation
Stabilization Time
Settings
1
0
1
6 MHz
4 MHz
2 MHz
Unit
0
8192 states
0.51
0.63
0.82
1.0
1.4
2.0
4.1
ms
1
16384 states
1.0
1.3
1.6
2.0
2.7
4.1
0
32768 states
2.0
2.5
3.3
4.1
5.5
1
65536 states
4.1
5.0
6.6
0
131072 states
1
262144 states
16.4
20.2
0
2048 states
0.13
1
16 states
1.0
8.2
10.1
13.1
8.2
10.9
8.2
16.4
8.2
16.4
32.8
16.4
21.8
32.8
65.5
26.2
32.8
43.7
65.5
131.1
0.16
0.20
0.26
0.34
0.51
1.0
1.2
1.6
2.0
2.7
4.0
8.0
µs
: Recommended time setting
18.7 Usage Note
659
Title added
• Characteristics of
the F-ZTAT and
Mask ROM Versions
• General Notes on
Printed Circuit
Board Deign
Description added
Rev.4.00 Sep. 18, 2008 Page xxiii of lx
REJ09B0189-0400
Page
A.1 Instruction List 665
Revisions (See Manual for Details)
Note added
Table A.1 Data
Transfer Instructions
Addressing Mode/
Instruction Length (Bytes)
Mnemonic
LDM*
LDM @SP+,(ERm-ERn)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Item
L
4
Operation
(@SP ERn32,SP+4 SP)
Condition Code
No. of States*1
I H N Z V C
Advanced
— — — — — —
7/9/11 [1]
— — — — — —
7/9/11 [1]
Repeated for each register restored
STM*
STM (ERm-ERn),@-SP
L
4
(SP-4 SP,ERn32 @SP)
Repeated for each register saved
Note : The STM/LDM instructions may only be used with the ER0
to ER6 registers.
669
Note added
TAS*
Mnemonic
TAS @ERd*2
B
Operation
4
@ERd-0→CCR set, (1)→
Condition Code
No. of States*1
I H N Z V C
Advanced
↔
↔
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Table A.2
Arithmetic
Instructions
4
— —
0 —
(<bit 7> of @ERd
Note : The TAS instruction may only be used with the ER0, ER1,
ER4, and ER5 registers.
A.4 Number of
711
States Required for
Instruction
Execution
Note added
Instruction
Mnemonic
I
Table A.15
Number of Cycles in
Instruction
Execution
LDM*4
LDM.L @SP+,
(ERn-ERn+1)
2
4
1
LDM.L @SP+,
(ERn-ERn+2)
2
6
1
LDM.L @SP+,
(ERn-ERn+3)
2
8
1
Branch
Instruction Address
Fetch
Read
Byte
Stack
Data
Operation Access
Word
Data
Access
Internal
Operation
K
M
N
715
Branch
Instruction Address
Fetch
Read
Word
Data
Access
Internal
Operation
K
M
N
L
Note amended
Instruction
Mnemonic
I
STM*4
STM.L (ERn-ERn+1),
@-SP
2
4
1
STM.L (ERn-ERn+2),
@-SP
2
6
1
STM.L (ERn-ERn+3),
@-SP
2
8
1
TAS @ERd
2
TAS*3
716
J
Byte
Stack
Data
Operation Access
J
L
2
Note added
Notes : 4. The STM/LDM instructions may only be used with the
ER0 to ER6 registers.
Rev.4.00 Sep. 18, 2008 Page xxiv of lx
REJ09B0189-0400
Item
Page
Revisions (See Manual for Details)
A.5 Bus States
during Instruction
Execution
724
Note added
Table A.16
Instruction
Execution Cycles
1
Instruction
LDM.L @SP+,
R:W 2nd
(ERn–ERn+1)*9
LDM.L @SP+,(ERn–ERn+2)*9 R:W 2nd
LDM.L @SP+,(ERn–ERn+3)*9 R:W 2nd
729
6
7
8
9
2
3
4
5
R:W:M NEXT Internal operation, W:W:M stack (H)*3 W:W stack (L)*3
1 state
3
*
R:W:M NEXT Internal operation, W:W:M stack (H) W:W stack (L)*3
1 state
R:W:M NEXT Internal operation, W:W:M stack (H)*3 W:W stack (L)*3
1 state
6
7
8
9
Note added
1
Instruction
STM.L(ERn–ERn+1),@–SP*9 R:W 2nd
STM.L(ERn–ERn+2),@–SP*9
R:W 2nd
STM.L(ERn–ERn+3),@–SP*9 R:W 2nd
730
2
3
4
5
R:W:M NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3
1 state
Internal operation, R:W:M stack (H)*3 R:W stack (L)*3
1 state
R:W NEXT
Internal operation, R:W:M stack (H)*3 R:W stack (L)*3
1 state
R:W NEXT
Note added
Notes : 9. The STM/LDM instructions may only be used with the
ER0 to ER6 registers.
A.6 Condition
Code Modification
Table A.17
Condition Code
Modification
733
Note added
Instruction
LDM*
735
2
N
Z
V
C
Definition
— — — — —
Note added
Instruction
STM*
736
H
2
H
N
Z
V
C
Definition
— — — — —
Note added
Instruction
H
1
—
TAS*
N
Z
V
C
Definition
0
—
N = Dm
Z = Dm · Dm–1 · ...... · D0
Notes : 2. The STM/LDM instructions may only be used with the
ER0 to ER6 registers.
B.2 Functions
TCR1—Timer
Control Register 1
785
Description added
Clock Edge 1 and 0
0 0 Count at rising edge
1 Count at falling edge
1 — Count at both edges
Note: The internal clock edge selection is valid when the input
clock is φ/4 or slower. This setting is ignored if the input
clock is φ/1, or when overflow/underflow of another
channel is selected. (Counting occurs on the falling edge
of φ when φ/1 is selected.)
Rev.4.00 Sep. 18, 2008 Page xxv of lx
REJ09B0189-0400
Item
Page
Revisions (See Manual for Details)
B.2 Functions
791
Description added
TCR2—Timer
Control Register 2
Clock Edge 1 and 0
0 0 Count at rising edge
1 Count at falling edge
1 — Count at both edges
Note: The internal clock edge selection is valid when the input clock is
φ/4 or slower. This setting is ignored if the input clock is φ/1, or
when overflow/underflow of another channel is selected.
(Counting occurs on the falling edge of φ when φ/1 is selected.)
TCSR0—Timer
Control/Status
Register
801
Note added
Bit
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
—
—
CKS2
CKS1
CKS0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/(W)*1
R/W
R/W
—
—
R/W
R/W
R/W
Clock Select 2 to 0
CKS2 CKS1 CKS0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Clock
φ/2 (Initial value)
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Overflow Period*
(when φ = 10 MHz)
51.2 µs
1.6 ms
3.2 ms
13.2 ms
52.4 ms
209.8 ms
838.8 ms
3.36 s
Note: * The overflow period is the time from when TCNT
starts counting up from H'00 until overflow occurs.
Timer Enable
0 TCNT is initialized to H'00 and
count operation is halted
1 TCNT counts
Timer Mode Select
0 Interval timer mode: Interval timer interrupt (WOVI) request is sent to CPU when
TCNT overflows
1 Watchdog timer mode: Internal reset can be selected when TCNT overflows*
Note: * For details of the case where TCNT overflows in watchdog timer mode,
see section 11.2.3, Reset Control/Status Register (RSTCSR).
Overflow Flag
0 [Clearing condition]
• Cleared by reading*2 TCSR when OVF = 1, then writing 0 to OVF
1 [Setting condition]
• When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog
timer mode, OVF is cleared automatically by the internal reset.
Notes: 1. Only 0 can be written, to clear the flag.
TCSR is write-protected by a password to prevent accidental overwriting. For details
see section 11.2.4, Notes on Register Access.
2. If the interval timer interrupt is disabled and the OVF flag is polled, the application
should read the OVF = 1 state at least twice.
Rev.4.00 Sep. 18, 2008 Page xxvi of lx
REJ09B0189-0400
Item
Page
Revisions (See Manual for Details)
B.2 Functions
807
Note added
SSR0—Serial
Status Register 0
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
0
0
0
0
1
R/(W)*1
R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1
1
0
0
R
R
R/W
Multiprocessor Bit Transfer
0 Data with a 0 multiprocessor bit is transmitted
1 Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
• When data with a 0 multiprocessor bit is received
1 [Setting condition]
• When data with a 1 multiprocessor bit is received
Transmit End
0
1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC*2 is activated by a TXI interrupt request and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit
character
Parity Error
0 [Clearing condition]
• When 0 is written to PER after reading PER = 1
1 [Setting condition]
• When, in reception, the number of 1 bits in the receive data plus
the parity bit does not match the parity setting (even or odd)
specified by the O/E bit in SMR
Framing Error
0 [Clearing condition]
• When 0 is written to FER after reading FER = 1
1 [Setting condition]
• When the SCI checks whether the stop bit at the end of the receive
data is 1 when reception ends, and the stop bit is 0
Overrun Error
0 [Clearing condition]
• When 0 is written to ORER after reading ORER = 1
1 [Setting condition]
• When the next serial reception is completed while RDRF = 1
Receive Data Register Full
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC*2 is activated by an RXI interrupt request and reads data to RDR
1 [Setting condition]
• When serial reception ends normally and receive data is transferred from RSR
to RDR
Transmit Data Register Empty
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC*2 is activated by a TXI interrupt request and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Notes: 1. Only 0 can be written, to clear the flag.
2. Flags are only cleared when DISEL is 0 and furthermore the transfer counter is not 0.
Rev.4.00 Sep. 18, 2008 Page xxvii of lx
REJ09B0189-0400
Item
Page
Revisions (See Manual for Details)
B.2 Functions
813
Note added
SSR1—Serial
Status Register 1
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
0
0
0
0
1
R/(W)*1
R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1
1
0
0
R
R
R/W
Multiprocessor Bit Transfer
0 Data with a 0 multiprocessor bit is transmitted
1 Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
• When data with a 0 multiprocessor bit is received
1 [Setting condition]
• When data with a 1 multiprocessor bit is received
Transmit End
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC*2 is activated by a TXI interrupt request and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte serial
transmit character
Parity Error
0 [Clearing condition]
• When 0 is written to PER after reading PER = 1
1 [Setting condition]
• When, in reception, the number of 1 bits in the receive data plus
the parity bit does not match the parity setting (even or odd)
specified by the O/E bit in SMR
Framing Error
0 [Clearing condition]
• When 0 is written to FER after reading FER = 1
1 [Setting condition]
• When the SCI checks whether the stop bit at the end of the
receive data is 1 when reception ends, and the stop bit is 0
Overrun Error
0 [Clearing condition]
• When 0 is written to ORER after reading ORER = 1
1 [Setting condition]
• When the next serial reception is completed while RDRF = 1
Receive Data Register Full
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC*2 is activated by an RXI interrupt request and reads data from RDR
1 [Setting condition]
• When serial reception ends normally and receive data is transferred from
RSR to RDR
Transmit Data Register Empty
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC*2 is activated by a TXI interrupt request and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Notes: 1. Only 0 can be written, to clear the flag.
2. Flags are only cleared when DISEL is 0 and furthermore the transfer counter is not 0.
Rev.4.00 Sep. 18, 2008 Page xxviii of lx
REJ09B0189-0400
Item
Page
Revisions (See Manual for Details)
B.2 Functions
819
Note added
SSR2—Serial
Status Register 2
:
Bit
Initial value :
R/W
:
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
0
0
0
0
1
R/(W)*1
R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1
1
0
0
R
R
R/W
Multiprocessor Bit Transfer
0 Data with a 0 multiprocessor bit is transmitted
1 Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
• When data with a 0 multiprocessor bit is received
1 [Setting condition]
• When data with a 1 multiprocessor bit is received
Transmit End
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC*2 is activated by a TXI interrupt request and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte serial
transmit character
Parity Error
0 [Clearing condition]
• When 0 is written to PER after reading PER = 1
1 [Setting condition]
• When, in reception, the number of 1 bits in the receive data plus
the parity bit does not match the parity setting (even or odd)
specified by the O/E bit in SMR
Framing Error
0 [Clearing condition]
• When 0 is written to FER after reading FER = 1
1 [Setting condition]
• When the SCI checks whether the stop bit at the end of the
receive data when reception ends, and the stop bit is 0
Overrun Error
0 [Clearing condition]
• When 0 is written to ORER after reading ORER = 1
1 [Setting condition]
• When the next serial reception is completed while RDRF = 1
Receive Data Register Full
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC*2 is activated by an RXI interrupt request and reads data from RDR
1 [Setting condition]
• When serial reception ends normally and receive data is transferred from
RSR to RDR
Transmit Data Register Empty
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC*2 is activated by a TXI interrupt request and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Notes: 1. Only 0 can be written, to clear the flag.
2. Flags are only cleared when DISEL is 0 and furthermore the transfer counter is not 0.
Rev.4.00 Sep. 18, 2008 Page xxix of lx
REJ09B0189-0400
Item
Page
Revisions (See Manual for Details)
C.3 Port 4 Block
Diagram
835
Legend amended
RPOR4: Read port 4
Figure C.9 Port 4
Block Diagram (Pins
P40 to P44, P46,
and P47)
Figure C.10 Port 4
Block Diagram (Pin
P45)
Legend amended
RPOR4: Read port 4
869
Figure replaced
Figure G.2 TFP100G, TFP-100GA
Package
Dimensions
870
Figure replaced
Figure G.3 TBP112A, TBP-112AV
Package
Dimensions
871
Figure replaced
Figure G.4 BP-112, 872
BP-112V Package
Dimensions
Figure replaced
Appendix G
Package
Dimensions
Figure G.1 TFP100B, TFP-100BV
Package
Dimensions
All trademarks and registered trademarks are the property of their respective owners.
Rev.4.00 Sep. 18, 2008 Page xxx of lx
REJ09B0189-0400
Contents
Section 1 Overview............................................................................................... 1
1.1
1.2
1.3
Overview................................................................................................................................ 1
Internal Block Diagrams ........................................................................................................ 5
Pin Description....................................................................................................................... 6
1.3.1 Pin Arrangements...................................................................................................... 6
1.3.2 Pin Functions in Each Operating Mode .................................................................... 8
1.3.3 Pin Functions .......................................................................................................... 12
Section 2 CPU..................................................................................................... 17
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Overview.............................................................................................................................. 17
2.1.1 Features................................................................................................................... 17
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 18
2.1.3 Differences from H8/300 CPU................................................................................ 19
2.1.4 Differences from H8/300H CPU............................................................................. 19
CPU Operating Modes ......................................................................................................... 20
Address Space ...................................................................................................................... 25
Register Configuration ......................................................................................................... 26
2.4.1 Overview................................................................................................................. 26
2.4.2 General Registers .................................................................................................... 27
2.4.3 Control Registers .................................................................................................... 28
2.4.4 Initial Register Values............................................................................................. 30
Data Formats ........................................................................................................................ 31
2.5.1 General Register Data Formats ............................................................................... 31
2.5.2 Memory Data Formats ............................................................................................ 33
Instruction Set ...................................................................................................................... 34
2.6.1 Overview................................................................................................................. 34
2.6.2 Instructions and Addressing Modes ........................................................................ 35
2.6.3 Table of Instructions Classified by Function .......................................................... 37
2.6.4 Basic Instruction Formats ....................................................................................... 47
2.6.5 Notes on Use of Bit-Manipulation Instructions ...................................................... 48
Addressing Modes and Effective Address Calculation ........................................................ 48
2.7.1 Addressing Mode .................................................................................................... 48
2.7.2 Effective Address Calculation................................................................................. 52
Processing States.................................................................................................................. 56
2.8.1 Overview................................................................................................................. 56
2.8.2 Reset State............................................................................................................... 57
2.8.3 Exception-Handling State ....................................................................................... 58
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REJ09B0189-0400
2.8.4 Program Execution State......................................................................................... 61
2.8.5 Bus-Released State ................................................................................................. 61
2.8.6 Power-Down State .................................................................................................. 61
2.9 Basic Timing........................................................................................................................ 62
2.9.1 Overview................................................................................................................. 62
2.9.2 On-Chip Memory (ROM, RAM) ............................................................................ 62
2.9.3 On-Chip Supporting Module Access Timing ......................................................... 64
2.9.4 External Address Space Access Timing ................................................................. 65
2.10 Usage Notes ......................................................................................................................... 65
2.10.1 TAS Instruction....................................................................................................... 65
2.10.2 STM/LDM Instruction Usage ................................................................................. 66
2.10.3 Bit Manipulation Instructions ................................................................................. 66
2.10.4 Access Methods for Registers with Write-Only Bits .............................................. 68
Section 3 MCU Operating Modes .......................................................................71
3.1
3.2
3.3
3.4
3.5
Overview.............................................................................................................................. 71
3.1.1 Operating Mode Selection ...................................................................................... 71
3.1.2 Register Configuration............................................................................................ 72
Register Descriptions ........................................................................................................... 72
3.2.1 Mode Control Register (MDCR) ............................................................................ 72
3.2.2 System Control Register (SYSCR) ......................................................................... 73
Operating Mode Descriptions .............................................................................................. 75
3.3.1 Mode 4 .................................................................................................................... 75
3.3.2 Mode 5 .................................................................................................................... 75
3.3.3 Mode 6 .................................................................................................................... 76
3.3.4 Mode 7 .................................................................................................................... 76
Pin Functions in Each Operating Mode ............................................................................... 77
Memory Map in Each Operating Mode ............................................................................... 77
Section 4 Exception Handling .............................................................................79
4.1
4.2
4.3
Overview.............................................................................................................................. 79
4.1.1 Exception Handling Types and Priority.................................................................. 79
4.1.2 Exception Handling Operation................................................................................ 80
4.1.3 Exception Sources and Vector Table ...................................................................... 80
Reset ................................................................................................................................ 82
4.2.1 Overview................................................................................................................. 82
4.2.2 Reset Types............................................................................................................. 82
4.2.3 Reset Sequence ....................................................................................................... 83
4.2.4 Interrupts after Reset............................................................................................... 85
4.2.5 State of On-Chip Supporting Modules after Reset Release .................................... 85
Traces ................................................................................................................................ 86
Rev.4.00 Sep. 18, 2008 Page xxxii of lx
REJ09B0189-0400
4.4
4.5
4.6
4.7
Interrupts .............................................................................................................................. 87
Trap Instruction.................................................................................................................... 88
Stack Status after Exception Handling................................................................................. 89
Notes on Use of the Stack .................................................................................................... 90
Section 5 Interrupt Controller ............................................................................. 91
5.1
5.2
5.3
5.4
5.5
5.6
Overview.............................................................................................................................. 91
5.1.1 Features................................................................................................................... 91
5.1.2 Block Diagram ........................................................................................................ 92
5.1.3 Pin Configuration.................................................................................................... 93
5.1.4 Register Configuration............................................................................................ 93
Register Descriptions ........................................................................................................... 94
5.2.1 System Control Register (SYSCR) ......................................................................... 94
5.2.2 Interrupt Priority Registers A to D, F, G, J, K, M
(IPRA to IPRD, IPRF, IPRG, IPRJ, IPRK, IPRM)................................................. 95
5.2.3 IRQ Enable Register (IER) ..................................................................................... 96
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 97
5.2.5 IRQ Status Register (ISR)....................................................................................... 98
Interrupt Sources .................................................................................................................. 99
5.3.1 External Interrupts .................................................................................................. 99
5.3.2 Internal Interrupts.................................................................................................. 101
5.3.3 Interrupt Exception Handling Vector Table.......................................................... 101
Interrupt Operation............................................................................................................. 104
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................. 104
5.4.2 Interrupt Control Mode 0 ...................................................................................... 107
5.4.3 Interrupt Control Mode 2 ...................................................................................... 109
5.4.4 Interrupt Exception Handling Sequence ............................................................... 111
5.4.5 Interrupt Response Times ..................................................................................... 112
Usage Notes ....................................................................................................................... 113
5.5.1 Contention between Interrupt Generation and Disabling...................................... 113
5.5.2 Instructions that Disable Interrupts ....................................................................... 114
5.5.3 Times when Interrupts Are Disabled .................................................................... 114
5.5.4 Interrupts during Execution of EEPMOV Instruction........................................... 115
5.5.5 IRQ Interrupts ....................................................................................................... 115
5.5.6 NMI Interrupt Usage Notes................................................................................... 115
DTC and DMAC Activation by Interrupt .......................................................................... 116
5.6.1 Overview............................................................................................................... 116
5.6.2 Block Diagram ...................................................................................................... 116
5.6.3 Operation .............................................................................................................. 117
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REJ09B0189-0400
Section 6 Bus Controller....................................................................................119
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Overview............................................................................................................................ 119
6.1.1 Features................................................................................................................. 119
6.1.2 Block Diagram...................................................................................................... 120
6.1.3 Pin Configuration.................................................................................................. 121
6.1.4 Register Configuration.......................................................................................... 122
Register Descriptions ......................................................................................................... 123
6.2.1 Bus Width Control Register (ABWCR)................................................................ 123
6.2.2 Access State Control Register (ASTCR) .............................................................. 124
6.2.3 Wait Control Registers H and L (WCRH, WCRL)............................................... 125
6.2.4 Bus Control Register H (BCRH) .......................................................................... 129
6.2.5 Bus Control Register L (BCRL) ........................................................................... 131
6.2.6 Pin Function Control Register (PFCR) ................................................................. 132
Overview of Bus Control ................................................................................................... 134
6.3.1 Area Divisions ...................................................................................................... 134
6.3.2 Bus Specifications................................................................................................. 135
6.3.3 Memory Interfaces................................................................................................ 136
6.3.4 Interface Specifications for Each Area ................................................................. 137
6.3.5 Chip Select Signals ............................................................................................... 138
Basic Bus Interface ............................................................................................................ 139
6.4.1 Overview............................................................................................................... 139
6.4.2 Data Size and Data Alignment.............................................................................. 139
6.4.3 Valid Strobes......................................................................................................... 141
6.4.4 Basic Timing......................................................................................................... 142
6.4.5 Wait Control ......................................................................................................... 150
Burst ROM Interface.......................................................................................................... 152
6.5.1 Overview............................................................................................................... 152
6.5.2 Basic Timing......................................................................................................... 152
6.5.3 Wait Control ......................................................................................................... 154
Idle Cycle........................................................................................................................... 155
6.6.1 Operation .............................................................................................................. 155
6.6.2 Pin States in Idle Cycle ......................................................................................... 158
Bus Release........................................................................................................................ 159
6.7.1 Overview............................................................................................................... 159
6.7.2 Operation .............................................................................................................. 159
6.7.3 Pin States in External Bus Released State............................................................. 160
6.7.4 Transition Timing ................................................................................................. 161
6.7.5 Usage Note............................................................................................................ 162
Bus Arbitration................................................................................................................... 162
6.8.1 Overview............................................................................................................... 162
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REJ09B0189-0400
6.8.2 Operation .............................................................................................................. 162
6.8.3 Bus Transfer Timing ............................................................................................. 163
6.8.4 External Bus Release Usage Note......................................................................... 163
6.9 Resets and the Bus Controller ............................................................................................ 164
6.10 External Module Expansion Function................................................................................ 164
6.10.1 Overview............................................................................................................... 164
6.10.2 Pin Configuration.................................................................................................. 165
6.10.3 Register Configuration.......................................................................................... 165
6.10.4 Interrupt Request Input Pin Select Register 0 (IPINSEL0)................................... 166
6.10.5 External Module Connection Output Pin Select Register (OPINSEL) ................. 168
6.10.6 Module Stop Control Register B (MSTPCRB)..................................................... 170
6.10.7 Basic Timing......................................................................................................... 171
6.10.8 Notes on Use of External Module Extended Functions ........................................ 172
Section 7 DMA Controller................................................................................ 173
7.1
7.2
7.3
7.4
7.5
Overview............................................................................................................................ 173
7.1.1 Features................................................................................................................. 173
7.1.2 Block Diagram ...................................................................................................... 174
7.1.3 Overview of Functions.......................................................................................... 175
7.1.4 Pin Configuration.................................................................................................. 177
7.1.5 Register Configuration.......................................................................................... 178
Register Descriptions (1) (Short Address Mode) ............................................................... 179
7.2.1 Memory Address Register (MAR)........................................................................ 180
7.2.2 I/O Address Register (IOAR) ............................................................................... 180
7.2.3 Execute Transfer Count Register (ETCR) ............................................................ 181
7.2.4 DMA Control Register (DMACR)........................................................................ 182
7.2.5 DMA Band Control Register (DMABCR)............................................................ 186
Register Descriptions (2) (Full Address Mode) ................................................................. 191
7.3.1 Memory Address Register (MAR)........................................................................ 191
7.3.2 I/O Address Register (IOAR) ............................................................................... 191
7.3.3 Execute Transfer Count Register (ETCR) ............................................................ 192
7.3.4 DMA Control Register (DMACR)........................................................................ 194
7.3.5 DMA Band Control Register (DMABCR)............................................................ 198
Register Descriptions (3).................................................................................................... 204
7.4.1 DMA Write Enable Register (DMAWER) ........................................................... 204
7.4.2 DMA Terminal Control Register (DMATCR)...................................................... 207
7.4.3 Module Stop Control Register A (MSTPCRA) .................................................... 208
Operation............................................................................................................................ 209
7.5.1 Transfer Modes ..................................................................................................... 209
7.5.2 Sequential Mode ................................................................................................... 211
7.5.3 Idle Mode.............................................................................................................. 214
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REJ09B0189-0400
7.6
7.7
7.5.4 Repeat Mode ......................................................................................................... 217
7.5.5 Normal Mode........................................................................................................ 221
7.5.6 Block Transfer Mode ............................................................................................ 224
7.5.7 DMAC Activation Sources ................................................................................... 230
7.5.8 Basic DMAC Bus Cycles...................................................................................... 232
7.5.9 DMAC Bus Cycles (Dual Address Mode)............................................................ 233
7.5.10 DMAC Multi-Channel Operation ......................................................................... 240
7.5.11 Relation between the DMAC, External Bus Requests, and the DTC ................... 242
7.5.12 NMI Interrupts and DMAC .................................................................................. 243
7.5.13 Forced Termination of DMAC Operation............................................................. 244
7.5.14 Clearing Full Address Mode................................................................................. 245
Interrupts............................................................................................................................ 246
Usage Notes ....................................................................................................................... 247
Section 8 Data Transfer Controller (DTC) ........................................................251
8.1
8.2
8.3
Overview............................................................................................................................ 251
8.1.1 Features................................................................................................................. 251
8.1.2 Block Diagram...................................................................................................... 252
8.1.3 Register Configuration.......................................................................................... 253
Register Descriptions ......................................................................................................... 254
8.2.1 DTC Mode Register A (MRA) ............................................................................. 254
8.2.2 DTC Mode Register B (MRB).............................................................................. 256
8.2.3 DTC Source Address Register (SAR)................................................................... 257
8.2.4 DTC Destination Address Register (DAR)........................................................... 257
8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 258
8.2.6 DTC Transfer Count Register B (CRB)................................................................ 258
8.2.7 DTC Enable Register (DTCER) ........................................................................... 259
8.2.8 DTC Vector Register (DTVECR)......................................................................... 260
8.2.9 Module Stop Control Register A (MSTPCRA) .................................................... 261
Operation ........................................................................................................................... 262
8.3.1 Overview............................................................................................................... 262
8.3.2 Activation Sources................................................................................................ 264
8.3.3 DTC Vector Table ................................................................................................ 265
8.3.4 Location of Register Information in Address Space ............................................. 268
8.3.5 Normal Mode........................................................................................................ 269
8.3.6 Repeat Mode ......................................................................................................... 270
8.3.7 Block Transfer Mode ............................................................................................ 271
8.3.8 Chain Transfer ...................................................................................................... 273
8.3.9 Operation Timing.................................................................................................. 274
8.3.10 Number of DTC Execution States ........................................................................ 275
8.3.11 Procedures for Using DTC.................................................................................... 277
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REJ09B0189-0400
8.4
8.5
8.3.12 Examples of Use of the DTC ................................................................................ 278
Interrupts ............................................................................................................................ 280
Usage Notes ....................................................................................................................... 280
Section 9 I/O Ports ............................................................................................ 281
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
Overview............................................................................................................................ 281
Port 1 .............................................................................................................................. 285
9.2.1 Overview............................................................................................................... 285
9.2.2 Register Configuration.......................................................................................... 286
9.2.3 Pin Functions ........................................................................................................ 288
Port 3 .............................................................................................................................. 296
9.3.1 Overview............................................................................................................... 296
9.3.2 Register Configuration.......................................................................................... 297
9.3.3 Pin Functions ........................................................................................................ 302
Port 4 .............................................................................................................................. 304
9.4.1 Overview............................................................................................................... 304
9.4.2 Register Configuration.......................................................................................... 304
9.4.3 Pin Functions ........................................................................................................ 307
Port 7 .............................................................................................................................. 308
9.5.1 Overview............................................................................................................... 308
9.5.2 Register Configuration.......................................................................................... 309
9.5.3 Pin Functions ........................................................................................................ 312
Port 9 .............................................................................................................................. 314
9.6.1 Overview............................................................................................................... 314
9.6.2 Register Configuration.......................................................................................... 314
9.6.3 Pin Functions ........................................................................................................ 315
Port A .............................................................................................................................. 315
9.7.1 Overview............................................................................................................... 315
9.7.2 Register Configuration.......................................................................................... 316
9.7.3 Pin Functions ........................................................................................................ 319
9.7.4 MOS Input Pull-Up Function................................................................................ 321
Port B .............................................................................................................................. 322
9.8.1 Overview............................................................................................................... 322
9.8.2 Register Configuration.......................................................................................... 323
9.8.3 Pin Functions ........................................................................................................ 325
9.8.4 MOS Input Pull-Up Function................................................................................ 329
Port C .............................................................................................................................. 330
9.9.1 Overview............................................................................................................... 330
9.9.2 Register Configuration.......................................................................................... 331
9.9.3 Pin Functions in Each Mode ................................................................................. 333
9.9.4 MOS Input Pull-Up Function................................................................................ 336
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REJ09B0189-0400
9.10 Port D .............................................................................................................................. 337
9.10.1 Overview............................................................................................................... 337
9.10.2 Register Configuration.......................................................................................... 338
9.10.3 Pin Functions in Each Mode ................................................................................. 340
9.10.4 MOS Input Pull-Up Function................................................................................ 341
9.11 Port E .............................................................................................................................. 342
9.11.1 Overview............................................................................................................... 342
9.11.2 Register Configuration.......................................................................................... 343
9.11.3 Pin Functions in Each Mode ................................................................................. 345
9.11.4 MOS Input Pull-Up Function................................................................................ 346
9.12 Port F .............................................................................................................................. 348
9.12.1 Overview............................................................................................................... 348
9.12.2 Register Configuration.......................................................................................... 349
9.12.3 Pin Functions ........................................................................................................ 351
9.13 Port G .............................................................................................................................. 353
9.13.1 Overview............................................................................................................... 353
9.13.2 Register Configuration.......................................................................................... 354
9.13.3 Pin Functions ........................................................................................................ 356
9.14 Handling of Unused Pins ................................................................................................... 358
Section 10 16-Bit Timer Pulse Unit (TPU) .......................................................359
10.1 Overview............................................................................................................................ 359
10.1.1 Features................................................................................................................. 359
10.1.2 Block Diagram...................................................................................................... 363
10.1.3 Pin Configuration.................................................................................................. 364
10.1.4 Register Configuration.......................................................................................... 365
10.2 Register Descriptions ......................................................................................................... 366
10.2.1 Timer Control Register (TCR).............................................................................. 366
10.2.2 Timer Mode Register (TMDR) ............................................................................. 370
10.2.3 Timer I/O Control Register (TIOR) ...................................................................... 372
10.2.4 Timer Interrupt Enable Register (TIER) ............................................................... 379
10.2.5 Timer Status Register (TSR)................................................................................. 381
10.2.6 Timer Counter (TCNT)......................................................................................... 385
10.2.7 Timer General Register (TGR) ............................................................................. 385
10.2.8 Timer Start Register (TSTR) ................................................................................ 386
10.2.9 Timer Synchro Register (TSYR) .......................................................................... 387
10.2.10 Module Stop Control Register A (MSTPCRA) .................................................... 388
10.3 Interface to Bus Master ...................................................................................................... 389
10.3.1 16-Bit Registers .................................................................................................... 389
10.3.2 8-Bit Registers ...................................................................................................... 389
10.4 Operation ........................................................................................................................... 391
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10.4.1 Overview............................................................................................................... 391
10.4.2 Basic Functions..................................................................................................... 392
10.4.3 Synchronous Operation......................................................................................... 399
10.4.4 Buffer Operation ................................................................................................... 401
10.4.5 PWM Modes ......................................................................................................... 405
10.4.6 Phase Counting Mode ........................................................................................... 411
10.5 Interrupts ............................................................................................................................ 416
10.5.1 Interrupt Sources and Priorities............................................................................. 416
10.5.2 DTC and DMAC Activation ................................................................................. 417
10.6 Operation Timing............................................................................................................... 418
10.6.1 Input/Output Timing ............................................................................................. 418
10.6.2 Interrupt Signal Timing......................................................................................... 423
10.7 Usage Notes ....................................................................................................................... 427
Section 11 Watchdog Timer (WDT)................................................................. 437
11.1 Overview............................................................................................................................ 437
11.1.1 Features................................................................................................................. 437
11.1.2 Block Diagram ...................................................................................................... 438
11.1.3 Register Configuration.......................................................................................... 439
11.2 Register Descriptions ......................................................................................................... 440
11.2.1 Timer Counter (TCNT)......................................................................................... 440
11.2.2 Timer Control/Status Register (TCSR) ................................................................. 440
11.2.3 Reset Control/Status Register (RSTCSR) ............................................................. 442
11.2.4 Notes on Register Access...................................................................................... 444
11.3 Operation............................................................................................................................ 446
11.3.1 Watchdog Timer Operation .................................................................................. 446
11.3.2 Interval Timer Operation ...................................................................................... 447
11.3.3 Timing of Setting of Overflow Flag (OVF) .......................................................... 448
11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) .......................... 449
11.4 Interrupts ............................................................................................................................ 449
11.5 Usage Notes ....................................................................................................................... 450
11.5.1 Contention between Timer Counter (TCNT) Write and Increment ...................... 450
11.5.2 Changing Value of CKS2 to CKS0....................................................................... 450
11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................. 451
11.5.4 Internal Reset in Watchdog Timer Mode.............................................................. 451
11.5.5 OVF Flag Clear Operation in Interval Timer Mode.............................................. 451
Section 12 Serial Communication Interface (SCI) ........................................... 453
12.1 Overview............................................................................................................................ 453
12.1.1 Features................................................................................................................. 453
12.1.2 Block Diagram ...................................................................................................... 455
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12.2
12.3
12.4
12.5
12.1.3 Pin Configuration.................................................................................................. 457
12.1.4 Register Configuration.......................................................................................... 458
Register Descriptions ......................................................................................................... 459
12.2.1 Receive Shift Register (RSR) ............................................................................... 459
12.2.2 Receive Data Register (RDR) ............................................................................... 459
12.2.3 Transmit Shift Register (TSR) .............................................................................. 460
12.2.4 Transmit Data Register (TDR).............................................................................. 460
12.2.5 Serial Mode Register (SMR) ................................................................................ 461
12.2.6 Serial Control Register (SCR)............................................................................... 464
12.2.7 Serial Status Register (SSR) ................................................................................. 467
12.2.8 Bit Rate Register (BRR) ....................................................................................... 472
12.2.9 Smart Card Mode Register (SCMR) ..................................................................... 480
12.2.10 Serial Extended Mode Register 0 (SEMR0) ......................................................... 481
12.2.11 Module Stop Control Register B (MSTPCRB)..................................................... 486
Operation ........................................................................................................................... 487
12.3.1 Overview............................................................................................................... 487
12.3.2 Operation in Asynchronous Mode ........................................................................ 490
12.3.3 Multiprocessor Communication Function............................................................. 501
12.3.4 Operation in Clocked Synchronous Mode ............................................................ 509
SCI Interrupts..................................................................................................................... 518
Usage Notes ....................................................................................................................... 520
Section 13 D/A Converter .................................................................................531
13.1 Overview............................................................................................................................ 531
13.1.1 Features................................................................................................................. 531
13.1.2 Block Diagram...................................................................................................... 532
13.1.3 Pin Configuration.................................................................................................. 533
13.1.4 Register Configuration.......................................................................................... 533
13.2 Register Descriptions ......................................................................................................... 534
13.2.1 D/A Data Register 0 (DADR0)............................................................................. 534
13.2.2 D/A Control Register (DACR) ............................................................................. 534
13.2.3 Module Stop Control Register C (MSTPCRC)..................................................... 535
13.3 Operation ........................................................................................................................... 536
Section 14 RAM ................................................................................................539
14.1 Overview............................................................................................................................ 539
14.1.1 Block Diagram...................................................................................................... 539
14.1.2 Register Configuration.......................................................................................... 540
14.2 Register Descriptions ......................................................................................................... 540
14.2.1 System Control Register (SYSCR) ....................................................................... 540
14.3 Operation ........................................................................................................................... 541
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14.4 Usage Note......................................................................................................................... 541
Section 15 ROM ............................................................................................... 543
15.1 Overview............................................................................................................................ 543
15.1.1 Block Diagram ...................................................................................................... 543
15.1.2 Register Configuration.......................................................................................... 544
15.2 Register Descriptions ......................................................................................................... 544
15.2.1 Mode Control Register (MDCR) .......................................................................... 544
15.3 Operation............................................................................................................................ 545
15.4 Overview of Flash Memory ............................................................................................... 546
15.4.1 Features................................................................................................................. 546
15.4.2 Block Diagram ...................................................................................................... 547
15.4.3 Mode Transitions .................................................................................................. 548
15.4.4 On-Board Programming Modes............................................................................ 549
15.4.5 Flash Memory Emulation in RAM ....................................................................... 551
15.4.6 Differences between Boot Mode and User Program Mode................................... 552
15.4.7 Block Divisions..................................................................................................... 553
15.5 Pin Configuration............................................................................................................... 554
15.6 Register Configuration ....................................................................................................... 555
15.7 Register Descriptions ......................................................................................................... 556
15.7.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 556
15.7.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 559
15.7.3 Erase Block Register 1 (EBR1)............................................................................. 560
15.7.4 Erase Block Register 2 (EBR2)............................................................................. 560
15.7.5 RAM Emulation Register (RAMER).................................................................... 561
15.7.6 Serial Control Register X (SCRX) ........................................................................ 563
15.8 On-Board Programming Modes ......................................................................................... 564
15.8.1 Boot Mode ............................................................................................................ 564
15.8.2 User Program Mode.............................................................................................. 569
15.9 Programming/Erasing Flash Memory ................................................................................ 571
15.9.1 Program Mode ...................................................................................................... 571
15.9.2 Program-Verify Mode........................................................................................... 572
15.9.3 Erase Mode ........................................................................................................... 574
15.9.4 Erase-Verify Mode................................................................................................ 574
15.10 Protection ........................................................................................................................... 576
15.10.1 Hardware Protection ............................................................................................. 576
15.10.2 Software Protection............................................................................................... 577
15.10.3 Error Protection..................................................................................................... 578
15.11 Flash Memory Emulation in RAM..................................................................................... 580
15.12 Interrupt Handling when Programming/Erasing Flash Memory........................................ 582
15.13 Flash Memory Programmer Mode ..................................................................................... 582
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15.13.1 Socket Adapter Pin Correspondence Diagram...................................................... 583
15.13.2 Programmer Mode Operation ............................................................................... 585
15.13.3 Memory Read Mode ............................................................................................. 586
15.13.4 Auto-Program Mode ............................................................................................. 590
15.13.5 Auto-Erase Mode.................................................................................................. 592
15.13.6 Status Read Mode ................................................................................................. 594
15.13.7 Status Polling ........................................................................................................ 595
15.13.8 Programmer Mode Transition Time ..................................................................... 596
15.13.9 Notes on Memory Programming........................................................................... 597
15.14 Flash Memory and Power-Down States............................................................................. 597
15.14.1 Note on Power-Down States ................................................................................. 598
15.15 Flash Memory Programming and Erasing Precautions...................................................... 598
15.16 Note on Switching from F-ZTAT Version to Masked ROM Version ............................... 604
Section 16 Clock Pulse Generator .....................................................................605
16.1 Overview............................................................................................................................ 605
16.1.1 Block Diagram...................................................................................................... 605
16.1.2 Register Configuration.......................................................................................... 606
16.2 Register Descriptions ......................................................................................................... 606
16.2.1 System Clock Control Register (SCKCR) ............................................................ 606
16.2.2 Low-Power Control Register (LPWRCR) ............................................................ 607
16.3 System Clock Oscillator..................................................................................................... 609
16.3.1 Connecting a Crystal Resonator............................................................................ 609
16.3.2 External Clock Input............................................................................................. 611
16.4 Duty Adjustment Circuit.................................................................................................... 615
16.5 Medium-Speed Clock Divider ........................................................................................... 615
16.6 Bus Master Clock Selection Circuit................................................................................... 615
16.7 Note on Crystal Resonator ................................................................................................. 615
Section 17 Power-Down Modes ........................................................................617
17.1 Overview............................................................................................................................ 617
17.1.1 Register Configuration.......................................................................................... 620
17.2 Register Descriptions ......................................................................................................... 620
17.2.1 Standby Control Register (SBYCR) ..................................................................... 620
17.2.2 System Clock Control Register (SCKCR) ............................................................ 622
17.2.3 Module Stop Control Register (MSTPCR) ........................................................... 623
17.3 Medium-Speed Mode......................................................................................................... 624
17.4 Sleep Mode ........................................................................................................................ 625
17.4.1 Sleep Mode ........................................................................................................... 625
17.4.2 Clearing Sleep Mode............................................................................................. 625
17.5 Module Stop Mode ............................................................................................................ 626
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17.5.1 Module Stop Mode ............................................................................................... 626
17.5.2 Usage Notes .......................................................................................................... 628
17.6 Software Standby Mode..................................................................................................... 628
17.6.1 Software Standby Mode........................................................................................ 628
17.6.2 Clearing Software Standby Mode ......................................................................... 629
17.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode.... 629
17.6.4 Software Standby Mode Application Example..................................................... 630
17.6.5 Usage Notes .......................................................................................................... 631
17.7 Hardware Standby Mode.................................................................................................... 632
17.7.1 Hardware Standby Mode ...................................................................................... 632
17.7.2 Hardware Standby Mode Timing.......................................................................... 632
17.8 φ Clock Output Disabling Function ................................................................................... 633
Section 18 Electrical Characteristics ................................................................ 635
18.1
18.2
18.3
18.4
Absolute Maximum Ratings .............................................................................................. 635
Power Supply Voltage and Operating Frequency Range ................................................... 636
DC Characteristics ............................................................................................................. 637
AC Characteristics ............................................................................................................. 642
18.4.1 Clock Timing ........................................................................................................ 642
18.4.2 Control Signal Timing .......................................................................................... 644
18.4.3 Bus Timing ........................................................................................................... 646
18.4.4 Timing of On-Chip Supporting Modules.............................................................. 653
18.4.5 DMAC Timing...................................................................................................... 656
18.5 D/A Convervion Characteristics ........................................................................................ 657
18.6 Flash Memory Characteristics............................................................................................ 658
18.7 Usage Note......................................................................................................................... 659
Appendix A Instruction Set .............................................................................. 661
A.1
A.2
A.3
A.4
A.5
A.6
Instruction List ................................................................................................................... 661
Instruction Codes ............................................................................................................... 685
Operation Code Map.......................................................................................................... 699
Number of States Required for Instruction Execution ....................................................... 703
Bus States during Instruction Execution ............................................................................ 717
Condition Code Modification ............................................................................................ 731
Appendix B Internal I/O Register ..................................................................... 737
B.1
B.2
Addresses ........................................................................................................................... 737
Functions............................................................................................................................ 744
Appendix C I/O Port Block Diagrams .............................................................. 827
C.1
Port 1 Block Diagrams....................................................................................................... 827
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C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10
C.11
C.12
Port 3 Block Diagrams....................................................................................................... 831
Port 4 Block Diagram ........................................................................................................ 835
Port 7 Block Diagrams....................................................................................................... 836
Port 9 Block Diagram ........................................................................................................ 841
Port A Block Diagrams ...................................................................................................... 842
Port B Block Diagram........................................................................................................ 846
Port C Block Diagram........................................................................................................ 847
Port D Block Diagram........................................................................................................ 848
Port E Block Diagram ........................................................................................................ 849
Port F Block Diagrams....................................................................................................... 850
Port G Block Diagrams ...................................................................................................... 856
Appendix D Pin States.......................................................................................861
D.1
Port States in Each Processing State .................................................................................. 861
Appendix E Timing of Transition to and Recovery
from Hardware Standby Mode ......................................................865
E.1
E.2
Timing of Transition to Hardware Standby Mode ............................................................. 865
Timing of Recovery from Hardware Standby Mode.......................................................... 865
Appendix F Product Code Lineup .....................................................................867
Appendix G Package Dimensions .....................................................................869
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Figures
Section 1 Overview
Figure 1.1 H8S/2214 Group Internal Block Diagram................................................................... 5
Figure 1.2 H8S/2214 Group Pin Arrangement
(TFP-100B, TFP-100BV, TFP-100G, TFP-100GV: Top View)................................. 6
Figure 1.3 H8S/2214 Group Pin Arrangement
(BP-112, BP-112V, TBP-112A, TBP-112AV: Top View) ......................................... 7
Section 2 CPU
Figure 2.1 CPU Operating Modes .............................................................................................. 20
Figure 2.2 Exception Vector Table (Normal Mode)................................................................... 21
Figure 2.3 Stack Structure in Normal Mode............................................................................... 22
Figure 2.4 Exception Vector Table (Advanced Mode)............................................................... 23
Figure 2.5 Stack Structure in Advanced Mode........................................................................... 24
Figure 2.6 Memory Map............................................................................................................. 25
Figure 2.7 CPU Registers ........................................................................................................... 26
Figure 2.8 Usage of General Registers ....................................................................................... 27
Figure 2.9 Stack .......................................................................................................................... 28
Figure 2.10 General Register Data Formats (1)............................................................................ 31
Figure 2.11 General Register Data Formats (2)............................................................................ 32
Figure 2.12 Memory Data Formats............................................................................................... 33
Figure 2.13 Instruction Formats (Examples) ................................................................................ 47
Figure 2.14 Branch Address Specification in Memory Indirect Mode ......................................... 52
Figure 2.15 Processing States ....................................................................................................... 56
Figure 2.16 State Transitions ........................................................................................................ 57
Figure 2.17 Stack Structure after Exception Handling (Examples) .............................................. 60
Figure 2.18 On-Chip Memory Access Cycle................................................................................ 62
Figure 2.19 Pin States during On-Chip Memory Access.............................................................. 63
Figure 2.20 On-Chip Supporting Module Access Cycle .............................................................. 64
Figure 2.21 Pin States during On-Chip Supporting Module Access............................................. 65
Figure 2.22 Flowchart for Access Methods for Registers that Include Write-Only Bits .............. 69
Section 3 MCU Operating Modes
Figure 3.1 Memory Map in Each Operating Mode in the H8S/2214.......................................... 78
Section 4 Exception Handling
Figure 4.1 Exception Sources ..................................................................................................... 80
Figure 4.2 Reset Sequence (Modes 2 and 3: Not available in the H8S/2214) ............................ 84
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Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Reset Sequence (Mode 4).......................................................................................... 85
Interrupt Sources and Number of Interrupts.............................................................. 87
Stack Status after Exception Handling
(Normal Modes: Not available in the H8S/2214)...................................................... 89
Stack Status after Exception Handling (Advanced Modes) ...................................... 89
Operation when SP Value Is Odd.............................................................................. 90
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller...................................................................... 92
Figure 5.2 Block Diagram of Interrupts IRQn.......................................................................... 100
Figure 5.3 Timing of Setting IRQnF ........................................................................................ 100
Figure 5.4 Block Diagram of Interrupt Control Operation ....................................................... 105
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0.. 108
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2.. 110
Figure 5.7 Interrupt Exception Handling.................................................................................. 111
Figure 5.8 Contention between Interrupt Generation and Disabling ........................................ 114
Figure 5.9 Interrupt Control for DTC and DMAC ................................................................... 116
Section 6 Bus Controller
Figure 6.1 Block Diagram of Bus Controller ........................................................................... 120
Figure 6.2 Overview of Area Divisions.................................................................................... 134
Figure 6.3 CSn Signal Output Timing (n = 0 to 7) ................................................................... 138
Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space) ........................... 139
Figure 6.5 Access Sizes and Data Alignment Control (16-Bit Access Space) ......................... 140
Figure 6.6 Bus Timing for 8-Bit 2-State Access Space ............................................................ 142
Figure 6.7 Bus Timing for 8-Bit 3-State Access Space ............................................................ 143
Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (Even Address Byte Access)............ 144
Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (Odd Address Byte Access) ............. 145
Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (Word Access) ................................. 146
Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (Even Address Byte Access)............ 147
Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (Odd Address Byte Access) ............. 148
Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (Word Access) ................................. 149
Figure 6.14 Example of Wait State Insertion Timing................................................................. 151
Figure 6.15 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1).................. 153
Figure 6.16 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0).................. 154
Figure 6.17 Example of Idle Cycle Operation (1) ...................................................................... 155
Figure 6.18 Example of Idle Cycle Operation (2) ...................................................................... 156
Figure 6.19 Relationship between Chip Select (CS) and Read (RD) ......................................... 157
Figure 6.20 Bus-Released State Transition Timing.................................................................... 161
Figure 6.21 Multichip Block Diagram........................................................................................ 165
Figure 6.22 Timing of External Module Area Access by DTC .................................................. 171
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Figure 6.23 On-Chip ROM Valid Extended Mode (Mode 6) Address Map............................... 172
Section 7 DMA Controller
Figure 7.1 Block Diagram of DMAC ....................................................................................... 174
Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)............................. 204
Figure 7.3 Operation in Sequential Mode................................................................................. 212
Figure 7.4 Example of Sequential Mode Setting Procedure ..................................................... 213
Figure 7.5 Operation in Idle Mode ........................................................................................... 215
Figure 7.6 Example of Idle Mode Setting Procedure................................................................ 216
Figure 7.7 Operation in Repeat mode....................................................................................... 219
Figure 7.8 Example of Repeat Mode Setting Procedure........................................................... 220
Figure 7.9 Operation in Normal Mode ..................................................................................... 222
Figure 7.10 Example of Normal Mode Setting Procedure.......................................................... 223
Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 0) ................................................. 225
Figure 7.12 Operation in Block Transfer Mode (BLKDIR = 1) ................................................. 226
Figure 7.13 Operation Flow in Block Transfer Mode ................................................................ 228
Figure 7.14 Example of Block Transfer Mode Setting Procedure.............................................. 229
Figure 7.15 Example of DMA Transfer Bus Timing.................................................................. 232
Figure 7.16 Example of Short Address Mode Transfer .............................................................. 233
Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer .......................................... 234
Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer.......................................... 235
Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer .......................... 236
Figure 7.20 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer................. 237
Figure 7.21 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer..... 238
Figure 7.22 Example of DREQ Level Activated Normal Mode Transfer .................................. 239
Figure 7.23 Example of DREQ Level Activated Block Transfer Mode Transfer ...................... 240
Figure 7.24 Example of Multi-Channel Transfer ....................................................................... 241
Figure 7.25 Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt ..................................................................................................... 243
Figure 7.26 Example of Procedure for Forcibly Terminating DMAC Operation....................... 244
Figure 7.27 Example of Procedure for Clearing Full Address Mode ......................................... 245
Figure 7.28 Block Diagram of Transfer End/Transfer Break Interrupt ...................................... 246
Figure 7.29 DMAC Register Update Timing ............................................................................. 247
Figure 7.30 Contention between DMAC Register Update and CPU Read................................. 248
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ........................................................................................... 252
Figure 8.2 Flowchart of DTC Operation................................................................................... 262
Figure 8.3 Block Diagram of DTC Activation Source Control ................................................ 265
Figure 8.4 Correspondence between DTC Vector Address and Register Information ............. 268
Figure 8.5 Location of Register Information in Address Space................................................ 268
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Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10
Figure 8.11
Memory Mapping in Normal Mode ........................................................................ 269
Memory Mapping in Repeat Mode ......................................................................... 270
Memory Mapping in Block Transfer Mode ............................................................ 272
Chain Transfer Memory Map.................................................................................. 273
DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................... 274
DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2)...................................... 274
Figure 8.12 DTC Operation Timing (Example of Chain Transfer) ............................................ 275
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Functions ................................................................................................ 285
Figure 9.2 Port 3 Pin Functions ................................................................................................ 296
Figure 9.3 Port 4 Pin Functions ................................................................................................ 304
Figure 9.4 Port 7 Pin Functions ................................................................................................ 308
Figure 9.5 Port 9 Pin Functions ................................................................................................ 314
Figure 9.6 Port A Pin Functions ............................................................................................... 315
Figure 9.7 Port B Pin Functions ............................................................................................... 322
Figure 9.8 Port C Pin Functions ............................................................................................... 330
Figure 9.9 Port C Pin Functions (Modes 4 and 5) .................................................................... 333
Figure 9.10 Port C Pin Functions (Mode 6)................................................................................ 334
Figure 9.11 Port C Pin Functions (Mode 7)................................................................................ 335
Figure 9.12 Port D Pin Functions ............................................................................................... 337
Figure 9.13 Port D Pin Functions (Modes 4 to 6)....................................................................... 340
Figure 9.14 Port D Pin Functions (Mode 7) ............................................................................... 341
Figure 9.15 Port E Pin Functions................................................................................................ 342
Figure 9.16 Port E Pin Functions (Modes 4 to 6) ....................................................................... 345
Figure 9.17 Port E Pin Functions (Mode 7)................................................................................ 346
Figure 9.18 Port F Pin Functions................................................................................................ 348
Figure 9.19 Port G Pin Functions ............................................................................................... 353
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1 Block Diagram of TPU ........................................................................................... 363
Figure 10.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ...................... 389
Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)].................. 390
Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] ............. 390
Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] ....... 390
Figure 10.6 Example of Counter Operation Setting Procedure .................................................. 392
Figure 10.7 Free-Running Counter Operation ............................................................................ 393
Figure 10.8 Periodic Counter Operation..................................................................................... 394
Figure 10.9 Example Of Setting Procedure For Waveform Output By Compare Match ........... 395
Figure 10.10 Example of 0 Output/1 Output Operation ............................................................... 396
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Figure 10.11 Example of Toggle Output Operation ..................................................................... 396
Figure 10.12 Example of Input Capture Operation Setting Procedure ......................................... 397
Figure 10.13 Example of Input Capture Operation....................................................................... 398
Figure 10.14 Example of Synchronous Operation Setting Procedure .......................................... 399
Figure 10.15 Example of Synchronous Operation........................................................................ 400
Figure 10.16 Compare Match Buffer Operation........................................................................... 401
Figure 10.17 Input Capture Buffer Operation............................................................................... 402
Figure 10.18 Example of Buffer Operation Setting Procedure..................................................... 402
Figure 10.19 Example of Buffer Operation (1) ............................................................................ 403
Figure 10.20 Example of Buffer Operation (2) ............................................................................ 404
Figure 10.21 Example of PWM Mode Setting Procedure ............................................................ 407
Figure 10.22 Example of PWM Mode Operation (1) ................................................................... 408
Figure 10.23 Example of PWM Mode Operation (2) ................................................................... 409
Figure 10.24 Example of PWM Mode Operation (3) ................................................................... 410
Figure 10.25 Example of Phase Counting Mode Setting Procedure............................................. 411
Figure 10.26 Example of Phase Counting Mode 1 Operation ...................................................... 412
Figure 10.27 Example of Phase Counting Mode 2 Operation ...................................................... 413
Figure 10.28 Example of Phase Counting Mode 3 Operation ...................................................... 414
Figure 10.29 Example of Phase Counting Mode 4 Operation ...................................................... 415
Figure 10.30 Count Timing in Internal Clock Operation.............................................................. 418
Figure 10.31 Count Timing in External Clock Operation ............................................................ 418
Figure 10.32 Output Compare Output Timing ............................................................................. 419
Figure 10.33 Input Capture Input Signal Timing.......................................................................... 420
Figure 10.34 Counter Clear Timing (Compare Match) ................................................................ 421
Figure 10.35 Counter Clear Timing (Input Capture) .................................................................... 421
Figure 10.36 Buffer Operation Timing (Compare Match) ........................................................... 422
Figure 10.37 Buffer Operation Timing (Input Capture) ............................................................... 422
Figure 10.38 TGI Interrupt Timing (Compare Match) ................................................................. 423
Figure 10.39 TGI Interrupt Timing (Input Capture) ..................................................................... 424
Figure 10.40 TCIV Interrupt Setting Timing................................................................................ 425
Figure 10.41 TCIU Interrupt Setting Timing................................................................................ 425
Figure 10.42 Timing for Status Flag Clearing by CPU ................................................................ 426
Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC Activation ................................. 426
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .................. 427
Figure 10.45 Contention between TCNT Write and Clear Operations......................................... 428
Figure 10.46 Contention between TCNT Write and Increment Operations ................................. 429
Figure 10.47 Contention between TGR Write and Compare Match............................................. 430
Figure 10.48 Contention between Buffer Register Write and Compare Match............................ 431
Figure 10.49 Contention between TGR Read and Input Capture ................................................. 432
Figure 10.50 Contention between TGR Write and Input Capture ................................................ 433
Figure 10.51 Contention between Buffer Register Write and Input Capture................................ 434
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Figure 10.52 Contention between Overflow and Counter Clearing ............................................. 435
Figure 10.53 Contention between TCNT Write and Overflow .................................................... 436
Section 11
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Watchdog Timer (WDT)
Block Diagram of WDT.......................................................................................... 438
Format of Data Written to TCNT and TCSR (Example of WDT0) ........................ 444
Format of Data Written to RSTCSR (Example of WDT0) ..................................... 445
Operation in Watchdog Timer Mode ...................................................................... 446
Operation in Interval Timer Mode .......................................................................... 447
Timing of OVF Setting ........................................................................................... 448
Timing of WOVF Setting........................................................................................ 449
Contention between TCNT Write and Increment.................................................... 450
Section 12
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Serial Communication Interface (SCI)
Block Diagram of SCI0........................................................................................... 455
Block Diagram of SCI1 and SCI2 ........................................................................... 456
Examples of Base Clock when Average Transfer Rate Is Selected (1)................... 484
Examples of Base Clock when Average Transfer Rate Is Selected (2)................... 485
Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 490
Figure 12.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode). 492
Figure 12.7 Sample SCI Initialization Flowchart ....................................................................... 493
Figure 12.8 Sample Serial Transmission Flowchart ................................................................... 494
Figure 12.9 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 496
Figure 12.10 Sample Serial Reception Data Flowchart (1) .......................................................... 497
Figure 12.11 Sample Serial Reception Data Flowchart (2) .......................................................... 498
Figure 12.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 500
Figure 12.13 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ............................................ 502
Figure 12.14 Sample Multiprocessor Serial Transmission Flowchart .......................................... 503
Figure 12.15 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)................................ 505
Figure 12.16 Sample Multiprocessor Serial Reception Flowchart (1).......................................... 506
Figure 12.17 Sample Multiprocessor Serial Reception Flowchart (2).......................................... 507
Figure 12.18 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)................................ 508
Figure 12.19 Data Format in Synchronous Communication ........................................................ 509
Figure 12.20 Sample SCI Initialization Flowchart ....................................................................... 511
Figure 12.21 Sample Serial Transmission Flowchart ................................................................... 512
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Figure 12.22 Example of SCI Operation in Transmission............................................................ 514
Figure 12.23 Sample Serial Reception Flowchart ........................................................................ 515
Figure 12.24 Example of SCI Operation in Reception ................................................................. 516
Figure 12.25 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ........ 517
Figure 12.26 Receive Data Sampling Timing in Asynchronous Mode ........................................ 522
Figure 12.27 Example of Clocked Synchronous Transmission by DTC ...................................... 524
Figure 12.28 Sample Flowchart for Mode Transition during Transmission................................. 525
Figure 12.29 Asynchronous Transmission Using Internal Clock ................................................. 526
Figure 12.30 Synchronous Transmission Using Internal Clock ................................................... 526
Figure 12.31 Sample Flowchart for Mode Transition during Reception ...................................... 527
Figure 12.32 Operation when Switching from SCK Pin Function to Port Pin Function .............. 528
Figure 12.33 Operation when Switching from SCK Pin Function to Port Pin Function
(Example of Preventing Low-Level Output)........................................................... 529
Section 13 D/A Converter
Figure 13.1 Block Diagram of D/A Converter ........................................................................... 532
Figure 13.2 Example of D/A Converter Operation..................................................................... 537
Section 14 RAM
Figure 14.1 Block Diagram of RAM .......................................................................................... 539
Section 15 ROM
Figure 15.1 Block Diagram of ROM .......................................................................................... 543
Figure 15.2 Block Diagram of Flash Memory............................................................................ 547
Figure 15.3 Flash Memory State Transitions.............................................................................. 548
Figure 15.4 Boot Mode............................................................................................................... 549
Figure 15.5 User Program Mode ................................................................................................ 550
Figure 15.6 Reading Overlap RAM Data in User Mode or User Program Mode....................... 551
Figure 15.7 Writing Overlap RAM Data in User Program Mode............................................... 552
Figure 15.8 Flash Memory Blocks ............................................................................................. 553
Figure 15.9 System Configuration in Boot Mode....................................................................... 565
Figure 15.10 Boot Mode Execution Procedure............................................................................. 566
Figure 15.11 Automatic SCI Bit Rate Adjustment ....................................................................... 567
Figure 15.12 RAM Areas in Boot Mode ...................................................................................... 568
Figure 15.13 User Program Mode Execution Procedure .............................................................. 570
Figure 15.14 Program/Program-Verify Flowchart........................................................................ 573
Figure 15.15 Erase/Erase-Verify Flowchart ................................................................................. 575
Figure 15.16 Flash Memory State Transitions.............................................................................. 579
Figure 15.17 Flowchart for Flash Memory Emulation in RAM ................................................... 580
Figure 15.18 Example of RAM Overlap Operation...................................................................... 581
Figure 15.19 On-Chip ROM Memory Map.................................................................................. 583
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Figure 15.20 Socket Adapter Pin Correspondence Diagram ........................................................ 584
Figure 15.21 Timing Waveforms for Memory Read after Memory Write ................................... 587
Figure 15.22 Timing Waveforms in Transition from Memory Read Mode to Another Mode..... 588
Figure 15.23 CE and OE Enable State Read Timing Waveforms ................................................ 589
Figure 15.24 CE and OE Clock System Read Timing Waveforms .............................................. 589
Figure 15.25 Auto-Program Mode Timing Waveforms ............................................................... 591
Figure 15.26 Auto-Erase Mode Timing Waveforms .................................................................... 593
Figure 15.27 Status Read Mode Timing Waveforms ................................................................... 594
Figure 15.28 Oscillation Stabilization Time, Boot Program Transfer Time,
and Power-Down Sequence..................................................................................... 596
Figure 15.29 Power-On/Off Timing (Boot Mode) ....................................................................... 601
Figure 15.30 Power-On/Off Timing (User Program Mode) ......................................................... 602
Figure 15.31 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode).............................. 603
Section 16
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.4
Figure 16.5
Figure 16.6
Figure 16.7
Figure 16.8
Clock Pulse Generator
Block Diagram of Clock Pulse Generator ............................................................... 605
Connection of Crystal Resonator (Example)........................................................... 609
Crystal Resonator Equivalent Circuit...................................................................... 609
Example of Incorrect Board Design ........................................................................ 610
External Clock Input (Examples) ............................................................................ 611
External Clock Input Timing................................................................................... 612
Example of External Clock Switching Circuit ........................................................ 613
Example of External Clock Switchover Timing...................................................... 614
Section 17
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Power-Down Modes
Mode Transitions..................................................................................................... 619
Medium-Speed Mode Transition and Clearance Timing ........................................ 625
Software Standby Mode Application Example ....................................................... 631
Hardware Standby Mode Timing (Example) .......................................................... 633
Section 18
Figure 18.1
Figure 18.2
Figure 18.3
Figure 18.4
Figure 18.5
Figure 18.6
Figure 18.7
Figure 18.8
Figure 18.9
Electrical Characteristics
Power Supply Voltage and Operating Ranges ........................................................ 636
Output Load Circuit ................................................................................................ 642
System Clock Timing.............................................................................................. 643
Oscillator Settling Timing ....................................................................................... 643
Reset Input Timing.................................................................................................. 644
Interrupt Input Timing............................................................................................. 645
Basic Bus Timing/Two-State Access ...................................................................... 648
Basic Bus Timing/Three-State Access .................................................................... 649
Basic Bus Timing/Three-State Access with One Wait State................................... 650
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Figure 18.10 Burst ROM Access Timing/Two-State Access ....................................................... 651
Figure 18.11 External Bus Release Timing .................................................................................. 652
Figure 18.12 I/O Port Input/Output Timing.................................................................................. 654
Figure 18.13 TPU Input/Output Timing ....................................................................................... 654
Figure 18.14 TPU Clock Input Timing......................................................................................... 654
Figure 18.15 SCK Clock Input Timing ........................................................................................ 655
Figure 18.16 SCI Input/Output Timing/Clock Synchronous Mode.............................................. 655
Figure 18.17 DMAC TEND Output Timing................................................................................. 656
Figure 18.18 DMAC DREQ Output Timing ................................................................................ 656
Appendix A Instruction Set
Figure A.1 Address Bus, RD, HWR, and LWR Timing
(8-Bit Bus, Three-State Access, No Wait States) .................................................... 718
Appendix C I/O Port Block Diagrams
Figure C.1 Port 1 Block Diagram (Pins P10 and P11) .............................................................. 827
Figure C.2 Port 1 Block Diagram (Pins P12 and P13) .............................................................. 828
Figure C.3 Port 1 Block Diagram (Pins P14 and P16) .............................................................. 829
Figure C.4 Port 1 Block Diagram (Pins P15 and P17) .............................................................. 830
Figure C.5 Port 3 Block Diagram (Pins P30 and P33) .............................................................. 831
Figure C.6 Port 3 Block Diagram (Pins P31 and P34) .............................................................. 832
Figure C.7 Port 3 Block Diagram (Pins P32 and P35) .............................................................. 833
Figure C.8 Port 3 Block Diagram (Pin P36).............................................................................. 834
Figure C.9 Port 4 Block Diagram (Pins P40 to P44, P46, and P47).......................................... 835
Figure C.10 Port 4 Block Diagram (Pin P45).............................................................................. 835
Figure C.11 Port 7 Block Diagram (Pins P70 and P71) .............................................................. 836
Figure C.12 Port 7 Block Diagram (Pins P72 and P73) .............................................................. 837
Figure C.13 Port 7 Block Diagram (Pin P74).............................................................................. 838
Figure C.14 Port 7 Block Diagram (Pins P75 and P76) .............................................................. 839
Figure C.15 Port 7 Block Diagram (Pin P77).............................................................................. 840
Figure C.16 Port 9 Block Diagram (Pin P96).............................................................................. 841
Figure C.17 Port A Block Diagram (Pin PA0) ............................................................................ 842
Figure C.18 Port A Block Diagram (Pin PA1) ............................................................................ 843
Figure C.19 Port A Block Diagram (Pin PA2) ............................................................................ 844
Figure C.20 Port A Block Diagram (Pin PA3) ............................................................................ 845
Figure C.21 Port B Block Diagram (Pins PB0 to PB7) ............................................................... 846
Figure C.22 Port C Block Diagram (Pins PC0 to PC7) ............................................................... 847
Figure C.23 Port D Block Diagram (Pins PD0 to PD7) .............................................................. 848
Figure C.24 Port E Block Diagram (Pins PE0 to PE7)................................................................ 849
Figure C.25 Port F Block Diagram (Pin PF0) ............................................................................. 850
Figure C.26 Port F Block Diagram (Pin PF1) ............................................................................. 851
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Figure C.27
Figure C.28
Figure C.29
Figure C.30
Figure C.31
Figure C.32
Figure C.33
Figure C.34
Port F Block Diagram (Pin PF2) ............................................................................. 852
Port F Block Diagram (Pin PF3) ............................................................................. 853
Port F Block Diagram (Pins PF4 to PF6) ................................................................ 854
Port F Block Diagram (Pin PF7) ............................................................................. 855
Port G Block Diagram (Pin PG0)............................................................................ 856
Port G Block Diagram (Pin PG1)............................................................................ 857
Port G Block Diagram (Pins PG2 and PG3) ........................................................... 858
Port G Block Diagram (Pin PG4)............................................................................ 859
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Figure E.1 Timing of Transition to Hardware Standby Mode .................................................. 865
Figure E.2 Timing of Recovery from Hardware Standby Mode............................................... 865
Appendix G Package Dimensions
Figure G.1 TFP-100B, TFP-100BV Package Dimensions ........................................................ 869
Figure G.2 TFP-100G, TFP-100GA Package Dimensions........................................................ 870
Figure G.3 TBP-112A, TBP-112AV Package Dimensions....................................................... 871
Figure G.4 BP-112, BP-112V Package Dimensions ................................................................. 872
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Tables
Section 1 Overview
Table 1.1
Overview ..................................................................................................................... 2
Table 1.2
Pin Functions in Each Operating Mode....................................................................... 8
Table 1.3
Pin Functions............................................................................................................. 12
Section 2 CPU
Table 2.1
Instruction Classification........................................................................................... 34
Table 2.2
Combinations of Instructions and Addressing Modes............................................... 35
Table 2.3
Instructions Classified by Function ........................................................................... 38
Table 2.4
Addressing Modes..................................................................................................... 49
Table 2.5
Absolute Address Access Ranges ............................................................................. 50
Table 2.6
Effective Address Calculation................................................................................... 53
Table 2.7
Exception Handling Types and Priority .................................................................... 58
Section 3 MCU Operating Modes
Table 3.1
MCU Operating Mode Selection............................................................................... 71
Table 3.2
MCU Registers .......................................................................................................... 72
Table 3.3
Relationship between RES and MRES pin Values and Type of Reset...................... 74
Table 3.4
Pin Functions in Each Mode...................................................................................... 77
Section 4 Exception Handling
Table 4.1
Exception Handling Types and Priority .................................................................... 79
Table 4.2
Exception Vector Table............................................................................................. 81
Table 4.3
Reset Types ............................................................................................................... 82
Table 4.4
Status of CCR and EXR after Trace Exception Handling ......................................... 86
Table 4.5
Status of CCR and EXR after Trap Instruction Exception Handling ........................ 88
Section 5 Interrupt Controller
Interrupt Controller Pins............................................................................................ 93
Table 5.1
Table 5.2
Interrupt Controller Registers.................................................................................... 93
Table 5.3
Correspondence between Interrupt Sources and IPR Settings................................... 95
Table 5.4
Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................. 102
Table 5.5
Interrupt Control Modes.......................................................................................... 104
Table 5.6
Interrupts Selected in Each Interrupt Control Mode (1) .......................................... 105
Table 5.7
Interrupts Selected in Each Interrupt Control Mode (2) .......................................... 106
Table 5.8
Operations and Control Signal Functions in Each Interrupt Control Mode ............ 106
Table 5.9
Interrupt Response Times........................................................................................ 112
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Table 5.10
Table 5.11
Number of States in Interrupt Handling Routine Execution Statuses ..................... 113
Interrupt Source Selection and Clearing Control .................................................... 118
Section 6 Bus Controller
Bus Controller Pins ................................................................................................. 121
Table 6.1
Table 6.2
Bus Controller Registers ......................................................................................... 122
Table 6.3
Bus Specifications for Each Area (Basic Bus Interface) ......................................... 136
Table 6.4
Data Buses Used and Valid Strobes ........................................................................ 141
Table 6.5
Pin States in Idle Cycle ........................................................................................... 158
Table 6.6
Pin States in Bus Released State ............................................................................. 160
Table 6.7
External Module Expansion Function Pins ............................................................. 165
Table 6.8
Bus Controller Registers ......................................................................................... 166
Section 7 DMA Controller
Table 7.1
Overview of DMAC Functions (Short Address Mode)........................................... 175
Table 7.2
Overview of DMAC Functions (Full Address Mode)............................................. 176
Table 7.3
DMAC Pins ............................................................................................................. 177
Table 7.4
DMAC Registers ..................................................................................................... 178
Table 7.5
Short Address Mode and Full Address Mode
(For 1 Channel: Example of Channel 0).................................................................. 179
Table 7.6
DMAC Transfer Modes .......................................................................................... 209
Table 7.7
Register Functions in Sequential Mode................................................................... 211
Table 7.8
Register Functions in Idle Mode ............................................................................. 214
Table 7.9
Register Functions in Repeat Mode ........................................................................ 217
Table 7.10 Register Functions in Normal Mode ....................................................................... 221
Table 7.11 Register Functions in Block Transfer Mode ........................................................... 224
Table 7.12 DMAC Activation Sources ..................................................................................... 230
Table 7.13 DMAC Channel Priority Order ............................................................................... 241
Table 7.14 Interrupt Source Priority Order ............................................................................... 246
Section 8 Data Transfer Controller (DTC)
DTC Registers ......................................................................................................... 253
Table 8.1
Table 8.2
DTC Functions ........................................................................................................ 263
Table 8.3
Activation Source and DTCER Clearance .............................................................. 264
Table 8.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................. 266
Table 8.5
Register Information in Normal Mode .................................................................... 269
Table 8.6
Register Information in Repeat Mode ..................................................................... 270
Table 8.7
Register Information in Block Transfer Mode ........................................................ 271
Table 8.8
DTC Execution Statuses.......................................................................................... 275
Table 8.9
Number of States Required for Each Execution Status ........................................... 276
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Section 9 I/O Ports
H8S/2214 Group Port Functions ............................................................................. 282
Table 9.1
Table 9.2
Port 1 Registers ....................................................................................................... 286
Table 9.3
Port 1 Pin Functions ................................................................................................ 288
Table 9.4
Port 3 Registers ....................................................................................................... 297
Table 9.5
Port 3 Pin Functions ................................................................................................ 302
Table 9.6
Port 4 Registers ....................................................................................................... 304
Table 9.7
Port 7 Registers ....................................................................................................... 309
Table 9.8
Port 7 Pin Functions ................................................................................................ 312
Table 9.9
Port 9 Registers ....................................................................................................... 314
Table 9.10 Port A Registers ...................................................................................................... 316
Table 9.11 Port A Pin Functions ............................................................................................... 319
Table 9.12 MOS Input Pull-Up States (Port A)......................................................................... 321
Table 9.13 Port B Registers....................................................................................................... 323
Table 9.14 Port B Pin Functions................................................................................................ 325
Table 9.15 MOS Input Pull-Up States (Port B)......................................................................... 329
Table 9.16 Port C Registers....................................................................................................... 331
Table 9.17 MOS Input Pull-Up States (Port C)......................................................................... 336
Table 9.18 Port D Registers ...................................................................................................... 338
Table 9.19 MOS Input Pull-Up States (Port D)......................................................................... 341
Table 9.20 Port E Registers ....................................................................................................... 343
Table 9.21 MOS Input Pull-Up States (Port E) ......................................................................... 347
Table 9.22 Port F Registers ....................................................................................................... 349
Table 9.23 Port F Pin Functions ................................................................................................ 351
Table 9.24 Port G Registers ...................................................................................................... 354
Table 9.25 Port G Pin Functions ............................................................................................... 356
Table 9.26 Handling of Unused Input Pins ............................................................................... 358
Section 10
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.10
Table 10.11
16-Bit Timer Pulse Unit (TPU)
TPU Functions......................................................................................................... 361
TPU Pins ................................................................................................................. 364
TPU Registers ......................................................................................................... 365
TPU Clock Sources ................................................................................................. 368
Register Combinations in Buffer Operation............................................................ 401
PWM Output Registers and Output Pins................................................................. 406
Phase Counting Mode Clock Input Pins.................................................................. 411
Up/Down-Count Conditions in Phase Counting Mode 1 ........................................ 412
Up/Down-Count Conditions in Phase Counting Mode 2 ........................................ 413
Up/Down-Count Conditions in Phase Counting Mode 3 ........................................ 414
Up/Down-Count Conditions in Phase Counting Mode 4 ........................................ 415
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Table 10.12 Interrupt Sources and DMA Controller (DMAC) and Data Transfer (DTC)
Activation................................................................................................................ 416
Section 11 Watchdog Timer (WDT)
Table 11.1 WDT Registers........................................................................................................ 439
Section 12 Serial Communication Interface (SCI)
Table 12.1 SCI Pins................................................................................................................... 457
Table 12.2 SCI Registers........................................................................................................... 458
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) ................................... 473
Table 12.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ....................... 476
Table 12.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode, when ABCS = 0). 478
Table 12.6 Maximum Bit Rate with External Clock Input
(Asynchronous Mode, when ABCS = 0)................................................................ 479
Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)....... 479
Table 12.8 SMR Settings and Serial Transfer Format Selection............................................... 488
Table 12.9 SMR and SCR Settings and SCI Clock Source Selection ....................................... 488
Table 12.10 SMR0, SCR0, SEMR0 Settings and SCI Clock Source Selection (SCI0 Only) ..... 489
Table 12.11 Serial Transfer Formats (Asynchronous Mode) ...................................................... 491
Table 12.12 Receive Errors and Conditions for Occurrence....................................................... 500
Table 12.13 SCI Interrupt Sources .............................................................................................. 519
Table 12.14 State of SSR Status Flags and Transfer of Receive Data ....................................... 521
Section 13 D/A Converter
Table 13.1 Pin Configuration .................................................................................................... 533
Table 13.2 D/A Converter Registers ......................................................................................... 533
Section 14 RAM
Table 14.1 RAM Register ......................................................................................................... 540
Section 15 ROM
Table 15.1 ROM Register ......................................................................................................... 544
Table 15.2 Operating Modes and ROM Area (F-ZTAT Version and Masked ROM Version) 545
Table 15.3 Differences between Boot Mode and User Program Mode..................................... 552
Table 15.4 Pin Configuration .................................................................................................... 554
Table 15.5 Register Configuration ............................................................................................ 555
Table 15.6 Flash Memory Erase Blocks.................................................................................... 561
Table 15.7 Flash Memory Area Divisions ................................................................................ 562
Table 15.8 Setting On-Board Programming Modes.................................................................. 564
Table 15.9 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is
Possible ................................................................................................................... 567
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Table 15.10
Table 15.11
Table 15.12
Table 15.13
Table 15.14
Table 15.15
Table 15.16
Table 15.17
Table 15.18
Table 15.19
Table 15.20
Table 15.21
Table 15.22
Table 15.23
Table 15.24
Table 15.25
Hardware Protection................................................................................................ 576
Software Protection ................................................................................................. 577
Programmer Mode Pin Settings............................................................................... 583
Settings for Various Operating Modes In Programmer Mode................................. 585
Programmer Mode Commands................................................................................ 586
AC Characteristics in Transition to Memory Read Mode ....................................... 586
AC Characteristics in Transition from Memory Read Mode to Another Mode ...... 587
AC Characteristics in Memory Read Mode ............................................................ 588
AC Characteristics in Auto-Program Mode ............................................................ 591
AC Characteristics in Auto-Erase Mode ................................................................. 592
AC Characteristics in Status Read Mode ................................................................ 594
Status Read Mode Return Commands..................................................................... 595
Status Polling Output Truth Table........................................................................... 595
Stipulated Transition Times to Command Wait State ............................................. 596
Flash Memory Operating States .............................................................................. 597
Registers Present in F-ZTAT Version but Absent in Masked ROM Version ......... 604
Section 16 Clock Pulse Generator
Table 16.1 Clock Pulse Generator Register............................................................................... 606
Table 16.2 Damping Resistance Value...................................................................................... 609
Table 16.3 Crystal Resonator Parameters.................................................................................. 610
Table 16.4 External Clock Input Conditions ............................................................................. 612
Table 16.5 External Clock Input Conditions when the Duty Adjustment Circuit Is not Used .. 612
Section 17 Power-Down Modes
Table 17.1 LSI Internal States in Each Mode............................................................................ 618
Table 17.2 Power-Down Mode Registers.................................................................................. 620
Table 17.3 MSTP Bits and Corresponding On-Chip Supporting Modules ............................... 627
Table 17.4 Oscillation Stabilization Time Settings ................................................................... 630
Table 17.5 φ Pin State in Each Processing Mode ...................................................................... 633
Section 18 Electrical Characteristics
Table 18.1 Absolute Maximum Ratings.................................................................................... 635
Table 18.2 DC Characteristics (1) ............................................................................................. 637
Table 18.3 DC Characteristics (2) ............................................................................................. 639
Table 18.4 DC Characteristics (3) ............................................................................................. 640
Table 18.5 Permissible Output Currents.................................................................................... 641
Table 18.6 Clock Timing........................................................................................................... 642
Table 18.7 Control Signal Timing............................................................................................. 644
Table 18.8 Bus Timing.............................................................................................................. 646
Table 18.9 Timing of On-Chip Supporting Modules ................................................................ 653
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Table 18.10 DMAC Timing ........................................................................................................ 656
Table 18.11 D/A Conversion Characteristics .............................................................................. 657
Table 18.12 Flash Memory Characteristics................................................................................. 658
Appendix A Instruction Set
Table A.1 Data Transfer Instructions ....................................................................................... 663
Table A.2 Arithmetic Instructions............................................................................................ 666
Table A.3 Logical Instructions................................................................................................. 670
Table A.4 Shift Instructions ..................................................................................................... 671
Table A.5 Bit-Manipulation Instructions ................................................................................. 674
Table A.6 Branch Instructions ................................................................................................. 679
Table A.7 System Control Instructions .................................................................................... 682
Table A.8 Block Transfer Instructions ..................................................................................... 684
Table A.9 Instruction Codes..................................................................................................... 685
Table A.10 Operation Code Map (1) ......................................................................................... 699
Table A.11 Operation Code Map (2) ......................................................................................... 700
Table A.12 Operation Code Map (3) ......................................................................................... 701
Table A.13 Operation Code Map (4) ......................................................................................... 702
Table A.14 Number of States per Cycle..................................................................................... 704
Table A.15 Number of Cycles in Instruction Execution ............................................................ 705
Table A.16 Instruction Execution Cycles................................................................................... 719
Table A.17 Condition Code Modification.................................................................................. 732
Appendix D Pin States
Table D.1 I/O Port States in Each Processing State ................................................................. 861
Appendix F Product Code Lineup
H8S/2214 Product Code Lineup.............................................................................. 867
Table F.1
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Section 1 Overview
Section 1 Overview
1.1
Overview
The H8S/2214 Group is a microcomputer (MCU: microcomputer unit), built around the H8S/2000
CPU, employing Renesas' proprietary architecture, and equipped with the on-chip peripheral
functions necessary for system configuration.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip peripheral functions required for system configuration include DMA controller (DMAC)
data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer-pulse unit
(TPU), watchdog timer (WDT), serial communication interface (SCI), D/A converter, and I/O
ports.
The on-chip ROM is either flash memory (F-ZTAT™*) or masked ROM, with a capacity of 128
kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to
be accessed in one state. Instruction fetching has been speeded up, and processing speed increased.
Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or
external expansion mode.
The features of the H8S/2214 Group are shown in table 1.1.
Note: * F-ZTAT is a trademark of Renesas Technology, Corp.
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Section 1 Overview
Table 1.1
Overview
Item
Specification
CPU
•
General-register machine
⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
•
High-speed operation suitable for realtime control
⎯ Maximum clock rate 16 MHz
⎯ High-speed arithmetic operations (at 16-MHz operation)
8/16/32-bit register-register add/subtract : 62.5 ns
16 × 16-bit register-register multiply
: 1250 ns
32 ÷ 16-bit register-register divide
: 1250 ns
•
Instruction set suitable for high-speed operation
⎯ Sixty-five basic instructions
⎯ 8/16/32-bit move/arithmetic and logic instructions
⎯ Unsigned/signed multiply and divide instructions
⎯ Powerful bit-manipulation instructions
•
Two CPU operating modes
⎯ Normal mode
: 64-kbyte address space (not available in the
H8S/2214 Group)
⎯ Advanced mode : 16-Mbyte address space
Bus controller
DMA controller
(DMAC)
•
Address space divided into 8 areas, with bus specifications settable
independently for each area
•
Chip select output possible for each area
•
Choice of 8-bit or 16-bit access space for each area
•
2-state or 3-state access space can be designated for each area
•
Number of program wait states can be set for each area
•
Burst ROM directly connectable
•
External bus release function
•
Choice of short address mode or full address mode
•
Four channels in short address mode
Two channels in full address mode
•
Transfer possible in repeat mode, block transfer mode, etc.
•
Can be activated by internal interrupt
Rev.4.00 Sep. 18, 2008 Page 2 of 872
REJ09B0189-0400
Section 1 Overview
Item
Specification
Data transfer
controller (DTC)
•
Can be activated by internal interrupt or software
•
Multiple transfers or multiple types of transfer possible for one activation
source
•
Transfer possible in repeat mode, block transfer mode, etc.
•
Request can be sent to CPU for interrupt that activated DTC
•
3-channel 16-bit timer on-chip
•
Pulse I/O processing capability for up to 8 pins
•
Automatic 2-phase encoder count capability
Watchdog timer
(WDT) × 1 channel
•
Watchdog timer or interval timer selectable
Serial
communication
interface (SCI) × 3
channels (SCI0 to
SCI2)
•
Asynchronous mode or synchronous mode selectable
•
Multiprocessor communication function
D/A converter
•
Resolution: 8 bits
•
Output: 1 channel
I/O ports
•
72 I/O pins, 9 input-only pins
Memory
•
Flash memory or masked ROM: 128 kbytes
•
High-speed static RAM: 12 kbytes
•
Nine external interrupt pins (NMI, IRQ0 to IRQ7)
16-bit timer-pulse
unit (TPU)
Interrupt controller
Eight external expansion interrupt pins (EXIRQ7 to EXIRQ0)
Power-down state
•
31 internal interrupt sources
•
Eight priority levels settable
•
Medium-speed mode
•
Sleep mode
•
Module stop mode
•
Software standby mode
•
Hardware standby mode
Rev.4.00 Sep. 18, 2008 Page 3 of 872
REJ09B0189-0400
Section 1 Overview
Item
Specification
Operating modes
Four MCU operating modes
Clock pulse
generator
External Data Bus
CPU
Operating
Description
Mode Mode
On-Chip
ROM
Initial
Value
Maximum
Value
4
Advanced On-chip ROM disabled
expansion mode
Disabled
16 bits
16 bits
5
On-chip ROM disabled
expansion mode
Disabled
8 bits
16 bits
6
On-chip ROM enabled
expansion mode
Enabled
8 bits
16 bits
7
Single-chip mode
Enabled
—
Clock pulse generators
•
System clock pulse generator: 2 to 16 MHz
On-chip duty correction circuit
Packages
Product lineup
•
100-pin plastic TQFP (TFP-100B, TFP-100BV, TFP-100G, TFP-100GV)
•
112-pin plastic FBGA (BP-112, BP-112V, TBP-112A, TBP-112AV)
Model Name
Masked ROM
Version
F-ZTAT
Version
ROM/RAM
(Bytes)
HD6432214
HD64F2214
128 k/12 k
Package Code
TFP-100B, TFP-100BV,
TFP-100G, TFP-100GV,
TBP-112A, TBP-112AV,
BP-112, BP-112V
Note: Package codes ending in the letter V designate Pb-free products.
Rev.4.00 Sep. 18, 2008 Page 4 of 872
REJ09B0189-0400
Section 1 Overview
1.2
Internal Block Diagrams
Port A
P36 /EXIRQ7
P35 /SCK1/IRQ5
P34 /RxD1
P33 /TxD1
P32 /SCK0/IRQ4
P31 /RxD0
P30 /TxD0
Peripheral address bus
SCI0 (1 channel, High speed UART)
SCI1, 2 (2 channels)
RAM
(12 kB)
AVCC
Vref
AVSS
Port 7
P70 /DREQ0/CS4
P71 /DREQ1/CS5
P72 /TEND0/CS6
P73 /TEND1/CS7
P74/MRES/EXDTCE
P75/EXMS
P76/EXMSTP
P77
Port 4
Port 9
P96/DA0
RESERVE
Port 1
P40/ EXIRQ0
P41/ EXIRQ1
P42/ EXIRQ2
P43/ EXIRQ3
P44/ EXIRQ4
P45
P46/ EXIRQ5
P47/ EXIRQ6
D/A converter
(1 channel)
TPU (3 channels)
P10/TIOCA0 /A20
P11/TIOCB0 /A21
P12/TIOCC0/ TCLKA/A22
P13/TIOCD0/ TCLKB/A23
P14/TIOCA1/IRQ0
P15/TIOCB1/ TCLKC
P16/TIOCA2/IRQ1
P17/TIOCB2/TCLKD
Port G
Port B
Port F
ROM
(128 kB)
Peripheral data bus
WDT0
PG4 /CS0
PG3 /CS1
PG2 /CS2
PG1 /CS3/IRQ7
PG0 /IRQ6
PC7 /A7
PC6 /A6
PC5 /A5
PC4 /A4
PC3 /A3
PC2 /A2
PC1 /A1
PC0 /A0
DMAC
DTC
PF7 /φ
PF6 /AS
PF5 /RD
PF4 /HWR
PF3 /LWR/IRQ3
PF2 /WAIT
PF1 /BACK
PF0 /BREQ/IRQ2
PB7 /A15
PB6 /A14
PB5 /A13
PB4 /A12
PB3 / A11
PB2 /A10
PB1 /A9
PB0 /A8
Port C
Interrupt controller
PA3 /A19/SCK2
PA2 /A18/RxD2
PA1 /A17/TxD2
PA0 /A16
Port 3
H8S/2000 CPU
Bus controller
PE7 / D7
PE6 / D6
PE5/ D5
PE4/ D4
PE3/ D3
PE2/ D2
PE1/ D1
PE0/ D0
Port E
Internal address bus
Port D
Internal data bus
System
clock pulse
generator
MD2
MD1
MD0
EXTAL
XTAL
STBY
RES
NMI
FWE
PD7 / D15
PD6 / D14
PD5 / D13
PD4 / D12
PD3 / D11
PD2 / D10
PD1 / D9
PD0 / D8
VCC
VCC
VSS
VSS
RESERVE
VSS
Figures 1.1 shows internal block diagram of the H8S/2214.
Figure 1.1 H8S/2214 Group Internal Block Diagram
Rev.4.00 Sep. 18, 2008 Page 5 of 872
REJ09B0189-0400
Section 1 Overview
1.3
Pin Description
1.3.1
Pin Arrangements
TFP-100B
TFP-100BV
TFP-100G
TFP-100GV
(Top view)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P42/EXIRQ2
P43/EXIRQ3
P44/EXIRQ4
P45
P46/EXIRQ5
P47/EXIRQ6
P96/DA0
RESERVE
AVSS
P17/TIOCB2/TCLKD
P16/TIOCA2/IRQ1
P15/TIOCB1/TCLKC
P14/TIOCA1/IRQ0
P13/TIOCD0/TCLKB/A23
P12/TIOCC0/TCLKA/A22
P11/TIOCB0/A21
P10/TIOCA0/A20
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PE5/D5
PE6/D6
PE7/D7
PD0/D8
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
PD6/D14
PD7/D15
VCC
PC0/A0
VSS
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
PC6/A6
PC7/A7
PB0/A8
PB1/A9
PB2/A10
PB3/A11
P30/TxD0
P31/RxD0
P32/SCK0/IRQ4
P33/TxD1
P34/RxD1
P35/SCK1/IRQ5
P36/EXIRQ7
P77
P76/EXMSTP
P75/EXMS
P74/MRES/EXDTCE
P73/TEND1/CS7
P72/TEND0/CS6
P71/DREQ1/CS5
P70/DREQ0/CS4
PG0/IRQ6
PG1/CS3/IRQ7
PG2/CS2
PG3/CS1
PG4/CS0
PE0/D0
PE1/D1
PE2/D2
PE3/D3
PE4/D4
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PF0/BREQ/IRQ2
PF1/BACK
PF2/WAIT
PF3/LWR/IRQ3
PF4/HWR
PF5/RD
PF6/AS
PF7/φ
MD2
FWE
EXTAL
VSS
XTAL
VCC
STBY
NMI
RES
VSS
RESERVE
MD1
MD0
AVCC
Vref
P40/EXIRQ0
P41/EXIRQ1
Figures 1.2 and 1.3 show the pin arrangements of the H8S/2214.
Figure 1.2 H8S/2214 Group Pin Arrangement
(TFP-100B, TFP-100BV, TFP-100G, TFP-100GV: Top View)
Rev.4.00 Sep. 18, 2008 Page 6 of 872
REJ09B0189-0400
Section 1 Overview
11
10
INDEX
Reserve
PF1/
BACK
P30/TxD0 Reserve
9
P33/TxD1
P32/
SCK0/
IRQ4
8
P36/
EXIRQ7
P35/
SCK1/
IRQ5
7
P75/
EXMS
PF4/HWR
PF7/φ
EXTAL
XTAL
STBY
VSS
MD0
P40/
EXIRQ0
Reserve
PF2/
WAIT
PF5/RD
FWE
VSS
VCC
Reserve
AVCC
P41/
EXIRQ1
P42/
EXIRQ2
PF0/
BREQ/
IRQ2
PF3/
LWR/
IRQ3
MD2
VCC
NMI
MD1
Reserve
P43/
EXIRQ3
P45
VSS
RES
Vref
P44/
EXIRQ4
P46/
EXIRQ5
P96/DA0
P47/
EXIRQ6
Reserve
AVSS
AVSS
P17/
TIOCB2/
TCLKD
P14/
TIOCA1/
IRQ0
P16/
TIOCA2/
IRQ1
P15/
TIOCB1/
TCLKC
P10/
TIOCA0/
A20
P11/
TIOCB0/
A21
P13/
TIOCD0/
TCLKB/
A23
P12/
TIOCC0/
TCLKA/
A22
P34/RxD1 P31/RxD1 PF6/AS
P74/
P76/
MRES/
EXDTCE EXMSTP
6
P72/
TEND0/
CS6
5
PG0/
IRQ6
4
PG3/CS1
PE0/D0
PE2/D2
3
PE1/D1
PE3/D3
2
PE4/D4
1
P71/
DREQ1/
CS5
P73/
TEND1/
CS7
P77
BP-112
BP-112V
TBP-112
TBP-112V
(Top view)
P70/
DREQ0/
CS4
PG1/CS3/
PG2/CS2 PG4/CS0
IRQ7
PD5/D13
VSS
PC5/A5
PB6/A14
PA1/A17/ PA2/A18/ PA3/A19/
TxD2
RxD2
SCK2
Reserve
PD2/D10 PD6/D14
VCC
PC3/A3
PB0/A8
PB3/A11
PB7/A15
PA0/A16
PE5/D5
PD0/D8
PD3/D11
VCC
VSS
PC2/A2
PC6/A6
PB1/A9
PB4/A12
PB5/A13
Reserve
PE6/D6
PD1/D9
PD4/D12
PD7/D15
PC0/A0
PC1/A1
PC4/A4
PC7/A7
PB2/A10
Reserve
A
B
C
D
E
F
G
H
J
K
L
PE7/D7
Figure 1.3 H8S/2214 Group Pin Arrangement
(BP-112, BP-112V, TBP-112A, TBP-112AV: Top View)
Rev.4.00 Sep. 18, 2008 Page 7 of 872
REJ09B0189-0400
Section 1 Overview
1.3.2
Pin Functions in Each Operating Mode
Table 1.2 shows the pin functions of the H8S/2214 Group in each of the operating modes.
Table 1.2
Pin Functions in Each Operating Mode
Pin No.
Pin Name
TFP-100B,
TFP-100BV,
TFP-100G,
TFP-100GV
BP-112,
BP-112V,
TBP-112A,
TBP-112AV Mode 4
Mode 5
Mode 6
Mode 7
PROM
Mode*
1
B2
PE5/D5
PE5/D5
PE5/D5
PE5
NC
2
B1
PE6/D6
PE6/D6
PE6/D6
PE6
NC
3
D4
PE7/D7
PE7/D7
PE7/D7
PE7
NC
4
C2
D8
D8
D8
PD0
D0
5
C1
D9
D9
D9
PD1
D1
6
D3
D10
D10
D10
PD2
D2
7
D2
D11
D11
D11
PD3
D3
8
D1
D12
D12
D12
PD4
D4
9
E4
D13
D13
D13
PD5
D5
10
E3
D14
D14
D14
PD6
D6
11
E1
D15
D15
D15
PD7
D7
12
E2, F3
VCC
VCC
VCC
VCC
VCC
13
F1
A0
A0
PC0/A0
PC0
A0
14
F2, F4
VSS
VSS
VSS
VSS
VSS
15
G1
A1
A1
PC1/A1
PC1
A1
16
G2
A2
A2
PC2/A2
PC2
A2
17
G3
A3
A3
PC3/A3
PC3
A3
18
H1
A4
A4
PC4/A4
PC4
A4
19
G4
A5
A5
PC5/A5
PC5
A5
20
H2
A6
A6
PC6/A6
PC6
A6
21
J1
A7
A7
PC7/A7
PC7
A7
22
H3
PB0/A8
PB0/A8
PB0/A8
PB0
A8
23
J2
PB1/A9
PB1/A9
PB1/A9
PB1
OE
24
K1
PB2/A10
PB2/A10
PB2/A10
PB2
A10
Rev.4.00 Sep. 18, 2008 Page 8 of 872
REJ09B0189-0400
Section 1 Overview
Pin No.
Pin Name
TFP-100B,
TFP-100BV,
TFP-100G,
TFP-100GV
BP-112,
BP-112V,
TBP-112A,
TBP-112AV Mode 4
Mode 5
Mode 6
Mode 7
PROM
Mode*
25
J3
PB3/A11
PB3/A11
PB3/A11
PB3
A11
26
K2
PB4/A12
PB4/A12
PB4/A12
PB4
A12
27
L2
PB5/A13
PB5/A13
PB5/A13
PB5
A13
28
H4
PB6/A14
PB6/A14
PB6/A14
PB6
A14
29
K3
PB7/A15
PB7/A15
PB7/A15
PB7
A15
30
L3
PA0/A16
PA0/A16
PA0/A16
PA0
A16
31
J4
PA1/A17/TxD2
PA1/A17/TxD2
PA1/A17/TxD2
PA1/TxD2
VCC
32
K4
PA2/A18/RxD2
PA2/A18/RxD2
PA2/A18/RxD2
PA2/RxD2
VCC
33
L4
PA3/A19/SCK2
PA3/A19/SCK2
PA3/A19/SCK2
PA3/SCK2
34
H5
P10/TIOCA0/A20 P10/TIOCA0/A20 P10/TIOCA0/A20 P10/TIOCA0
NC
35
J5
P11/TIOCB0/A21 P11/TIOCB0/A21 P11/TIOCB0/A21 P11/TIOCB0
NC
36
L5
P12/TIOCC0/
TCLKA/A22
P12/TIOCC0/
TCLKA/A22
P12/TIOCC0/
TCLKA/A22
P12/TIOCC0/
TCLKA
NC
37
K5
P13/TIOCD0/
TCLKB/A23
P13/TIOCD0/
TCLKB/A23
P13/TIOCD0/
TCLKB/A23
P13/TIOCD0/
TCLKB
NC
38
J6
P14/TIOCA1/
IRQ0
P14/TIOCA1/
IRQ0
P14/TIOCA1/
IRQ0
P14/TIOCA1/
IRQ0
VSS
39
L6
P15/TIOCB1/
TCLKC
P15/TIOCB1/
TCLKC
P15/TIOCB1/
TCLKC
P15/TIOCB1/
TCLKC
NC
40
K6
P16/TIOCA2/
IRQ1
P16/TIOCA2/
IRQ1
P16/TIOCA2/
IRQ1
P16/TIOCA2/
IRQ1
VSS
41
H6
P17/TIOCB2/
TCLKD
P17/TIOCB2/
TCLKD
P17/TIOCB2/
TCLKD
P17/TIOCB2/
TCLKD
NC
42
K7, L7
AVSS
AVSS
AVSS
AVSS
VSS
43
J7
Reserve
Reserve
Reserve
Reserve
NC
44
L8
P96/DA0
P96/DA0
P96/DA0
P96/DA0
NC
45
H7
P47/EXIRQ6
P47/EXIRQ6
P47/EXIRQ6
P47/EXIRQ6
NC
46
K8
P46/EXIRQ5
P46/EXIRQ5
P46/EXIRQ5
P46/EXIRQ5
NC
47
L9
P45
P45
P45
P45
NC
48
J8
P44/EXIRQ4
P44/EXIRQ4
P44/EXIRQ4
P44/EXIRQ4
NC
49
K9
P43/EXIRQ3
P43/EXIRQ3
P43/EXIRQ3
P43/EXIRQ3
NC
NC
Rev.4.00 Sep. 18, 2008 Page 9 of 872
REJ09B0189-0400
Section 1 Overview
Pin No.
Pin Name
TFP-100B,
TFP-100BV,
TFP-100G,
TFP-100GV
BP-112,
BP-112V,
TBP-112A,
TBP-112AV Mode 4
Mode 5
Mode 6
Mode 7
PROM
Mode*
50
L10
P42/EXIRQ2
P42/EXIRQ2
P42/EXIRQ2
P42/EXIRQ2
NC
51
K10
P41/EXIRQ1
P41/EXIRQ1
P41/EXIRQ1
P41/EXIRQ1
NC
52
K11
P40/EXIRQ0
P40/EXIRQ0
P40/EXIRQ0
P40/EXIRQ0
NC
53
H8
Vref
Vref
Vref
Vref
VCC
54
J10
AVCC
AVCC
AVCC
AVCC
VCC
55
J11
MD0
MD0
MD0
MD0
VSS
56
H9
MD1
MD1
MD1
MD1
VSS
57
H10
Reserve
Reserve
Reserve
Reserve
NC
58
H11
VSS
VSS
VSS
VSS
NC
59
G8
RES
RES
RES
RES
VPP
60
G9
NMI
NMI
NMI
NMI
A9
61
G11
STBY
STBY
STBY
STBY
VSS
62
F9, G10
VCC
VCC
VCC
VCC
VCC
63
F11
XTAL
XTAL
XTAL
XTAL
NC
64
F8, F10
VSS
VSS
VSS
VSS
VSS
65
E11
EXTAL
EXTAL
EXTAL
EXTAL
NC
66
E10
FWE
FWE
FWE
FWE
FWE
67
E9
MD2
MD2
MD2
MD2
VSS
68
D11
PF7/φ
PF7/φ
PF7/φ
PF7/φ
NC
69
E8
AS
AS
AS
PF6
NC
70
D10
RD
RD
RD
PF5
NC
71
C11
HWR
HWR
HWR
PF4
NC
72
D9
PF3/LWR/IRQ3
PF3/LWR/IRQ3
PF3/LWR/IRQ3
PF3/IRQ3
VCC
73
C10
PF2/WAIT
PF2/WAIT
PF2/WAIT
PF2
CE
74
B11
PF1/BACK
PF1/BACK
PF1/BACK
PF1
PGM
75
C9
PF0/BREQ/IRQ2 PF0/BREQ/IRQ2 PF0/BREQ/IRQ2 PF0/IRQ2
VCC
76
A10
P30/TxD0
P30/TxD0
P30/TxD0
P30/TxD0
NC
77
D8
P31/RxD1
P31/RxD1
P31/RxD1
P31/RxD1
NC
78
B9
P32/SCK0/IRQ4
P32/SCK0/IRQ4
P32/SCK0/IRQ4
P32/SCK0/IRQ4
NC
Rev.4.00 Sep. 18, 2008 Page 10 of 872
REJ09B0189-0400
Section 1 Overview
Pin No.
Pin Name
TFP-100B,
TFP-100BV,
TFP-100G,
TFP-100GV
BP-112,
BP-112V,
TBP-112A,
TBP-112AV Mode 4
Mode 5
Mode 6
Mode 7
PROM
Mode*
79
A9
P33/TxD1
P33/TxD1
P33/TxD1
P33/TxD1
NC
80
C8
P34/RxD1
P34/RxD1
P34/RxD1
P34/RxD1
NC
81
B8
P35/SCK1/IRQ5
P35/SCK1/IRQ5
P35/SCK1/IRQ5
P35/SCK1/IRQ5
NC
82
A8
P36/EXIRQ7
P36/EXIRQ7
P36/EXIRQ7
P36/EXIRQ7
NC
83
D7
P77
P77
P77
P77
NC
84
C7
P76/EXMSTP
P76/EXMSTP
P76/EXMSTP
P76/EXMSTP
NC
85
A7
P75/EXMS
P75/EXMS
P75/EXMS
P75/EXMS
NC
86
B7
P74/MRES/
EXDTCE
P74/MRES/
EXDTCE
P74/MRES/
EXDTCE
P74/MRES/
EXDTCE
NC
87
C6
P73/TEND1/CS7 P73/TEND1/CS7 P73/TEND1/CS7 P73/TEND1
NC
88
A6
P72/TEND0/CS6 P72/TEND0/CS6 P72/TEND0/CS6 P72/TEND0
NC
89
B6
P71/DREQ1/CS5 P71/DREQ1/CS5 P71/DREQ1/CS5 P71/DREQ1
NC
90
D6
P70/DREQ0/CS4 P70/DREQ0/CS4 P70/DREQ0/CS4 P70/DREQ0
NC
91
A5
PG0/IRQ6
NC
92
B5
PG1/CS3/IRQ7
PG1/CS3/IRQ7
PG1/CS3/IRQ7
PG1/IRQ7
NC
93
C5
PG2/CS2
PG2/CS2
PG2/CS2
PG2
NC
94
A4
PG3/CS1
PG3/CS1
PG3/CS1
PG3
NC
95
D5
PG4/CS0
PG4/CS0
PG4/CS0
PG4
NC
96
B4
PE0/D0
PE0/D0
PE0/D0
PE0
NC
97
A3
PE1/D1
PE1/D1
PE1/D1
PE1
NC
98
C4
PE2/D2
PE2/D2
PE2/D2
PE2
NC
99
B3
PE3/D3
PE3/D3
PE3/D3
PE3
NC
100
A2
PE4/D4
PE4/D4
PE4/D4
PE4
VSS
—
A1, A11, B10, Reserve
C3, J9, L1,
L11
Reserve
Reserve
Reserve
Reserve
Note:
*
PG0/IRQ6
PG0/IRQ6
PG0/IRQ6
NC pins must be left open.
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Section 1 Overview
1.3.3
Pin Functions
Table 1.3 outlines the pin functions of the H8S/2214.
Table 1.3
Pin Functions
Type
Symbol
I/O
Name and Function
Power
VCC
Input
Power supply: For connection to the power supply. All VCC
pins should be connected to the system power supply.
VSS
Input
Ground: For connection to ground (0 V). All VSS pins should
be connected to the system power supply (0 V).
XTAL
Input
Crystal: Connects to a crystal oscillator. See section 16,
Clock Pulse Generator, for typical connection diagrams for
a crystal oscillator and external clock input.
EXTAL
Input
External clock: Connects to a crystal oscillator. The EXTAL
pin can also input an external clock. See section 16, Clock
Pulse Generator, for typical connection diagrams for a
crystal oscillator and external clock input.
φ
Output System clock: Supplies the system clock to an external
device.
MD2 to
MD0
Input
Clock
Operating
mode control
Mode pins: These pins set the operating mode. The relation
between the settings of pins MD2 to MD0 and the operating
mode is shown below. These pins should not be changed
while the H8S/2214 is operating. Except when the mode is
changed, the mode pins (MD2 to MD0) must be pulled
down or pulled up to a fixed level until powering off.
MD2
MD1
MD0
Operating Mode
0
0
0
—
1
—
1
0
—
1
—
0
Mode 4
1
Mode 5
0
Mode 6
1
Mode 7
1
0
1
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Section 1 Overview
Type
Symbol
I/O
Name and Function
System control
RES
Input
Reset input: When this pin is driven low, the chip enters the
power-on reset state.
MRES
Input
Manual reset: When this pin is driven low, the chip enters
the manual reset state.
STBY
Input
Standby: When this pin is driven low, a transition is made to
hardware standby mode.
BREQ
Input
Bus request: Used by an external bus master to issue a bus
request to the H8S/2214.
BACK
Output Bus request acknowledge: Indicates that the bus has been
released to an external bus master.
FWE
Input
Flash write enable: Enables/disables flash memory
programming.
NMI
Input
Nonmaskable interrupt: Requests a nonmaskable interrupt.
When this pin is not used, it should be fixed high.
IRQ7 to
IRQ0
Input
Interrupt request 7 to 0: These pins request a maskable
interrupt.
Address bus
A23 to
A0
Output Address bus: These pins output an address.
Data bus
D15 to
D0
I/O
Bus control
CS7 to
CS0
Output Chip select: Signals for selecting areas 7 to 0.
AS
Output Address strobe: When this pin is low, it indicates that
address output on the address bus is enabled.
RD
Output Read: When this pin is low, it indicates that the external
address space can be read.
HWR
Output High write: A strobe signal that writes to external space and
indicates that the upper half (D15 to D8) of the data bus is
enabled.
LWR
Output Low write: A strobe signal that writes to external space and
indicates that the lower half (D7 to D0) of the data bus is
enabled.
WAIT
Input
Interrupts
External
expansion
EXIRQ7 to Input
EXIRQ0
EXMS
Data bus: These pins constitute a bidirectional data bus.
Wait: Requests insertion of a wait state in the bus cycle
when accessing external 3-state address space.
External expansion interrupt request 7 to 0: Input pins for
interrupt requests from external modules.
Output External expansion module select: Select signal for external
modules.
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Section 1 Overview
Type
Symbol
I/O
External
expansion
EXDTC
Output External expansion DTC transfer end: DTC data transfer
end signal for EXIRQ7 to EXIRQ0 input.
EXMSTP
Output External expansion module stop: Module stop signal for
external modules.
DREQ1,
DREQ0
Input
TEND1,
TEND0
Output DMA transfer end 1 and 0: These pins indicate the end of
DMAC data transfer.
DMA controller
(DMAC)
16-bit timerTCLKD to
pulse unit (TPU) TCLKA
Serial
communication
interface (SCI)
D/A converter
Name and Function
DMA request 1 and 0: These pins request DMAC activation.
Input
Clock input D to A: These pins input an external clock.
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0
I/O
Input capture/output compare match A0 to D0: The TGR0A
to TGR0D input capture input or output compare output, or
PWM output pins.
TIOCA1,
TIOCB1
I/O
Input capture/output compare match A1 and B1: The
TGR1A and TGR1B input capture input or output compare
output, or PWM output pins.
TIOCA2,
TIOCB2
I/O
Input capture/output compare match A2 and B2: The
TGR2A and TGR2B input capture input or output compare
output, or PWM output pins.
TxD2,
TxD1,
TxD0
Output Transmit data: Data output pins.
RxD2,
RxD1,
RxD0
Input
Receive data: Data input pins.
SCK2,
SCK1
SCK0
I/O
Serial clock: Clock I/O pins.
DA0
Output Analog output: D/A converter analog output pins.
AVCC
Input
Analog power supply: This is the power supply pin for the
D/A converter. When the D/A converter is not used, this pin
should be connected to the system power supply (VCC).
AVSS
Input
Analog ground: This is the ground pin for the D/A converter.
This pin should be connected to the system power supply
(0 V).
Vref
Input
Analog reference power supply: This is the reference
voltage input pin for the D/A converter. When the D/A
converter is not used, this pin should be connected to the
system power supply (VCC).
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Section 1 Overview
Type
Symbol
I/O
Name and Function
I/O ports
P17 to
P10
I/O
Port 1: An 8-bit I/O port. Input or output can be designated
for each bit by means of the port 1 data direction register
(P1DDR).
P36 to
P30
I/O
Port 3: A 7-bit I/O port. Input or output can be designated for
each bit by means of the port 3 data direction register
(P3DDR).
P47 to
P40
Input
Port 4: An 8-bit input port.
P77 to
P70
I/O
Port 7: An 8-bit I/O port. Input or output can be designated
for each bit by means of the port 7 data direction register
(P7DDR).
P96
Input
Port 9: A 1-bit input port.
PA3 to
PA0
I/O
Port A: A 4-bit I/O port. Input or output can be designated
for each bit by means of the port A data direction register
(PADDR).
PB7 to
PB0
I/O
Port B: An 8-bit I/O port. Input or output can be designated
for each bit by means of the port B data direction register
(PBDDR).
PC7 to
PC0
I/O
Port C: An 8-bit I/O port. Input or output can be designated
for each bit by means of the port C data direction register
(PCDDR).
PD7 to
PD0
I/O
Port D: An 8-bit I/O port. Input or output can be designated
for each bit by means of the port D data direction register
(PDDDR).
PE7 to
PE0
I/O
Port E: An 8-bit I/O port. Input or output can be designated
for each bit by means of the port E data direction register
(PEDDR).
PF7 to
PF0
I/O
Port F: An 8-bit I/O port. Input or output can be designated
for each bit by means of the port F data direction register
(PFDDR).
PG4 to
PG0
I/O
Port G: A 5-bit I/O port. Input or output can be designated
for each bit by means of the port G data direction register
(PGDDR).
RESERVE
RESERVE —
Reserved pins: These pins should be open and should not
be connected to any device.
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Section 2 CPU
Section 2 CPU
2.1
Overview
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is
ideal for realtime control.
2.1.1
Features
The H8S/2000 CPU has the following features.
• Upward-compatible with H8/300 and H8/300H CPUs
⎯ Can execute H8/300 and H8/300H object programs
• General-register architecture
⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit
registers)
• Sixty-five basic instructions
⎯ 8/16/32-bit arithmetic and logic instructions
⎯ Multiply and divide instructions
⎯ Powerful bit-manipulation instructions
• Eight addressing modes
⎯ Register direct [Rn]
⎯ Register indirect [@ERn]
⎯ Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
⎯ Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
⎯ Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
⎯ Immediate [#xx:8, #xx:16, or #xx:32]
⎯ Program-counter relative [@(d:8,PC) or @(d:16,PC)]
⎯ Memory indirect [@@aa:8]
• 16-Mbyte address space
⎯ Program: 16 Mbytes
⎯ Data:
16 Mbytes (4 Gbytes architecturally)
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Section 2 CPU
• High-speed operation
⎯ All frequently-used instructions execute in one or two states
⎯ Maximum clock rate
: 16 MHz
⎯ 8/16/32-bit register-register add/subtract : 62.5 ns
⎯ 8 × 8-bit register-register multiply
: 750 ns
⎯ 16 ÷ 8-bit register-register divide
: 750 ns
⎯ 16 × 16-bit register-register multiply
: 1250 ns
⎯ 32 ÷ 16-bit register-register divide
: 1250 ns
• Two CPU operating modes
⎯ Normal mode*
⎯ Advanced mode
Note: * Not available in the H8S/2214 Group.
• Power-down state
⎯ Transition to power-down state by SLEEP instruction
⎯ CPU clock speed selection
2.1.2
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of exection states of the MULXU and MULXS instructions.
Internal Operation
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
3
12
MULXU.W Rs, ERd
4
20
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
MULXS
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Section 2 CPU
There are also differences in the address space, CCR and EXR register functions, power-down
state, etc., depending on the product.
2.1.3
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
⎯ Eight 16-bit expanded registers, plus one 8-bit and two 32-bit control registers, have been
added
• Expanded address space
⎯ Normal mode* supports the same 64-kbyte address space as the H8/300 CPU
⎯ Advanced mode supports a maximum 16-Mbyte address space
Note: * Not available in the H8S/2214 Group.
• Enhanced addressing
⎯ The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space
• Enhanced instructions
⎯ Addressing modes of bit-manipulation instructions have been enhanced
⎯ Signed multiply and divide instructions have been added
⎯ Two-bit shift instructions have been added
⎯ Instructions for saving and restoring multiple registers have been added
⎯ A test and set instruction has been added
• Higher speed
⎯ Basic instructions execute twice as fast
2.1.4
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
⎯ One 8-bit and two 32-bit control registers have been added
• Enhanced instructions
⎯ Addressing modes of bit-manipulation instructions have been enhanced
⎯ Two-bit shift instructions have been added
⎯ Instructions for saving and restoring multiple registers have been added
⎯ A test and set instruction has been added
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Section 2 CPU
• Higher speed
⎯ Basic instructions execute twice as fast
2.2
CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal* and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for
program and data areas combined). The mode is selected by the mode pins of the microcontroller.
Note: * Not available in the H8S/2214 Group.
Normal mode*
Maximum 64-kbytes, program
and data areas combined
CPU operating modes
Advanced mode
Maximum 16-Mbytes for
program and data areas
combined
Note: * Not available in the H8S/2214 Group.
Figure 2.1 CPU Operating Modes
(1) Normal Mode (not available in the H8S/2214 Group)
The exception vector table and stack have the same structure as in the H8/300 CPU.
(a) Address Space
A maximum address space of 64 kbytes can be accessed.
(b) Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments
of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the
corresponding general register (Rn) is used as an address register. If the general register is
referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment
(@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register
(En) will be affected.
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Section 2 CPU
(c) Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses
(EA) are valid.
(d) Exception Vector Table and Memory Indirect Branch Addresses
In normal mode the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The configuration of the exception vector table in normal
mode is shown in figure 2.2. For details of the exception vector table, see section 4, Exception
Handling.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Power-on reset exception vector
Manual reset exception vector
(Reserved for system use)
Exception
vector table
Exception vector 1
Exception vector 2
Figure 2.2 Exception Vector Table (Normal Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note
that this area is also used for the exception vector table.
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Section 2 CPU
(e) Stack Structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in
exception handling, they are stored as shown in figure 2.3. When EXR is invalid, it is not pushed
onto the stack. For details, see section 4, Exception Handling.
SP
PC
(16 bits)
EXR*1
Reserved*1 *3
CCR
CCR*3
SP
*2
(SP )
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
Figure 2.3 Stack Structure in Normal Mode
(2) Advanced Mode
(a) Address Space
Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program
and data areas combined).
(b) Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments
of 32-bit registers or address registers.
(c) Instruction Set
All instructions and addressing modes can be used.
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Section 2 CPU
(d) Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in
units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the
lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception
Handling.
H'00000000
Reserved
Power-on reset exception vector
H'00000003
H'00000004
Reserved
Manual reset exception vector
H'00000007
H'00000008
Exception vector table
H'0000000B
(Reserved for system use)
H'0000000C
H'00000010
Reserved
Exception vector 1
Figure 2.4 Exception Vector Table (Advanced Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing
a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as
H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the
first part of this range is also the exception vector table.
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Section 2 CPU
(e) Stack Structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call,
and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto
the stack in exception handling, they are stored as shown in figure 2.5. When EXR is invalid, it is
not pushed onto the stack. For details, see section 4, Exception Handling.
EXR*1
Reserved*1 *3
CCR
SP
SP
Reserved
PC
(24 bits)
(a) Subroutine Branch
*2
(SP )
PC
(24 bits)
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
Figure 2.5 Stack Structure in Advanced Mode
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Section 2 CPU
2.3
Address Space
Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. Note that the modes and address spaces
that can actually be used differ between individual products. See section 3, MCU Operating
Modes, for details.
H'0000
H'00000000
64 kbyte
H'FFFF
16 Mbyte
H'00FFFFFF
Program area
Data area
Cannot be
used by the
H8S/2214 Group
H'FFFFFFFF
(a) Normal Mode*
(b) Advanced Mode
Note: * Not available in the H8S/2214 Group.
Figure 2.6 Memory Map
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Section 2 CPU
2.4
Register Configuration
2.4.1
Overview
The CPU has the internal registers shown in figure 2.7. There are two types of registers: general
registers and control registers.
General Registers (Rn) and Extended Registers (En)
15
07
07
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
EXR T — — — — I2 I1 I0
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
Legend:
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit*
H:
U:
N:
Z:
V:
C:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Note: * In the H8S/2214 Group, this bit cannot be used as an interrupt mask.
Figure 2.7 CPU Registers
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Section 2 CPU
2.4.2
General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and
can be used as both address registers and data registers. When a general register is used as a data
register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used
as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
RH registers
(R0H to R7H)
ER registers
(ER0 to ER7)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.8 Usage of General Registers
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Section 2 CPU
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the
stack.
Free area
SP (ER7)
Stack area
Figure 2.9 Stack
2.4.3
Control Registers
The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),
and 8-bit condition-code register (CCR).
(1) Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored (When an
instruction is fetched, the least significant PC bit is regarded as 0).
(2) Extended Control Register (EXR)
This 8-bit register contains the trace bit (T) and interrupt mask bit (I).
Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed
in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is
executed.
Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1.
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Section 2 CPU
Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to
7). For details, refer to section 5, Interrupt Controller.
Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. All interrupts, including NMI, are disabled for three states after one of these
instructions is executed, except for STC.
(3) Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted
regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. With the H8S/2214 Group, this bit cannot be
used as an interrupt mask bit.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to indicate a carry
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Section 2 CPU
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction
on the flag bits, refer to appendix A.1, Instruction List.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
2.4.4
Initial Register Values
Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
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Section 2 CPU
2.5
Data Formats
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.
Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte
operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit
BCD data.
2.5.1
General Register Data Formats
Figures 2.10 and 2.11 show the data formats in general registers.
Data Type
Register Number
Data Format
1-bit data
RnH
7
0
7 6 5 4 3 2 1 0
Don’t care
Don’t care
7
0
7 6 5 4 3 2 1 0
1-bit data
4-bit BCD data
RnL
RnH
4 3
7
Upper
4-bit BCD data
0
Lower
Don’t care
Upper
Don’t care
Byte data
RnH
4 3
7
RnL
7
0
Lower
0
Don’t care
MSB
Byte data
LSB
7
RnL
0
Don’t care
MSB
LSB
Legend:
ERn: General register ER
En:
General register E
Rn:
General register R
RnH: General register RH
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2.10 General Register Data Formats (1)
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Section 2 CPU
Data Type
Register Number
Word data
Rn
Word data
En
Data Format
15
0
MSB
15
0
MSB
Longword data
LSB
ERn
31
MSB
LSB
16 15
En
0
Rn
Legend:
ERn: General register ER
En:
General register E
Rn:
General register R
RnH: General register RH
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2.11 General Register Data Formats (2)
Rev.4.00 Sep. 18, 2008 Page 32 of 872
REJ09B0189-0400
LSB
Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.12 shows the data formats in memory. The CPU can access word data and longword data
in memory, but word or longword data must begin at an even address. If an attempt is made to
access word or longword data at an odd address, no address error occurs but the least significant
bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to
instruction fetches.
Data Type
Data Format
Address
7
1-bit data
Address L
Byte data
Address L MSB
Word data
7
0
6
5
4
2
1
0
LSB
Address 2M MSB
Address 2M + 1
Longword data
3
LSB
Address 2N MSB
Address 2N + 1
Address 2N + 2
Address 2N + 3
LSB
Figure 2.12 Memory Data Formats
When ER7 is used as an address register to access the stack, the operand size should be word size
or longword size.
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Section 2 CPU
2.6
Instruction Set
2.6.1
Overview
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Size
Types
Data transfer
MOV
1
1
POP* , PUSH*
BWL
5
5
LDM* , STM*
5
WL
L
3
MOVFPE, MOVTPE*
B
ADD, SUB, CMP, NEG
BWL
ADDX, SUBX, DAA, DAS
B
INC, DEC
BWL
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
BW
EXTU, EXTS
4
TAS*
B
Logic operations
AND, OR, XOR, NOT
BWL
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
BWL
8
Bit manipulation
B
14
Branch
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
2
Bcc* , JMP, BSR, JSR, RTS
—
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
9
Block data transfer
EEPMOV
1
Arithmetic
operations
19
WL
—
Total: 65
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in the H8S/2214 Group.
4. This instruction should be used with the ER0, ER1, ER4, or ER5 general register only.
5. The STM/LDM instructions may only be used with the ER0 to ER6 registers.
Rev.4.00 Sep. 18, 2008 Page 34 of 872
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BW
BW
B
—
—
—
—
—
ADDX, SUBX
ADDS, SUBS
INC, DEC
DAA, DAS
MULXU,
DIVXU
MULXS,
DIVXS
—
—
EXTU, EXTS
TAS*2
BWL
WL
—
—
NEG
B
BWL
L
B
BWL
WL
SUB
BWL
BWL
ADD, CMP
BWL
@ERn
B
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
@(d:16,ERn)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
@(d:32,ERn)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
@–ERn/@ERn+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
@aa:8
Notes: 1. Cannot be used in the H8S/2214 Group.
2. This instruction should be used with the ER0, ER1, ER4, or ER5 general register only.
3. The STM/LDM instructions may only be used with the ER0 to ER6 registers.
Arithmetic
operations
—
—
—
—
MOVFPE*1,
MOVTPE*1
—
BWL
#xx
—
BWL
Rn
POP, PUSH
LDM*3, STM*3
BWL
@aa:16
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
@aa:24
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
@aa:32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@(d:8,PC)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@(d:16,PC)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@@aa:8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
L
WL
Table 2.2
MOV
Instruction
2.6.2
Data
transfer
Function
Addressing Modes
Section 2 CPU
Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU
can use.
Combinations of Instructions and Addressing Modes
Rev.4.00 Sep. 18, 2008 Page 35 of 872
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BWL
—
Bit manipulation
—
—
—
—
—
—
B
—
B
—
—
RTS
TRAPA
RTE
SLEEP
LDC
STC
ANDC,
ORC, XORC
NOP
Block data transfer
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Legend:
B: Byte
W: Word
L: Longword
System
control
—
—
—
B
B
—
—
—
—
—
—
JMP, JSR
Branch
Bcc, BSR
B
BWL
—
NOT
BWL
—
BWL
#xx
AND, OR,
XOR
Instruction
Rn
Shift
Logic
operations
Function
@ERn
—
—
—
W
W
—
—
—
—
—
—
B
—
—
—
@(d:16,ERn)
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
@(d:32,ERn)
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
@–ERn/@ERn+
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
Addressing Modes
@aa:8
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
@aa:16
—
—
—
W
W
—
—
—
—
—
—
B
—
—
—
@aa:24
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@aa:32
—
—
—
W
W
—
—
—
—
—
—
B
—
—
—
@(d:8,PC)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@(d:16,PC)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@@aa:8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
—
—
—
—
—
—
—
—
—
Section 2 CPU
Section 2 CPU
2.6.3
Table of Instructions Classified by Function
Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3
is defined below.
Operation Notation
Rs
General register (destination)*
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
Rd
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move
¬
NOT (logical complement)
:8/:16/:24/:32
8-, 16-, 24-, or 32-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Instructions Classified by Function
Type
Instruction
1
Size*
Data transfer
MOV
B/W/L
(EAs) → Rd, Rs → (Ead)
Moves data between two general registers or between a
general register and memory, or moves immediate data
to a general register.
MOVFPE
B
Cannot be used in the H8S/2214.
MOVTPE
B
Cannot be used in the H8S/2214.
POP
W/L
@SP+ → Rn
Pops a register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L
@SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a register onto the stack. PUSH.W Rn is
identical to MOV.W Rn, @–SP. PUSH.L ERn is identical
to MOV.L ERn, @–SP.
2
LDM*
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
2
STM*
L
Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
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Function
Section 2 CPU
Type
Instruction
1
Size*
Arithmetic
operations
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general
registers, or on immediate data and data in a general
register (Immediate byte data cannot be subtracted from
byte data in a general register. Use the SUBX or ADD
instruction).
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on
byte data in two general registers, or on immediate data
and data in a general register.
INC
DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2.
(Byte operands can be incremented or decremented by
1 only.)
ADDS
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a
32-bit register.
DAA
DAS
B
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a
general register by referring to the CCR to produce 4-bit
BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder.
Function
Rev.4.00 Sep. 18, 2008 Page 39 of 872
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Section 2 CPU
Type
Instruction
1
Size*
Arithmetic
operations
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the result.
NEG
B/W/L
0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of
data in a general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
3
TAS*
B
@ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
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Function
Section 2 CPU
Type
Instruction
1
Size*
Logic
operations
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register
and another general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate data.
NOT
B/W/L
¬ (Rd) → (Rd)
Takes the one’s complement of general register
contents.
SHAL
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.
SHLL
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.
ROTL
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
ROTXL
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.
Shift
operations
Function
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Section 2 CPU
Type
Instruction
1
Size*
Bitmanipulation
instructions
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory
operand to 1. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory
operand to 0. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory
operand. The bit number is specified by 3-bit immediate
data or the lower three bits of a general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory
operand and sets or clears the Z flag accordingly. The
bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
BIAND
B
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in
a general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
BIOR
B
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
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Function
Section 2 CPU
Type
Instruction
1
Size*
Bitmanipulation
instructions
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a
general register or memory operand and stores the
result in the carry flag.
BIXOR
B
C ⊕ ¬ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with the inverse of a
specified bit in a general register or memory operand
and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory
operand to the carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general
register or memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a
general register or memory operand.
BIST
B
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a
specified bit in a general register or memory operand.
The bit number is specified by 3-bit immediate data.
Function
Rev.4.00 Sep. 18, 2008 Page 43 of 872
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Section 2 CPU
Type
Instruction
Size
Function
Branch
instructions
Bcc
—
Branches to a specified address if a specified condition
is true. The branching conditions are listed below.
Mnemonic
Description
Condition
BRA(BT)
Always (true)
Always
BRN(BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC(BHS)
Carry clear
(high or same)
C=0
BCS(BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address.
BSR
—
Branches to a subroutine at a specified address.
JSR
—
Branches to a subroutine at a specified address.
RTS
—
Returns from a subroutine
Rev.4.00 Sep. 18, 2008 Page 44 of 872
REJ09B0189-0400
Section 2 CPU
Type
Instruction
System control TRAPA
instructions
RTE
1
Size*
Function
—
Starts trap-instruction exception handling.
—
Returns from an exception-handling routine.
SLEEP
—
Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves the source operand contents or immediate data
to CCR or EXR. Although CCR and EXR are 8-bit
registers, word-size transfers are performed between
them and memory. The upper 8 bits are valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or
memory. Although CCR and EXR are 8-bit registers,
word-size transfers are performed between them and
memory. The upper 8 bits are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with
immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate
data.
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with
immediate data.
NOP
—
PC + 2 → PC
Only increments the program counter.
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Section 2 CPU
Type
Instruction
Size
Function
Block data
transfer
instruction
EEPMOV.B
—
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W
—
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block according to parameters set in
general registers R4L or R4, ER5, and ER6.
R4L or R4: size of block (bytes)
ER5: starting source address
ER6: starting destination address
Execution of the next instruction begins as soon as the
transfer is completed.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. The STM/LDM instructions may only be used with the ER0 to ER6 registers.
3. This instruction should be used with the ER0, ER1, ER4, or ER5 general register only.
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Section 2 CPU
2.6.4
Basic Instruction Formats
The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (op field), a register field (r field), an effective address extension (EA field), and a condition
field (cc field).
Figure 2.13 shows examples of instruction formats.
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16, etc
Figure 2.13 Instruction Formats (Examples)
(1) Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried out
on the operand. The operation field always includes the first four bits of the instruction. Some
instructions have two operation fields.
(2) Register Field
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4
bits. Some instructions have two register fields. Some have no register field.
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Section 2 CPU
(3) Effective Address Extension
Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
(4) Condition Field
Specifies the branching condition of Bcc instructions.
2.6.5
Notes on Use of Bit-Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit
manipulation, then write back the byte of data. Caution is therefore required when using these
instructions on a register containing write-only bits, or a port.
The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant
flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling
routine, etc.
See section 2.10.3, Bit Manipulation Instructions Usage Notes, for details.
2.7
Addressing Modes and Effective Address Calculation
2.7.1
Addressing Mode
The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of
these addressing modes. Arithmetic and logic instructions can use the register direct and
immediate modes. Data transfer instructions can use all addressing modes except program-counter
relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
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Section 2 CPU
Table 2.4
Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
(1) Register Direct—Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
(2) Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address
register contents and the sum is stored in the address register. The value added is 1 for byte
access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or
longword transfer instruction, the register value should be even.
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Section 2 CPU
• Register indirect with pre-decrement—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the result becomes the address of a memory operand. The result is
also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer
instruction, or 4 for longword transfer instruction. For word or longword transfer instruction,
the register value should be even.
(5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1
(H'FFFFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute
address can access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.5 indicates the accessible absolute address ranges.
Table 2.5
Absolute Address Access Ranges
Normal Mode*
Advanced Mode
8 bits (@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
Absolute Address
Data address
32 bits (@aa:32)
Program instruction
address
24 bits (@aa:24)
Note: * Not available in the H8S/2214 Group.
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H'000000 to H'FFFFFF
Section 2 CPU
(6) Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
(7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.
Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0
(H'00). The PC value to which the displacement is added is the address of the first byte of the next
instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
(8) Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF* in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode
the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
Note: * Not available in the H8S/2214 Group.
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Section 2 CPU
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(b) Advanced Mode
Note: * Not available in the H8S/2214 Group.
Figure 2.14 Branch Address Specification in Memory Indirect Mode
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
2.7.2
Effective Address Calculation
Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
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4
3
rm
rn
r
r
disp
r
op
r
• Register indirect with pre-decrement @–ERn
op
Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
op
Register indirect with displacement
@(d:16, ERn) or @(d:32, ERn)
op
Register indirect (@ERn)
op
Register direct (Rn)
Addressing Mode and Instruction Format
disp
1
2
4
0
1, 2, or 4
General register contents
Byte
Word
Longword
0
0
0
0
1, 2, or 4
General register contents
Sign extension
General register contents
General register contents
Operand Size Value added
31
31
31
31
31
Effective Address Calculation
24 23
24 23
24 23
24 23
Don’t care
31
Don’t care
31
Don’t care
31
Don’t care
31
Operand is general register contents.
Effective Address (EA)
0
0
0
0
Table 2.6
2
1
No.
Section 2 CPU
Effective Address Calculation
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6
op
op
abs
abs
abs
op
IMM
Immediate #xx:8/#xx:16/#xx:32
@aa:32
op
@aa:24
@aa:16
op
abs
Absolute address
5
@aa:8
Addressing Mode and Instruction Format
No.
Effective Address Calculation
24 23
24 23
24 23
24 23
87
16 15
Sign extension
H'FFFF
Operand is immediate data.
Don’t care
31
Don’t care
31
Don’t care
31
Don’t care
31
Effective Address (EA)
0
0
0
0
Section 2 CPU
abs
op
abs
• Advanced mode
op
• Normal mode*
Memory indirect @@aa:8
op
@(d:8, PC)/@(d:16, PC)
Program-counter relative
disp
Addressing Mode and Instruction Format
Note: * Not available in the H8S/2214 Group.
8
7
No.
31
31
31
87
abs
87
abs
Memory contents
15
Memory contents
H'000000
H'000000
disp
PC contents
Sign
extension
23
23
Effective Address Calculation
0
0
0
0
0
0
24 23
24 23
24 23
Don’t care
31
Don’t care
31
Don’t care
31
H'00
16 15
Effective Address (EA)
0
0
0
Section 2 CPU
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Section 2 CPU
2.8
Processing States
2.8.1
Overview
The CPU has five main processing states: the reset state, exception handling state, program
execution state, bus-released state, and power-down state. Figure 2.15 shows a diagram of the
processing states. Figure 2.16 indicates the state transitions.
Reset state
The CPU and all on-chip supporting modules have been
initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal
processing flow in response to a reset, interrupt, or trap
instruction.
Processing
states
Program execution
state
The CPU executes program instructions in sequence.
Bus-released state
The external bus has been released in response to a bus
request signal from a bus master other than the CPU.
Sleep mode
Power-down state
CPU operation is stopped
to conserve power.*
Software standby
mode
Hardware standby
mode
Note: * The power-down state also includes a medium-speed mode and module stop mode.
See section 17, Power-Down Modes, for details.
Figure 2.15 Processing States
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Section 2 CPU
End of bus request
Bus request
Program execution
state
End of bus
request
Bus
request
SLEEP
instruction
with
SSBY = 1
Bus-released state
End of
exception
handling
SLEEP
instruction
with
SSBY = 0
Request for
exception
handling
Sleep mode
Interrupt
request
Exception-handling state
Software standby mode
External interrupt
RES = high
MRES = high
STBY = high, RES = low
Manual reset state*1
Power-on reset
state*1
Hardware standby mode*2
Low Power States
Reset state
Notes: 1. From any state except hardware standby mode, a transition to the power-on reset state occurs whenever
RES goes low. From any state except hardware standby mode and the power-on reset state, a transition
to the manual reset state occurs whenever MRES goes low. A transition can also be made to the reset
state when the watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.16 State Transitions
2.8.2
Reset State
When the RES input goes low all current processing stops and the CPU enters the power-on reset
state. When the MRES input goes low, the CPU enters the manual reset state. All interrupts are
disabled in the reset state. Reset exception handling starts when the RES or MRES signal changes
from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 11,
Watchdog Timer (WDT).
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Section 2 CPU
2.8.3
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
(1) Types of Exception Handling and Their Priority
Exception handling is performed for resets, traces, interrupts, and trap instructions. Table 2.7
indicates the types of exception handling and their priority. Trap instruction exception handling is
always accepted, in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2.7
Exception Handling Types and Priority
Priority
Type of Exception
Detection Timing
Start of Exception Handling
High
Reset
Synchronized with clock
Exception handling starts
immediately after a low-to-high
transition at the RES or MRES
pin, or when the watchdog timer
overflows.
Trace
End of instruction
execution or end of
exception-handling
1
sequence*
When the trace (T) bit is set to
1, the trace starts at the end of
the current instruction or current
exception-handling sequence
Interrupt
End of instruction
execution or end of
exception-handling
2
sequence*
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence
Trap instruction
When TRAPA instruction
is executed
Exception handling starts when
a trap (TRAPA) instruction is
3
executed*
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not
executed at the end of the RTE instruction.
2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
3. Trap instruction exception handling is always accepted, in the program execution state.
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Section 2 CPU
(2) Reset Exception Handling
After the RES or MRES pin has gone low and the reset state has been entered, reset exception
handling starts when RES or MRES goes high again. The CPU enters the power-on reset state
when the RES pin is low, and the manual reset state when the MRES pin is low. When reset
exception handling starts the CPU fetches a start address (vector) from the exception vector table
and starts program execution from that address. All interrupts, including NMI, are disabled during
reset exception handling and after it ends.
(3) Traces
Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR
is set to 1. When trace mode is established, trace exception handling starts at the end of each
instruction.
At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode
is cleared. Interrupt masks are not affected.
The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to
return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction.
Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit.
(4) Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer
(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU
alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start
address (vector) from the exception vector table and program execution starts from that start
address.
Figure 2.17 shows the stack after exception handling ends.
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Section 2 CPU
Normal mode*2
SP
SP
EXR
Reserved*1
CCR
CCR*1
CCR
CCR*1
PC
(16 bits)
PC
(16 bits)
(a) Interrupt control mode 0
(b) Interrupt control mode 2
Advanced mode
SP
SP
EXR
Reserved*1
CCR
CCR
PC
(24 bits)
PC
(24 bits)
(c) Interrupt control mode 0
(d) Interrupt control mode 2
Notes: 1. Ignored when returning.
2. Not available in the H8S/2214 Group.
Figure 2.17 Stack Structure after Exception Handling (Examples)
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Section 2 CPU
2.8.4
Program Execution State
In this state the CPU executes program instructions in sequence.
2.8.5
Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts operations.
There are two other bus masters in addition to the CPU: the DMA controller (DMAC) and data
transfer controller (DTC).
For further details, refer to section 6, Bus Controller.
2.8.6
Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,
software standby mode, and hardware standby mode. There are also three other power-down
modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode the
CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting
of the operation of individual modules, other than the CPU. For details, refer to section 17, PowerDown Modes.
(1) Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit in
SBYCR and the LSON bit in LPWRCR are both cleared to 0. In sleep mode, CPU operations stop
immediately after execution of the SLEEP instruction. The contents of CPU registers are retained.
(2) Software Standby Mode
A transition to software standby mode is made if the SLEEP instruction is executed while the
SSBY bit in SBYCR is set to 1, and the LSON bit in LPWRCR and the PSS bit in TCSR (WDT1)
are both cleared to 0. In software standby mode, the CPU and clock halt and all MCU operations
stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM
are retained. The I/O ports also remain in their existing states.
(3) Hardware Standby Mode
A transition to hardware standby mode is made when the STBY pin goes low. In hardware
standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting
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Section 2 CPU
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
2.9
Basic Timing
2.9.1
Overview
The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge
of φ to the next is referred to as a “state”. The memory cycle or bus cycle consists of one, two, or
three states. Different methods are used to access on-chip memory, on-chip supporting modules,
and the external address space.
2.9.2
On-Chip Memory (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2.18 shows the on-chip memory access cycle. Figure 2.19 shows
the pin states.
Bus cycle
T1
φ
Internal address bus
Read
access
Address
Internal read signal
Internal data bus
Read data
Internal write signal
Write
access
Internal data bus
Write data
Figure 2.18 On-Chip Memory Access Cycle
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Bus cycle
T1
φ
Address bus
Unchanged
AS
High
RD
High
HWR, LWR
High
Data bus
High-impedance state
Figure 2.19 Pin States during On-Chip Memory Access
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Section 2 CPU
2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2.20 shows the
access timing for the on-chip supporting modules. Figure 2.21 shows the pin states.
Bus cycle
T2
T1
φ
Internal address bus
Address
Internal read signal
Read
access
Internal data bus
Read data
Internal write signal
Write
access
Internal data bus
Write data
Figure 2.20 On-Chip Supporting Module Access Cycle
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Section 2 CPU
Bus cycle
T1
T2
φ
Address bus
Unchanged
AS
High
RD
High
HWR, LWR
High
Data bus
High-impedance state
Figure 2.21 Pin States during On-Chip Supporting Module Access
2.9.4
External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 6, Bus Controller.
2.10
Usage Notes
2.10.1
TAS Instruction
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Renesas Technology H8S and H8/300 Series C/C++ compilers.
If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0,
ER1, ER4, or ER5 is used.
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2.10.2
STM/LDM Instruction Usage
With the STM or LDM instruction, the ER7 register is used as the stack pointer, and thus cannot
be used as a register that allows save (STM) or restore (LDM) operation.
With a single STM or LDM instruction, two to four registers can be saved or restored. The
available registers are as follows:
For two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5
For three registers: ER0 to ER2, or ER4 to ER6
For four registers: ER0 to ER3
For the Renesas Technology H8S or H8/300 Series C/C++ Compiler, the STM/LDM instruction
including ER7 is not created.
2.10.3
Bit Manipulation Instructions
When a register that includes write-only bits is manipulated by a bit manipulation instruction,
there are cases where the bits manipulated are not manipulated correctly or bits unrelated to the
bits manipulated are changed.
When a register containing write-only bits is read, the value read is either a fixed value or an
undefined value. This means that the bit manipulation instructions that use the value of bits read in
their operation (BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, and BILD)
will not perform correct bit operations.
Also, bit manipulation instructions that perform a write operation on the data read after the
calculation (BSET, BCLR, BNOT, BST, and BIST) may change bits unrelated to the bits
manipulated. Thus extreme care is required when performing bit manipulation instructions on
registers that include write-only bits.
The BSET, BCLR, BNOT, BST, and BIST instructions perform their operations in the following
order.
1. Read the data in byte units
2. Perform the bit manipulation operation according to the instruction on the data read.
3. Write the data back in byte units
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Section 2 CPU
Example: Using the BCLR instruction to clear only P14 in the port 1 P1DDR register.
The P1DDR register consists of 8 write-only bits and sets the I/O direction of the port 1 pins.
Reading this register is invalid. When read, the values returned are undefined.
Here we present an example in which P14 is specified to be an input port using the BCLR
instruction. Currently, P17 to 14 are set to be output pins and P13 to P10 are set to be input pins.
At this point, the value of P1DDR is H'F0.
I/O
P1DDR
P17
P16
P15
P14
P13
P12
P11
P10
Output
Output
Output
Output
Input
Input
Input
Input
1
1
1
1
0
0
0
0
To switch P14 from the Output pin to the input pin function, the value of P1DDR bit 4 must be
changed from 1 to 0 (H'F0 → H'E0). Here we assume that the BCLR instruction is used to clear
P1DDR bit 4.
BCLR
#4,
@P1DDR
However if a bit manipulation instruction of the type shown above is used on P1DDR, which is a
write-only register, the following problem may occur.
Although the first thing that happens is that data is read from P1DDR in byte units, the value read
at this time is undefined. An undefined value is a value that is either 0 or 1 in the register but reads
out as an arbitrary value whose relationship to the actual value is unknown. Since the P1DDR bits
are all write-only bits, every bit reads out as an undefined value. Although the actual value of
P1DDR at this point is H'F0, assume that bit 3 becomes a 1 here, and the value read out is H'F8.
P17
P16
P15
P14
P13
P12
P11
P10
Output
Output
Output
Output
Input
Input
Input
Input
P1DDR
1
1
1
1
0
0
0
0
Read value
1
1
1
1
1
0
0
0
I/O
Rev.4.00 Sep. 18, 2008 Page 67 of 872
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Section 2 CPU
The bit manipulation operation is performed on this value that was read. In this example, bit 4 will
be cleared for H'F8.
P17
P16
P15
P14
P13
P12
P11
P10
Output
Output
Output
Output
Input
Input
Input
Input
P1DDR
1
1
1
1
0
0
0
0
After bit
manipulation
1
1
1
0
1
0
0
0
I/O
After the bit manipulation operation, this data will be written to P1DDR, and the BCLR
instruction completes.
P17
P16
P15
P14
P13
P12
P11
P10
Output
Output
Output
Input
Output
Input
Input
Input
P1DDR
1
1
1
0
1
0
0
0
Write value
1
1
1
0
1
0
0
0
I/O
Although the instruction was expected to write H'E0 back to P1DDR, it actually wrote H'E8, and
P13, which was expected to be an input pin, is changed to function as an output pin. While this
section described the case where P13 was read out as a 1, since the values read are undefined
when P17 to P10 are read, when this bit manipulation instruction completes, bits that were 0 may
be changed to 1, and bits that were 1 may be changed to 0. To avoid this sort of problem, see
section 2.10.4, Access Methods for Registers with Write-Only Bits for methods for modifying
registers that include write-only bits.
Also note that it is possible to use the BCLR instruction to clear to 0 flags in internal I/O registers.
In this case, if it is clear from the interrupt handler or other information that the corresponding flag
is set to 1, then there is no need to read the value of the corresponding flag in advance.
2.10.4
Access Methods for Registers with Write-Only Bits
Undefined values will be read out if a data transfer instruction is executed for a register that
includes write-only bits, or if a bit manipulation instruction is executed for a register that includes
write-only bits. To avoid reading undefined values, use methods such as those shown below to
access registers that include write-only bits.
The basic method for writing to a register that includes write-only bits is to create a work area in
internal RAM or other memory area and first write the data to that area. Then, perform the desired
access operation for that memory and finally write that data to the register that includes write-only
bits.
Rev.4.00 Sep. 18, 2008 Page 68 of 872
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Section 2 CPU
Write data to the work area
Initial value write
Write the work area data to the
register that includes write-only bits
Access the work area data
(data transfer and bit manipulation
instructions can be used)
Modifying the value of a register
that includes write-only bits
Write the work area data to the register
that includes write-only bits
Figure 2.22 Flowchart for Access Methods for Registers that Include Write-Only Bits
Example: To clear only P14 in the port 1 P1DDR
The P1DDR register consists of 8 write-only bits and sets the I/O direction of the port 1 pins.
Reading this register is invalid. When read, the values returned are undefined.
Here we present an example in which P14 is specified to be an input port using the BCLR
instruction. First, we write the initial value H'F0 written to P1DDR to the work area in RAM
(RAM0).
MOV.B
#H'F0,
R0L
MOV.B
R0L,
@PAM0
MOV.B
R0L,
@P1DDR
P17
P16
P15
P14
P13
P12
P11
P10
Output
Output
Output
Output
Input
Input
Input
Input
P1DDR
1
1
1
1
0
0
0
0
RAM0
1
1
1
1
0
0
0
0
I/O
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Section 2 CPU
To switch P14 from being an output pin to being an input pin, we must change the value of
P1DDR bit 4 from 1 to 0 (H'F0 → H'E0). Here, were execute a BCLR instruction for RAM0.
BCLR
I/O
#4,
@RAM0
P17
P16
P15
P14
P13
P12
P11
P10
Output
Output
Output
Output
Input
Input
Input
Input
P1DDR
1
1
1
1
0
0
0
0
RAM0
1
1
1
0
0
0
0
0
Since RAM0 can be read and written, when the bit manipulation instruction is executed, only bit 4
in RAM0 is cleared. Then we write this RAM0 value to P1DDR.
MOV.B
@RAM0,
R0L
MOV.B
R0L,
@P1DDR
P17
P16
P15
P14
P13
P12
P11
P10
Output
Output
Output
Input
Input
Input
Input
Input
P1DDR
1
1
1
0
0
0
0
0
RAM0
1
1
1
0
0
0
0
0
I/O
If this procedure is used to write registers that include write-only bits, programs can be written
without depending on the type of the instructions used.
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Overview
3.1.1
Operating Mode Selection
The H8S/2214 Group has four operating modes (modes 4 to 7). These modes enable selection of
the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by
setting the mode pins (MD2 to MD0).
Table 3.1 lists the MCU operating modes.
Table 3.1
MCU Operating Mode Selection
External Data Bus
CPU
MCU
Operating
Operating
Description
Mode
MD2 MD1 MD0 Mode
0*
1*
0
0
1
3*
7
—
—
—
Max.
Width
0
1
1
0
5
6
—
Initial
Width
1
2*
4
0
On-Chip
ROM
0
1
1
Advanced On-chip ROM disabled, Disabled
expanded mode
16 bits
16 bits
8 bits
16 bits
16 bits
0
On-chip ROM enabled, Enabled
expanded mode
8 bits
1
Single-chip mode
—
Note: * Not available in the H8S/2214 Group.
The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2214 Group actually
accesses a maximum of 16 Mbytes.
Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral
devices.
The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program
execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus
controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit
access is selected for all areas, 8-bit bus mode is set.
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Section 3 MCU Operating Modes
Note that the functions of each pin depend on the operating mode.
The H8S/2214 Group can be used only in modes 4 to 7. This means that the mode pins must be set
to select one of these modes. Do not change the inputs at the mode pins during operation.
3.1.2
Register Configuration
The H8S/2214 Group has a mode control register (MDCR) that indicates the inputs at the mode
pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the
H8S/2214 Group. Table 3.2 summarizes these registers.
Table 3.2
MCU Registers
Name
Abbreviation
R/W
Initial Value
Address*
Mode control register
MDCR
R
Undetermined
H'FDE7
System control register
SYSCR
R/W
H'01
H'FDE5
Note: * Lower 16 bits of the address.
3.2
Register Descriptions
3.2.1
Mode Control Register (MDCR)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
—
MDS2
MDS1
MDS0
Initial value:
1
0
0
0
0
—*
—*
—*
R/W
—
—
—
—
—
R
R
R
:
Note: * Determined by pins MD2 to MD0.
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2214
Group.
Bit 7—Reserved: Read-only bit, always read as 1.
Bits 6 to 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0.
MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input
Rev.4.00 Sep. 18, 2008 Page 72 of 872
REJ09B0189-0400
Section 3 MCU Operating Modes
levels are latched into these bits when MDCR is read. These latches are canceled by a power-on
reset, but are retained after a manual reset.
3.2.2
Bit
System Control Register (SYSCR)
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
—
—
INTM1
INTM0
NMIEG
MRESE
—
RAME
0
0
0
0
0
0
0
1
R/W
—
R/W
R/W
R/W
R/W
—
R/W
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, the detected
edge for NMI, and enables or disables MRES pin input and on-chip RAM.
SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. In a manual
reset, the INTM1, INTM0, NMIEG, and RAME bits are initialized, but the MRESE bit is not.
SYSCR is not initialized in software standby mode.
Bit 7—Reserved: Only 0 should be written to this bit.
Bit 6—Reserved: Read-only bit, always read as 0.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5
Bit 4
INTM1
INTM0
Interrupt
Control Mode
Description
0
0
0
Control of interrupts by I bit
1
—
Setting prohibited
0
2
Control of interrupts by I2 to I0 bits and IPR
1
—
Setting prohibited
1
(Initial value)
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
Description
0
An interrupt is requested at the falling edge of NMI input
1
An interrupt is requested at the rising edge of NMI input
(Initial value)
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Section 3 MCU Operating Modes
Bit 2—Manual Reset Select (MRESE): Enables or disables the MRES pin. Table 3.3 shows the
relationship between the RES and MRES pin values and type of reset. For details of resets, see
section 4.2, Resets.
Bit 2
MRESE
Description
0
Manual reset is disabled
P74/MRES pin can be used as P74 I/O pin
1
Table 3.3
(Initial value)
Manual reset is enabled
P74/MRES pin can be used as MRES input pin
Relationship between RES and MRES pin Values and Type of Reset
Pins
RES
MRES
Type of Reset
0
*
Power-on reset
1
0
Manual reset
1
1
Operating state
*: Don’t care
Bit 1—Reserved: Read-only bit, always read as 0.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Note: When the DTC is used, the RAME bit should not be cleared to 0.
Rev.4.00 Sep. 18, 2008 Page 74 of 872
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(Initial value)
Section 3 MCU Operating Modes
3.3
Operating Mode Descriptions
3.3.1
Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a
data bus, and part of port F carries bus control signals.
Pins P13 to P11 function as input ports immediately after a reset. Address (A23 to A21) output
can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR)
regardless of the corresponding data direction register (DDR) values. Pin 10 and ports A and B
function as address (A20 to A8) outputs immediately after a reset. Address output can be enabled
or disabled by bits AE3 to AE0 in PFCR regardless of the corresponding DDR values. Pins for
which address output is disabled among pins P13 to P10 and in ports A and B become port outputs
when the corresponding DDR bits are set to 1.
Port C always has an address (A7 to A0) output function.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3.3.2
Mode 5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a
data bus, and part of port F carries bus control signals.
Pins P13 to P11 function as input ports immediately after a reset. Address (A23 to A21) output
can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR)
regardless of the corresponding data direction register (DDR) values. Pin 10 and ports A and B
function as address (A20 to A8) outputs immediately after a reset. Address output can be enabled
or disabled by bits AE3 to AE0 in PFCR regardless of the corresponding DDR values. Pins for
which address output is disabled among pins P13 to P10 and in ports A and B become port outputs
when the corresponding DDR bits are set to 1.
Port C always has an address (A7 to A0) output function.
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Section 3 MCU Operating Modes
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and
port E becomes a data bus.
3.3.3
Mode 6
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
Pins P13 to P10, and ports A and B function as input ports immediately after a reset. Address
(A23 to A8) output can be enabled or disabled by bits AE3 to AE0 in the pin function control
register (PFCR) regardless of the corresponding data direction register (DDR) values. Pins for
which address output is disabled among pins P13 to P10 and in ports A and B become port outputs
when the corresponding DDR bits are set to 1.
Ports D and E function as a data bus, and part of port F carries data bus signals.
Port C is an input port immediately after a reset. Addresses A7 to A0 are output by setting the
corresponding DDR bits to 1.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and
port E becomes a data bus.
3.3.4
Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
but external addresses cannot be accessed.
All I/O ports are available for use as input-output ports.
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Section 3 MCU Operating Modes
3.4
Pin Functions in Each Operating Mode
The pin functions of ports 1, and A to F vary depending on the operating mode. Table 3.4 shows
their functions in each operating mode.
Table 3.4
Pin Functions in Each Mode
Port
Port 1
Port A
Mode 4
Mode 5
Mode 6
Mode 7
P13 to P11
P*/A
P*/A
P*/A
P
P10
P/A*
P/A*
P*/A
P
PA3 to PA0
P/A*
P/A*
P/A*
P/A*
P*/A
P*/A
P
P
Port B
P
Port C
A
A
P*/A
Port D
D
Port E
D
P*/D
D
P*/D
P
PF7
P/D*
P/C*
P/C*
P/C*
P*/C
PF6 to PF4
C
P/C*
P*/C
C
P*/C
P
PF3
C
P*/C
P*/C
P*/C
Port F
PF2 to PF0
P
Legend:
P: I/O port
A: Address bus output
D: Data bus I/O
C: Control signals, clock I/O
*: After reset
3.5
Memory Map in Each Operating Mode
The H8S/2214 memory map is shown in figure 3.1.
The address space is 16 Mbytes in modes 4 to 7 (advanced modes).
The address space is divided into eight areas for modes 4 to 7. For details, see section 6, Bus
Controller.
Rev.4.00 Sep. 18, 2008 Page 77 of 872
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Section 3 MCU Operating Modes
Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
H'000000
Mode 6
(advanced expanded mode
with on-chip ROM enabled)
H'000000
Mode 7
(advanced single-chip mode)
H'000000
On-chip ROM
On-chip ROM
External address
space
H'01FFFF
H'FFB000
Reserved area*
H'FFC000
H'020000
External address
space
H'FFB000
Reserved area*
H'FFC000
On-chip RAM*
H'FFEFC0
External address
space
On-chip RAM*
H'FFEFC0
External address
space
H'FFC000
H'FFEFBF
On-chip RAM
H'FFF800 Internal I/O registers
H'FFFF40 External address
H'FFF800 Internal I/O registers
H'FFFF40 External address
H'FFF800 Internal I/O registers
H'FFFF3F
H'FFFF60 Internal I/O registers
H'FFFFC0
On-chip RAM*
H'FFFFFF
H'FFFF60
Internal I/O registers
H'FFFFC0
On-chip RAM*
H'FFFFFF
H'FFFF60
Internal I/O registers
H'FFFFC0
On-chip RAM
H'FFFFFF
space
space
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.1 Memory Map in Each Operating Mode in the H8S/2214
Rev.4.00 Sep. 18, 2008 Page 78 of 872
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Section 4 Exception Handling
Section 4 Exception Handling
4.1
Overview
4.1.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times, in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4.1
Exception Handling Types and Priority
Priority
Exception Handling Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the
RES or MRES pin, or when the watchdog timer
overflows. The CPU enters the power-on reset state
when the RES pin is low, and the manual reset state
when the MRES pin is low.
1
Trace*
Starts when execution of the current instruction or
exception handling ends, if the trace (T) bit is set to 1
Interrupt
Starts when execution of the current instruction or
exception handling ends, if an interrupt request has
2
been issued*
Low
Trap instruction (TRAPA)*
3
Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in program
execution state.
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Section 4 Exception Handling
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:
1. The program counter (PC), condition code register (CCR), and extended register (EXR) are
pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
4.1.3
Exception Sources and Vector Table
The exception sources are classified as shown in figure 4.1. Different vector addresses are
assigned to different exception sources.
Table 4.2 lists the exception sources and their vector addresses.
Power-on reset
Reset
Manual reset
Trace
Exception
sources
Direct transition
External interrupts: NMI, IRQ7 to IRQ0
Interrupts
External expansion interrupts: EXIRQ7 to EXIRQ0
Internal interrupts: 31 interrupt sources
Trap instruction
Figure 4.1 Exception Sources
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Section 4 Exception Handling
Table 4.2
Exception Vector Table
Vector Address*
Exception Source
Vector Number
Advanced Mode
Power-on reset
0
H'0000 to H'0003
Manual reset
1
H'0004 to H'0007
Reserved for system use
2
H'0008 to H'000B
3
H'000C to H'000F
4
H'0010 to H'0013
Trace
5
H'0014 to H'0017
Direct transition
6
H'0018 to H'001B
7
H'001C to H'001F
External interrupt
NMI
Trap instruction (4 sources)
8
H'0020 to H'0023
9
H'0024 to H'0027
10
H'0028 to H'002B
11
H'002C to H'002F
12
H'0030 to H'0033
13
H'0034 to H'0037
14
H'0038 to H'003B
15
H'003C to H'003F
IRQ0
16
H'0040 to H'0043
IRQ1
17
H'0044 to H'0047
IRQ2
18
H'0048 to H'004B
Reserved for system use
External interrupt
2
Internal interrupt*
1
IRQ3
19
H'004C to H'004F
IRQ4
20
H'0050 to H'0053
IRQ5
21
H'0054 to H'0057
IRQ6
22
H'0058 to H'005B
IRQ7
23
H'005C to H'005F
24
⎜
111
H'0060 to H'0063
⎜
H'01BC to H'01BF
Notes: 1. Lower 16 bits of the address.
2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling
Vector Table.
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Section 4 Exception Handling
4.2
Reset
4.2.1
Overview
A reset has the highest exception priority.
When the RES or MRES pin goes low, all processing halts and the H8S/2214 enters the reset state.
A reset initializes the internal state of the CPU and the registers of on-chip supporting modules.
Immediately after a reset, interrupt control mode 0 is set.
Reset exception handling begins when the RES or MRES pin changes from low to high.
The levels of the RES and MRES pins at reset determine whether a power-on reset or a manual
reset is effected.
The H8S/2214 can also be reset by overflow of the watchdog timer. For details see section 11,
Watchdog Timer (WDT).
4.2.2
Reset Types
A reset can be of either of two types: a power-on reset or a manual reset. Reset types are shown in
table 4.3. A power-on reset should be used when powering on.
The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes
all the registers in the on-chip supporting modules, while a manual reset initializes all the registers
in the on-chip supporting modules except for the bus controller and I/O ports, which retain their
previous states.
With a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip
supporting module I/O pins are switched to I/O ports controlled by DDR and DR.
Table 4.3
Reset Types
Reset Transition
Conditions
Internal State
Type
MRES
RES
CPU
On-Chip Supporting Modules
Power-on reset
*
Low
Initialized
Initialized
Manual reset
Low
High
Initialized
Initialized, except for bus controller
and I/O ports
*: Don’t care
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Section 4 Exception Handling
A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a
manual reset.
When the MRES pin is used, MRES pin input must be enabled by setting the MRESE bit to 1 in
SYSCR.
4.2.3
Reset Sequence
The H8S/2214 Group enters the reset state when the RES or MRES pin goes low.
To ensure that the H8S/2214 Group is reset, hold the RES or MRES pin low for at least 20 ms at
power-up. To reset the H8S/2214 Group during operation, hold the RES or MRES pin low for at
least 20 states.
When the RES or MRES pin goes high after being held low for the necessary time, the chip starts
reset exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.2 and 4.3 show examples of the reset sequence.
Rev.4.00 Sep. 18, 2008 Page 83 of 872
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Section 4 Exception Handling
Vector Internal
Prefetch of first program
fetch processing instruction
φ
RES, MRES
Internal
address bus
(1)
Internal read
signal
Internal write
signal
Internal data
bus
(3)
High
(2)
(4)
(1) Reset exception handling vector address (for a power-on reset, (1) = H'0000;
for a manual reset, (1) = H'0002)
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First program instruction
Figure 4.2 Reset Sequence (Modes 2 and 3: Not available in the H8S/2214)
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Section 4 Exception Handling
Internal
Prefetch of first
processing program instruction
Vector fetch
φ
*
*
*
(1)
(3)
(5)
RES, MRES
Address bus
RD
High
HWR, LWR
(2)
D15 to D0
(4)
(6)
(1) (3) Reset exception handling vector address (for a power-on reset, (1) = H'000000,
(3) = H'000002; for a manual reset, (1) = H'000004, (3) = H'000006)
(2) (4) Start address (contents of reset exception handling vector address)
(5)
Start address ((5) = (2) (4))
(6)
First program instruction
Note: * Three program wait states are inserted.
Figure 4.3 Reset Sequence (Mode 4)
4.2.4
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx:32, SP).
4.2.5
State of On-Chip Supporting Modules after Reset Release
After reset release, MSTPCRA is initialized to H'3F, MSTPCRB and MSTPCRC are initialized to
H'FF, and all modules except the DMAC and DTC enter module stop mode. Consequently, onchip supporting module registers cannot be read or written to. Register reading and writing is
enabled when module stop mode is exited.
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Section 4 Exception Handling
4.3
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction.
Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking.
Table 4.4 shows the state of CCR and EXR after execution of trace exception handling.
Interrupts are accepted even within the trace exception handling routine.
The T bit saved on the stack retains its value of 1, and when control is returned from the trace
exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Table 4.4
Status of CCR and EXR after Trace Exception Handling
CCR
Interrupt Control Mode
I
0
2
UI
EXR
I2 to I0
T
Trace exception handling cannot be used.
1
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
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—
—
0
Section 4 Exception Handling
4.4
Interrupts
Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0),
eight external expansion sources (EXIRQ7 to EXIRQ0), and 31 internal sources in the on-chip
supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of
each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer controller
(DTC), and DMA controller (DMAC). Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The
interrupt controller has two interrupt control modes and can assign interrupts other than NMI to
eight priority/mask levels to enable multiplexed interrupt control.
For details of interrupts, see section 5, Interrupt Controller.
External
interrupts
Interrupts
IRQ7 to IRQ0 (8)
External
expansion
interrupts: EXIRQ7 to EXIRQ0 (8)
Internal
interrupts
Notes:
NMI (1)
WDT* (1)
TPU (13)
SCI (12)
DTC (1)
DMAC (4)
Numbers in parentheses are the numbers of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates
an interrupt request at each counter overflow.
Figure 4.4 Interrupt Sources and Number of Interrupts
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Section 4 Exception Handling
4.5
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.5
Status of CCR and EXR after Trap Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
I2 to I0
T
0
1
—
—
—
2
1
—
—
0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
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Section 4 Exception Handling
4.6
Stack Status after Exception Handling
Figures 4.5 and 4.6 show the stack after completion of trap instruction exception handling and
interrupt exception handling.
SP
SP
CCR
CCR*
PC
(16 bits)
(a) Interrupt control mode 0
EXR
Reserved*
CCR
CCR*
PC
(16 bits)
(b) Interrupt control mode 2
Note: * Ignored on return.
Figure 4.5 Stack Status after Exception Handling (Normal Modes: Not available in the
H8S/2214)
SP
SP
CCR
EXR
Reserved*
CCR
PC
(24 bits)
PC
(24 bits)
(a) Interrupt control mode 0
(b) Interrupt control mode 2
Note: * Ignored on return.
Figure 4.6 Stack Status after Exception Handling (Advanced Modes)
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Section 4 Exception Handling
4.7
Notes on Use of the Stack
When accessing word data or longword data, the H8S/2214 Group assumes that the lowest address
bit is 0. The stack should always be accessed by word transfer instruction or longword transfer
instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the
following instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.7 shows an example of what
happens when the SP value is odd.
CCR
SP
R1L
SP
PC
PC
SP
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFF
TRAP instruction executed MOV.B R1L, @–ER7
SP set to H'FFFEFF
Data saved above SP
Contents of CCR lost
Legend: CCR: Condition code register
PC: Program counter
R1L: General register R1L
SP: Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced
mode.
Figure 4.7 Operation when SP Value Is Odd
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Overview
5.1.1
Features
The H8S/2214 Group controls interrupts by means of an interrupt controller. The interrupt
controller has the following features:
• Two interrupt control modes
⎯ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in
the system control register (SYSCR).
• Priorities settable with IPR
⎯ An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI.
⎯ NMI is assigned the highest priority level of 8, and can be accepted at all times.
• Independent vector addresses
⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Nine external interrupts
⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
edge can be selected for NMI.
⎯ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7
to IRQ0.
• DTC or DMAC control
⎯ DTC or DMAC activation is performed by means of interrupts.
• Eight external expansion interrupt input pins
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Section 5 Interrupt Controller
5.1.2
Block Diagram
A block diagram of the interrupt controller is shown in figure 5.1.
CPU
INTM1 INTM0
SYSCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
ISCR
IER
Interrupt
request
Vector
number
Priority
determination
I
Internal interrupt
request
SWDTEND to
TEI2
I2 to I0
External expansion
interrupt sources
EXIRQ0 to EXIRQ7
IPR
Interrupt controller
Legend:
ISCR:
IER:
ISR:
IPR:
SYSCR:
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register
System control register
Figure 5.1 Block Diagram of Interrupt Controller
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CCR
EXR
Section 5 Interrupt Controller
5.1.3
Pin Configuration
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1
Interrupt Controller Pins
Name
Symbol
I/O
Function
Nonmaskable interrupt
NMI
Input
Nonmaskable external interrupt; rising or
falling edge can be selected
External interrupt
requests 7 to 0
IRQ7 to IRQ0 Input
Maskable external interrupts; rising, falling, or
both edges, or level sensing, can be selected
External expansion
interrupt sources 7 to 0
EXIRQ7 to
EXIRQ0
Interrupts from external expansion modules.
Interrupt is accepted on low level.
5.1.4
Input
Register Configuration
Table 5.2 summarizes the registers of the interrupt controller.
Table 5.2
Interrupt Controller Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
System control register
SYSCR
R/W
H'01
H'FDE5
IRQ sense control register H
ISCRH
R/W
H'00
H'FE12
IRQ sense control register L
ISCRL
R/W
H'00
H'FE13
IRQ enable register
IER
R/W
H'00
H'FE14
IRQ status register
ISR
2
R/(W)*
H'00
H'FE15
Interrupt priority register A
IPRA
R/W
H'77
H'FEC0
Interrupt priority register B
IPRB
R/W
H'77
H'FEC1
Interrupt priority register C
IPRC
R/W
H'77
H'FEC2
Interrupt priority register D
IPRD
R/W
H'77
H'FEC3
Interrupt priority register F
IPRF
R/W
H'77
H'FEC5
Interrupt priority register G
IPRG
R/W
H'77
H'FEC6
Interrupt priority register J
IPRJ
R/W
H'77
H'FEC9
Interrupt priority register K
IPRK
R/W
H'77
H'FECA
Interrupt priority register M
IPRM
R/W
H'77
H'FECC
Notes: 1. Lower 16 bits of the address.
2. Can only be written with 0 for flag clearing.
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Section 5 Interrupt Controller
5.2
Register Descriptions
5.2.1
System Control Register (SYSCR)
Bit
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
—
—
INTM1
INTM0
NMIEG
MRESE
—
RAME
0
0
0
0
0
0
0
1
R/W
—
R/W
R/W
R/W
R/W
—
R/W
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI.
Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control
Register (SYSCR).
SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. In a manual
reset, the INTM1, INTM0, NMIEG, and RAME bits are initialized, but the MRESE bit is not.
SYSCR is not initialized in software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two
interrupt control modes for the interrupt controller.
Bit 5
Bit 4
INTM1
INTM0
Interrupt
Control Mode
Description
0
0
0
Interrupts are controlled by I bit
1
—
Setting prohibited
0
2
Interrupts are controlled by bits I2 to I0, and IPR
1
—
Setting prohibited
1
(Initial value)
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG
Description
0
Interrupt request generated at falling edge of NMI input
1
Interrupt request generated at rising edge of NMI input
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(Initial value)
Section 5 Interrupt Controller
5.2.2
Interrupt Priority Registers A to D, F, G, J, K, M (IPRA to IPRD, IPRF, IPRG,
IPRJ, IPRK, IPRM)
Bit
:
7
6
5
4
3
2
1
0
—
IPR6
IPR5
IPR4
—
IPR2
IPR1
IPR0
Initial value:
0
1
1
1
0
1
1
1
R/W
—
R/W
R/W
R/W
—
R/W
R/W
R/W
:
The IPR registers are nine 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5.3.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Bits 7 and 3—Reserved: Read-only bits, always read as 0.
Table 5.3
Correspondence between Interrupt Sources and IPR Settings
Bits
Register
6 to 4
2 to 0
IPRA
IRQ0
IRQ1
IPRB
IRQ2
IRQ3
IRQ4
IRQ5
IPRC
IRQ6
IRQ7
DTC
IPRD
Watchdog timer 0
—*
IPRF
TPU channel 0
TPU channel 1
IPRG
TPU channel 2
—
IPRJ
DMAC
SCI channel 0
IPRK
SCI channel 1
SCI channel 2
IPRM
EXIRQ3 to EXIRQ0
EXIRQ7 to EXIRQ4
Note: * Reserved bits. These bits cannot be modified and are always read as 1.
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Section 5 Interrupt Controller
As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range
from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding
interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority
level, level 7, by setting H'7.
When interrupt requests are generated, the highest-priority interrupt according to the priority
levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt
mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if
the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to
the CPU.
5.2.3
Bit
IRQ Enable Register (IER)
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests
IRQ7 to IRQ0.
IER is initialized to H'00 by a reset and in hardware standby mode.
It is not initialized in software standby mode.
Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to
IRQ0 are enabled or disabled.
Bit n
IRQnE
Description
0
IRQn interrupts disabled
1
IRQn interrupts enabled
(Initial value)
(n = 7 to 0)
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Section 5 Interrupt Controller
5.2.4
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCRH
Bit
15
:
14
13
12
11
10
9
8
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
0
0
0
0
0
0
0
0
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
7
6
5
4
3
2
1
0
Initial value:
R/W
ISCRL
Bit
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
Initial value:
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or
both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and
B (IRQ0SCA, IRQ0SCB)
Bits 15 to 0
IRQ7SCB to
IRQ0SCB
IRQ7SCA to
IRQ0SCA
0
0
Interrupt request generated at IRQ7 to IRQ0 input low level
(initial value)
1
Interrupt request generated at falling edge of IRQ7 to IRQ0 input
0
Interrupt request generated at rising edge of IRQ7 to IRQ0 input
1
Interrupt request generated at both falling and rising edges of
IRQ7 to IRQ0 input
1
Description
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Section 5 Interrupt Controller
5.2.5
IRQ Status Register (ISR)
Bit
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Note: * Only 0 can be written, to clear the flag.
ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
It is not initialized in software standby mode.
Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to
IRQ0 interrupt requests.
Bit n
IRQnF
Description
0
[Clearing conditions]
1
(Initial value)
•
Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
•
When interrupt exception handling is executed when low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high
•
When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
•
When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
[Setting conditions]
•
When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
0)
•
When a falling edge occurs in IRQn input when falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
•
When a rising edge occurs in IRQn input when rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
•
When a falling or rising edge occurs in IRQn input when both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
(n = 7 to 0)
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Section 5 Interrupt Controller
5.3
Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (53
sources).
5.3.1
External Interrupts
There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can
be used to restore the H8S/2214 Group from software standby mode.
(1) NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt
control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used
to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
(2) IRQ7 to IRQ0 Interrupts
Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to
IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
A block diagram of interrupts IRQn is shown in figure 5.2.
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Section 5 Interrupt Controller
IRQnE
IRQnSCA, IRQnSCB
IRQnF
Edge/level
detection circuit
IRQn interrupt
S
Q
request
R
IRQn input
Clear signal
Note: n = 7 to 0
Figure 5.2 Block Diagram of Interrupts IRQn
Figure 5.3 shows the timing of setting IRQnF.
φ
IRQn
input pin
IRQnF
Note: n = 7 to 0
Figure 5.3 Timing of Setting IRQnF
The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function. Since interrupt request
flags IRQ7F to IRQ0F are set when the setting condition is satisfied, regardless of the IER setting,
only the necessary flags should be referenced.
(3) EXIRQ7 to EXIRQ0 Interrupts
Interrupts EXIRQ7 to EXIRQ0 are for use by external expansion modules. An interrupt is
requested by a low-level input signal at one of pins EXIRQ7 to EXIRQ0.
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Section 5 Interrupt Controller
5.3.2
Internal Interrupts
There are 31 sources for internal interrupts from on-chip supporting modules.
• For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular interrupt source, an interrupt request is issued to the interrupt controller.
• The interrupt priority level can be set by means of IPR.
• The DMAC and DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request.
When the DMAC and DTC is activated by an interrupt, the interrupt control mode and
interrupt mask bits are not affected.
5.3.3
Interrupt Exception Handling Vector Table
Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of the IPR. The situation when two or more
modules are set to the same priority, and priorities within a module, are fixed as shown in
table 5.4.
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Section 5 Interrupt Controller
Table 5.4
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector
Address*
Origin of
Interrupt
Source
Vector
Number
External
pin
7
H'001C
16
H'0040
IPRA6 to
IPRA 4
IRQ1
17
H'0044
IPRA2 to
IPRA 0
IRQ2
IRQ3
18
19
H'0048
H'004C
IPRB6 to
IPRB 4
IRQ4
IRQ5
20
21
H'0050
H'0054
IPRB2 to
IPRB 0
IRQ6
IRQ7
22
23
H'0058
H'005C
IPRC6 to
IPRC 4
SWDTEND
DTC
(software activation interrupt end)
24
H'0060
IPRC2 to
IPRC 0
WOVI0 (interval timer)
Watchdog
timer 0
25
H'0064
IPRD6 to
IPRD 4
TGI0A (TGR0A input
capture/compare match)
TGI0B (TGR0B input
capture/compare match)
TGI0C (TGR0C input
capture/compare match)
TGI0D (TGR0D input
capture/compare match)
TCI0V (overflow 0)
TPU
channel 0
32
H'0080
IPRF6 to
IPRF 4
33
H'0084
34
H'0088
35
H'008C
36
H'0090
Reserved
—
37
38
39
H'0094
H'0098
H'009C
Interrupt Source
NMI
IRQ0
Note: * Lower 16 bits of the start address.
Rev.4.00 Sep. 18, 2008 Page 102 of 872
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Advanced
Mode
IPR
Priority
High
Low
Section 5 Interrupt Controller
Interrupt Source
Origin of
Interrupt
Source
TGI1A (TGR1A input
capture/compare match)
TGI1B (TGR1B input
capture/compare match)
TCI1V (overflow 1)
TCI1U (underflow 1)
TPU
channel 1
TGI2A (TGR2A input
capture/compare match)
TGI2B (TGR2B input
capture/compare match)
TCI2V (overflow 2)
TCI2U (underflow 2)
TPU
channel 2
Vector
Address*
Vector
Number
Advanced
Mode
40
H'00A0
41
H'00A4
42
43
H'00A8
H'00AC
44
H'00B0
45
H'00B4
46
47
H'00B8
H'00BC
IPR
Priority
IPRF2 to
IPRF 0
High
IPRG6 to
IPRG 4
DEND0A (channel 0/channel 0A DMAC
transfer end)
DEND0B (channel 0B transfer end)
DEND1A (channel 1/channel 1A
transfer end)
DEND1B (channel 1B transfer end)
72
H'0120
73
74
H'0124
H'0128
75
H'012C
ERI0 (receive error 0)
RXI0 (reception completed 0)
TXI0 (transmit data empty 0)
TEI0 (transmission end 0)
SCI
channel 0
80
81
82
83
H'0140
H'0144
H'0148
H'014C
IPRJ2 to
IPRJ 0
ERI1 (receive error 1)
RXI1 (reception completed 1)
TXI1 (transmit data empty 1)
TEI1 (transmission end 1)
SCI
channel 1
84
85
86
87
H'0150
H'0154
H'0158
H'015C
IPRK6 to
IPRK 4
ERI2 (receive error 2)
RXI2 (reception completed 2)
TXI2 (transmit data empty 2)
TEI2 (transmission end 2)
SCI
channel 2
88
89
90
91
H'0160
H'0164
H'0168
H'016C
IPRK2 to
IPRK 0
EXIRQ0
EXIRQ1
EXIRQ2
EXIRQ3
External
module
104
105
106
107
H'01A0
H'01A4
H'01A8
H'01AC
IPRM6 to
IPRM4
108
109
110
111
H'01B0
H'01B4
H'01B8
H'01DC
IPRM2 to
IPRM0
EXIRQ4
EXIRQ5
EXIRQ6
EXIRQ7
IPRJ6 to
IPRJ4
Low
Note: * Lower 16 bits of the start address.
Rev.4.00 Sep. 18, 2008 Page 103 of 872
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Section 5 Interrupt Controller
5.4
Interrupt Operation
5.4.1
Interrupt Control Modes and Interrupt Operation
Interrupt operations in the H8S/2214 Group differ depending on the interrupt control mode.
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for
each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt
sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 5.5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated
by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR.
Table 5.5
Interrupt Control Modes
SYSCR
Interrupt
Priority Setting
Control Mode INTM1 INTM0 Registers
Interrupt
Mask Bits Description
0
0
—
2
—
1
0
—
I
Interrupt mask control is
performed by the I bit.
1
—
—
Setting prohibited
0
IPR
I2 to I0
8-level interrupt mask control
is performed by bits I2 to I0.
8 priority levels can be set with
IPR.
1
—
—
Setting prohibited
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Section 5 Interrupt Controller
Figure 5.4 shows a block diagram of the priority decision circuit.
Interrupt
control
mode 0
I
Interrupt
acceptance
control
Default priority
determination
Interrupt source
Vector number
8-level
mask control
IPR
I2 to I0
Interrupt control mode 2
Figure 5.4 Block Diagram of Interrupt Control Operation
(1) Interrupt Acceptance Control
In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.
Table 5.6 shows the interrupts selected in each interrupt control mode.
Table 5.6
Interrupts Selected in Each Interrupt Control Mode (1)
Interrupt Mask Bits
Interrupt Control Mode
I
0
0
All interrupts
1
NMI interrupts
*
All interrupts
2
Selected Interrupts
*: Don't care
(2) 8-Level Control
In interrupt control mode 2, 8-level mask level determination is performed for the selected
interrupts in interrupt acceptance control according to the interrupt priority level (IPR).
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Section 5 Interrupt Controller
The interrupt source selected is the interrupt with the highest priority level, and whose priority
level set in IPR is higher than the mask level.
Table 5.7
Interrupts Selected in Each Interrupt Control Mode (2)
Interrupt Control Mode
Selected Interrupts
0
All interrupts
2
Highest-priority-level (IPR) interrupt whose priority level is greater
than the mask level (IPR > I2 to I0).
(3) Default Priority Determination
When an interrupt is selected by 8-level control, its priority is determined and a vector number is
generated.
If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.8 shows operations and control signal functions in each interrupt control mode.
Table 5.8
Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt
Setting
Control
Mode
INTM1 INTM0
Interrupt Acceptance
Control
I
0
0
0
IM
1
2
1
0
X
—*
Legend:
: Interrupt operation control performed
X : No operation. (All interrupts enabled)
IM : Used as interrupt mask bit
PR : Sets priority.
— : Not used.
Notes: 1. Set to 1 when interrupt is accepted.
2. Keep the initial setting.
Rev.4.00 Sep. 18, 2008 Page 106 of 872
REJ09B0189-0400
Default
Priority
Determination
8-Level Control
I2 to I0 IPR
X
—
IM
—*
PR
2
T
(Trace)
—
T
Section 5 Interrupt Controller
5.4.2
Interrupt Control Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by
means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and
disabled when set to 1.
Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
[2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I
bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending.
[3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
the priority system is accepted, and other interrupt requests are held pending.
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
[5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
[6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
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Section 5 Interrupt Controller
Program execution status
No
Interrupt generated?
Yes
Yes
NMI
No
No
I=0
Hold pending
Yes
No
IRQ0
Yes
IRQ1
No
Yes
EXIRQ7
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 0
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Section 5 Interrupt Controller
5.4.3
Interrupt Control Mode 2
Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts
by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR.
Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
[2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.4 is selected.
[3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
[5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
[6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
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Section 5 Interrupt Controller
Program execution status
Interrupt generated?
No
Yes
Yes
NMI
No
Level 7 interrupt?
No
Yes
Mask level 6
or below?
Yes
Level 6 interrupt?
No
No
Yes
Mask level 5
or below?
Level 1 interrupt?
No
Yes
Yes
Mask level 0?
Yes
Save PC, CCR, and EXR
Hold pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 2
Rev.4.00 Sep. 18, 2008 Page 110 of 872
REJ09B0189-0400
No
No
(1)
(2)
(4)
(3)
Instruction
prefetch
Internal
operation
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address)
(2) (4) Instruction code (Not executed)
(3)
Instruction prefetch address (Not executed)
(5)
SP-2
(7)
SP-4
(1)
Internal
data us
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
φ
Interrupt level determination
Wait for end of instruction
(5)
(7)
(8)
(9)
(10)
Vector fetch
(12)
(11)
(14)
(13)
Interrupt service
routine instruction
prefetch
(6) (8)
Saved PC and saved CCR
(9) (11) Vector address
(10) (12) Interrupt handling routine start address (vector
address contents)
(13)
Interrupt handling routine start address ((13) = (10) (12))
(14)
First instruction of interrupt handling routine
(6)
Stack
Internal
operation
5.4.4
Interrupt
acceptance
Section 5 Interrupt Controller
Interrupt Exception Handling Sequence
Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Figure 5.7 Interrupt Exception Handling
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REJ09B0189-0400
Section 5 Interrupt Controller
5.4.5
Interrupt Response Times
The H8S/2214 Group is capable of fast word transfer instruction to on-chip memory, and the
program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing.
Table 5.9 shows interrupt response times—the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.9 are explained in table 5.10.
Table 5.9
Interrupt Response Times
Normal Mode*
5
Advanced Mode
No.
Execution Status
INTM1 = 0
INTM1 = 1
INTM1 = 0
INTM1 = 1
1
1
Interrupt priority determination*
3
3
3
3
2
Number of wait states until executing (1 to 19)
2
instruction ends*
+ 2 · SI
(1 to 19)
+ 2 · SI
(1 to 19)
+ 2 · SI
(1 to 19)
+ 2 · SI
3
PC, CCR, EXR stack save
2 · SK
3 · SK
2 · SK
3 · SK
4
Vector fetch
SI
SI
2 · SI
2 · SI
5
3
Instruction fetch*
2 · SI
2 · SI
2 · SI
2 · SI
6
4
Internal processing*
2
2
2
2
11 to 31
12 to 32
12 to 32
13 to 33
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
5.
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and interrupt handling routine prefetch.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Not available in the H8S/2214 Group.
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Section 5 Interrupt Controller
Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8 Bit Bus
Symbol
Instruction fetch
SI
Branch address read
SJ
Stack manipulation
SK
16 Bit Bus
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
1
4
6+2m
2
3+m
m: Number of wait states in an external device access.
5.5
Usage Notes
5.5.1
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes
effective after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.8 shows and example in which the TGIEA bit in 16-bit timer TIER0 is cleared to 0.
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Rev.4.00 Sep. 18, 2008 Page 113 of 872
REJ09B0189-0400
Section 5 Interrupt Controller
TIER0 write cycle by CPU
TGIOA exception handling
φ
Internal
address bus
TIER0 address
Internal
write signal
TGIEA
TGFA
TGIOA
interrupt signal
Figure 5.8 Contention between Interrupt Generation and Disabling
5.5.2
Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.5.3
Times when Interrupts Are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
Rev.4.00 Sep. 18, 2008 Page 114 of 872
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Section 5 Interrupt Controller
5.5.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1:
5.5.5
EEPMOV.W
MOV.W
R4,R4
BNE
L1
IRQ Interrupts
When operating from a clock signal, interrupt requests are accepted in synchronization with the
clock.
Interrupt requests are accepted asynchronously in software standby mode.
See section 18.4.2, Control Signal Timing, for the input conditions.
5.5.6
NMI Interrupt Usage Notes
The NMI interrupt invokes exception handling that is performed by cooperation between the
interrupt controller and the CPU built into this IC during normal operation under the conditions
stipulated in the electrical characteristics. No operations, including the NMI interrupt, are
guaranteed if there are abnormal inputs to the IC pins or if there are software problems (e.g. if the
application has crashed or gone into an infinite loop). In such cases, the IC can be returned to the
normal program execution state by applying an external reset.
Rev.4.00 Sep. 18, 2008 Page 115 of 872
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Section 5 Interrupt Controller
5.6
DTC and DMAC Activation by Interrupt
5.6.1
Overview
The DTC and DMAC can be activated by an interrupt. In this case, the following options are
available:
• Interrupt request to CPU
• Activation request to DTC
• Activation request to DMAC
• Selection of a number of the above
For details of interrupt requests that can be used with to activate the DTC and DMAC, see section
7, DMA Controller (DMAC) and section 8, Data Transfer Controller (DTC).
5.6.2
Block Diagram
Figure 5.9 shows a block diagram of the DTC and DMAC interrupt controller.
Interrupt
request
IRQ
interrupt
On-chip
supporting
module
Interrupt source
clear signal
Clear signal
Disenable
signal
DMAC
DTC activation
request vector
number
Selection
circuit
Select
signal
Clear signal
DTCER
Control logic
DTC
Clear signal
DTVECR
SWDTE
clear signal
Determination of
priority
CPU interrupt
request vector
number
CPU
I, I2 to I0
Interrupt controller
Figure 5.9 Interrupt Control for DTC and DMAC
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Section 5 Interrupt Controller
5.6.3
Operation
The interrupt controller has three main functions in DTC and DMAC control.
(1) Selection of Interrupt Source
DMAC inputs activation factor directly to each channel. The activation factors for each channel of
DMAC are selected by DTF3 to DTF0 bits of DMACR. The DTA bit of DMABCR can be used to
select whether the selected activation factors are managed by DMAC. By setting the DTA bit to 1,
the interrupt factor which were the activation factor for that DMAC do not act as the DTC
activation factor or the CPU interrupt factor.
Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation
request or CPU interrupt request by the DTCE bit of the DTCEA to DTCEG of DTC.
By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after
DTC data transfer, and request a CPU interrupt.
If DTC carries out the designate number of data transfers and the transfer counter reads 0, after
DTC data transfer, the DTCE bit is also cleared to 0, and a CPU interrupt requested.
(2) Determination of Priority
The DTC activation source is selected in accordance with the default priority order, and is not
affected by mask or priority levels. See section 8.4, Interrupts, and section 8.3.3, DTC Vector
Table for the respective priority.
(3) Operation Order
If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC
data transfer is performed first, followed by CPU interrupt exception handling.
If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or
CPU interrupt factor, these operate independently. They operate in accordance with the respective
operating states and bus priorities.
Table 5.11 shows the interrupt factor clear control and selection of interrupt factors by
specification of the DTA bit of DMAC's DMABCR, DTCE bits of DTC's DTCEA to DTCEG,
and the DISEL bit of DTC's MRB.
Rev.4.00 Sep. 18, 2008 Page 117 of 872
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Section 5 Interrupt Controller
Table 5.11 Interrupt Source Selection and Clearing Control
Settings
DMAC
DTC
Interrupt Sources Selection/Clearing Control
DTA
DTCE
DISEL
0
0
1
*
0
1
*
DMAC
DTC
CPU
X
1
*
X
Legend:
: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
X
X
: The relevant interrupt is used. The interrupt source is not cleared.
X : The relevant bit cannot be used.
* : Don’t care
(4) Notes on Use
The SCI interrupt source is cleared when the DMAC or DTC reads or writes to the prescribed
register, and is not dependent upon the DTA bit, DTCE bit, or DISEL bit.
Rev.4.00 Sep. 18, 2008 Page 118 of 872
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Section 6 Bus Controller
Section 6 Bus Controller
6.1
Overview
The H8S/2214 Group has an on-chip bus controller (BSC) that manages the external address space
divided into eight areas. The bus specifications, such as bus width and number of access states,
can be set independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC).
6.1.1
Features
The features of the bus controller are listed below.
• Manages external address space in area units
⎯ Manages the external space as 8 areas of 2-Mbytes
⎯ Bus specifications can be set independently for each area
⎯ Burst ROM interface can be set
• Basic bus interface
⎯ Chip select (CS0 to CS7) can be output for areas 0 to 7
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ 2-state access or 3-state access can be selected for each area
⎯ Program wait states can be inserted for each area
• Burst ROM interface
⎯ Burst ROM interface can be set for area 0
⎯ Choice of 1- or 2-state burst access
• Idle cycle insertion
⎯ An idle cycle can be inserted in case of an external read cycle between different areas
⎯ An idle cycle can be inserted in case of an external write cycle immediately after an
external read cycle
• Bus arbitration function
⎯ Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC
• Other features
⎯ External bus release function
Rev.4.00 Sep. 18, 2008 Page 119 of 872
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Section 6 Bus Controller
6.1.2
Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
CS0 to CS7
Internal
address bus
Area decoder
ABWCR
External bus control signals
ASTCR
BCRH
BCRL
BACK
Bus
controller
Wait
controller
WAIT
Internal data bus
BREQ
Internal control
signals
Bus mode signal
WCRH
WCRL
CPU bus request signal
DTC bus request signal
Bus arbiter
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
Legend:
ABWCR: Bus width control register
ASTCR: Access state control register
BCRH: Bus control register H
BCRL: Bus control register L
WCRH: Wait state control register H
WCRL: Wait state control register L
DMAC bus acknowledge signal
Figure 6.1 Block Diagram of Bus Controller
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Section 6 Bus Controller
6.1.3
Pin Configuration
Table 6.1 summarizes the pins of the bus controller.
Table 6.1
Bus Controller Pins
Name
Symbol
I/O
Function
Address strobe
AS
Output
Strobe signal indicating that address output on address
bus is enabled.
Read
RD
Output
Strobe signal indicating that external space is being
read.
High write
HWR
Output
Strobe signal indicating that external space is to be
written, and upper half (D15 to D8) of data bus is
enabled.
Low write
LWR
Output
Strobe signal indicating that external space is to be
written, and lower half (D7 to D0) of data bus is enabled.
Chip select 0 to 7
CS0 to
CS7
Output
Strobe signal indicating that areas 0 to 7 are selected.
Wait
WAIT
Input
Wait request signal when accessing external 3-state
access space.
Bus request
BREQ
Input
Request signal that releases bus to external device.
Bus request
acknowledge
BACK
Output
Acknowledge signal indicating that bus has been
released.
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Section 6 Bus Controller
6.1.4
Register Configuration
Table 6.2 summarizes the registers of the bus controller.
Table 6.2
Bus Controller Registers
Initial Value
Name
Abbreviation
R/W
Power-On
Reset
Bus width control register
ABWCR
R/W
H'FF/H'00*
Access state control register
ASTCR
R/W
H'FF
2
Manual
Reset
Address*
Retained
H'FED0
Retained
H'FED1
1
Wait control register H
WCRH
R/W
H'FF
Retained
H'FED2
Wait control register L
WCRL
R/W
H'FF
Retained
H'FED3
Bus control register H
BCRH
R/W
H'D0
Retained
H'FED4
Bus control register L
BCRL
R/W
H'08
Retained
H'FED5
R/W
3
H'0D/H'00*
Retained
H'FDEB
Pin function control register
PFCR
Notes: 1. Lower 16 bits of the address.
2. Determined by the MCU operating mode. Initialized to H'00 in mode 4, and to H'FF in
modes 5 to 7.
3. Initialized to H'0D in modes 4 and 5, and to H'00 in modes 6 and 7.
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Section 6 Bus Controller
6.2
Register Descriptions
6.2.1
Bus Width Control Register (ABWCR)
Bit
:
Modes 5 to 7
Initial value :
RW
:
7
6
5
4
3
2
1
0
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode 4
Initial value :
RW
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or
16-bit access.
ABWCR sets the data bus width for the external memory space. The bus width for on-chip
memory and internal I/O registers is fixed regardless of the settings in ABWCR.
After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5,
6, and 7, and to H'00 in mode 4. It is not initialized by a manual reset or in software standby mode.
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the
corresponding area is to be designated for 8-bit access or 16-bit access.
Bit n
ABWn
Description
0
Area n is designated for 16-bit access
1
Area n is designated for 8-bit access
(n = 7 to 0)
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Section 6 Bus Controller
6.2.2
Bit
Access State Control Register (ASTCR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access
space or a 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is to be designated as a 2-state access space or a 3-state access space.
Wait state insertion is enabled or disabled at the same time.
Bit n
ASTn
Description
0
Area n is designated for 2-state access
Wait state insertion in area n external space is disabled
1
Area n is designated for 3-state access
Wait state insertion in area n external space is enabled
(Initial value)
(n = 7 to 0)
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Section 6 Bus Controller
6.2.3
Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait
states for each area.
Program waits are not inserted in the case of on-chip memory or internal I/O registers.
WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode.
They are not initialized by a manual reset or in software standby mode.
(1) WCRH
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
W71
W70
W61
W60
W51
W50
W41
W40
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of
program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set
to 1.
Bit 7
Bit 6
W71
W70
Description
0
0
Program wait not inserted when external space area 7 is accessed
1
1 program wait state inserted when external space area 7 is accessed
0
2 program wait states inserted when external space area 7 is accessed
1
3 program wait states inserted when external space area 7 is accessed
(Initial value)
1
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Section 6 Bus Controller
Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of
program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set
to 1.
Bit 5
Bit 4
W61
W60
Description
0
0
Program wait not inserted when external space area 6 is accessed
1
1 program wait state inserted when external space area 6 is accessed
0
2 program wait states inserted when external space area 6 is accessed
1
3 program wait states inserted when external space area 6 is accessed
(Initial value)
1
Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of
program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set
to 1.
Bit 3
Bit 2
W51
W50
Description
0
0
Program wait not inserted when external space area 5 is accessed
1
1 program wait state inserted when external space area 5 is accessed
0
2 program wait states inserted when external space area 5 is accessed
1
3 program wait states inserted when external space area 5 is accessed
(Initial value)
1
Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of
program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set
to 1.
Bit 1
Bit 0
W41
W40
Description
0
0
Program wait not inserted when external space area 4 is accessed
1
1 program wait state inserted when external space area 4 is accessed
0
2 program wait states inserted when external space area 4 is accessed
1
3 program wait states inserted when external space area 4 is accessed
(Initial value)
1
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Section 6 Bus Controller
(2) WCRL
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
W31
W30
W21
W20
W11
W10
W01
W00
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of
program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set
to 1.
Bit 7
Bit 6
W31
W30
Description
0
0
Program wait not inserted when external space area 3 is accessed
1
1 program wait state inserted when external space area 3 is accessed
0
2 program wait states inserted when external space area 3 is accessed
1
3 program wait states inserted when external space area 3 is accessed
(Initial value)
1
Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of
program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set
to 1.
Bit 5
Bit 4
W21
W20
Description
0
0
Program wait not inserted when external space area 2 is accessed
1
1 program wait state inserted when external space area 2 is accessed
0
2 program wait states inserted when external space area 2 is accessed
1
3 program wait states inserted when external space area 2 is accessed
(Initial value)
1
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Section 6 Bus Controller
Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of
program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set
to 1.
Bit 3
Bit 2
W11
W10
Description
0
0
Program wait not inserted when external space area 1 is accessed
1
1 program wait state inserted when external space area 1 is accessed
0
2 program wait states inserted when external space area 1 is accessed
1
3 program wait states inserted when external space area 1 is accessed
(Initial value)
1
Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1
Bit 0
W01
W00
Description
0
0
Program wait not inserted when external space area 0 is accessed
1
1 program wait state inserted when external space area 0 is accessed
0
2 program wait states inserted when external space area 0 is accessed
1
3 program wait states inserted when external space area 0 is accessed
(Initial value)
1
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Section 6 Bus Controller
6.2.4
Bit
Bus Control Register H (BCRH)
:
Initial value :
R/W
:
7
6
ICIS1
ICIS0
1
1
0
1
0
R/W
R/W
R/W
R/W
R/W
5
4
3
BRSTRM BRSTS1 BRSTS0
2
1
0
—
—
—
0
0
0
R/W
R/W
R/W
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for area 0.
BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1
Description
0
Idle cycle not inserted in case of successive external read cycles in different areas
1
Idle cycle inserted in case of successive external read cycles in different areas
(Initial value)
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed.
Bit 6
ICIS0
Description
0
Idle cycle not inserted in case of successive external read and external write cycles
1
Idle cycle inserted in case of successive external read and external write cycles
(Initial value)
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Section 6 Bus Controller
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM
interface.
Bit 5
BRSTRM
Description
0
Area 0 is basic bus interface
1
Area 0 is burst ROM interface
(Initial value)
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1
Description
0
Burst cycle comprises 1 state
1
Burst cycle comprises 2 states
(Initial value)
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
Description
0
Max. 4 words in burst access
1
Max. 8 words in burst access
Bits 2 to 0—Reserved: Only 0 should be written to these bits.
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(Initial value)
Section 6 Bus Controller
6.2.5
Bit
Bus Control Register L (BCRL)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
BRLE
—
—
—
—
—
—
WAITE
0
0
0
0
1
0
0
0
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'08 by a power-on reset and in hardware standby mode. It is not initialized
by a manual reset or in software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
Description
0
External bus release is disabled. BREQ and BACK can be used as I/O ports.
(Initial value)
1
External bus release is enabled.
Bit 6—Reserved: Only 0 should be written to this bit.
Bit 5—Reserved: This bit cannot be modified and is always read as 0.
Bit 4—Reserved: Only 0 should be written to this bit.
Bit 3—Reserved: Only 1 should be written to this bit.
Bits 2 and 1—Reserved: Only 0 should be written to these bits.
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE
Description
0
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port.
1
Wait input by WAIT pin enabled
(Initial value)
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Section 6 Bus Controller
6.2.6
Pin Function Control Register (PFCR)
7
6
5
4
3
2
1
0
—
—
—
—
AE3
AE2
AE1
AE0
:
0
0
0
0
1
1
0
1
Initial value
:
0
0
0
0
0
0
0
0
R/W
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
:
Modes 4 and 5
Initial value
Modes 6 and 7
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
PFCR is initialized to H'0D (modes 4 and 5) or H'00 (modes 6 and 7) by a power-on reset and in
hardware standby mode. It retains its previous state in a manual reset and in software standby
mode.
Bits 7 to 4—Reserved: Only 0 should be written to these bits.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or
disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When
a pin is enabled for address output, the address is output regardless of the corresponding DDR
setting. When a pin is disabled for address output, it becomes an output port when the
corresponding DDR bit is set to 1.
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Section 6 Bus Controller
Bit 3
Bit 2
Bit 1
Bit 0
AE3
AE2
AE1
AE0
Description
0
0
0
0
A8 to A23 output disabled
1
A8 output enabled; A9 to A23 output disabled
0
A8, A9 output enabled; A10 to A23 output disabled
1
A8 to A10 output enabled; A11 to A23 output disabled
0
A8 to A11 output enabled; A12 to A23 output disabled
1
A8 to A12 output enabled; A13 to A23 output disabled
1
0
A8 to A13 output enabled; A14 to A23 output disabled
1
A8 to A14 output enabled; A15 to A23 output disabled
0
0
A8 to A15 output enabled; A16 to A23 output disabled
1
A8 to A16 output enabled; A17 to A23 output disabled
0
A8 to A17 output enabled; A18 to A23 output disabled
1
A8 to A18 output enabled; A19 to A23 output disabled
0
A8 to A19 output enabled; A20 to A23 output disabled
1
A8 to A20 output enabled; A21 to A23 output disabled
(Initial value*2)
0
A8 to A21 output enabled; A22, A23 output disabled
1
A8 to A23 output enabled
1
1
1
0
0
1
1
0
1
(Initial value*1)
Notes: 1. In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.
In expanded mode with ROM, address pins A0 to A7 are made address outputs by
setting the corresponding DDR bits to 1.
2. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.
In ROMless expanded mode, address pins A0 to A7 are always made address output.
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Section 6 Bus Controller
6.3
Overview of Bus Control
6.3.1
Area Divisions
In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to
7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it
controls a 64-kbyte address space comprising part of area 0. Figure 6.2 shows an outline of the
memory map.
Chip select signals (CS0 to CS7) can be output for each area.
Note: * Not available in the H8S/2214 Group.
H'000000
H'0000
Area 0
(2 Mbytes)
H'1FFFFF
H'200000
Area 1
(2 Mbytes)
H'3FFFFF
H'400000
Area 2
(2 Mbytes)
H'FFFF
H'5FFFFF
H'600000
Area 3
(2 Mbytes)
H'7FFFFF
H'800000
Area 4
(2 Mbytes)
H'9FFFFF
H'A00000
Area 5
(2 Mbytes)
H'BFFFFF
H'C00000
Area 6
(2 Mbytes)
H'DFFFFF
H'E00000
Area 7
(2 Mbytes)
H'FFFFFF
(1)
Advanced mode
(2)
Normal mode*
Note: * Not available in the H8S/2214 Group.
Figure 6.2 Overview of Area Divisions
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Section 6 Bus Controller
6.3.2
Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access
states, and number of program wait states.
The bus width and number of access states for on-chip memory and internal I/O registers are
fixed, and are not affected by the bus controller.
(1) Bus Width
A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is
selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions
as a16-bit access space.
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit
access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is
always set.
(2) Number of Access States
Two or three access states can be selected with ASTCR. An area for which 2-state access is
selected functions as a 2-state access space, and an area for which 3-state access is selected
functions as a 3-state access space.
With the burst ROM interface, the number of access states may be determined without regard to
ASTCR.
When 2-state access space is designated, wait insertion is disabled.
(3) Number of Program Wait States
When 3-state access space is designated by ASTCR, the number of program wait states to be
inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be
selected.
Table 6.3 shows the bus specifications for each basic bus interface area.
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Section 6 Bus Controller
Table 6.3
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR
ASTCR
WCRH, WCRL
ABWn
ASTn
Wn1
Wn0
Bus Width
Program Wait
Access States States
0
0
—
—
16
2
0
1
0
0
3
0
1
1
6.3.3
1
1
0
2
1
3
0
—
—
1
0
0
1
Bus Specifications (Basic Bus Interface)
8
2
0
3
0
1
1
0
2
1
3
Memory Interfaces
The H8S/2214 Group memory interfaces comprise a basic bus interface that allows direct
connection of ROM, SRAM, and so on, and a burst ROM interface (for area 0 only) that allows
direct connection of burst ROM.
An area for which the basic bus interface is designated functions as normal space, and an area for
which the burst ROM interface is designated functions as burst ROM space.
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Section 6 Bus Controller
6.3.4
Interface Specifications for Each Area
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (see section 6.4, Basic Bus Interface, and 6.5,
Burst ROM Interface) should be referred to for further details.
(1) Area 0
Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external
space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
(2) Areas 1 to 6
In external expansion mode, all of areas 1 to 6 is external space.
When area 1 to 6 external space is accessed, the CS1 to CS6 pin signals respectively can be
output.
Only the basic bus interface can be used for areas 1 to 6.
(3) Area 7
Area 7 includes the on-chip RAM, external module expansion function space, and internal l/O
registers. In external expansion mode, the space excluding the on-chip RAM, external module
expansion function space, and internal l/O registers, is external space. The on-chip RAM is
enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME
bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external
space.
When the P75MSOE bit in the external module connection output pin select register (OPINSEL)
is set to 1, the external module expansion function is enabled and the signal is output for addresses
H'FFFF40 to H'FFFF5F. When the P75MSOE bit is cleared to 0, the external module expansion
function is disabled and the corresponding addresses are external space.
When area 7 external space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7.
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Section 6 Bus Controller
6.3.5
Chip Select Signals
The H8S/2214 Group can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being
driven low when the corresponding external space area is accessed.
Figure 6.3 shows an example of CSn (n = 0 to 7) output timing.
Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR)
for the port corresponding to the particular CSn pin.
In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding
DDR should be set to 1 when outputting signals CS1 to CS7.
In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a poweron reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS7.
For details, see section 9, I/O Ports.
Bus cycle
T1
T2
T3
φ
Address bus
Area n external address
CSn
Figure 6.3 CSn Signal Output Timing (n = 0 to 7)
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Section 6 Bus Controller
6.4
Basic Bus Interface
6.4.1
Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table
6.3).
6.4.2
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
(1) 8-Bit Access Space
Figure 6.4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be
accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and
a longword transfer instruction, as four byte accesses.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
Word size
1st bus cycle
2nd bus cycle
1st bus cycle
Longword size
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space)
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Section 6 Bus Controller
(2) 16-Bit Access Space
Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access
space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The
amount of data that can be accessed at one time is one byte or one word, and a longword transfer
instruction is executed as two word transfer instructions.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Lower data bus
Upper data bus
D15
D8 D7
D0
Byte size
• Even address
Byte size
• Odd address
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 6.5 Access Sizes and Data Alignment Control (16-Bit Access Space)
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Section 6 Bus Controller
6.4.3
Valid Strobes
Table 6.4 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 6.4
Area
8-bit access
space
Data Buses Used and Valid Strobes
Access Read/
Size
Write
Address
Valid
Strobe
Upper Data Bus
(D15 to D8)
Lower data bus
(D7 to D0)
Byte
Read
—
RD
Valid
Invalid
Write
—
HWR
Even
RD
16-bit access Byte
space
Read
Odd
Valid
Invalid
Invalid
Valid
Even
HWR
Valid
Hi-Z
Odd
LWR
Hi-Z
Valid
Read
—
RD
Valid
Valid
Write
—
HWR, LWR Valid
Valid
Write
Word
Hi-Z
Notes: Hi-Z: High impedance.
Invalid: Input state; input value is ignored.
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Section 6 Bus Controller
6.4.4
Basic Timing
(1) 8-Bit 2-State Access Space
Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used.
Wait states cannot be inserted.
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
LWR
(16-bit bus mode)
High
LWR
(8-bit bus mode)
High impedance
D15 to D8
Valid
D7 to D0
High impedance
Note: n = 0 to 7
Figure 6.6 Bus Timing for 8-Bit 2-State Access Space
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Section 6 Bus Controller
(2) 8-Bit 3-State Access Space
Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used.
Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
(16-bit bus mode)
High
Write
LWR
(8-bit bus mode)
D15 to D8
D7 to D0
High impedance
Valid
High impedance
Note: n = 0 to 7
Figure 6.7 Bus Timing for 8-Bit 3-State Access Space
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Section 6 Bus Controller
(3) 16-Bit 2-State Access Space
Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space
is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower
half (D7 to D0) for the odd address.
Wait states cannot be inserted.
Bus cycle
T1
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Note: n = 0 to 7
Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (Even Address Byte Access)
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Section 6 Bus Controller
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
D7 to D0
High impedance
Valid
Note: n = 0 to 7
Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (Odd Address Byte Access)
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Section 6 Bus Controller
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Note: n = 0 to 7
Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (Word Access)
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Section 6 Bus Controller
(4) 16-Bit 3-State Access Space
Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access
space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the
lower half (D7 to D0) for the odd address.
Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Note: n = 0 to 7
Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (Even Address Byte Access)
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Section 6 Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
D7 to D0
High impedance
Valid
Note: n = 0 to 7
Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (Odd Address Byte Access)
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Section 6 Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Note: n = 0 to 7
Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (Word Access)
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Section 6 Bus Controller
6.4.5
Wait Control
When accessing external space, the H8S/2214 Group can extend the bus cycle by inserting one or
more wait states (Tw). There are two ways of inserting wait states: (1) program wait insertion and
(2) pin wait insertion using the WAIT pin.
(1) Program Wait Insertion
From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an
individual area basis in 3-state access space, according to the settings of WCRH and WCRL.
(2) Pin Wait Insertion
Setting the WAITE bit in BCRH to 1 enables wait insertion by means of the WAIT pin. When
external space is accessed in this state, program wait insertion is first carried out according to the
settings in WCRH and WCRL. Then, if the WAIT pin is low at the falling edge of φ in the last T2
or TW state, a TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes
high.
This is useful when inserting four or more TW states, or when changing the number of TW states for
different external devices.
The WAITE bit setting applies to all areas.
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Section 6 Bus Controller
Figure 6.14 shows an example of wait state insertion timing.
By program wait By WAIT pin
T1
T2
TW
TW
TW
T3
φ
WAIT
Address bus
AS
RD
Read
Data bus
Read data
HWR, LWR
Write
Data bus
Note:
Write data
indicates the timing of WAIT pin sampling.
Figure 6.14 Example of Wait State Insertion Timing
The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT
input disabled. When a manual reset is performed, the contents of bus controller registers are
retained, and the wait control settings remain the same as before the reset.
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Section 6 Bus Controller
6.5
Burst ROM Interface
6.5.1
Overview
With the H8S/2214 Group, external space area 0 can be designated as burst ROM space, and burst
ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration
ROM with burst access capability to be accessed at high speed.
Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH.
Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU
instruction fetches only. One or two states can be selected for burst access.
6.5.2
Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is in accordance
with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state
insertion is possible. One or two states can be selected for the burst cycle, according to the setting
of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst
ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR.
When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when
the BRSTS0 bit is set to 1, burst access of up to 8 words is performed.
The basic access timing for burst ROM space is shown in figures 6.15 and 6.16. The timing shown
in figure 6.15 is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure
6.16 is for the case where both these bits are cleared to 0.
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Section 6 Bus Controller
Full access
T1
T2
Burst access
T3
T1
T2
T1
T2
φ
Only lower address changed
Address bus
CS0
AS
RD
Data bus
Read data
Read data
Read data
Figure 6.15 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
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Section 6 Bus Controller
Full access
T1
T2
Burst access
T1
T1
φ
Only lower address changed
Address bus
CS0
AS
RD
Data bus
Read data
Read data Read data
Figure 6.16 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)
6.5.3
Wait Control
As with the basic bus interface, either (1) program wait insertion or (2) pin wait insertion using the
WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section
6.4.5, Wait Control.
Wait states cannot be inserted in a burst cycle.
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Section 6 Bus Controller
6.6
Idle Cycle
6.6.1
Operation
When the H8S/2214 Group accesses external space, it can insert a 1-state idle cycle (TI) between
bus cycles in the following two cases: (1) when read accesses between different areas occur
consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an
idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output
floating time, and high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle.
Figure 6.17 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Bus cycle A
φ
T1
T2
Bus cycle B
T3
T1
Bus cycle A
T2
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
Data bus
Data bus
Long output
floating time
(a) Idle cycle not inserted
(ICIS1 = 0)
T1
T2
T3
Bus cycle B
TI
T1
T2
Data
collision
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 6.17 Example of Idle Cycle Operation (1)
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Section 6 Bus Controller
(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle.
Figure 6.18 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
T1
T2
Bus cycle B
T3
T1
Bus cycle A
T1
T2
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
HWR
HWR
Data bus
Data bus
Long output
floating time
(a) Idle cycle not inserted
(ICIS1 = 0)
T2
TI
T1
Data
collision
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 6.18 Example of Idle Cycle Operation (2)
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T3
Bus cycle B
T2
Section 6 Bus Controller
(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 6.19.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
T2
T3
Bus cycle B
TI
T1
T2
Possibility of overlap between
CS (area B) and RD
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 6.19 Relationship between Chip Select (CS) and Read (RD)
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Section 6 Bus Controller
6.6.2
Pin States in Idle Cycle
Table 6.5 shows pin states in an idle cycle.
Table 6.5
Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of next bus cycle
D15 to D0
High impedance
CSn
High
AS
High
RD
High
HWR
High
LWR
High
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Section 6 Bus Controller
6.7
Bus Release
6.7.1
Overview
The H8S/2214 Group can release the external bus in response to a bus request from an external
device. In the external bus released state, the internal bus master continues to operate as long as
there is no external access.
6.7.2
Operation
In external expansion mode, the bus can be released to an external device by setting the BRLE bit
in BCRL to 1. Driving the BREQ pin low issues an external bus request to this LSI. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus-released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus request from the external bus master to be
dropped.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
In the event of simultaneous external bus release request and external access request generation,
the order of priority is as follows:
(High) External bus release > Internal bus master external access (Low)
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Section 6 Bus Controller
6.7.3
Pin States in External Bus Released State
Table 6.6 shows pin states in the external bus released state.
Table 6.6
Pin States in Bus Released State
Pins
Pin State
A23 to A0
High impedance
D15 to D0
High impedance
CSn
High impedance
AS
High impedance
RD
High impedance
HWR
High impedance
LWR
High impedance
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Section 6 Bus Controller
6.7.4
Transition Timing
Figure 6.20 shows the timing for transition to the bus-released state.
CPU cycle
T0
CPU
cycle
External bus released state
T1
T2
φ
High impedance
Address bus
Address
High impedance
Data bus
High impedance
CSn
High impedance
AS
High impedance
RD
High impedance
HWR, LWR
BREQ
BACK
Minimum
1 state
[1]
[1]
[2]
[3]
[4]
[5]
[2]
[3]
[4]
[5]
Low level of BREQ pin is sampled at rise of T2 state.
BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
Note: n = 0 to 7
Figure 6.20 Bus-Released State Transition Timing
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Section 6 Bus Controller
6.7.5
Usage Note
When MSTPCR is set to H'FFFFFF and a transition is made to sleep mode, the external bus
release function halts. Therefore, MSTPCR should not be set to H'FFFFFF if the external bus
release function is to be used in sleep mode.
6.8
Bus Arbitration
6.8.1
Overview
The H8S/2214 Group has a bus arbiter that arbitrates bus master operations.
There are three bus masters, the CPU, DMAC, and DTC, which perform read/write operations
when they have possession of the bus. Each bus master requests the bus by means of a bus request
signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by
means of a bus request acknowledge signal. The selected bus master then takes possession of the
bus and begins its operation.
6.8.2
Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
more than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is canceled.
The order of priority of the bus masters is as follows:
(High) DMAC > DTC > CPU (Low)
An internal bus access by an internal bus master, and external bus release, can be executed in
parallel.
In the event of simultaneous external bus release request, and internal bus master external access
request generation, the order of priority is as follows:
(High) External bus release > Internal bus master external access (Low)
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Section 6 Bus Controller
6.8.3
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
(1) CPU
The CPU is the lowest-priority bus master, and if a bus request is received from the DMAC and
DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for
transfer of the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the operations. See appendix A.5, Bus States during Instruction Execution, for timings at
which the bus is not transferred.
• If the CPU is in sleep mode, it transfers the bus immediately.
(2) DTC
The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
(3) DMAC
The DMAC sends the bus arbiter a request for the bus when an activation request is generated.
In the case of an external request in short address mode or normal mode, and in cycle steal mode,
the DMAC releases the bus after a single transfer.
In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after
completion of the transfer.
6.8.4
External Bus Release Usage Note
External bus release can be performed on completion of an external bus cycle. The CS signal
remains low until the end of the external bus cycle. Therefore, when external bus release is
performed, the CS signal may change from the low level to the high-impedance state.
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Section 6 Bus Controller
6.9
Resets and the Bus Controller
In a power-on reset, the H8S/2214 Group, including the bus controller, enters the reset state at that
point, and an executing bus cycle is discontinued.
In a manual reset, the bus controller’s registers and internal state are maintained, and an executing
external bus cycle is completed. In this case, WAIT input is ignored and write data is not
guaranteed.
6.10
External Module Expansion Function
6.10.1
Overview
The H8S/2214 Group has an external module expansion function to provide for the addition of
peripheral devices. Using this function to provide a combination of H8S/2214 Group and external
modules makes it possible to implement a multichip system on the user board.
Figure 6.21 shows a block diagram.
Bus access states can be changed by means of a bus controller setting.
The EXMS signal is output to external modules for addresses H'FFFF40 to H'FFFF5F.
Priority and DTC activation can be specified for interrupts EXIRQ7 to EXIRQ0 in the same way
as for the H8S/2214’s on-chip supporting functions.
The DTC data transfer end signal for EXIRQ7 to EXIRQ0 interrupt input is output from
EXDTCE. Also, the inverse of the value of bit 0 in module stop control register B is output from
EXMSTP.
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Section 6 Bus Controller
A23 to A0
D15 to D0
H8S/2214
Group
EXMSTP
External module
EXMS
EXDTCE
EXIRQ7 to EXIRQ0
Figure 6.21 Multichip Block Diagram
6.10.2
Pin Configuration
Table 6.7 summarizes the pins of the external module expansion function.
Table 6.7
External Module Expansion Function Pins
Name
Symbol
I/O
Function
External expansion
interrupt request 7 to 0
EXIRQ7 to
EXIRQ0
Input
Input pins for interrupt requests from
external modules
External expansion
module select
EXMS
Output
Select signal for external modules
External expansion
DTC transfer end
EXDTCE
Output
DTC transfer end signal for EXIRQ7 to
EXIRQ0 interrupt input
External expansion
module stop
EXMSTP
Output
Module stop signal for external
modules
6.10.3
Register Configuration
Table 6.8 summarizes the registers of the bus controller.
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Section 6 Bus Controller
Table 6.8
Bus Controller Registers
Initial Value
R/W
Power-On
Reset
Manual
Reset
Address*
Interrupt request input pin select IPINSEL0
register 0
R/W
H'00
Retained
H'FE4A
External module connection
output pin select register
OPINSEL
R/W
B'-000----
Retained
H'FE4E
Module stop control register B
MSTPCRB
R/W
H'FF
H'FF
H'FDE9
Name
Abbreviation
Note: * Lower 16 bits of the address.
6.10.4
Interrupt Request Input Pin Select Register 0 (IPINSEL0)
Bit
:
Initial value :
R/W
:
7
P36
IRQ7E
6
P47
IRQ6E
5
P46
IRQ5E
4
P44
IRQ4E
3
P43
IRQ3E
2
P42
IRQ2E
1
P41
IRQ1E
0
P40
IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IPINSEL0 is an 8-bit readable/writable register that selects which pins are to be used for interrupt
request input signals (EXIRQ7 to EXIRQ0) from externally connected modules when operating as
H8S/2214 modules. IPINSEL0 is initialized to H'00 by a power-on reset and in hardware standby
mode. It retains its previous state in a manual reset and in software standby mode.
Bit 7—Enable of EXIRQ7 Input from P36 (P36IRQ7E): Selects whether or not P36 is used as
the EXIRQ7 input pin.
Bit 7
P36IRQ7E
Description
0
P36 is not used as EXIRQ7 input
1
P36 is used as EXIRQ7 input
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(Initial value)
Section 6 Bus Controller
Bit 6—Enable of EXIRQ6 Input from P47 (P47IRQ6E): Selects whether or not P47 is used as
the EXIRQ6 input pin.
Bit 6
P47IRQ6E
Description
0
P47 is not used as EXIRQ6 input
1
P47 is used as EXIRQ6 input
(Initial value)
Bit 5—Enable of EXIRQ5 Input from P46 (P46IRQ5E): Selects whether or not P46 is used as
the EXIRQ5 input pin.
Bit 5
P46IRQ5E
Description
0
P46 is not used as EXIRQ5 input
1
P46 is used as EXIRQ5 input
(Initial value)
Bit 4—Enable of EXIRQ4 Input from P44 (P44IRQ4E): Selects whether or not P44 is used as
the EXIRQ4 input pin.
Bit 4
P44IRQ4E
Description
0
P44 is not used as EXIRQ4 input
1
P44 is used as EXIRQ4 input
(Initial value)
Bit 3—Enable of EXIRQ3 Input from P43 (P43IRQ3E): Selects whether or not P43 is used as
the EXIRQ3 input pin.
Bit 3
P43IRQ3E
Description
0
P43 is not used as EXIRQ3 input
1
P43 is used as EXIRQ3 input
(Initial value)
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Section 6 Bus Controller
Bit 2—Enable of EXIRQ2 Input from P42 (P42IRQ2E): Selects whether or not P42 is used as
the EXIRQ2 input pin.
Bit 2
P42IRQ2E
Description
0
P42 is not used as EXIRQ2 input
1
P42 is used as EXIRQ2 input
(Initial value)
Bit 1—Enable of EXIRQ1 Input from P41 (P41IRQ1E): Selects whether or not P41 is used as
the EXIRQ1 input pin.
Bit 1
P41IRQ1E
Description
0
P41 is not used as EXIRQ1 input
1
P41 is used as EXIRQ1 input
(Initial value)
Bit 0—Enable of EXIRQ0 Input from P40 (P40IRQ0E): Selects whether or not P40 is used as
the EXIRQ0 input pin.
Bit 0
P40IRQ0E
Description
0
P40 is not used as EXIRQ0 input
1
P40 is used as EXIRQ0 input
6.10.5
Bit
External Module Connection Output Pin Select Register (OPINSEL)
:
7
—
Initial value :
R/W
(Initial value)
:
6
P76
STPOE
5
P75
MSOE
4
P74
DTCOE
Undefined
0
0
0
R/W
R/W
R/W
R/W
3
2
1
0
—
—
—
—
Undefined Undefined Undefined Undefined
—
—
—
—
OPINSEL is an 8-bit readable/writable register that selects whether or not output signals
(EXDTCEN, EXMSTP, EXMSN) to externally connected modules are output to pins P77 to P74
in H8S/2214 Group operation. OPINSEL bits 6 to 4 are initialized to 000 by a power-on reset and
in hardware standby mode. They retain their previous states in a manual reset and in software
standby mode.
Rev.4.00 Sep. 18, 2008 Page 168 of 872
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Section 6 Bus Controller
Bit 7—Reserved: This bit will return an undefined value if read, and should only be written with
0.
Bit 6—Enable of EXMSTP Output to P76 (P76STPOE): Selects whether or not the EXMSTP
module stop signal to external modules (corresponding to bit 0 in MSTPCRB) is output to P76.
Bit 6
P76STPOE
Description
0
EXMSTP is not output to P76
1
EXMSTP is output to P76
(Initial value)
Bit 5—Enable of EXMS Output to P75 (P75MSOE): Selects whether or not the EXMS module
stop signal to external modules (corresponding to addresses H'FFFF40 to H'FFFF5F) is output to
P75.
Bit 5
P75MSOE
Description
0
EXMS is not output to P75
1
EXMS is output to P75
(Initial value)
Bit 4—Enable of EXDTCE Output to P74 (P74DTCOE): Selects whether or not the EXDTCE
signal, indicating that DTC transfer corresponding to EXIRQ0—F input is in progress, is output to
P74. This signal is used, for example, when the DTC in the chip has been activated by an interrupt
(EXIRQ0 to EXIRQF) from an external module, and the interrupt request is to be cleared
automatically on the external module side by DTC transfer.
Bit 4
P74DTCOE
Description
0
EXDTCE is not output to P74
1
EXDTCE is output to P74
(Initial value)
Bits 3 to 0—Reserved: These bits will return an undefined value if read, and should only be
written with 0.
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Section 6 Bus Controller
6.10.6
Bit
Module Stop Control Register B (MSTPCRB)
:
7
6
5
4
3
2
0
1
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
Initial value :
R/W
:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRB is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPB0 bit is set to 1, the external module expansion function stops operation at the
end of the bus cycle, and enters module stop mode. For details, see section 17.5, Module Stop
Mode.
MSTPCRB is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 0—Module Stop (MSTPB0): Specifies the external module expansion function module stop
mode.
Bit 0
MSTPB0
Description
0
External module expansion function module stop mode is cleared
1
External module expansion function module stop mode is set
Rev.4.00 Sep. 18, 2008 Page 170 of 872
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(Initial value)
Section 6 Bus Controller
6.10.7
Basic Timing
Figure 6.22 shows the timing of external module area (H'FFFF40 to H'FFFF5F) DTC data transfer
using 3-state access.
External module area read
T1
T2
T3
Write
T1
T2
T3
φ
Address
EXMS
RD
EXDTCE
(a) Timing of external module area read by DTC
Read
T1
T2
External module area write
T3
T1
T2
T3
φ
Address
EXMS
WR
EXDTCE
(b) Timing of external module area write by DTC
Figure 6.22 Timing of External Module Area Access by DTC
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Section 6 Bus Controller
6.10.8
Notes on Use of External Module Extended Functions
When accessing addresses in the range H'FFFF40 to H'FFFF5F in the LSI’s on-chip ROM valid
extended mode (mode 6), care must be taken with regard to the following.
Figure 6.23 is an address map for the on-chip ROM valid extended mode (mode 6). When bit
P75MSOE in the external module connection output pin register (OPINSEL) is set to 1 and EXMS
output from pin 75 is enabled, accessing external address [3] (address range: H'FFFF40 to
H'FFFF5F) causes low-level output from EXMS. This low-level output is maintained thereafter
even if on-chip ROM, on-chip RAM, or the on-chip I/O registers are accessed.
As a countermeasure, output from EXMS can be driven high by accessing external addresses [1]
and [2]. Consequently, after accessing external address [3], make sure to perform a dummy read of
1 byte to external addresses [1] and [2] to drive output from EXMS high before accessing on-chip
RAM or the on-chip I/O registers.
EXMS output state
H'000000
On-chip ROM
H'020000
H'FFB000
H'FFC000
H'FFEFC0
H'FFF800
H'FFFF40
H'FFFF60
H'FFFFC0
External address [1]
Previous value maintained
High
Reserved area
Previous value maintained
On-chip RAM
Previous value maintained
External address [2]
High
Internal I/O registers
Previous value maintained
External address [3]
Low
Internal I/O registers
Previous value maintained
On-chip RAM
Previous value maintained
H'FFFFFF
Figure 6.23 On-Chip ROM Valid Extended Mode (Mode 6) Address Map
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Section 7 DMA Controller
Section 7 DMA Controller
7.1
Overview
The H8S/2214 Group has an on-chip DMA controller (DMAC) which can carry out data transfer
on up to 4 channels.
7.1.1
Features
The features of the DMAC are listed below.
• Choice of short address mode or full address mode
Short address mode
⎯ Maximum of 4 channels can be used
⎯ Choice of dual address mode
⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as16 bits
⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode
Full address mode
⎯ Maximum of 2 channels can be used
⎯ Transfer source and transfer destination address specified as 24 bits
⎯ Choice of normal mode or block transfer mode
• 16-Mbyte address space can be specified directly
• Byte or word can be set as the transfer unit
• Activation sources: internal interrupt, external request, auto-request (depending on transfer
mode)
⎯ Three 16-bit timer-pulse unit (TPU) compare match/input capture interrupts
⎯ Serial communication interface (SCI0, SCI1) transmission complete interrupt, reception
complete interrupt
⎯ External request
⎯ Auto-request
• Module stop mode can be set
⎯ The initial setting enables DMAC registers to be accessed. DMAC operation is halted by
setting module stop mode
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Section 7 DMA Controller
7.1.2
Block Diagram
A block diagram of the DMAC is shown in figure 7.1.
Internal address bus
Address buffer
Internal interrupts
TGI0A
TGI1A
TGI2A
DMATCR
DMACR0A
DMACR0B
DMACR1A
DMACR1B
DMABCR
Data buffer
Internal data bus
Legend:
DMAWER:
DMATCR:
DMABCR:
DMACR:
MAR:
IOAR:
ETCR:
DMA write enable register
DMA terminal control register
DMA band control register (for all channels)
DMA control register
Memory address register
I/O address register
Executive transfer counter register
Figure 7.1 Block Diagram of DMAC
Rev.4.00 Sep. 18, 2008 Page 174 of 872
REJ09B0189-0400
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
Module data bus
DMAWER
Channel 1B Channel 1A Channel 0B Channel 0A
Channel 0
Control logic
Channel 1
TXI0
RXI0
TXI1
RXI1
External pins
DREQ0
DREQ1
TEND0
TEND1
Interrupt signals
DEND0A
DEND0B
DEND1A
DEND1B
Processor
Section 7 DMA Controller
7.1.3
Overview of Functions
Tables 7.1 and 7.2 summarize DMAC functions in short address mode and full address mode,
respectively.
Table 7.1
Overview of DMAC Functions (Short Address Mode)
Address Register Bit Length
Transfer Mode
Transfer Source
Dual address mode
•
TPU channel 0 to 24/16
2 compare
match/input
capture A interrupt
•
SCI transmission
complete interrupt
•
SCI reception
complete interrupt
•
External request
•
Sequential mode
⎯ 1-byte or 1-word transfer
executed for one transfer request
⎯ Memory address
incremented/decremented by 1
or 2
⎯ 1 to 65536 transfers
•
Idle mode
Source
Destination
16/24
⎯ 1-byte or 1-word transfer
executed for one transfer request
⎯ Memory address fixed
⎯ 1 to 65536 transfers
•
Repeat mode
⎯ 1-byte or 1-word transfer
executed for one transfer request
⎯ Memory address incremented/
decremented by 1 or 2
⎯ After specified number of
transfers (1 to 256), initial state is
restored and operation continues
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Section 7 DMA Controller
Table 7.2
Overview of DMAC Functions (Full Address Mode)
Address Register Bit Length
Transfer Mode
Transfer Source
Source
Destination
•
•
Auto-request
24
24
•
External request
•
TPU channel 0 to 24
2 compare
match/input
capture A interrupt
24
⎯ Either source or destination
specifiable as block area
•
SCI transmission
complete interrupt
⎯ Block size: 1 to 256 bytes or
words
•
SCI reception
complete interrupt
•
External request
Normal mode
Auto-request
⎯ Transfer request retained
internally
⎯ Transfers continue for the
specified number of times (1 to
65536)
⎯ Choice of burst or cycle steal
transfer
External request
⎯ 1-byte or 1-word transfer
executed for one transfer request
⎯ 1 to 65536 transfers
•
Block transfer mode
⎯ Specified block size transfer
executed for one transfer request
⎯ 1 to 65536 transfers
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Section 7 DMA Controller
7.1.4
Pin Configuration
Table 7.3 summarizes the DMAC pins.
In short address mode, external request transfer, and transfer end output are not performed for
channel A.
When the DREQ pin is used, do not designate the corresponding port for output.
With regard to the TEND pins, whether or not the corresponding port is used as a TEND pin can
be specified by means of a register setting.
Table 7.3
DMAC Pins
Channel
Pin Name
Symbol
I/O
Function
0
DMA request 0
DREQ0
Input
DMAC channel 0 external
request
DMA transfer end 0
TEND0
Output
DMAC channel 0 transfer end
DMA request 1
DREQ1
Input
DMAC channel 1 external
request
DMA transfer end 1
TEND1
Output
DMAC channel 1 transfer end
1
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Section 7 DMA Controller
7.1.5
Register Configuration
Table 7.4 summarizes the DMAC registers.
Table 7.4
DMAC Registers
Channel Name
Abbreviation R/W
Initial
Value
0
Memory address register 0A
MAR0A
R/W
Undefined H'FEE0
16 bits
I/O address register 0A
IOAR0A
R/W
Undefined H'FEE4
16 bits
Transfer count register 0A
ETCR0A
R/W
Undefined H'FEE6
16 bits
Memory address register 0B
MAR0B
R/W
Undefined H'FEE8
16 bits
I/O address register 0B
IOAR0B
R/W
Undefined H'FEEC
16 bits
1
0, 1
Address* Bus Width
Transfer count register 0B
ETCR0B
R/W
Undefined H'FEEE
16 bits
Memory address register 1A
MAR1A
R/W
Undefined H'FEF0
16 bits
I/O address register 1A
IOAR1A
R/W
Undefined H'FEF4
16 bits
Transfer count register 1A
ETCR1A
R/W
Undefined H'FEF6
16 bits
Memory address register 1B
MAR1B
R/W
Undefined H'FEF8
16 bits
I/O address register 1B
IOAR1B
R/W
Undefined H'FEFC
16 bits
Transfer count register 1B
ETCR1B
R/W
Undefined H'FEFE
16 bits
DMA write enable register
DMAWER
R/W
H'00
H'FF60
8 bits
DMA terminal control register DMATCR
R/W
H'00
H'FF61
8 bits
DMA control register 0A
DMACR0A
R/W
H'00
H'FF62
16 bits
DMA control register 0B
DMACR0B
R/W
H'00
H'FF63
16 bits
DMA control register 1A
DMACR1A
R/W
H'00
H'FF64
16 bits
DMA control register 1B
DMACR1B
R/W
H'00
H'FF65
16 bits
DMA band control register
DMABCR
R/W
H'0000
H'FF66
16 bits
R/W
H'3F
H'FDE8
8 bits
Module stop control register A MSTPCRA
Note: * Lower 16 bits of the address.
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Section 7 DMA Controller
7.2
Register Descriptions (1) (Short Address Mode)
Short address mode transfer can be performed for channels A and B independently.
Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to
0, as shown in table 7.5. Short address mode or full address mode can be selected for channels 1
and 0 independently by means of bits FAE1 and FAE0.
Table 7.5
Short Address Mode and Full Address Mode (For 1 Channel: Example of
Channel 0)
0
Short address mode specified (channels A and B operate independently)
MAR0A
MAR0B
Specifies transfer source/transfer destination address
IOAR0A
Specifies transfer destination/transfer source address
ETCR0A
Specifies number of transfers
DMACR0A
Specifies transfer size, mode, activation source, etc.
Specifies transfer source/transfer destination address
IOAR0B
Specifies transfer destination/transfer source address
ETCR0B
Specifies number of transfers
DMACR0B
Specifies transfer size, mode, activation source, etc.
Full address mode specified (channels A and B operate in combination)
Channel 0
1
Channel 0A
Description
Channel 0B
FAE0
MAR0A
Specifies transfer source address
MAR0B
Specifies transfer destination address
IOAR0A
IOAR0B
ETCR0A
ETCR0B
DMACR0A DMACR0B
Not used
Not used
Specifies number of transfers
Specifies number of transfers (used in block transfer
mode only)
Specifies transfer size, mode, activation source, etc.
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Section 7 DMA Controller
7.2.1
Memory Address Register (MAR)
Bit
:
31
30
29
28
27
26
25
24
MAR
23
22
21
20
19
18
17
16
*
*
*
*
*
*
*
*
:
—
—
—
—
—
—
—
—
Initial value :
0
0
0
0
0
0
0
0
R/W
:
—
—
—
—
—
—
—
— R/W R/W R/W R/W R/W R/W R/W R/W
Bit
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MAR
:
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Initial value :
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
MAR is a 32-bit readable/writable register that specifies the transfer source address or destination
address.
The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified.
Whether MAR functions as the source address register or as the destination address register can be
selected by means of the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control
Register (DMACR).
MAR is not initialized by a reset or in standby mode.
7.2.2
I/O Address Register (IOAR)
Bit
:
IOAR
:
Initial value :
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
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Section 7 DMA Controller
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source
address or destination address. The upper 8 bits of the transfer address are automatically set to
H'FF.
Whether IOAR functions as the source address register or as the destination address register can
be selected by means of the DTDIR bit in DMACR.
IOAR is invalid in single address mode.
IOAR is not incremented or decremented each time a transfer is executed, so that the address
specified by IOAR is fixed.
IOAR is not initialized by a reset or in standby mode.
7.2.3
Execute Transfer Count Register (ETCR)
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of
this register is different for sequential mode and idle mode on the one hand, and for repeat mode
on the other.
(1) Sequential Mode and Idle Mode
Transfer Counter
Bit
:
ETCR
:
Initial value :
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range
of 1 to 65536). ETCR is decremented by 1 each time a transfer is performed, and when the count
reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends.
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Section 7 DMA Controller
(2) Repeat Mode
Transfer Number Storage
Bit
:
ETCRH
:
15
14
13
12
11
10
9
8
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value :
R/W
:
Transfer Counter
Bit
:
ETCRL
:
Initial value :
R/W
:
*: Undefined
In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and
transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is
performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this
point, MAR is automatically restored to the value it had when the count was started. The DTE bit
in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is
cleared by the user.
ETCR is not initialized by a reset or in standby mode.
7.2.4
DMA Control Register (DMACR)
Bit
:
7
6
5
4
3
2
1
0
DMACR
:
DTSZ
DTID
RPE
DTDIR
DTF3
DTF2
DTF1
DTF0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value :
R/W
:
DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.
DMACR is initialized to H'00 by a reset, and in standby mode.
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Section 7 DMA Controller
Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 7
DTSZ
Description
0
Byte-size transfer
1
Word-size transfer
(Initial value)
Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of
MAR every data transfer in sequential mode or repeat mode.
In idle mode, MAR is neither incremented nor decremented.
Bit 6
DTID
Description
0
MAR is incremented after a data transfer
1
(Initial value)
•
When DTSZ = 0, MAR is incremented by 1 after a transfer
•
When DTSZ = 1, MAR is incremented by 2 after a transfer
MAR is decremented after a data transfer
•
When DTSZ = 0, MAR is decremented by 1 after a transfer
•
When DTSZ = 1, MAR is decremented by 2 after a transfer
Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the
mode (sequential, idle, or repeat) in which transfer is to be performed.
Bit 5
DMABCR
RPE
DTIE
Description
0
0
Transfer in sequential mode (no transfer end interrupt)
1
Transfer in sequential mode (with transfer end interrupt)
0
Transfer in repeat mode (no transfer end interrupt)
1
Transfer in idle mode (with transfer end interrupt)
1
(Initial value)
For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode,
section 7.5.3, Idle Mode, and section 7.5.4, Repeat Mode.
Bit 4—Data Transfer Direction (DTDIR): To specify the data transfer direction (source or
destination).
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Section 7 DMA Controller
Bit 4
DTDIR
Description
0
Transfer with MAR as source address and IOAR as destination address (Initial value)
1
Transfer with IOAR as source address and MAR as destination address
Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor
(activation source). There are some differences in activation sources for channel A and for channel
B.
Channel A
Bit 3
Bit 2
Bit 1
Bit 0
DTF3
DTF2
DTF1
DTF0
Description
0
0
0
0
—
1
—
0
—
1
—
0
Activated by SCI channel 0 transmission complete interrupt
1
Activated by SCI channel 0 reception complete interrupt
0
Activated by SCI channel 1 transmission complete interrupt
1
Activated by SCI channel 1 reception complete interrupt
0
Activated by TPU channel 0 compare match/input capture
A interrupt
1
Activated by TPU channel 1 compare match/input capture
A interrupt
0
Activated by TPU channel 2 compare match/input capture
A interrupt
1
—
0
—
1
—
0
—
1
—
1
1
0
1
1
0
0
1
1
0
1
Rev.4.00 Sep. 18, 2008 Page 184 of 872
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(Initial value)
Section 7 DMA Controller
Channel B
Bit 3
Bit 2
Bit 1
Bit 0
DTF3
DTF2
DTF1
DTF0
Description
0
0
0
0
—
1
—
0
Activated by DREQ pin falling edge input*
1
Activated by DREQ pin low-level input
0
Activated by SCI channel 0 transmission complete interrupt
1
Activated by SCI channel 0 reception complete interrupt
0
Activated by SCI channel 1 transmission complete interrupt
1
Activated by SCI channel 1 reception complete interrupt
0
Activated by TPU channel 0 compare match/input capture
A interrupt
1
Activated by TPU channel 1 compare match/input capture
A interrupt
0
Activated by TPU channel 2 compare match/input capture
A interrupt
1
—
0
—
1
—
0
—
1
—
1
1
0
1
1
0
0
1
1
0
1
(Initial value)
Note: * Detected as a low level in the first transfer after transfer is enabled.
The same factor can be selected for more than one channel. In this case, activation starts with the
highest-priority channel according to the relative channel priorities. For relative channel priorities,
see section 7.5.10, DMAC Multi-Channel Operation.
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Section 7 DMA Controller
7.2.5
Bit
DMA Band Control Register (DMABCR)
:
15
14
13
12
11
10
9
8
DMABCRH :
FAE1
FAE0
—
—
DTA1B
DTA1A
DTA0B
DTA0A
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
Bit
:
7
6
5
4
3
2
1
0
DMABCRL :
DTE1B
DTE1A
DTE0B
DTE0A
DTIE1B
DTIE1A
DTIE0B
DTIE0A
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC
channel.
DMABCR is initialized to H'0000 by a reset, and in standby mode.
Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short
address mode or full address mode.
In short address mode, channels 1A and 1B are used as independent channels.
Bit 15
FAE1
Description
0
Short address mode
1
Full address mode
(Initial value)
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short
address mode or full address mode.
In short address mode, channels 0A and 0B are used as independent channels.
Bit 14
FAE0
Description
0
Short address mode
1
Full address mode
Rev.4.00 Sep. 18, 2008 Page 186 of 872
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(Initial value)
Section 7 DMA Controller
Bit 13 and 12—Reserved: This bit is reserved and only 0 can be written to, writing 1 causes a
malfunction error.
Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when
DMA transfer is performed, of the internal interrupt source selected by the data transfer factor
setting.
When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor
setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal
interrupt source selected by the data transfer factor setting does not issue an interrupt request to the
CPU or DTC.
When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor
setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU
or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC
transfer.
When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an
interrupt request to the CPU or DTC regardless of the DTA bit setting.
Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1B data transfer
factor setting.
Bit 11
DTA1B
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1A data transfer
factor setting.
Bit 10
DTA1A
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
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Section 7 DMA Controller
Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0B data transfer
factor setting.
Bit 9
DTA0B
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0A data transfer
factor setting.
Bit 8
DTA0A
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the
activation source selected by the data transfer factor setting is ignored. If the activation source is
an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1
when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer
end interrupt request to the CPU or DTC.
The conditions for the DTE bit being cleared to 0 are as follows:
• When initialization is performed
• When the specified number of transfers have been completed in a transfer mode other than
repeat mode
• When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason
When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation
source selected by the data transfer factor setting. When a request is issued by the activation
source, DMA transfer is executed.
The condition for the DTE bit being set to 1 is as follows:
• When 1 is written to the DTE bit after the DTE bit is read as 0
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Section 7 DMA Controller
Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B.
Bit 7
DTE1B
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A.
Bit 6
DTE1A
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B.
Bit 5
DTE0B
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A.
Bit 4
DTE0A
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an
interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to
the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the transfer counter
and address register again, and then setting the DTE bit to 1.
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Section 7 DMA Controller
Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B
transfer end interrupt.
Bit 3
DTIE1B
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
(Initial value)
Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A
transfer end interrupt.
Bit 2
DTIE1A
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
(Initial value)
Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B
transfer end interrupt.
Bit 1
DTIE0B
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
(Initial value)
Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A
transfer end interrupt.
Bit 0
DTIE0A
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
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(Initial value)
Section 7 DMA Controller
7.3
Register Descriptions (2) (Full Address Mode)
Full address mode transfer is performed with channels A and B together. For details of full address
mode setting, see table 7.5.
7.3.1
Memory Address Register (MAR)
Bit
:
31
30
29
28
27
26
25
24
MAR
:
—
—
—
—
—
—
—
—
23
22
21
20
19
18
17
16
*
*
*
*
*
*
*
*
Initial value :
0
0
0
0
0
0
0
0
R/W
:
—
—
—
—
—
—
—
— R/W R/W R/W R/W R/W R/W R/W R/W
Bit
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MAR
:
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Initial value :
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
MAR is a 32-bit readable/writable register; MARA functions as the transfer source address
register, and MARB as the destination address register.
MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are
reserved: they are always read as 0, and cannot be modified.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination memory address can be updated automatically. For details, see section 7.3.4,
DMA Control Register (DMACR).
MAR is not initialized by a reset or in standby mode.
7.3.2
I/O Address Register (IOAR)
IOAR is not used in full address transfer.
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Section 7 DMA Controller
7.3.3
Execute Transfer Count Register (ETCR)
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of
this register is different in normal mode and in block transfer mode.
ETCR is not initialized by a reset or in standby mode.
(1) Normal Mode
ETCRA
Transfer Counter
Bit
:
ETCR
:
Initial value :
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each
time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used
at this time.
ETCRB
ETCRB is not used in normal mode.
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Section 7 DMA Controller
(2) Block Transfer Mode
ETCRA
Holds block size
Bit
:
ETCRAH
:
15
14
13
12
11
10
9
8
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value :
R/W
:
Block size counter
Bit
:
ETCRAL
:
Initial value :
R/W
:
*: Undefined
ETCRB
Block Transfer Counter
Bit
:
ETCRB
:
Initial value :
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the
block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when
the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block
size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any
desired number of bytes or words.
ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time a block is transferred, and transfer ends when the count reaches
H'0000.
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Section 7 DMA Controller
7.3.4
DMA Control Register (DMACR)
DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
In full address mode, DMACRA and DMACRB have different functions.
DMACR is initialized to H'0000 by a reset, and in standby mode.
(1) DMACRA
Bit
15
14
13
12
11
10
9
8
DMACRA :
DTSZ
SAID
SAIDE
BLKDIR
BLKE
—
—
—
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
7
6
5
4
3
2
1
0
DMACRB :
—
DAID
DAIDE
—
DTF3
DTF2
DTF1
DTF0
R/W
:
:
(2) DMACRB
Bit
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 15
DTSZ
Description
0
Byte-size transfer
1
Word-size transfer
Rev.4.00 Sep. 18, 2008 Page 194 of 872
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(Initial value)
Section 7 DMA Controller
Bit 14—Source Address Increment/Decrement (SAID)
Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether
source address register MARA is to be incremented, decremented, or left unchanged, when data
transfer is performed.
Bit 14
Bit 13
SAID
SAIDE
Description
0
0
MARA is fixed
1
MARA is incremented after a data transfer
1
(Initial value)
•
When DTSZ = 0, MARA is incremented by 1 after a transfer
•
When DTSZ = 1, MARA is incremented by 2 after a transfer
0
MARA is fixed
1
MARA is decremented after a data transfer
•
When DTSZ = 0, MARA is decremented by 1 after a transfer
•
When DTSZ = 1, MARA is decremented by 2 after a transfer
Bit 12—Block Direction (BLKDIR)
Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode
is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side
or the destination side is to be the block area.
Bit 12
Bit 11
BLKDIR
BLKE
Description
0
0
Transfer in normal mode
1
Transfer in block transfer mode, destination side is block area
0
Transfer in normal mode
1
Transfer in block transfer mode, source side is block area
1
(Initial value)
For operation in normal mode and block transfer mode, see section 7.5, Operation.
Bits 10 to 7—Reserved: Although these bits are readable/writable, only 0 should be written here.
Rev.4.00 Sep. 18, 2008 Page 195 of 872
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Section 7 DMA Controller
Bit 6—Destination Address Increment/Decrement (DAID)
Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify
whether destination address register MARB is to be incremented, decremented, or left unchanged,
when data transfer is performed.
Bit 6
Bit 5
DAID
DAIDE
Description
0
0
MARB is fixed
1
MARB is incremented after a data transfer
1
(Initial value)
•
When DTSZ = 0, MARB is incremented by 1 after a transfer
•
When DTSZ = 1, MARB is incremented by 2 after a transfer
0
MARB is fixed
1
MARB is decremented after a data transfer
•
When DTSZ = 0, MARB is decremented by 1 after a transfer
•
When DTSZ = 1, MARB is decremented by 2 after a transfer
Bit 4—Reserved: Although this bit is readable/writable, only 0 should be written here.
Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor
(activation source). The factors that can be specified differ between normal mode and block
transfer mode.
• Normal Mode
Bit 3
Bit 2
Bit 1
Bit 0
DTF3
DTF2
DTF1
DTF0
Description
0
0
0
0
—
1
—
0
Activated by DREQ pin falling edge input
1
1
1
*
1
Activated by DREQ pin low-level input
0
*
—
1
0
Auto-request (cycle steal)
1
Auto-request (burst)
*
—
*
(Initial value)
*: Don't care
Rev.4.00 Sep. 18, 2008 Page 196 of 872
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Section 7 DMA Controller
• Block Transfer Mode
Bit 3
Bit
Bit 1
Bit 0
DTF3
DTF2
DTF1
DTF0
Description
0
0
0
0
—
1
—
0
Activated by DREQ pin falling edge input*
1
Activated by DREQ pin low-level input
0
Activated by SCI channel 0 transmission complete interrupt
1
Activated by SCI channel 0 reception complete interrupt
0
Activated by SCI channel 1 transmission complete interrupt
1
Activated by SCI channel 1 reception complete interrupt
0
Activated by TPU channel 0 compare match/input capture
A interrupt
1
Activated by TPU channel 1 compare match/input capture
A interrupt
0
Activated by TPU channel 2 compare match/input capture
A interrupt
1
—
0
—
1
—
0
—
1
—
1
1
0
1
1
0
0
1
1
0
1
(Initial value)
Note: * Detected as a low level in the first transfer after transfer is enabled.
The same factor can be selected for more than one channel. In this case, activation starts with the
highest-priority channel according to the relative channel priorities. For relative channel priorities,
see section 7.5.10, DMAC Multi-Channel Operation.
Rev.4.00 Sep. 18, 2008 Page 197 of 872
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Section 7 DMA Controller
7.3.5
Bit
DMA Band Control Register (DMABCR)
:
15
14
13
12
11
10
9
8
DMABCRH :
FAE1
FAE0
—
—
DTA1B
DTA1A
DTA0B
DTA0A
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
Bit
:
7
6
5
4
3
2
1
0
DMABCRL :
DTME1
DTE1
DTME0
DTE0
DTIE1B
DTIE1A
DTIE0B
DTIE0A
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC
channel.
DMABCR is initialized to H'0000 by a reset, and in standby mode.
Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short
address mode or full address mode.
In full address mode, channels 1A and 1B are used together as a single channel.
Bit 15
FAE1
Description
0
Short address mode
1
Full address mode
(Initial value)
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short
address mode or full address mode.
In full address mode, channels 0A and 0B are used together as a single channel.
Bit 14
FAE0
Description
0
Short address mode
1
Full address mode
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(Initial value)
Section 7 DMA Controller
Bits 13 and 12—Reserved: This bit is reserved and only 0 can be written to, writing 1 causes a
malfunction error.
Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when
DMA transfer is performed, of the internal interrupt source selected by the data transfer factor
setting.
When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor
setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal
interrupt source selected by the data transfer factor setting does not issue an interrupt request to the
CPU or DTC.
When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer
factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the
CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC
transfer.
When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues
an interrupt request to the CPU or DTC regardless of the DTA bit setting.
The state of the DTME bit does not affect the above operations.
Bit 11—Data Transfer Acknowledge 1 (DTA1B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor
setting.
Bit 11
DTA1B
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
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Section 7 DMA Controller
Bit 9—Data Transfer Acknowledge 0 (DTA0B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor
setting.
Bit 9
DTA0B
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bits 10 and 8—Reserved (DTA1A, DTA0A): Reserved bits in full address mode. Although these
bits are readable/writable, only 0 should be written here.
Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits
control enabling or disabling of data transfer on the relevant channel. When both the DTME bit
and the DTE bit are set to 1, transfer is enabled for the channel.
If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is
generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the
CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In
block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is
not interrupted.
The conditions for the DTME bit being cleared to 0 are as follows:
• When initialization is performed
• When NMI is input in burst mode
• When 0 is written to the DTME bit
The condition for DTME being set to 1 is as follows:
• When 1 is written to DTME after DTME is read as 0
Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel
1.
Bit 7
DTME1
Description
0
Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt
1
Data transfer enabled
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(Initial value)
Section 7 DMA Controller
Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel
0.
Bit 5
DTME0
Description
0
Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value)
1
Data transfer enabled
Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the
activation source selected by the data transfer factor setting is ignored. If the activation source is
an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1
when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer
end interrupt request to the CPU.
The conditions for the DTE bit being cleared to 0 are as follows:
• When initialization is performed
• When the specified number of transfers have been completed
• When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason
When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the
activation source selected by the data transfer factor setting. When a request is issued by the
activation source, DMA transfer is executed.
The condition for the DTE bit being set to 1 is as follows:
• When 1 is written to the DTE bit after the DTE bit is read as 0
Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1.
Bit 6
DTE1
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
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Section 7 DMA Controller
Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0.
Bit 4
DTE0
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an
interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when
DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer
break interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the DTME bit to 1.
Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1
transfer break interrupt.
Bit 3
DTIE1B
Description
0
Transfer break interrupt disabled
1
Transfer break interrupt enabled
(Initial value)
Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0
transfer break interrupt.
Bit 1
DTIE0B
Description
0
Transfer break interrupt disabled
1
Transfer break interrupt enabled
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(Initial value)
Section 7 DMA Controller
Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable
an interrupt to the CPU or DTC when transfer ends. If DTIEA bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to
the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the transfer counter
and address register again, and then setting the DTE bit to 1.
Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1
transfer end interrupt.
Bit 2
DTIE1A
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
(Initial value)
Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0
transfer end interrupt.
Bit 0
DTIE0A
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
(Initial value)
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Section 7 DMA Controller
7.4
Register Descriptions (3)
7.4.1
DMA Write Enable Register (DMAWER)
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions
so that only specific bits of DMACR for the specific channel and also DMATCR and DMABCR
can be changed to prevent inadvertent changes being made to registers other than those for the
channel concerned. The restrictions applied by DMAWER are valid for the DTC.
Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end
interrupt, and reactivating channel 0A. The address register and count register area is re-set by the
first DTC transfer, then the control register area is re-set by the second DTC chain transfer.
When re-setting the control register area, perform masking by setting bits in DMAWER to prevent
modification of the contents of the other channels.
First transfer area
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
DTC
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
Second transfer area
using chain transfer
DMAWER
DMATCR
DMACR0A
DMACR0B
DMACR1A
DMACR1B
DMABCR
Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)
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Section 7 DMA Controller
Bit
:
7
6
5
4
3
2
1
0
DMAWER :
—
—
—
—
WE1B
WE1A
WE0B
WE0A
Initial value :
0
0
0
0
0
0
0
0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
:
DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the
DMACR, DMABCR, and DMATCR by the DTC.
DMAWER is initialized to H'00 by a reset, and in standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 0.
Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7,
and 3 in DMABCR, and bit 5 in DMATCR by the DTC.
Bit 3
WE1B
Description
0
Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR
are disabled
(Initial value)
1
Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR
are enabled
Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits
10, 6, and 2 in DMABCR by the DTC.
Bit 2
WE1A
Description
0
Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled
(Initial value)
1
Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled
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Section 7 DMA Controller
Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5,
and 1 in DMABCR, and bit 4 in DMATCR.
Bit 1
WE0B
Description
0
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are disabled
(Initial value)
1
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are enabled
Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits
8, 4, and 0 in DMABCR.
Bit 0
WE0A
Description
0
Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled
(Initial value)
1
Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When
modifying these registers, the channel for which the modification is to be made should be halted.
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Section 7 DMA Controller
7.4.2
DMA Terminal Control Register (DMATCR)
Bit
:
7
6
5
4
3
2
1
0
DMATCR
:
—
—
TEE1
TEE0
—
—
—
—
Initial value :
0
0
0
0
0
0
0
0
R/W
—
—
R/W
R/W
—
—
—
—
:
DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC
transfer end pin output. A port can be set for output automatically, and a transfer end signal output,
by setting the appropriate bit.
DMATCR is initialized to H'00 by a reset, and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 0.
Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output.
Bit 5
TEE1
Description
0
TEND1 pin output disabled
1
TEND1 pin output enabled
(Initial value)
Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output.
Bit 4
TEE0
Description
0
TEND0 pin output disabled
1
TEND0 pin output enabled
(Initial value)
The TEND pins are assigned only to channel B in short address mode.
The transfer end signal indicates the transfer cycle in which the transfer counter reached 0,
regardless of the transfer source. An exception is block transfer mode, in which the transfer end
signal indicates the transfer cycle in which the block counter reached 0.
Bits 3 to 0—Reserved: Read-only bits, always read as 0.
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Section 7 DMA Controller
7.4.3
Bit
Module Stop Control Register A (MSTPCRA)
:
7
6
5
4
3
2
1
0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
R/W
:
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPA7 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus
cycle and a transition is made to module stop mode. For details, see section 17.5, Module Stop
Mode.
MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a
manual reset and in software standby mode.
Bit 7—Module Stop (MSTP7): Specifies the DMAC module stop mode.
Bits 7
MSTPA7
Description
0
DMAC module stop mode cleared
1
DMAC module stop mode set
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(Initial value)
Section 7 DMA Controller
7.5
Operation
7.5.1
Transfer Modes
Table 7.6 lists the DMAC modes.
Table 7.6
DMAC Transfer Modes
Transfer Mode
Short
address
mode
Full address
mode
Transfer Source
Dual
(1) Sequential mode •
address (2) Idle mode
mode
(3) Repeat mode
•
(4) Normal mode
(5) Block transfer
mode
Remarks
TPU channel 0 to 2
compare match/input
capture A interrupt
•
Up to 4 channels
can operate
independently
SCI transmission
complete interrupt
•
External request
applies to channel B
only
•
Max. 2-channel
operation,
combining channels
A and B
•
With auto-request,
burst mode transfer
or cycle steal
transfer can be
selected
•
SCI reception complete
interrupt
•
External request
•
External request
•
Auto-request
•
TPU channel 0 to 2
compare match/input
capture A interrupt
•
SCI transmission
complete interrupt
•
SCI reception complete
interrupt
•
External request
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Section 7 DMA Controller
Operation in each mode is summarized below.
(1) Sequential Mode
In response to a single transfer request, the specified number of transfers are carried out, one byte
or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified
number of transfers have been completed. One address is specified as 24 bits, and the other as 16
bits. The transfer direction is programmable.
(2) Idle Mode
In response to a single transfer request, the specified number of transfers are carried out, one byte
or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified
number of transfers have been completed. One address is specified as 24 bits, and the other as 16
bits. The transfer source address and transfer destination address are fixed. The transfer direction
is programmable.
(3) Repeat Mode
In response to a single transfer request, the specified number of transfers are carried out, one byte
or one word at a time. When the specified number of transfers have been completed, the addresses
and transfer counter are restored to their original settings, and operation is continued. No interrupt
request is sent to the CPU or DTC. One address is specified as 24 bits, and the other as 16 bits.
The transfer direction is programmable.
(4) Normal Mode
• Auto-request
By means of register settings only, the DMAC is activated, and transfer continues until the
specified number of transfers have been completed. An interrupt request can be sent to the
CPU or DTC when transfer is completed. Both addresses are specified as 24 bits.
⎯ Cycle steal mode: The bus is released to another bus master every byte or word transfer.
⎯ Burst mode: The bus is held and transfer continued until the specified number of transfers
have been completed.
• External request
In response to a single transfer request, the specified number of transfers are carried out, one
byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the
specified number of transfers have been completed. Both addresses are specified as 24 bits.
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Section 7 DMA Controller
(5) Block Transfer Mode
In response to a single transfer request, a block transfer of the specified block size is carried out.
This is repeated the specified number of times, once each time there is a transfer request. At the
end of each single block transfer, one address is restored to its original setting. An interrupt
request can be sent to the CPU or DTC when the specified number of block transfers have been
completed. Both addresses are specified as 24 bits.
7.5.2
Sequential Mode
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.7 summarizes register functions in sequential mode.
Table 7.7
Register Functions in Sequential Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0 Source
address
register
MAR
23
15
H'FF
Destination Start address of
Incremented/
address
transfer destination decremented every
register
or transfer source
transfer
0 Destination Source
IOAR
15
address
register
address
register
0 Transfer counter
ETCR
Operation
Fixed
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR: Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred.
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Section 7 DMA Controller
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
Figure 7.3 illustrates operation in sequential mode.
Transfer
Address T
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + (–1)DTID ⋅ (2DTSZ ⋅ (N–1))
Where : L = Value set in MAR
N = Value set in ETCR
Address B
Figure 7.3 Operation in Sequential Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
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Section 7 DMA Controller
Transfer requests (activation sources) consist of external requests, SCI transmission complete and
reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts.
External requests can be set for channel B only.
Figure 7.4 shows an example of the setting procedure for sequential mode.
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Sequential mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Sequential mode
Figure 7.4 Example of Sequential Mode Setting Procedure
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Section 7 DMA Controller
7.5.3
Idle Mode
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one
byte or word is transferred in response to a single transfer request, and this is executed the number
of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.8 summarizes register functions in idle mode.
Table 7.8
Register Functions in Idle Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0 Source
address
register
MAR
23
15
H'FF
15
address
register
address
register
0 Transfer counter
ETCR
Legend:
MAR:
IOAR:
ETCR:
DTDIR:
Destination Start address of
Fixed
address
transfer destination
register
or transfer source
0 Destination Source
IOAR
Operation
Start address of
Fixed
transfer source or
transfer destination
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
Memory address register
I/O address register
Transfer count register
Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
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Section 7 DMA Controller
Figure 7.5 illustrates operation in idle mode.
MAR
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Figure 7.5 Operation in Idle Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of external requests, SCI transmission complete and
reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts.
External requests can be set for channel B only.
When the DMAC is used in single address mode, only channel B can be set.
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Section 7 DMA Controller
Figure 7.6 shows an example of the setting procedure for idle mode.
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Idle mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Set the DTIE bit to 1.
• Set the DTE bit to 1 to enable transfer.
Read DMABCRL
[5]
Set DMABCRL
[6]
Idle mode
Figure 7.6 Example of Idle Mode Setting Procedure
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Section 7 DMA Controller
7.5.4
Repeat Mode
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in
DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to
a single transfer request, and this is executed the number of times specified in ETCR. On
completion of the specified number of transfers, MAR and ETCRL are automatically restored to
their original settings and operation continues.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.9 summarizes register functions in repeat mode.
Table 7.9
Register Functions in Repeat Mode
Function
Register
DTDIR = 0
23
0 Source
address
register
MAR
23
15
H'FF
DTDIR = 1 Initial Setting
Operation
Destination Start address of
address
transfer destination
register
or transfer source
Incremented/
decremented every
transfer. Initial
setting is restored
when value reaches
H'0000
0 Destination Source
address
register
IOAR
7
address
register
0 Holds number of
Fixed
Number of transfers Fixed
transfers
ETCRH
7
Start address of
transfer source or
transfer destination
0
Transfer counter
ETCRL
Number of transfers Decremented every
transfer. Loaded
with ETCRH value
when count reaches
H'00
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR: Data transfer direction bit
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Section 7 DMA Controller
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of
transfers, when H'00 is set in both ETCRH and ETCRL, is 256.
In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number
of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value
reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is
restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR
restoration operation is as shown below.
MAR = MAR – (–1)
DTID
·2
DTSZ
· ETCRH
The same value should be set in ETCRH and ETCRL.
In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation,
therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU
or DTC.
By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the
transfer after that terminated when the DTE bit was cleared.
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Section 7 DMA Controller
Figure 7.7 illustrates operation in repeat mode.
Address T
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Address B
Legend:
Address T = L
Address B = L + (–1)DTID ⋅ (2DTSZ ⋅ (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7.7 Operation in Repeat mode
Transfer requests (activation sources) consist of external requests, SCI transmission complete and
reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts.
External requests can be set for channel B only.
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Section 7 DMA Controller
Figure 7.8 shows an example of the setting procedure for repeat mode.
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Repeat mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in both ETCRH and
ETCRL.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Clear the DTIE bit to 0.
• Set the DTE bit to 1 to enable transfer.
Repeat mode
Figure 7.8 Example of Repeat Mode Setting Procedure
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Section 7 DMA Controller
7.5.5
Normal Mode
In normal mode, transfer is performed with channels A and B used in combination. Normal mode
can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA
to 0.
In normal mode, MAR is updated after each byte or word transfer in response to a single transfer
request, and this is executed the number of times specified in ETCRA. The transfer source is
specified by MARA, and the transfer destination by MARB.
Table 7.10 summarizes register functions in normal mode.
Table 7.10 Register Functions in Normal Mode
Register
Function
23
0 Source address
MARA
23
register
0 Destination
MARB
15
address register
0 Transfer counter
ETCRA
Initial Setting
Operation
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
Start address of
transfer destination
Incremented/decremented
every transfer, or fixed
Number of transfers Decremented every
transfer; transfer ends
when count reaches
H'0000
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Transfer count register A
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed.
Incrementing, decrementing, or holding a fixed value can be set separately for MARA and
MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a
transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
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Section 7 DMA Controller
Figure 7.9 illustrates operation in normal mode.
Transfer
Address TA
Address BB
Address BA
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
Address TB
= LA
= LB
= LA + SAIDE ⋅ (–1)SAID ⋅ (2DTSZ ⋅ (N – 1))
= LB + DAIDE ⋅ (–1)DAID ⋅ (2DTSZ ⋅ (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRA
Figure 7.9 Operation in Normal Mode
Transfer requests (activation sources) are external requests and auto-requests.
With auto-request, the DMAC is only activated by register setting, and the specified number of
transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be
selected. In cycle steal mode, the bus is released to another bus master each time a transfer is
performed. In burst mode, the bus is held continuously until transfer ends.
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Section 7 DMA Controller
For setting details, see section 7.3.4, DMA Controller Register (DMACR).
Figure 7.10 shows an example of the setting procedure for normal mode.
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Normal mode setting
Set DMABCRH
[1]
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the number of transfers in ETCRA.
Set transfer source and
transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Clear the BLKE bit to 0 to select normal
mode.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Normal mode
Figure 7.10 Example of Normal Mode Setting Procedure
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Section 7 DMA Controller
7.5.6
Block Transfer Mode
In block transfer mode, transfer is performed with channels A and B used in combination. Block
transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in
DMACRA to 1.
In block transfer mode, a transfer of the specified block size is carried out in response to a single
transfer request, and this is executed the specified number of times. The transfer source is
specified by MARA, and the transfer destination by MARB. Either the transfer source or the
transfer destination can be selected as a block area (an area composed of a number of bytes or
words).
Table 7.11 summarizes register functions in block transfer mode.
Table 7.11 Register Functions in Block Transfer Mode
Register
Function
23
0 Source address
register
MARA
23
0 Destination
address register
MARB
7
0 Holds block
ETCRAH
Initial Setting
Operation
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
Start address of
Incremented/decremented
transfer destination every transfer, or fixed
Block size
Fixed
Block size
Decremented every
transfer; ETCRH value
copied when count reaches
H'00
Number of block
transfers
Decremented every block
transfer; transfer ends
when count reaches
H'0000
size
Block size
0 counter
7
ETCRAL
15
0 Block transfer
ETCRB
Legend:
MARA:
MARB:
ETCRA:
ETCRB:
counter
Memory address register A
Memory address register B
Transfer count register A
Transfer count register B
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed.
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Section 7 DMA Controller
Incrementing, decrementing, or holding a fixed value can be set separately for MARA and
MARB.
Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in
DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
Figure 7.11 illustrates operation in block transfer mode when MARB is designated as a block area.
Address TB
Address TA
1st block
2nd block
Block area
Transfer
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Address BB
Nth block
Address BA
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
M
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (M · N – 1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 0)
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Section 7 DMA Controller
Figure 7.12 illustrates operation in block transfer mode when MARA is designated as a block area.
Address TA
Address TB
Block area
Transfer
1st block
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Address BA
2nd block
Nth block
Address BB
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
M
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (M · N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 7.12 Operation in Block Transfer Mode (BLKDIR = 1)
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Section 7 DMA Controller
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit
is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to
the CPU or DTC.
Figure 7.13 shows the operation flow in block transfer mode.
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Section 7 DMA Controller
Start
(DTE = DTME = 1)
Transfer request?
No
Yes
Acquire bus
Read address specified by MARA
MARA = MARA + SAIDE · (–1)SAID · 2DTSZ
Write to address specified by MARB
MARB = MARB + DAIDE · (–1)DAID · 2DTSZ
ETCRAL = ETCRAL – 1
ETCRAL = H'00
No
Yes
Release bus
ETCRAL = ETCRAH
BLKDIR = 0
No
Yes
MARB = MARB – DAIDE · (–1)DAID · 2DTSZ · ETCRAH
MARA = MARA – SAIDE · (–1)SAID · 2DTSZ · ETCRAH
ETCRB = ETCRB – 1
No
ETCRB = H'0000
Yes
Clear DTE bit to 0
to end transfer
Figure 7.13 Operation Flow in Block Transfer Mode
Transfer requests (activation sources) consist of external requests, SCI transmission complete and
reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts.
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Section 7 DMA Controller
For details, see section 7.3.4, DMA Control Register (DMACR).
Figure 7.14 shows an example of the setting procedure for block transfer mode.
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Block transfer
mode setting
Set DMABCRH
Set transfer source
and transfer destination
addresses
[1]
[2]
Set number of transfers
[3]
Set DMACR
[4]
Read DMABCRL
[5]
Set DMABCRL
[6]
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the block size in both ETCRAH and
ETCRAL. Set the number of transfers in
ETCRB.
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Set the BLKE bit to 1 to select block transfer
mode.
• Specify whether the transfer source or the
transfer destination is a block area with the
BLKDIR bit.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
Block transfer mode
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts to the CPU with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Figure 7.14 Example of Block Transfer Mode Setting Procedure
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Section 7 DMA Controller
7.5.7
DMAC Activation Sources
DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The
activation sources that can be specified depend on the transfer mode and the channel, as shown in
table 7.12.
Table 7.12 DMAC Activation Sources
Short Address Mode
Activation Source
Internal
Interrupts
Channels
0A and 1A
Channels
0B and 1B
Normal
Mode
TXI0
X
RXI0
X
TXI1
X
RXI1
X
TGI0A
X
TGI1A
X
TGI2A
External
Requests
Full Address Mode
X
DREQ pin falling edge input
X
DREQ pin low-level input
X
Auto-request
Block
Transfer
Mode
X
X
X
Legend:
: Can be specified
X : Cannot be specified
(1) Activation by Internal Interrupt
An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU
and DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt, the DMAC accepts the request independently of the
interrupt controller. Consequently, interrupt controller priority settings are not accepted.
If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a
DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA
transfer. With TXI and RXI interrupts, however, the interrupt source flag is not cleared unless the
prescribed register is accessed in a DMA transfer. If the same interrupt is used as an activation
source for more than one channel, the interrupt request flag is cleared when the highest-priority
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Section 7 DMA Controller
channel is activated first. Transfer requests for other channels are held pending in the DMAC, and
activation is carried out in order of priority.
When DTE = 0, such as after completion of a transfer, a request from the selected activation
source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt
request is sent to the CPU or DTC.
In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt
request flag is not cleared by the DMAC.
(2) Activation by External Request
If an external request (DREQ pin) is specified as an activation source, the relevant port should be
set to input mode in advance.
Level sensing or edge sensing can be used for external requests.
External request operation in normal mode (short address mode or full address mode) is described
below.
When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low
transition is detected on the DREQ pin. The next transfer may not be performed if the next edge is
input before transfer is completed.
When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is
held high. While the DREQ pin is held low, transfers continue in succession, with the bus being
released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
(3) Activation by Auto-Request
Auto-request activation is performed by register setting only, and transfer continues to the end.
With auto-request activation, cycle steal mode or burst mode can be selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles usually alternate.
In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is
performed continuously.
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Section 7 DMA Controller
7.5.8
Basic DMAC Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7.15. In this example, wordsize transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between these
read and write operations. As with CPU cycles, DMA cycles conform to the bus controller
settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
CPU cycle
DMAC cycle (1-word transfer)
T1
T2
T1
T2
T3
T1
T2
CPU cycle
T3
φ
Source
address
Destination address
Address bus
RD
HWR
LWR
Figure 7.15 Example of DMA Transfer Bus Timing
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Section 7 DMA Controller
7.5.9
DMAC Bus Cycles (Dual Address Mode)
(1) Short Address Mode
Figure 7.16 shows a transfer example in which TEND output is enabled and byte-size short
address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state
access space to internal I/O space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Bus release
Bus release
Last transfer
cycle
Bus
release
Figure 7.16 Example of Short Address Mode Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in
which the transfer counter reaches 0.
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Section 7 DMA Controller
(2) Full Address Mode (Cycle Steal Mode)
Figure 7.17 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Bus release
Bus release
Last transfer
cycle
Bus
release
Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer
Either a one-byte or a one-word transfer is performed for each transfer request, and after the
transfer the bus is released. While the bus is released one bus cycle is inserted by the CPU or
DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
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Section 7 DMA Controller
(3) Full Address Mode (Burst Mode)
Figure 7.18 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Last transfer cycle
Bus release
Bus release
Burst transfer
Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer
In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that
channel has to wait until the burst transfer ends.
If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state,
the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer
has already been activated inside the DMAC, the bus is released on completion of a one-byte or
one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer
cycle of the burst transfer has already been activated inside the DMAC, execution continues to the
end of the transfer even if the DTME bit is cleared.
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Section 7 DMA Controller
(4) Full Address Mode (Block Transfer Mode)
Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to
external 16-bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Block transfer
Bus release
Last block transfer
Bus
release
Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer
A one-block transfer is performed for one transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle.
One block is transmitted without interruption. NMI generation does not affect block transfer
operation.
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Section 7 DMA Controller
(5) DREQ Pin Falling Edge Activation Timing
Set the DTA bit for the channel for which the DREQ pin is selected to 1.
Figure 7.20 shows an example of DREQ pin falling edge activated normal mode transfer.
DMA
read
DMA
write
Transfer
source
Transfer
destination
Bus release
Bus
release
DMA
read
DMA
write
Transfer
source
Transfer
destination
Bus
release
φ
DREQ
Address bus
DMA control
Channel
Read
Idle
[2]
[3]
Read
Idle
Request clear period
Request
Minimum of 2 cycles
[1]
Write
Write
Idle
Request clear period
Request
Minimum of 2 cycles
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of φ, and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the
write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request
is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.20 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA write cycle ends, acceptance
resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
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Figure 7.21 shows an example of DREQ pin falling edge activated block transfer mode transfer.
1 block transfer
DMA
read
Bus release
1 block transfer
DMA
write
DMA Bus
dead release
DMA
read
DMA
write
Transfer
source
Transfer
destination
DMA
dead
Bus
release
φ
DREQ
Transfer
source
Address bus
DMA control
Channel
Read
Idle
Request
[2]
Dead
Write
Request clear period
Minimun of 2 cycles
[1]
Transfer
destination
[3]
Idle Read
Write
Dead
Idle
Request clear period
Request
Minimun of 2 cycles
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.21 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA dead cycle ends, acceptance
resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this
operation is repeated until the transfer ends.
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Section 7 DMA Controller
(6) DREQ Level Activation Timing (Normal Mode)
Set the DTA bit for the channel for which the DREQ pin is selected to 1.
Figure 7.22 shows an example of DREQ level activated normal mode transfer.
DMA
read
DMA
write
Transfer
source
Transfer
destination
Bus
release
Bus
release
DMA
read
DMA
write
Transfer
source
Transfer
destination
Bus
release
φ
DREQ
Address bus
DMA control
Channel
Read
Idle
Request
[2]
[3]
Read
Idle
Request clear period
Minimum of 2 cycles
[1]
Write
Write
Idle
Request clear period
Request
Minimum of 2 cycles
[4]
[5]
[6]
Acceptance resumes
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of φ, and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.22 Example of DREQ Level Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
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Section 7 DMA Controller
Figure 7.23 shows an example of DREQ level activated block transfer mode transfer.
1 block transfer
DMA
read
Bus release
1 block transfer
DMA
right
DMA Bus
dead release
DMA
read
DMA
right
DMA
dead
Bus
release
¿
DREQ
Transfer
source
Address bus
DMA control
Channel
Read
Idle
Transfer
destination
Dead
Write
Request clear period
Request
Minimum of 2 cycles
[1]
[2]
Transfer
source
Idle Read
Write
Transfer
destination
Dead
Idle
Request clear period
Request
Minimum of 2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of φ, and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.23 Example of DREQ Level Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
7.5.10
DMAC Multi-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B.
Table 7.13 summarizes the priority order for DMAC channels.
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Section 7 DMA Controller
Table 7.13 DMAC Channel Priority Order
Short Address Mode
Full Address Mode
Priority
Channel 0A
Channel 0
High
Channel 0B
Channel 1A
Channel 1
Channel 1B
Low
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.13.
During burst transfer, or when one block is being transferred in block transfer, the channel will not
be changed until the end of the transfer.
Figure 7.24 shows a transfer example in which transfer requests are issued simultaneously for
channels 0A, 0B, and 1.
DMA read
DMA write
DMA read
DMA write
DMA read
DMA
DMA write read
φ
Address bus
RD
HWR
LWR
DMA control Idle Read
Channel 0A
Write
Idle
Read
Write
Idle
Read
Write
Read
Request clear
Channel 0B
Request
hold
Selection
Channel 1
Request
hold
Nonselection
Bus
release
Channel 0A
transfer
Request clear
Request
hold
Bus
release
Selection
Channel 0B
transfer
Request clear
Bus
release
Channel 1 transfer
Figure 7.24 Example of Multi-Channel Transfer
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Section 7 DMA Controller
7.5.11
Relation between the DMAC, External Bus Requests, and the DTC
There can be no break between a DMA cycle read and a DMA cycle write. This means that an
external bus release cycle, or DTC cycle is not generated between the external read and external
write in a DMA cycle.
In the case of successive read and write cycles, such as in burst transfer or block transfer, an
external bus released state may be inserted after a write cycle. Since the DTC has a lower priority
than the DMAC, the DTC does not operate until the DMAC releases the bus.
When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these
DMA cycles can be executed at the same time as external bus release. However, simultaneous
operation may not be possible when a write buffer is used.
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Section 7 DMA Controller
7.5.12
NMI Interrupts and DMAC
When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An
NMI interrupt does not affect the operation of the DMAC in other modes.
In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit
are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on
completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the
CPU.
The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again.
Figure 7.25 shows the procedure for continuing transfer when it has been interrupted by an NMI
interrupt on a channel designated for burst mode transfer.
Resumption of
transfer on interrupted
channel
DTE = 1
DTME = 0
[1]
Check that DTE = 1 and
DTME = 0 in DMABCRL
[2]
Write 1 to the DTME bit.
[1]
No
Yes
Set DTME bit to 1
Transfer continues
[2]
Transfer ends
Figure 7.25 Example of Procedure for Continuing Transfer on Channel Interrupted by
NMI Interrupt
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Section 7 DMA Controller
7.5.13
Forced Termination of DMAC Operation
If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion
of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to
1 again.
In full address mode, the same applies to the DTME bit.
Figure 7.26 shows the procedure for forcibly terminating DMAC operation by software.
[1]
Forced termination
of DMAC
Clear DTE bit to 0
Clear the DTE bit in DMABCRL to 0.
If you want to prevent interrupt generation after
forced termination of DMAC operation, clear the
DTIE bit to 0 at the same time.
[1]
Forced termination
Figure 7.26 Example of Procedure for Forcibly Terminating DMAC Operation
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Section 7 DMA Controller
7.5.14
Clearing Full Address Mode
Figure 7.27 shows the procedure for releasing and initializing a channel designated for full address
mode. After full address mode has been cleared, the channel can be set to another transfer mode
using the appropriate setting procedure.
Clearing full
address mode
Stop the channel
[1]
[1] Clear both the DTE bit and the DTME bit in
DMABCRL to 0; or wait until the transfer ends
and the DTE bit is cleared to 0, then clear the
DTME bit to 0.
Also clear the corresponding DTIE bit to 0 at the
same time.
[2] Clear all bits in DMACRA and DMACRB to 0.
[3] Clear the FAE bit in DMABCRH to 0.
Initialize DMACR
[2]
Clear FAE bit to 0
[3]
Initialization;
operation halted
Figure 7.27 Example of Procedure for Clearing Full Address Mode
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Section 7 DMA Controller
7.6
Interrupts
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.14
shows the interrupt sources and their priority order.
Table 7.14 Interrupt Source Priority Order
Interrupt
Name
Interrupt Source
Interrupt
Priority Order
Short Address Mode
Full Address Mode
DEND0A
Interrupt due to end of
transfer on channel 0A
Interrupt due to end of
transfer on channel 0
DEND0B
Interrupt due to end of
transfer on channel 0B
Interrupt due to break in
transfer on channel 0
DEND1A
Interrupt due to end of
transfer on channel 1A
Interrupt due to end of
transfer on channel 1
DEND1B
Interrupt due to end of
transfer on channel 1B
Interrupt due to break in
transfer on channel 1
High
Low
Enabling or disabling of each interrupt source is set by means of the DTIE bit for the
corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt
controller independently.
The relative priority of transfer end interrupts on each channel is decided by the interrupt
controller, as shown in table 7.14.
Figure 7.28 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is
always generated when the DTIE bit is set to 1 while DTE bit is cleared to 0.
DTE/
DTME
Transfer end/transfer
break interrupt
DTIE
Figure 7.28 Block Diagram of Transfer End/Transfer Break Interrupt
In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to o
while DTIEB bit is set to 1.
In both short address mode and full address mode, DMABCR should be set so as to prevent the
occurrence of a combination that constitutes a condition for interrupt generation during setting.
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Section 7 DMA Controller
7.7
Usage Notes
(1) DMAC Register Access during Operation
Except for forced termination, the operating (including transfer waiting state) channel setting
should not be changed. The operating channel setting should only be changed when transfer is
disabled.
Also, the DMAC register should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
(a) DMAC control starts one cycle before the bus cycle, with output of the internal address.
Consequently, MAR is updated in the bus cycle before DMAC transfer.
Figure 7.29 shows an example of the update timing for DMAC registers in dual address
transfer mode.
DMA last transfer cycle
DMA transfer cycle
DMA read
DMA read
DMA write
DMA write
DMA
dead
φ
DMA Internal
address
DMA control
DMA register
operation
Idle
[1]
Transfer
source
Transfer
destination
Read
Write
[2]
Transfer
destination
Transfer
source
Read
Idle
[1]
Write
[2']
Dead
Idle
[3]
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode
Block size counter ETCR restore (in block transfer mode)
Notes: 1. In single address transfer mode, the update timing is the same as [1].
2. The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Figure 7.29 DMAC Register Update Timing
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Section 7 DMA Controller
(b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
register is read as shown in figure 7.30.
DMA transfer cycle
CPU longword read
MAR upper
word read
MAR lower
word read
DMA read
DMA write
φ
DMA internal
address
DMA control
Idle
DMA register
operation
[1]
Transfe
source
Transfer
destination
Read
Write
Idle
[2]
Note: The lower word of MAR is the updated value after the operation in [1].
Figure 7.30 Contention between DMAC Register Update and CPU Read
(2) Module Stop
When the MSTPA7 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state
is entered. However, 1 cannot be written to the MSTPA7 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
• Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)
• TEND pin enable (TEE = 1)
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Section 7 DMA Controller
(3) Medium-Speed Mode
When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edgedetected.
In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting
modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt
source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is
generated, is less than one state with respect to the DMAC clock (bus master clock), edge
detection may not be possible and the interrupt may be ignored.
Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the mediumspeed clock.
(4) Activation by Falling Edge on DREQ Pin
DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
switches to [1].
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is
enabled is performed by detection of a low level.
(5) Activation Source Acceptance
At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge
sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is
detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that
occurs before execution of the DMABCRL write to enable transfer.
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ
pin low level remaining from the end of the previous transfer, etc.
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Section 7 DMA Controller
(6) Internal Interrupt after End of Transfer
When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt
request will be sent to the CPU or DTC even if DTA is set to 1.
Also, if internal DMAC activation has already been initiated when operation is aborted, the
transfer is executed but flag clearing is not performed for the selected internal interrupt even if
DTA is set to 1.
An internal interrupt request following the end of transfer or an abort should be handled by the
CPU as necessary.
(7) Channel Re-Setting
To reactivate a number of channels when multiple channels are enabled, use exclusive handling of
transfer end interrupts, and perform DMABCR control bit operations exclusively.
Note, in particular, that in cases where multiple interrupts are generated between reading and
writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the
DMABCR write data in the original interrupt handling routine will be incorrect, and the write may
invalidate the results of the operations by the multiple interrupts. Ensure that overlapping
DMABCR operations are not performed by multiple interrupts, and that there is no separation
between read and write operations by the use of a bit-manipulation instruction.
Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must
first be read while cleared to 0 before the CPU can write a 1 to them.
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Section 8 Data Transfer Controller (DTC)
Section 8 Data Transfer Controller (DTC)
8.1
Overview
The H8S/2214 Group includes a data transfer controller (DTC). The DTC can be activated by an
interrupt or software, to transfer data.
8.1.1
Features
The features of the DTC are:
• Transfer possible over any number of channels
⎯ Transfer information is stored in memory
⎯ One activation source can trigger a number of data transfers (chain transfer)
• Wide range of transfer modes
⎯ Normal, repeat, and block transfer modes available
⎯ Incrementing, decrementing, and fixing of source and destination addresses can be selected
• Direct specification of 16-Mbyte address space possible
⎯ 24-bit transfer source and destination addresses can be specified
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
⎯ An interrupt request can be issued to the CPU after one data transfer ends
⎯ An interrupt request can be issued to the CPU after the specified data transfers have
completely ended
• Activation by software is possible
• Module stop mode can be set
⎯ The initial setting enables DTC registers to be accessed. DTC operation is halted by setting
module stop mode.
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Section 8 Data Transfer Controller (DTC)
8.1.2
Block Diagram
Figure 8.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Internal address bus
On-chip
RAM
CPU interrupt
request
Register information
MRA MRB
CRA
CRB
DAR
SAR
DTC
Control logic
DTC service
request
DTVECR
Interrupt
request
DTCERA to
DTCERF,
DTCERI
Interrupt controller
Internal data bus
Legend:
MRA, MRB: DTC mode registers A and B
CRA, CRB: DTC transfer count registers A and B
SAR:
DTC source address register
DAR:
DTC destination address register
DTCERA to DTCERF,
DTCERI:
DTC enable registers A to F and I
DTVECR:
DTC vector register
Figure 8.1 Block Diagram of DTC
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Section 8 Data Transfer Controller (DTC)
8.1.3
Register Configuration
Table 8.1 summarizes the DTC registers.
Table 8.1
DTC Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
DTC mode register A
MRA
Undefined
DTC mode register B
MRB
—*
2
—*
3
—*
3
—*
DTC source address register
SAR
2
—*
Undefined
DTC destination address register
DAR
Undefined
DTC transfer count register A
CRA
2
—*
2
—*
DTC transfer count register B
CRB
—*
Undefined
DTC enable registers
DTCER
R/W
H'00
2
2
Undefined
Undefined
3
—*
3
—*
3
—*
3
—*
H'FF16 to H'FE1B,
H'FE1E
DTC vector register
DTVECR
R/W
H'00
H'FE1F
Module stop control register A
MSTPCRA
R/W
H'3F
H'FDE8
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot
be located in external memory space. When the DTC is used, do not clear the RAME
bit in SYSCR to 0.
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Section 8 Data Transfer Controller (DTC)
8.2
Register Descriptions
8.2.1
DTC Mode Register A (MRA)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
SM1
SM0
DM1
DM0
MD1
MD0
DTS
Sz
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7
Bit 6
SM1
SM0
Description
0
—
SAR is fixed
1
0
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
1
SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5
Bit 4
DM1
DM0
0
—
DAR is fixed
1
0
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
1
DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Description
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Section 8 Data Transfer Controller (DTC)
Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Bit 3
Bit 2
MD1
MD0
Description
0
0
Normal mode
1
Repeat mode
0
Block transfer mode
1
—
1
Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination
side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Bit 1
DTS
Description
0
Destination side is repeat area or block area
1
Source side is repeat area or block area
Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.
Bit 0
Sz
Description
0
Byte-size transfer
1
Word-size transfer
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Section 8 Data Transfer Controller (DTC)
8.2.2
Bit
DTC Mode Register B (MRB)
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
CHNE
DISEL
—
—
—
—
—
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
MRB is an 8-bit register that controls the DTC operating mode.
Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a
number of data transfers can be performed consecutively in response to a single transfer request.
In data transfer with CHNE set to 1, determination of the end of the specified number of transfers,
clearing of the interrupt source flag, and clearing of DTCER is not performed.
Bit 7
CHNE
Description
0
End of DTC data transfer (activation waiting state is entered)
1
DTC chain transfer (new register information is read, then data is transferred)
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL
Description
0
After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
1
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2214 Group, and
should always be written with 0.
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Section 8 Data Transfer Controller (DTC)
8.2.3
Bit
DTC Source Address Register (SAR)
23
:
21
20
19
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
Initial value:
R/W
22
:
4
3
2
1
0
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4
Bit
DTC Destination Address Register (DAR)
:
Initial value :
R/W
:
23
22
21
20
19
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
4
3
2
1
0
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
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Section 8 Data Transfer Controller (DTC)
8.2.5
Bit
DTC Transfer Count Register A (CRA)
:
Initial value:
R/W
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
— — — — — — — — — — — — — — — —
CRAH
CRAL
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH)
and the lower 8 bits (CRAL). In repeat mode, CRAH holds the transfer count and CRAL functions
as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH holds the block size and
functions as an 8-bit block size counter (1 to 256). CRAL is decremented by 1 every time data is
transferred and when the counter value becomes H'00 the contents of CRAH are transferred. This
operation is repeated.
8.2.6
Bit
DTC Transfer Count Register B (CRB)
:
Initial value:
R/W
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
— — — — — — — — — — — — — — — —
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
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Section 8 Data Transfer Controller (DTC)
8.2.7
Bit
DTC Enable Register (DTCER)
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to
DTCERG, with bits corresponding to the interrupt sources that can control enabling and disabling
of DTC activation. These bits enable or disable DTC service for the corresponding interrupt
sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
Description
0
DTC activation by this interrupt is disabled
(Initial value)
[Clearing conditions]
1
•
When the DISEL bit is 1 and the data transfer has ended
•
When the specified number of transfers have ended
DTC activation by this interrupt is enabled
[Holding condition]
•
When the DISEL bit is 0 and the specified number of transfers have not ended
(n = 7 to 0)
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 8.4, together with the vector number
generated for each interrupt controller.
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and
writing. If all interrupts are masked, multiple activation sources can be set at one time by writing
data after executing a dummy read on the relevant register.
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Section 8 Data Transfer Controller (DTC)
8.2.8
Bit
DTC Vector Register (DTVECR)
:
7
6
5
4
3
2
1
0
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
Initial value:
R/W
:
0
R/(W)*1
0
0
0
0
0
0
0
R/W*2
R/W*2
R/W*2
R/W*2
R/W*2
R/W*2
R/W*2
Notes: 1. Only 1 can be written to the SWDTE bit.
2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
Bit 7
SWDTE
Description
0
DTC software activation is disabled
(Initial value)
[Clearing conditions]
1
•
When the DISEL bit is 0 and the specified number of transfers have not ended
•
When 0 is written to the DISEL bit after a software-activated data transfer end
interrupt (SWDTEND) request has been sent to the CPU
DTC software activation is enabled
[Holding conditions]
•
When the DISEL bit is 1 and data transfer has ended
•
When the specified number of transfers have ended
•
During data transfer due to software activation
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number for DTC software activation.
The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit leftshift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
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Section 8 Data Transfer Controller (DTC)
8.2.9
Bit
Module Stop Control Register A (MSTPCRA)
:
7
6
5
4
3
2
1
0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
R/W
:
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operation stops at the end of the bus
cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTPA6
bit while the DTC is operating. For details, see section 17.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 6—Module Stop (MSTPA6): Specifies the DTC module stop mode.
Bit 6
MSTPA6
Description
0
DTC module stop mode cleared
1
DTC module stop mode set
(Initial value)
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Section 8 Data Transfer Controller (DTC)
8.3
Operation
8.3.1
Overview
When activated, the DTC reads register information that is already stored in memory and transfers
data on the basis of that register information. After the data transfer, it writes updated register
information back to memory. Pre-storage of register information in memory makes it possible to
transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to
perform a number of transfers with a single activation.
Figure 8.2 shows a flowchart of DTC operation.
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE = 1
Yes
No
Transfer Counter = 0
or DISEL = 1
Yes
No
Clear an activation flag
End
Clear DTCER
Interrupt exception *
handling
Note: * See the section on the corresponding peripheral module for details
on the content of the processing required for interrupt handling.
Figure 8.2 Flowchart of DTC Operation
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Section 8 Data Transfer Controller (DTC)
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 8.2 outlines the functions of the DTC.
Table 8.2
DTC Functions
Address Registers
Transfer Mode
Activation Source
Transfer
Source
Transfer
Destination
•
Normal mode
•
IRQ
24 bits
24 bits
⎯ One transfer request transfers one
byte or one word
•
TPU TGI
•
•
8-bit timer CMI
⎯ Memory addresses are incremented
or decremented by 1 or 2
•
SCI TXI or RXI
•
A/D converter ADI
⎯ Up to 65,536 transfers possible
•
Software
Repeat mode
⎯ One transfer request transfers one
byte or one word
⎯ Memory addresses are incremented
or decremented by 1 or 2
⎯ After the specified number of
transfers (1 to 256), the initial state
resumes and operation continues
•
Block transfer mode
⎯ One transfer request transfers a block
of the specified size
⎯ Block size is from 1 to 256 bytes or
words
⎯ Up to 65,536 transfers possible
⎯ A block area can be designated at
either the source or destination
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Section 8 Data Transfer Controller (DTC)
8.3.2
Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER
bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a
CPU interrupt source when the bit is cleared to 0.
At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source or corresponding DTCER bit is cleared. Table 8.3 shows activation source and
DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag
of SCI0.
Since there are multiple factors that can initiate DTC operation, the flag that initiated the transfer
is not cleared after the last byte (or word) is transferred. The corresponding interrupt handler must
perform the required processing.
Table 8.3
Activation Source and DTCER Clearance
When the DISEL Bit Is 0 and
the Specified Number of
Activation Source Transfers Have Not Ended
When the DISEL Bit Is 1, or when
the Specified Number of Transfers
Have Ended
Software activation The SWDTE bit is cleared to 0
The SWDTE bit remains set to 1
An interrupt is issued to the CPU
Interrupt activation
The corresponding DTCER bit
remains set to 1
The activation source flag is
cleared to 0
The corresponding DTCER bit is cleared
to 0
The activation source flag remains set to 1
A request is issued to the CPU for the
activation source interrupt
Figure 8.3 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
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Section 8 Data Transfer Controller (DTC)
Source flag cleared
Clear
controller
Clear
DTCER
Clear request
On-chip
supporting
module
IRQ interrupt
Interrupt
request
Selection circuit
Select
DTVECR
DTC
Interrupt controller
CPU
Interrupt mask
Figure 8.3 Block Diagram of DTC Activation Source Control
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
8.3.3
DTC Vector Table
Figure 8.4 shows the correspondence between DTC vector addresses and register information.
Table 8.4 shows the correspondence between activation and vector addresses. When the DTC is
activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where
<< 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420.
The DTC reads the start address of the register information from the vector address set for each
activation source, and then reads the register information from that start address. The register
information can be placed at predetermined addresses in the on-chip RAM. The start address of
the register information should be an integral multiple of four.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip
RAM.
Note: * Not available in the H8S/2214 Group.
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Section 8 Data Transfer Controller (DTC)
Table 8.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Interrupt Source
Origin of
Interrupt
Source
Vector
Number
Vector
Address
Write to DTVECR
Software
DTVECR
H'0400+
—
(DTVECR
[6:0]
<<1)
IRQ0
External pin
16
H'0420
DTCEA7
IRQ1
17
H'0422
DTCEA6
IRQ2
18
H'0424
DTCEA5
IRQ3
19
H'0426
DTCEA4
IRQ4
20
H'0428
DTCEA3
IRQ5
21
H'042A
DTCEA2
DTCE*
IRQ6
22
H'042C
DTCEA1
IRQ7
23
H'042E
DTCEA0
32
H'0440
DTCEB5
TGI0B (GR0B compare match/
input capture)
33
H'0442
DTCEB4
TGI0C (GR0C compare match/
input capture)
34
H'0444
DTCEB3
TGI0D (GR0D compare match/
input capture)
35
H'0446
DTCEB2
40
H'0450
DTCEB1
41
H'0452
DTCEB0
44
H'0458
DTCEC7
45
H'045A
DTCEC6
TGI0A (GR0A compare match/
input capture)
TGI1A (GR1A compare match/
input capture)
TPU
channel 0
TPU
channel 1
TGI1B (GR1B compare match/
input capture)
TGI2A (GR2A compare match/
input capture)
TPU
channel 2
TGI2B (GR2B compare match/
input capture)
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Priority
High
Low
Section 8 Data Transfer Controller (DTC)
Origin of
Interrupt
Source
Vector
Number
Vector
Address
DTCE*
Priority
DMAC
72
H'0490
DTCEE7
High
DEND0B (channel 0B transfer end)
73
H'0492
DTCEE6
DEND1A (channel 1/channel 1A
transfer end)
74
H'0494
DTCEE5
DEND1B (channel 1B transfer end)
75
H'0496
DTCEE4
81
H'04A2
DTCEE3
82
H'04A4
DTCEE2
SCI
channel 1
85
H'04AA
DTCEE1
86
H'04AC
DTCEE0
SCI
channel 2
89
H'04B2
DTCEF7
90
H'04B4
DTCEF6
104
H'04D0
DTCEG7
105
H'04D2
DTCEG6
EXIRQ2
106
H'04D4
DTCEG5
EXIRQ3
107
H'04D6
DTCEG4
EXIRQ4
108
H'04D8
DTCEG3
EXIRQ5
109
H'04DA
DTCEG2
EXIRQ6
110
H'04DC
DTCEG1
EXIRQ7
111
H'04DE
DTCEG0
Interrupt Source
DEND0A (channel 0/channel 0A
transfer end)
RXI0 (reception complete 0)
TXI0 (transmit data empty 0)
RXI1 (reception complete 1)
TXI1 (transmit data empty 1)
RXI2 (reception complete 2)
TXI2 (transmit data empty 2)
EXIRQ0
EXIRQ1
SCI
channel 0
External
module
Low
Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
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Section 8 Data Transfer Controller (DTC)
DTC vector
address
Register information
start address
Register information
Chain transfer
Figure 8.4 Correspondence between DTC Vector Address and Register Information
8.3.4
Location of Register Information in Address Space
Figure 8.5 shows how the register information should be located in the address space.
Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address
of the register information (contents of the vector address). In the case of chain transfer, register
information should be located in consecutive areas.
Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).
Lower address
Register
information
start address
Chain
transfer
0
1
2
3
MRA
SAR
MRB
DAR
CRA
Register information
CRB
MRA
SAR
MRB
DAR
CRA
Register information
for 2nd transfer in
chain transfer
CRB
4 bytes
Figure 8.5 Location of Register Information in Address Space
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Section 8 Data Transfer Controller (DTC)
8.3.5
Normal Mode
In normal mode, one operation transfers one byte or one word of data.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt can be requested.
Table 8.5 lists the register information in normal mode and figure 8.6 shows memory mapping in
normal mode.
Table 8.5
Register Information in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register A
CRA
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR
DAR
Transfer
Figure 8.6 Memory Mapping in Normal Mode
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Section 8 Data Transfer Controller (DTC)
8.3.6
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial state of the transfer counter and the address register specified as the repeat area is restored,
and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and
therefore CPU interrupts cannot be requested when DISEL = 0.
Table 8.6 lists the register information in repeat mode and figure 8.7 shows memory mapping in
repeat mode.
Table 8.6
Register Information in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR or
DAR
Repeat area
Transfer
Figure 8.7 Memory Mapping in Repeat Mode
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DAR or
SAR
Section 8 Data Transfer Controller (DTC)
8.3.7
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified as the block area is restored. The other address register
is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt is requested.
Table 8.7 lists the register information in block transfer mode and figure 8.8 shows memory
mapping in block transfer mode.
Table 8.7
Register Information in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Designates block size count
DTC transfer count register B
CRB
Transfer count
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Section 8 Data Transfer Controller (DTC)
First block
SAR or
DAR
·
·
·
Block area
Transfer
Nth block
Figure 8.8 Memory Mapping in Block Transfer Mode
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DAR or
SAR
Section 8 Data Transfer Controller (DTC)
8.3.8
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 8.9 shows the memory map for chain transfer. The DTC reads the start address for the
register information from the DTC vector address corresponding to the DTC activation factor.
After the data transfer completes, the CHNE bit in this register is tested, and if it is 1, the next
register information allocated sequentially is read and a transfer is performed. This operation
continues until a data transfer for register information whose CHNE bit is 0 completes.
Source
Destination
Register information
CHNE = 1
DTC vector
address
Register information
start address
Register information
CHNE = 0
Source
Destination
Figure 8.9 Chain Transfer Memory Map
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
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Section 8 Data Transfer Controller (DTC)
8.3.9
Operation Timing
Figures 8.10 to 8.12 show an example of DTC operation timing.
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Address
Read Write
Transfer
information read
Transfer
information write
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
φ
DTC activation
request
DTC request
Data transfer
Vector read
Address
Read Write Read Write
Transfer
information read
Transfer
information write
Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
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Section 8 Data Transfer Controller (DTC)
φ
DTC activation
request
DTC
request
Data transfer
Data transfer
Read Write
Read Write
Vector read
Address
Transfer
information
read
Transfer
Transfer
information information
write
read
Transfer
information
write
Figure 8.12 DTC Operation Timing (Example of Chain Transfer)
8.3.10
Number of DTC Execution States
Table 8.8 lists execution statuses for a single DTC data transfer, and table 8.9 shows the number of
states required for each execution status.
Table 8.8
DTC Execution Statuses
Mode
Vector Read
I
Register Information
Read/Write
Data Read
J
K
Data Write
L
Internal
Operations
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
N: Block size (initial setting of CRAH and CRAL)
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Section 8 Data Transfer Controller (DTC)
Table 8.9
Number of States Required for Each Execution Status
Object to be Accessed
OnChip
RAM
OnChip
ROM
On-Chip I/O
Registers
External Devices
Bus width
32
16
8
16
8
Access states
16
1
1
2
2
2
3
2
3
SI
—
1
—
—
4
6+2m
2
3+m
SJ
1
—
—
—
—
—
—
—
Byte data read
SK
1
1
2
2
2
3+m
2
3+m
Word data read
SK
1
1
4
2
4
6+2m
2
3+m
Byte data write
SL
1
1
2
2
2
3+m
2
3+m
Word data write
SL
1
1
4
2
4
6+2m
2
3+m
Internal operation SM
1
Execution Vector read
status
Register
information
read/write
m: Number of wait states in external device access
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
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Section 8 Data Transfer Controller (DTC)
8.3.11
Procedures for Using DTC
(1) Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
[5] After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue
transferring data, set the DTCE bit to 1.
(2) Activation by Software
The procedure for using the DTC with software activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Check that the SWDTE bit is 0.
[4] Write 1 to SWDTE bit and the vector number to DTVECR.
[5] Check the vector number written to DTVECR.
[6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested.
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Section 8 Data Transfer Controller (DTC)
8.3.12
Examples of Use of the DTC
(1) Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
[1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start address of the RAM area where the data will be received in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
[2] Set the start address of the register information at the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
[5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
[6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
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Section 8 Data Transfer Controller (DTC)
(2) Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
[2] Set the start address of the register information at the DTC vector address (H'04C0).
[3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
[4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
[5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
[6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
[7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
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Section 8 Data Transfer Controller (DTC)
8.4
Interrupts
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,
the interrupt set as the activation source is generated. These interrupts to the CPU are subject to
CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers
have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
8.5
Usage Notes
(1) Module Stop
When the MSTPA6 bit in MSTPCRA is set to 1, the DTC clock stops, and the DTC enters the
module stop state. However, 1 cannot be written in the MSTPA6 bit while the DTC is operating.
See section 17, Power-Down Modes, for details.
(2) On-Chip RAM
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0.
(3) DMAC Transfer End Interrupt
When DTC transfer is activated by a DMAC transfer end interrupt, the DMAC's DTE bit is not
subject to DTC control, regardless of the transfer counter and DISEL bit, and the write data has
priority. Consequently, an interrupt request is not sent to the CPU when the DTC transfer counter
reaches 0.
(4) DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are masked, multiple activation sources can be set at one time by writing data after executing a
dummy read on the relevant register.
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Section 9 I/O Ports
Section 9 I/O Ports
9.1
Overview
The H8S/2214 Group has ten I/O ports (ports 1, 3, 7, and A to G), and two input-only ports (ports
4 and 9).
Table 9.1 summarizes the port functions. The pins of each port also have other functions.
Each port includes a data direction register (DDR) that controls input/output (not provided for the
input-only ports), a data register (DR) that stores output data, and a port register (PORT) used to
read the pin states.
Ports A to E have an on-chip MOS input pull-up function, and in addition to DR and DDR, have a
MOS input pull-up control register (PCR) to control the on/off status of the MOS input pull-ups.
Ports 3 and A include an open-drain control register (ODR) that controls the on/off status of the
output buffer PMOS.
All the ports can drive a single TTL load and 30 pF capacitive load.
The IRQ pins and external expansion interrupt input pins are Schmitt-triggered inputs.
Block diagrams of each port are shown in appendix C, I/O Port Block Diagrams.
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Section 9 I/O Ports
Table 9.1
Port
H8S/2214 Group Port Functions
Description
Port 1 • 8-bit I/O port
• Schmitttriggered
input (IRQ1,
IRQ0)
Pins
P17/TIOCB2/TCLKD
P16/TIOCA2/IRQ1
P15/TIOCB1/TCLKC
Modes 4 and 5
Mode 6
Mode 7
8-bit I/O port also functioning as TPU I/O pins (TCLKA,
TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0,
TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2), and external
interrupt input (IRQ0, IRQ1)
P14/TIOCA1/IRQ0
P13/TIOCD0/TCLKB/ 8-bit I/O port also functioning as DMAC
output pins (DACK0, DACK1), TPU I/O
A23
pins
(TCLKA, TCLKB, TIOCA0,
P12/TIOCC0/TCLKA/
TIOCB0, TIOCC0, TIOCD0), and
A22
address output (A20 to A23)
P11/TIOCB0/A21
P10/TIOCA0/A20
Port 3 • 7-bit I/O port
• Open-drain
output
capability
• Schmitttriggered
input (IRQ5,
IRQ4,
EXIRQ7)
Port 4 • 8-bit input
port
• Schmitttriggered
input
(EXIRQ6, to
EXIRQ0)
P36/EXIRQ7
P35/SCK1/IRQ5
P34/RxD1
7-bit I/O port also functioning as SCI (channel 0 and 1) I/O
pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1) and interrupt
input (IRQ4, IRQ5), and external extended interrupt input
(EXIRQ7)
P33/TxD1
P32/SCK0/IRQ4
P31/RxD0
P30/TxD0
P47/EXIRQ6
P46/EXIRQ5
P45
P44/EXIRQ4
P43/EXIRQ3
P42/EXIRQ2
P41/EXIRQ1
P40/EXIRQ0
Rev.4.00 Sep. 18, 2008 Page 282 of 872
REJ09B0189-0400
8-bit input port also functioning as external extended
interrupt input pins (EXIRQ6 to EXIRQ0)
Section 9 I/O Ports
Port
Description
Port 7 • 8-bit I/O port
Pins
P77
P76/EXMSTP
P75/EXMS
P74/MRES/EXDTCE
P73/TEND1/CS7
Modes 4 and 5
Mode 6
8-bit I/O port also functioning as DMAC
I/O pins (DREQ0, TEND0, DREQ1,
TEND1), bus control output pins (CS4
to CS7), the manual reset input pin
(MRES), and external module output
pins (EXMSTP, EXMS, EXDTCE)
P72/TEND0/CS6
P71/DREQ1/CS5
P70/DREQ0/CS4
Mode 7
8-bit I/O port also
functioning as
DMAC I/O pins
(DREQ0, TEND0,
DREQ1, TEND1),
the manual reset
input pins
(MRES), and
external module
output pin
(EXMSTP, EXMS,
EXDTCE)
Port 9 • 1-bit input
port
P96/DA0
1-bit input port also functioning as D/A analog output pin
(D/A0)
Port A • 4-bit I/O port
PA3/A19/SCK2
I/O port also functioning as SCI
(channel 2) I/O pins (TxD2, RxD2,
SCK2) and address output (A16 to A19)
I/O port also
functioning as SCI
(channel 2) I/O
pins (TxD2, RxD2,
SCK2)
I/O port also functioning as address
output (A8 to A15)
I/O port
PC7/A7 to PC0/A0
Address output
(A0 to A7)
I/O port
PD7/D15 to PD0/D8
Data bus input/output
I/O port
PE7/D7 to PE0/D0
8-bit bus mode: I/O port
I/O port
• On-chip
MOS input
pull-up
• Open-drain
output
capability
Port B • 8-bit I/O port
• On-chip
MOS input
pull-up
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
Port C • 8-bit I/O port
• On-chip
MOS input
pull-up
Port D • 8-bit I/O port
When DDR = 0:
Input port
When DDR = 1:
Address output
• On-chip
MOS input
pull-up
Port E • 8-bit I/O port
• On-chip
MOS input
pull-up
16-bit bus mode: Data bus input/output
Rev.4.00 Sep. 18, 2008 Page 283 of 872
REJ09B0189-0400
Section 9 I/O Ports
Port
Description
Port F • 8-bit I/O port
Pins
PF7/φ
Modes 4 and 5
Mode 6
When DDR = 0: Input port
When DDR = 1 (after reset): φ output
• Schmitttriggered
input (IRQ3,
IRQ2)
Mode 7
When DDR = 0
(after reset): Input
port
When DDR = 1: φ
output
PF6/AS
AS, RD, HWR output
I/O port
16-bit bus mode: LWR output
I/O port also
functioning as
interrupt input pin
(IRQ3)
PF5/RD
PF4/HWR
PF3/LWR/IRQ3
8-bit bus mode: I/O port also
functioning as interrupt input pin (IRQ3)
PF2/WAIT
When WAITE = 0 (after reset): I/O port
I/O port
When WAITE = 1: WAIT input
PF1/BACK
When BRLE = 0 (after reset): I/O port
I/O port
When BRLE = 1: BACK output
PF0/BREQ/IRQ2
When BRLE = 0 (after reset): I/O port
also functioning as interrupt input pin
(IRQ2)
When BRLE = 1: BREQ input also
functioning as interrupt input pin (IRQ2)
Port G • 5-bit I/O port
PG4/CS0
• Schmitttriggered
input (IRQ7,
IRQ6)
When DDR = 0*1: Input port
When DDR = 1*2: CS0 output
PG3/CS1
When DDR = 0 (after reset): Input port
also functioning as interrupt input pin
(IRQ7)
PG2/CS2
PG1/CS3/IRQ7
When DDR = 1: Interrupt input pin
(IRQ7) also functions as CS1, CS2,
CS3 output
PG0/IRQ6
Notes: 1. After a mode 6 reset
2. After a mode 4 or 5 reset
Rev.4.00 Sep. 18, 2008 Page 284 of 872
REJ09B0189-0400
I/O port also
functioning as
interrupt input pin
(IRQ2)
I/O port also
functioning as
interrupt input pins
(IRQ6, IRQ7)
Section 9 I/O Ports
9.2
Port 1
9.2.1
Overview
Port 1 is an 8-bit I/O port. Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC,
TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2),
external interrupt pins (IRQ0 and IRQ1), and address bus output pins (A23 to A20). Port 1 pin
functions depend on the operating mode.
The interrupt input pins (IRQ0 and IRQ1) are Schmitt-triggered inputs.
Figure 9.1 shows the port 1 pin configuration.
Port 1 pins: Pin functions in modes 4 to 6
P17 (input/output) /TIOCB2 (input/output)/TCLKD (input)
P16 (input/output) /TIOCA2 (input/output) /IRQ1 (input)
P15 (input/output) /TIOCB1 (input/output)/TCLKC (input)
Port 1
P14 (input/output) /TIOCA1 (input/output) /IRQ0 (input)
P13 (input/output) /TIOCD0 (input/output)/TCLKB (input)/A23 (output)
P12 (input/output) /TIOCC0 (input/output)/TCLKA (input)/A22 (output)
P11 (input/output) /TIOCB0 (input/output) /A21(output)
P10 (input/output) /TIOCA0 (input/output) /A20(output)
Pin functions in mode 7
P17 (input/output) /TIOCB2 (input/output)/TCLKD (input)
P16 (input/output) /TIOCA2 (input/output) /IRQ1 (input)
P15 (input/output) /TIOCB1 (input/output)/TCLKC (input)
P14 (input/output) /TIOCA1 (input/output) /IRQ0 (input)
P13 (input/output) /TIOCD0 (input/output)/TCLKB (input)
P12 (input/output) /TIOCC0 (input/output)/TCLKA (input)
P11 (input/output) /TIOCB0 (input/output)
P10 (input/output) /TIOCA0 (input/output)
Figure 9.1 Port 1 Pin Functions
Rev.4.00 Sep. 18, 2008 Page 285 of 872
REJ09B0189-0400
Section 9 I/O Ports
9.2.2
Register Configuration
Table 9.2 shows the port 1 register configuration.
Table 9.2
Port 1 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 1 data direction register
P1DDR
W
H'00
H'FE30
Port 1 data register
P1DR
R/W
H'00
H'FF00
Port 1 register
PORT1
R
Undefined
H'FFB0
Note: * Lower 16 bits of the address.
(1) Port 1 Data Direction Register (P1DDR)
Bit
:
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit
to 0, makes that pin an input pin. Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section 2.10.4, Access Methods for
Registers with Write-Only Bits.
P1DDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode. As the TPU is initialized by a
manual reset, the pin states in this case are determined by the P1DDR and P1DR specifications.
The OPE bit in SBYCR is used to select whether the address output pins retain their output state
or become high-impedance when a transition is made to software standby mode.
(a) Modes 4, 5, and 6
If address output is enabled by the setting of bits AE3 to AE0 in PFCR, pins P13 to P10 are
address outputs. Pins P17 to P14, and pins P13 to P10 when address output is disabled, are
output ports when the corresponding P1DDR bits are set to 1, and input ports when the
corresponding P1DDR bits are cleared to 0.
Rev.4.00 Sep. 18, 2008 Page 286 of 872
REJ09B0189-0400
Section 9 I/O Ports
(b) Mode 7
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output port, while clearing the
bit to 0 makes the pin an input port.
(2) Port 1 Data Register (P1DR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10).
P1DR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(3) Port 1 Register (PORT1)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
—*
—*
—*
—*
—*
—*
—*
—*
R
R
R
R
R
R
R
R
Note: * Determined by the state of pins P17 to P10.
PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 1 pins (P17 to P10) must always be performed on P1DR.
If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1
read is performed while P1DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin
states, as P1DDR and P1DR are initialized. PORT1 retains its previous state after a manual reset
and in software standby mode.
Rev.4.00 Sep. 18, 2008 Page 287 of 872
REJ09B0189-0400
Section 9 I/O Ports
9.2.3
Pin Functions
Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0,
TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), external interrupt input
pins (IRQ0 and IRQ1), and address output pins (A23 to A20). Port 1 pin functions are shown in
table 9.3.
Table 9.3
Port 1 Pin Functions
Pin
Pin Functions and Selection Method
P17/
TIOCB2/
TCLKD
The pin function is switched as shown below according to the combination of the TPU
channel 2 settings (bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and bits
CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in TCR0 and TCR5, and bit
P17DDR.
TPU channel 2
settings
(1)
in table below
P17DDR
Pin function
(2)
in table below
—
0
1
TIOCB2 output
P17 input
P17 output
1
TIOCB2 input*
TCLKD input*
2
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2 to
TPSC0 = B'111.
Also, TCLKD input when channels 2 and 4 are set to phase counting
mode.
TPU channel 2
settings
(2)
(1)
(2)
(2)
MD3 to MD0
B'0000, B'01xx
B'0010
IOB3 to IOB0
B'0000 B'0001 to B'0011
B'0100 B'0101 to B'0111
B'1xxx
—
B'xx00
(1)
(2)
B'0011
Other than B'xx00
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output compare
output
—
—
PWM mode 2
output
—
x: Don’t care
Rev.4.00 Sep. 18, 2008 Page 288 of 872
REJ09B0189-0400
Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P16/
TIOCA2/
IRQ1
The pin function is switched as shown below according to the combination of the TPU
channel 2 settings (bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, and bits
CCLR1 and CCLR0 in TCR2) and bit P16DDR.
TPU channel 2
settings
(1)
in table below
P16DDR
Pin function
(2)
in table below
—
0
1
TIOCA2 output
P16 input
P16 output
TIOCA2 input*
2
IRQ1 input*
TPU channel 2
settings
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000, B'01xx
(2)
(1)
B'001x B'0010
B'0000 B'0001 to B'0011 B'xx00 Other
B'0100 B'0101 to B'0111
than
B'1xxx
B'xx00
CCLR1, CCLR0
—
—
—
Output function
—
Output compare
output
—
—
1
(1)
(2)
B'0011
Other than B'xx00
Other than
B'01
PWM PWM mode 2
mode 1
output
3
output*
B'01
—
x: Don’t care
Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
2. When used as an external interrupt pin, do not use for another function.
3. Output is disabled for TIOCB2.
Rev.4.00 Sep. 18, 2008 Page 289 of 872
REJ09B0189-0400
Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P15/
TIOCB1/
TCLKC
The pin function is switched as shown below according to the combination of the TPU
channel 1 settings (bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits
CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and
TCR5, and bit P15DDR.
TPU channel 1
settings
(1)
in table below
P15DDR
Pin function
(2)
in table below
—
0
TIOCB1 output
P15 input
1
P15 output
1
TIOCB1 input*
TCLKC input*
2
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 =
B'10xx.
2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2 to
TPSC0 = B'110, or the setting for either TCR4 or TCR5 is: TPSC2 to
TPSC0 = B'101.
Also, TCLKC input when channels 2 and 4 are set to phase counting
mode.
TPU channel 1
settings
(2)
(1)
(2)
(2)
MD3 to MD0
B'0000, B'01xx
B'0010
IOB3 to IOB0
B'0000 B'0001 to B'0011
B'0100 B'0101 to B'0111
B'1xxx
—
B'xx00
(1)
(2)
B'0011
Other than B'xx00
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output compare
output
—
—
PWM mode 2
output
—
x: Don’t care
Rev.4.00 Sep. 18, 2008 Page 290 of 872
REJ09B0189-0400
Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P14/
TIOCA1/
IRQ0
The pin function is switched as shown below according to the combination of the TPU
channel 1 settings (bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits
CCLR1 and CCLR0 in TCR1) and bit P14DDR.
TPU channel 1
settings
(1)
in table below
P14DDR
Pin function
(2)
in table below
—
0
1
TIOCA1 output
P14 input
P14 output
TIOCA1 input*
2
IRQ0 input*
TPU channel 1
settings
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000, B'01xx
(2)
(1)
B'001x B'0010
B'0000 B'0001 to B'0011 B'xx00 Other
B'0100 B'0101 to B'0111
than
B'1xxx
B'xx00
CCLR1, CCLR0
—
—
—
Output function
—
Output compare
output
—
—
1
(1)
(2)
B'0011
Other than B'xx00
Other than
B'01
PWM PWM mode 2
mode 1
output
3
output*
B'01
—
x: Don’t care
Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0=
B'10xx.
2. When used as an external interrupt pin, do not use for another function
3. Output is disabled for TIOCB1.
Rev.4.00 Sep. 18, 2008 Page 291 of 872
REJ09B0189-0400
Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P13/
TIOCD0/
TCLKB/
A23
The pin function is switched as shown below according to the combination of the
operating mode, the TPU channel 0 settings (bits MD3 to MD0 in TMDR0, bits IOD3 to
IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0
to TCR2, bits AE3 to AE0 in PFCR, and bit P13DDR.
Operating mode
Modes 4, 5, 6
AE3 to AE0
TPU channel 0
settings
Other than B'1111
B'1111
—
(1)
(2)
in table below in table below
—
(1)
(2)
in table below in table below
P13DDR
Pin function
Mode 7
—
0
TIOCD0
output
—
—
P13
P13
input output
—
TIOCD0
output
TIOCD0
1
input*
—
TCLKB input*
1
2
0
1
P13
P13
input output
TIOCD0
1
input*
TCLKB input*
A23
output
2
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
2. TCLKB input when the setting for any of TCR0 to TCR2 is: TPSC2 to
TPSC0 = B'101.
Also, TCLKB input when channels 1 and 5 are set to phase counting
mode.
TPU channel 0
settings
(2)
(1)
(2)
(2)
MD3 to MD0
B'0000
B'0010
IOD3 to IOD0
B'0000 B'0001 to B'0011
B'0100 B'0101 to B'0111
B'1xxx
—
B'xx00
(1)
(2)
B'0011
Other than B'xx00
CCLR2 to CCLR0
—
—
—
—
Other than
B'110
B'110
Output function
—
Output compare
output
—
—
PWM mode 2
output
—
x: Don’t care
Rev.4.00 Sep. 18, 2008 Page 292 of 872
REJ09B0189-0400
Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P12/
TIOCC0/
TCLKA/
A22
The pin function is switched as shown below according to the combination of the
operating mode, the TPU channel 0 settings (bits MD3 to MD0 in TMDR0, bits IOC3 to
IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0
to TCR5, bits AE3 to AE0 in PFCR, and bit P12DDR.
Operating mode
Modes 4, 5, 6
AE3 to AE0
TPU channel 0
settings
Other than B'1111
B'1111
—
(1)
(2)
in table below in table below
—
(1)
(2)
in table below in table below
P12DDR
Pin function
—
0
TIOCC0
output
—
—
P12
P12
input output
—
TIOCC0
output
TIOCC0
1
input*
—
TCLKA input*
TPU channel 0
settings
(2)
MD3 to MD0
IOC3 to IOC0
Mode 7
1
2
(1)
B'0000
(1)
B'0000 B'0001 to B'0011 B'xx00 Other
B'0100 B'0101 to B'0111
than
B'1xxx
B'xx00
—
—
—
Output function
—
Output compare
output
—
P12
P12
input output
TCLKA input*
B'001x B'0010
CCLR2 to CCLR0
1
TIOCC0
1
input*
A22
output
(2)
0
—
(1)
2
(2)
B'0011
Other than B'xx00
Other than
B'101
PWM PWM mode 2
mode 1
output
3
output*
B'101
—
x: Don’t care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. TCLKA input when the setting for any of TCR0 to TCR5 is: TPSC2 to
TPSC0 = B'100.
Also, TCLKA input when channels 1 and 5 are set to phase counting
mode.
3. Output is disabled for TIOCD0.
When BFA = 1 or BFB = 1 in TMDR0, output is disabled and the settings in
(2) apply.
Rev.4.00 Sep. 18, 2008 Page 293 of 872
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P11/
TIOCB0/
A21
The pin function is switched as shown below according to the combination of the
operating mode, the TPU channel 0 settings (bits MD3 to MD0 in TMDR0 and bits
IOB3 to IOB0 in TIOR0H), bits AE3 to AE0 in PFCR, and bit P11DDR.
Operating mode
Modes 4, 5, 6
AE3 to AE0
TPU channel0
settings
B'0000 to B'1101
(1) in table below
P11DDR
Pin function
(2) in table below
—
0
TIOCB0 output
P11 input
1
A21 output
—
(1) in table below
P11DDR
Note:
—
Mode 7
AE3 to AE0
Pin function
—
P11 output
1
TIOCB0 input*
Operating mode
TPU channel0
settings
B'1110 to B'1111
(2) in table below
—
0
1
TIOCB0 output
P11 input
P11 output
1
*
TIOCB0 input
1. TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
TPU channel 0
settings
(2)
(1)
(2)
(2)
MD3 to MD0
B'0000
B'0010
IOB3 to IOB0
B'0000 B'0001 to B'0011
B'0100 B'0101 to B'0111
B'1xxx
—
B'xx00
(1)
(2)
B'0011
Other than
B'xx00
CCLR2 to CCLR0
—
—
—
—
Other
than
B'010
B'010
Output function
—
Output compare
output
—
—
PWM
mode 2
output
—
x: Don’t care
Rev.4.00 Sep. 18, 2008 Page 294 of 872
REJ09B0189-0400
Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P10/
TIOCA0/
A20
The pin function is switched as shown below according to the combination of the
operating mode, the TPU channel 0 settings (bits MD3 to MD0 in TMDR0, bits IOA3 to
IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bits AE3 to AE0 in PFCR, and
bit P10DDR.
Operating mode
Modes 4, 5, 6
AE3 to AE0
TPU channel0
settings
B'0000 to B'1100
(1) in table below
P10DDR
Pin function
(2) in table below
—
0
TIOCA0 output
P10 input
1
(1) in table below
(2) in table below
—
0
TIOCA0 output
P10 input
(2)
MD3 to MD0
IOA3 to IOA0
A20 output
—
P10DDR
TPU channel 0
settings
—
Mode 7
AE3 to AE0
Pin function
—
P10 output
1
TIOCA0 input*
Operating mode
TPU channel0
settings
B'1101 to B'1111
1
P10 output
1
TIOCA0 input*
(1)
(2)
B'0000
(1)
B'001x B'0010
B'0000 B'0001 to B'0011 B'xx00 Other
B'0100 B'0101 to B'0111
than
B'1xxx
B'xx00
CCLR2 to CCLR0
—
—
—
Output function
—
Output compare
output
—
—
(1)
(2)
B'0011
Other than B'xx00
Other than
B'001
PWM PWM mode 2
mode 1
output
2
output*
B'001
—
x: Don’t care
Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. Output is disabled for TIOCB0.
Rev.4.00 Sep. 18, 2008 Page 295 of 872
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Section 9 I/O Ports
9.3
Port 3
9.3.1
Overview
Port 3 is a 7-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1,
RxD1, and SCK1), external interrupt input pins (IRQ4 and IRQ5), and an external expansion
interrupt input pin (EXIRQ7). Port 3 pin functions are the same in all operating modes.
The interrupt input pins (IRQ4 and IRQ5) and the external expansion interrupt input pin
(EXIRQ7) are Schmitt-triggered inputs.
Figure 9.2 shows the port 3 pin configuration.
Port 3 pins
P36 (input/output)/EXIRQ7 (input)
P35 (input/output)/SCK1(input/output)/IRQ5 (input)
P34 (input/output)/RxD1 (input)
Port 3
P33 (input/output)/TxD1 (output)
P32 (input/output)/SCK0(input/output)/IRQ4 (input)
P31 (input/output)/RxD0 (input)
P30 (input/output)/TxD0 (output)
Figure 9.2 Port 3 Pin Functions
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Section 9 I/O Ports
9.3.2
Register Configuration
Table 9.4 shows the port 3 register configuration.
Table 9.4
Port 3 Registers
Name
Abbreviation
R/W
2
1
Initial Value* Address*
Port 3 data direction register
P3DDR
W
H'00
H'FE32
Port 3 data register
P3DR
R/W
H'00
H'FF02
Port 3 register
PORT3
R
H'00
H'FFB2
Port 3 open-drain control register
P3ODR
R/W
H'00
H'FE46
R/W
H'00
H'FE4A
Interrupt request input pin select register 0 IPINTSEL0
Notes: 1. Lower 16 bits of the address.
2. Value of bits 6 to 0.
(1) Port 3 Data Direction Register (P3DDR)
Bit
:
7
—
6
5
4
3
2
1
0
P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value : Undefined
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
:
—
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 3. P3DDR cannot be read; if it is, an undefined value will be returned. Bit 7 is
reserved; this bit cannot be modified and will return an undefined value if read.
Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
Since this register is a write-only register, do not use bit manipulation instructions to write to this
register. See section 2.10.4, Access Methods for Registers with Write-Only Bits.
P3DDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode. As the SCI is initialized by a
manual reset, the pin states in this case are determined by the P3DDR and P3DR specifications.
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Section 9 I/O Ports
(2) Port 3 Data Register (P3DR)
Bit
:
7
6
5
4
3
2
1
0
—
P36DR
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : Undefined
R/W
:
—
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P36 to P30).
Bit 7 is reserved; this bit cannot be modified and will return an undefined value if read.
P3DR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(3) Port 3 Register (PORT3)
Bit
:
7
6
5
4
3
2
1
0
—
P36
P35
P34
P33
P32
P31
P30
—*
—*
—*
—*
—*
—*
—*
R
R
R
R
R
R
R
Initial value : Undefined
R/W
:
—
Note: * Determined by the state of pins P36 to P30.
PORT3 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 3 pins (P36 to P30) must always be performed on P3DR. Bit 7 is reserved;
this bit cannot be modified and will return an undefined value if read.
If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3
read is performed while P3DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin
states, as P3DDR and P3DR are initialized. PORT3 retains its previous state after a manual reset
and in software standby mode.
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Section 9 I/O Ports
(4) Port 3 Open-Drain Control Register (P3ODR)
Bit
:
7
6
—
:
4
3
2
0
1
P36ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Initial value : Undefined
R/W
5
—
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3
pin (P36 to P30). Bit 7 is reserved; this bit cannot be modified and will return an undefined value
if read.
Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin,
while clearing the bit to 0 makes the pin a CMOS output pin.
P3ODR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(5) Interrupt Request Input Pin Select Register 0 (IPINSEL0)
Bit
:
Initial value :
R/W :
7
6
5
4
3
2
1
0
P36
IRQ7E
P47
IRQ6E
P46
IRQ5E
P44
IRQ4E
P43
IRQ3E
P42
IRQ2E
P41
IRQ1E
P40
IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IPINSEL0 is an 8-bit readable/writable register that selects which pins are to be used for interrupt
request input signals (EXIRQ0 to EXIRQ7) from externally connected modules. IPINSEL0 is
initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state
in a manual reset and in software standby mode.
Bit 7—Enable of EXIRQ7 Input from P36 (P36IRQ7E): Selects whether or not P36 is used as
the EXIRQ7 input pin.
Bit 7
P36IRQ7E
Description
0
P36 is not used as EXIRQ7 input
1
P36 is used as EXIRQ7 input
(Initial value)
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Section 9 I/O Ports
Bit 6—Enable of EXIRQ6 Input from P47 (P47IRQ6E): Selects whether or not P47 is used as
the EXIRQ6 input pin.
Bit 6
P47IRQ6E
Description
0
P47 is not used as EXIRQ6 input
1
P47 is used as EXIRQ6 input
(Initial value)
Bit 5— Enable of EXIRQ5 Input from P46 (P46IRQ5E): Selects whether or not P46 is used as
the EXIRQ5 input pin.
Bit 5
P46IRQ5E
Description
0
P46 is not used as EXIRQ5 input
1
P46 is used as EXIRQ5 input
(Initial value)
Bit 4—Enable of EXIRQ4 Input from P44 (P44IRQ4E): Selects whether or not P44 is used as
the EXIRQ4 input pin.
Bit 4
P44IRQ4E
Description
0
P44 is not used as EXIRQ4 input
1
P44 is used as EXIRQ4 input
(Initial value)
Bit 3—Enable of EXIRQ3 Input from P43 (P43IRQ3E): Selects whether or not P43 is used as
the EXIRQ3 input pin.
Bit 3
P43IRQ3E
Description
0
P43 is not used as EXIRQ3 input
1
P43 is used as EXIRQ3 input
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(Initial value)
Section 9 I/O Ports
Bit 2—Enable of EXIRQ2 Input from P42 (P42IRQ2E): Selects whether or not P42 is used as
the EXIRQ2 input pin.
Bit 2
P42IRQ2E
Description
0
P42 is not used as EXIRQ2 input
1
P42 is used as EXIRQ2 input
(Initial value)
Bit 1—Enable of EXIRQ1 Input from P41 (P41IRQ1E): Selects whether or not P41 is used as
the EXIRQ1 input pin.
Bit 1
P41IRQ1E
Description
0
P41 is not used as EXIRQ1 input
1
P41 is used as EXIRQ1 input
(Initial value)
Bit 0—Enable of EXIRQ0 Input from P40 (P40IRQ0E): Selects whether or not P40 is used as
the EXIRQ0 input pin.
Bit 0
P40IRQ0E
Description
0
P40 is not used as EXIRQ0 input
1
P40 is used as EXIRQ0 input
(Initial value)
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Section 9 I/O Ports
9.3.3
Pin Functions
Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1), interrupt
input pins (IRQ4 and IRQ5), and an external expansion interrupt input pin (EXIRQ7). Port 3 pin
functions are shown in table 9.5.
Table 9.5
Port 3 Pin Functions
Pin
Pin Functions and Selection Method
P36
The pin function is switched as shown below according to the combinations of the
P36DDR bit and bit P36IRQ7E in IPINSELQ.
P36IRQ7E
0
P36DDR
Pin function
1
0
1
—
P36 input
P36 output*
EXIRQ7 input
Note: * NMOS open-drain output when P36ODR = 1.
P35/SCK1/ The pin function is switched as shown below according to the combination of bit C/A in
RQ5
SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P35DDR.
CKE1
0
C/A
CKE0
P35DDR
Pin function
1
0
0
0
1
1
—
—
—
1
—
—
—
1
1
1
*
*
*
P35 output SCK1 output SCK1 output SCK1 input
2
IRQ5 input*
P35 input
Notes: 1. NMOS open-drain output when P35ODR = 1.
2. When used as an external interrupt pin, do not use for another function.
P34/RxD1 The pin function is switched as shown below according to the combination of bit RE in
SCR of SCI1 and bit P34DDR.
RE
0
P34DDR
Pin function
1
0
1
—
P34 input
P34 output*
RxD1 input
Note: * NMOS open-drain output when P34ODR = 1.
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P33/TxD1
The pin function is switched as shown below according to the combination of bit TE in
SCR of SCI1 and bit P33DDR.
TE
0
P33DDR
Pin function
1
0
1
—
P33 input
P33 output*
TxD1 output*
Note: * NMOS open-drain output when P33ODR = 1.
P32/SCK0/ The pin function is switched as shown below according to the combination of bit C/A in
IRQ4
SMR of SCI0, bits CKE0 and CKE1 in SCR, and bit P32DDR.
CKE1
0
C/A
0
CKE0
P32DDR
Pin function
1
0
1
—
1
—
—
0
1
—
—
—
P32 input
1
P32 output*
SCK0
1
output*
SCK0
1
output*
SCK0 input
IRQ4 input*
2
Notes: 1. NMOS open-drain output when P32ODR = 1.
2. When used as an external interrupt pin, do not use for another function.
P31/RxD0 The pin function is switched as shown below according to the combination of bit RE in
SCR of SCI0 and bit P31DDR.
RE
P31DDR
Pin function
0
1
0
1
—
P31 input
P31 output*
RxD0 input
Note: * NMOS open-drain output when P31ODR = 1.
P30/TxD0
The pin function is switched as shown below according to the combination of bit TE in
SCR of SCI0 and bit P30DDR.
TE
P30DDR
Pin function
0
1
0
1
—
P30 input
P30 output*
TxD0 output*
Note: * NMOS open-drain output when P30ODR = 1.
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Section 9 I/O Ports
9.4
Port 4
9.4.1
Overview
Port 4 is an 8-bit input-only port. Port 4 pins also function as external expansion interrupt input
pins (EXIRQ6 to EXIRQ0). Port 4 pin functions are the same in all operating modes. Figure 9.3
shows the port 4 pin configuration.
Port 4 pins
P47 (input) /EXIRQ6 (input)
P46 (input) /EXIRQ5 (input)
P45 (input)
Port 4
P44 (input) /EXIRQ4 (input)
P43 (input) /EXIRQ3 (input)
P42 (input) /EXIRQ2 (input)
P41 (input) /EXIRQ1 (input)
P40 (input) /EXIRQ0 (input)
Figure 9.3 Port 4 Pin Functions
9.4.2
Register Configuration
Table 9.6 shows the port 4 register configuration. Port 4 is an input-only register, and does not
have a data direction register or data register.
Table 9.6
Port 4 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 4 register
PORT4
R
Undefined
H'FFB3
R/W
H'00
H'FE4A
Interrupt request input pin select register 0 IPINSEL0
Note: * Lower 16 bits of the address.
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Section 9 I/O Ports
(1) Port 4 Register (PORT4)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
—*
—*
—*
—*
—*
—*
—*
—*
R
R
R
R
R
R
R
R
Note: * Determined by the state of pins P47 to P40.
PORT4 is an 8-bit read-only register. The pin states are always read when a port 4 read is
performed. This register cannot be written to.
(2) Interrupt Request Input Pin Select Register 0 (IPINSEL0)
Bit
:
Initial value :
R/W :
7
6
5
4
3
2
1
0
P36
IRQ7E
P47
IRQ6E
P46
IRQ5E
P44
IRQ4E
P43
IRQ3E
P42
IRQ2E
P41
IRQ1E
P40
IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IPINSEL0 is an 8-bit readable/writable register that selects which pins are to be used for interrupt
request input signals (EXIRQ0 to EXIRQ7) from externally connected modules. IPINSEL0 is
initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state
in a manual reset and in software standby mode.
Bit 7—Enable of EXIRQ7 Input from P36 (P36IRQ7E): Selects whether or not P36 is used as
the EXIRQ7 input pin.
Bit 7
P36IRQ7E
Description
0
P36 is not used as EXIRQ7 input
1
P36 is used as EXIRQ7 input
(Initial value)
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Section 9 I/O Ports
Bit 6—Enable of EXIRQ6 Input from P47 (P47IRQ6E): Selects whether or not P47 is used as
the EXIRQ6 input pin.
Bit 6
P47IRQ6E
Description
0
P47 is not used as EXIRQ6 input
1
P47 is used as EXIRQ6 input
(Initial value)
Bit 5— Enable of EXIRQ5 Input from P46 (P46IRQ5E): Selects whether or not P46 is used as
the EXIRQ5 input pin.
Bit 5
P46IRQ5E
Description
0
P46 is not used as EXIRQ5 input
1
P46 is used as EXIRQ5 input
(Initial value)
Bit 4—Enable of EXIRQ4 Input from P44 (P44IRQ4E): Selects whether or not P44 is used as
the EXIRQ4 input pin.
Bit 4
P44IRQ4E
Description
0
P44 is not used as EXIRQ4 input
1
P44 is used as EXIRQ4 input
(Initial value)
Bit 3—Enable of EXIRQ3 Input from P43 (P43IRQ3E): Selects whether or not P43 is used as
the EXIRQ3 input pin.
Bit 3
P43IRQ3E
Description
0
P43 is not used as EXIRQ3 input
1
P43 is used as EXIRQ3 input
Rev.4.00 Sep. 18, 2008 Page 306 of 872
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(Initial value)
Section 9 I/O Ports
Bit 2—Enable of EXIRQ2 Input from P42 (P42IRQ2E): Selects whether or not P42 is used as
the EXIRQ2 input pin.
Bit 2
P42IRQ2E
Description
0
P42 is not used as EXIRQ2 input
1
P42 is used as EXIRQ2 input
(Initial value)
Bit 1—Enable of EXIRQ1 Input from P41 (P41IRQ1E): Selects whether or not P41 is used as
the EXIRQ1 input pin.
Bit 1
P41IRQ1E
Description
0
P41 is not used as EXIRQ1 input
1
P41 is used as EXIRQ1 input
(Initial value)
Bit 0—Enable of EXIRQ0 Input from P40 (P40IRQ0E): Selects whether or not P40 is used as
the EXIRQ0 input pin.
Bit 0
P40IRQ0E
Description
0
P40 is not used as EXIRQ0 input
1
P40 is used as EXIRQ0 input
9.4.3
(Initial value)
Pin Functions
Port 4 pins also function as external expansion interrupt input pins (EXIRQ6 to EXIRQ0).
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Section 9 I/O Ports
9.5
Port 7
9.5.1
Overview
Port 7 is an 8-bit I/O port. Port 7 pins also function as DMAC input pins (DREQ0, TEND0,
DREQ1, and TEND1), bus control output pins (CS4 to CS7), external module output pins
(EXMSTP, EXMS, and EXDTCE), and the manual reset input pin (MRES). The functions of pins
P77 to P74 are the same in all operating mode, but the functions of pins P73 to P70 depend on the
operating mode.
Figure 9.4 shows the port 7 pin configuration.
Port 7
Port 7 pins
Pin functions in modes 4 to 6
P77
P77 (input/output)
P76/ EXMSTP
P76 (input/output)/EXMSTP (output)
P75 /EXMS
P75 (input/output)/EXMS (output)
P74 /MRES/EXDTCE
P74 (input/output)/MRES(input)/EXDTCE (output)
P73/ TEND1/CS7
P73 (input)/TEND1 (output)/CS7 (output)
P72/ TEND0/CS6
P72 (input)/TEND0 (output)/CS6 (output)
P71/ DREQ1/ CS5
P71 (input)/DREQ1 (input)/CS5 (output)
P70/ DREQ0/CS4
P70 (input)/DREQ0 (input)/CS4 (output)
Pin functions in mode 7
P77 (input/output)
P76 (input/output)/EXMSTP (output)
P75 (input/output) /EXMS (output)
P74 (input/output) /MRES (input)/EXDTCE (output)
P73 (input/output)/TEND1 (output)
P72 (input/output) /TEND0 (output)
P71 (input/output) /DREQ1 (input)
P70 (input/output)/DREQ0 (input)
Figure 9.4 Port 7 Pin Functions
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Section 9 I/O Ports
9.5.2
Register Configuration
Table 9.7 shows the port 7 register configuration.
Table 9.7
Port 7 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 7 data direction register
P7DDR
W
H'00
H'FE36
Port 7 data register
P7DR
R/W
H'00
H'FF06
Port 7 register
PORT7
R
Undefined
H'FFB6
External module connection output pin
select register
OPINSEL
R/W
B'-000----
H'FE4E
Note: * Lower 16 bits of the address.
(1) Port 7 Data Direction Register (P7DDR)
Bit
:
7
6
5
4
3
2
1
0
P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
P7DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 7. P7DDR cannot be read; if it is, an undefined value will be read.
Setting a P7DDR bit to 1 makes the corresponding port 7 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
Since this register is a write-only register, do not use bit manipulation instructions to write to this
register. See section 2.10.4, Access Methods for Registers with Write-Only Bits.
P7DDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode. As the 8-bit timer and SCI are
initialized by a manual reset, the pin states in this case are determined by the P7DDR and P7DR
specifications.
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Section 9 I/O Ports
(2) Port 7 Data Register (P7DR)
Bit
:
7
6
5
4
3
2
1
0
P77DR
P76DR
P75DR
P74DR
P73DR
P72DR
P71DR
P70DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value :
R/W
:
P7DR is an 8-bit readable/writable register that stores output data for the port 7 pins (P77 to P70).
P7DR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(3) Port 7 Register (PORT7)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
—*
—*
—*
—*
—*
—*
—*
—*
R
R
R
R
R
R
R
R
Note: * Determined by the state of pins P77 to P70.
PORT7 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 7 pins (P77 to P70) must always be performed on P7DR.
If a port 7 read is performed while P7DDR bits are set to 1, the P7DR values are read. If a port 7
read is performed while P7DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT7 contents are determined by the pin
states, as P7DDR and P7DR are initialized. PORT7 retains its previous state after a manual reset
and in software standby mode.
(4) External Module Connection Output Pin Select Register (OPINSEL)
Bit
:
7
6
5
4
3
2
1
0
—
P76
STPOE
P75
MSOE
P74
DTCOE
—
—
—
—
0
0
0
R/W
R/W
R/W
Initial value : Undefined
R/W :
—
Rev.4.00 Sep. 18, 2008 Page 310 of 872
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Undefined Undefined Undefined Undefined
—
—
—
—
Section 9 I/O Ports
OPINSEL is an 8-bit readable/writable register that selects whether or not output signals
(EXDTCE, EXMSTP, EXMS) to externally connected modules are output to pins P76 to P74.
OPINSEL bits 6 to 4 are initialized to 000 by a power-on reset and in hardware standby mode.
They retain their previous states in a manual reset and in software standby mode.
Bit 7—Reserved: This bit will return an undefined value if read, and should only be written with
0.
Bit 6—Enable of EXMSTP Output to P76 (P76STPOE): Selects whether or not the EXMSTP
module stop signal to external modules (bit 0 in MSTPCRB) is output to P76.
Bit 6
P76STPOE
Description
0
EXMSTP is not output to P76
1
EXMSTP is output to P76
(Initial value)
Bit 5—Enable of EXMS Output to P75 (P75MSOE): Selects whether or not the EXMS module
stop signal to external modules (corresponding to addresses H'FFFF40 to H'FFFF5F) is output to
P75.
Bit 5
P75MSOE
Description
0
EXMS is not output to P75
1
EXMS is output to P75
(Initial value)
Bit 4—Enable of EXDTCE Output to P74 (P74DTCOE): Selects whether or not the EXDTCE
signal, indicating that DTC transfer corresponding to EXIRQ0 to EXIRQF input is in progress, is
output to P74. This signal is used, for example, when the DTC in the chip has been activated by an
interrupt (EXIRQ0 to EXIRQF) from an external module, and the interrupt request is to be cleared
automatically on the external module side by DTC transfer.
Bit 4
P74DTCOE
Description
0
EXDTCE is not output to P74
1
EXDTCE is output to P74
(Initial value)
Bits 3 to 0—Reserved: These bits will return an undefined value if read, and should only be
written with 0.
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Section 9 I/O Ports
9.5.3
Pin Functions
Port 7 pins also function as DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), bus control
output pins (CS4 to CS7), external module output pins (EXMSTP, EXMS, and EXDTCE), and the
manual reset input pin (MRES). Port 7 pin functions are shown in table 9.8.
Table 9.8
Port 7 Pin Functions
Pin
Pin Functions and Selection Method
P77
The pin function is switched as shown below according to the setting of bit P77DDR.
P77DDR
Pin function
P76/
EXMSTP
0
1
P77 input
P77 output
The pin function is switched as shown below according to the combination of bit
P76STPOE in OPINSEL and bit P76DDR.
P76STPOE
0
P76DDR
Pin function
1
0
1
—
P76 input
P76 output
EXMSTP output
P75/EXMS The pin function is switched as shown below according to the combination of bit
P75MSOE in OPINSEL and bit P75DDR.
P75MSOE
0
P75DDR
Pin function
1
0
1
—
P75 input
P75 output
EXMS output
P74/MRES/ The pin function is switched as shown below according to the combination of bit
EXDTCE
MRESE in SYSCR and bit P74DDR.
P74DTCOE
0
MRESE
P74DDR
Pin function
0
1
1
—
0
1
0
—
P74 input
P74 output
MRES input
EXDTCE output
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P73/TEND1/ The pin function is switched as shown below according to the combination of the
CS7
operating mode, bit TEE1 in DMATCR of the DMAC, and bit P73DDR.
Operating mode
Modes 4, 5, 6
TEE1
0
P73DDR
Pin function
Mode 7
1
0
1
0
1
—
0
1
—
P73
input
CS7
output
TEND1
output
P73 input
P73
output
TEND1
output
P72/TEND0/ The pin function is switched as shown below according to the combination of the
CS6
operating mode, bit TEE0 in DMATCR of the DMAC, and bit P72DDR.
Operating mode
Modes 4, 5, 6
TEE0
0
P72DDR
Pin function
Mode 7
1
0
1
0
1
—
0
1
—
P72
input
CS6
output
TEND0
output
P72
input
P72
output
TEND0
output
P71/DREQ1/ The pin function is switched as shown below according to the combination of the
CS5
operating mode and bit P71DDR.
Operating mode
P71DDR
Pin function
Modes 4, 5, 6
Mode 7
0
1
0
1
P71 input
CS5 output
P71 input
P71 output
DREQ1 input
P70/DREQ0/ The pin function is switched as shown below according to the combination of the
CS4
operating mode and bit P70DDR.
Operating mode
P70DDR
Pin function
Modes 4, 5, 6
Mode 7
0
1
0
1
P70 input
CS4 output
P70 input
P70 output
DREQ0 input
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Section 9 I/O Ports
9.6
Port 9
9.6.1
Overview
Port 9 is a 1-bit input-only port. Port 9 pins also function as D/A converter analog output pin
(DA0). Port 9 pin functions are the same in all operating modes. Figure 9.5 shows the port 9 pin
configuration.
Port 9 pins
Port 9
P96 (input)/DA0 (output)
Figure 9.5 Port 9 Pin Functions
9.6.2
Register Configuration
Table 9.9 shows the port 9 register configuration. Port 9 is an input-only register, and does not
have a data direction register or data register.
Table 9.9
Port 9 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 9 register
PORT9
R
Undefined
H'FFB8
Note: * Lower 16 bits of the address.
(1) Port 9 Register (PORT9)
Bit
:
7
6
5
4
3
2
1
0
—
P96
—
—
—
—
—
—
Initial value :
—
—*
—
—
—
—
—
—
R/W
R
R
R
R
R
R
R
R
:
Note: * Determined by the state of pin P96.
PORT9 is an 8-bit read-only register. The pin states are always read when a port 9 read is
performed. This register cannot be written to. Bits 7 and 5 to 0 are reserved, and will return an
undefined value if read.
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Section 9 I/O Ports
9.6.3
Pin Functions
Port 9 pins also function as D/A converter analog output pin (DA0).
9.7
Port A
9.7.1
Overview
Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and SCI2 I/O pins
(SCK2, RxD2, and TxD2). The pin functions depend on the operating mode.
Port A has an on-chip MOS input pull-up function that can be controlled by software.
Figure 9.6 shows the port A pin configuration.
Port A
Port A pins
Pin functions in modes 4, 5, and 6
PA3/A19/SCK2
PA3 (input/output) /A19 (output) /SCK2 (input/output)
PA2/ A18/RxD2
PA2 (input/output) /A18 (output) /RxD2 (input)
PA1/ A17/TxD2
PA1 (input/output) /A17 (output) /TxD2 (output)
PA0/ A16
PA0 (input/output)/A16 (output)
Pin functions in mode 7
PA3 (input/output) /SCK2 (input/output)
PA2 (input/output) /RxD2 (input)
PA1 (input/output) /TxD2 (output)
PA0 (input/output)
Figure 9.6 Port A Pin Functions
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Section 9 I/O Ports
9.7.2
Register Configuration
Table 9.10 shows the port A register configuration.
Table 9.10 Port A Registers
Name
Abbreviation
R/W
2
1
Initial Value* Address*
Port A data direction register
PADDR
W
H'0
Port A data register
PADR
R/W
H'0
H'FF09
Port A register
PORTA
R
Undefined
H'FFB9
Port A MOS pull-up control register
PAPCR
R/W
H'0
H'FE40
Port A open-drain control register
PAODR
R/W
H'0
H'FE47
H'FE39
Notes: 1. Lower 16 bits of the address.
2. Value of bits 3 to 0.
(1) Port A Data Direction Register (PADDR)
Bit
:
7
6
5
4
—
—
—
—
3
2
1
0
PA3DDR PA2DDR PA1DDR PA0DDR
Initial value : Undefined Undefined Undefined Undefined
0
0
0
0
R/W
W
W
W
W
:
—
—
—
—
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.
Since this register is a write-only register, do not use bit manipulation instructions to write to this
register. See section 2.10.4, Access Methods for Registers with Write-Only Bits.
PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its previous state after a manual reset and in software standby mode. The OPE bit in
SBYCR is used to select whether the address output pins retain their output state or become highimpedance when a transition is made to software standby mode.
(a) Modes 4 to 6
If address output is enabled by the setting of bits AE3 to AE0 in PFCR, the corresponding port
A pins are address outputs.
When address output is disabled, setting a PADDR bit to 1 makes the corresponding port A pin
an output port, while clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports
(b) Mode 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
(2) Port A Data Register (PADR)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
PA3DR
PA2DR
PA1DR
PA0DR
0
0
0
0
R/W
R/W
R/W
R/W
Initial value : Undefined Undefined Undefined Undefined
R/W
:
—
—
—
—
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to
PA0).
Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.
PADR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its previous state after a manual reset and in software standby mode.
(3) Port A Register (PORTA)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
PA3
PA2
PA1
PA0
Initial value : Undefined Undefined Undefined Undefined
—*
—*
—*
—*
R/W
R
R
R
R
:
—
—
—
—
Note: * Determined by the state of pins PA3 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA3 to PA0) must always be performed on PADR.
Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin
states, as PADDR and PADR are initialized. PORTA retains its previous state after a manual reset
and in software standby mode.
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Section 9 I/O Ports
(4) Port A MOS Pull-Up Control Register (PAPCR)
Bit
:
7
6
5
4
—
—
—
—
3
:
—
—
—
1
0
PA3PCR PA2PCR PA1PCR PA0PCR
Initial value : Undefined Undefined Undefined Undefined
R/W
2
—
0
0
0
0
R/W
R/W
R/W
R/W
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on a bit-by-bit basis.
Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.
PAPCR is valid for port input and SCI input pins. When a PADDR bit is cleared to 0 (input port
setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the
corresponding pin.
PAPCR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its previous state after a manual reset and in software standby mode.
(5) Port A Open-Drain Control Register (PAODR)
Bit
:
7
6
5
4
—
—
—
—
Initial value : Undefined Undefined Undefined Undefined
R/W
:
—
—
—
—
3
2
1
0
PA3ODR PA2ODR PA1ODR PA0ODR
0
0
0
0
R/W
R/W
R/W
R/W
PAODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port A
pin (PA3 to PA0).
Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.
PAODR is valid for port output and SCI output pins.
Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output pin,
while clearing the bit to 0 makes the pin a CMOS output pin.
PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its previous state after a manual reset and in software standby mode.
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Section 9 I/O Ports
9.7.3
Pin Functions
Port A pins also function as SCI2 I/O pins (TxD2, RxD2, and SCK2) and address output pins
(A19 to A16). Port A pin functions are shown in table 9.11.
Table 9.11 Port A Pin Functions
Pin
Pin Functions and Selection Method
PA3/A19/
SCK2
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, SCI channel 2 settings, and bit PA3DDR.
Operating mode
AE3 to AE0
Modes 4 to 6
11xx
CKE1
—
C/A
—
CKE0
—
PA3DDR
—
Pin function
Other than 11xx
0
1
—
1
—
—
1
—
—
—
PA3
output*
SCK2
output*
SCK2
output*
SCK2
input
0
0
A19 output PA3 input
Operating mode
Mode 7
AE3 to AE0
—
CKE1
0
C/A
Pin function
1
0
CKE0
PA3DDR
1
0
0
1
—
1
—
—
0
1
—
—
—
PA3 input
PA3 output*
SCK2
output*
SCK2
output*
SCK2 input
Note: * NMOS open-drain output when PA3ODR = 1 in PAODR.
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PA2/A18/
RxD2
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, SCI channel 2 settings, and bit PA2DDR.
Operating
mode
AE3 to AE0
Modes 4 to 6
1011 or
11xx
Mode 7
Other than (1011 or 11xx)
RE
—
PA2DDR
—
0
1
—
0
1
—
A18
output
PA2
input
PA2
output*
RxD2
input
PA2
input
PA2
output*
RxD2
input
Pin function
0
—
1
0
1
Note: * NMOS open-drain output when PA2ODR = 1 in PAODR.
PA1/A17/
TxD2
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, SCI channel 2 settings, and bit PA1DDR.
Operating
mode
AE3 to AE0
Modes 4 to 6
101x or
11xx
Mode 7
Other than (101x or 11xx)
TE
—
PA1DDR
—
0
1
—
0
1
—
A17
output
PA1
input
PA1
output*
TxD2
output*
PA1
input
PA1
output*
TxD2
output*
Pin function
0
—
1
0
1
Note: * NMOS open-drain output when PA1ODR = 1 in PAODR.
PA0/A16
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, and bit PA0DDR.
Operating mode
AE3 to AE0
PA1DDR
Pin function
Modes 4 to 6
Other than
(0xxx or 1000)
Mode 7
0xxx or 1000
—
—
0
1
0
1
A16 output
PA0 input
PA0
output*
PA0 input
PA0
output*
Note: * NMOS open-drain output when PA0ODR = 1 in PAODR.
Rev.4.00 Sep. 18, 2008 Page 320 of 872
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Section 9 I/O Ports
9.7.4
MOS Input Pull-Up Function
Port A has an on-chip MOS input pull-up function that can be controlled by software. MOS input
pull-up can be specified as on or off for individual bits.
With port input and SCI input pins, when a PADDR bit is cleared to 0, setting the corresponding
PAPCR bit to 1 turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a power-on reset and in hardware standby
mode. The previous state is retained after a manual reset and in software standby mode.
Table 9.12 summarizes the MOS input pull-up states.
Table 9.12 MOS Input Pull-Up States (Port A)
Hardware
Power-On Standby
Mode
Reset
Manual
Reset
Software
Standby
Mode
In Other
Operations
Address output, port output, SCI
output
OFF
OFF
OFF
OFF
OFF
Port input, SCI input
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
Pins
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PADDR = 0 and PAPCR = 1; otherwise off.
Rev.4.00 Sep. 18, 2008 Page 321 of 872
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Section 9 I/O Ports
9.8
Port B
9.8.1
Overview
Port B is an 8-bit I/O port. Port B pins also function as address bus outputs. The pin functions
depend on the operating mode.
Port B has an on-chip MOS input pull-up function that can be controlled by software.
Figure 9.7 shows the port B pin configuration.
Port B
Port B pins
Pin functions in modes 4 to 6
PB7/A15
PB7 (input/output)/A15 (output)
PB6/A14
PB6 (input/output)/A14 (output)
PB5/A13
PB5 (input/output)/A13 (output)
PB4/A12
PB4 (input/output)/A12 (output)
PB3/A11
PB3 (input/output)/A11 (output)
PB2/A10
PB2 (input/output)/A10 (output)
PB1/A9
PB1 (input/output)/A9 (output)
PB0/A8
PB0 (input/output)/A8 (output)
Pin functions in mode 7
PB7 (input/output)
PB6 (input/output)
PB5 (input/output)
PB4 (input/output)
PB3 (input/output)
PB2 (input/output)
PB1 (input/output)
PB0 (input/output)
Figure 9.7 Port B Pin Functions
Rev.4.00 Sep. 18, 2008 Page 322 of 872
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Section 9 I/O Ports
9.8.2
Register Configuration
Table 9.13 shows the port B register configuration.
Table 9.13 Port B Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port B data direction register
PBDDR
W
H'00
H'FE3A
Port B data register
PBDR
R/W
H'00
H'FF0A
Port B register
PORTB
R
Undefined
H'FFBA
Port B MOS pull-up control register
PBPCR
R/W
H'00
H'FE41
Note: * Lower 16 bits of the address.
(1) Port B Data Direction Register (PBDDR)
Bit
:
7
6
5
4
3
2
1
0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
Since this register is a write-only register, do not use bit manipulation instructions to write to this
register. See section 2.10.4, Access Methods for Registers with Write-Only Bits.
PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode. The OPE bit in SBYCR is used
to select whether the address output pins retain their output state or become high-impedance when
a transition is made to software standby mode.
(a) Modes 4 to 6
If address output is enabled by the setting of bits AE3 to AE0 in PFCR, the corresponding port
B pins are address outputs.
When address output is disabled, setting a PBDDR bit to 1 makes the corresponding port B pin
an output port, while clearing the bit to 0 makes the pin an input port.
(b) Mode 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
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Section 9 I/O Ports
(2) Port B Data Register (PBDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PB7DR
PB6DR
PB5DR
PB4DR
PB3DR
PB2DR
PB1DR
PB0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to
PB0).
PBDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(3) Port B Register (PORTB)
Bit
:
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Initial value :
—*
—*
—*
—*
—*
—*
—*
—*
R/W
R
R
R
R
R
R
R
R
:
Note: * Determined by the state of pins PB7 to PB0.
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port B pins (PB7 to PB0) must always be performed on PBDR.
If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B
read is performed while PBDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin
states, as PBDDR and PBDR are initialized. PORTB retains its previous state after a manual reset
and in software standby mode.
(4) Port B MOS Pull-Up Control Register (PBPCR)
Bit
:
7
6
5
4
3
2
1
0
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 9 I/O Ports
PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port B on a bit-by-bit basis.
PBPCR is valid for port input and TPU input pins.
When a PBDDR bit is cleared to 0 (input port setting), setting the corresponding PBPCR bit to 1
turns on the MOS input pull-up for the corresponding pin.
PBPCR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
9.8.3
Pin Functions
Port B pins also function as address output pins (A15 to A8). Port B pin functions are shown in
table 9.14.
Table 9.14 Port B Pin Functions
Pin
Pin Functions and Selection Method
PB7/A15
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, and bit PB7DDR.
Operating mode
AE3 to AE0 in
PFCR
PB7DDR
Pin function
Modes 4 to 6
B'1xxx
Other than B'1xxx
—
0
1
A15 output
PB7 input
PB7 output
Operating mode
Mode 7
—
AE3 to AE0 in
PFCR
PB7DDR
Pin function
0
1
PB7 input
PB7 output
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PB6/A14
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, and bit PB6DDR.
Operating mode
AE3 to AE0 in
PFCR
Modes 4 to 6
B'0111 or B'1xxx
PB6DDR
Pin function
—
0
1
A14 output
PB6 input
PB6 output
Operating mode
Mode 7
—
AE3 to AE0 in
PFCR
PB6DDR
Pin function
PB5/A13
Other than (B'0111 or B'1xxx)
0
1
PB6 input
PB6 output
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, and bit PB5DDR.
Operating mode
Modes 4 to 6
AE3 to AE0 in
B'011x or B'1xxx
Other than (B'011x or B'1xxx)
PFCR
PB5DDR
—
0
1
Pin function
A13 output
PB5 input
PB5 output
Operating mode
Mode 7
—
AE3 to AE0 in
PFCR
PB5DDR
Pin function
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0
1
PB5 input
PB5 output
Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PB4/A12
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, and bit PB4DDR.
Operating mode
Modes 4 to 6
AE3 to AE0 in
B'0100 or B'00xx
Other than (B'0100 or
PFCR
B'00xx)
PB5DDR
0
1
—
Pin function
PB4 input
PB4 output
A12 output
Operating mode
AE3 to AE0 in
PFCR
PB4DDR
Pin function
PB3/A11
Mode 7
—
0
PB4 input
1
PB4 output
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, and bit PB3DDR.
Operating mode
Modes 4 to 6
B'00xx
AE3 to AE0 in
PFCR
PB3DDR
Pin function
0
1
—
PB3 input
PB3 output
A11 output
Operating mode
Mode 7
—
AE3 to AE0 in
PFCR
PB3DDR
Pin function
Other than B'00xx
0
1
PB3 input
PB3 output
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PB2/A10
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, and bit PB2DDR.
Operating mode
Modes 4 to 6
B'0010 or B'000x
AE3 to AE0 in
PFCR
PB2DDR
Pin function
0
1
—
PB2 input
PB2 output
A10 output
Operating mode
Mode 7
—
AE3 to AE0 in
PFCR
PB2DDR
Pin function
PB1/A9
Other than B'0010
or B'000x
0
1
PB2 input
PB2 output
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, and bit PB1DDR.
Operating mode
Modes 4 to 6
B'000x
AE3 to AE0 in
PFCR
PB1DDR
Pin function
Other than B'000x
0
1
—
PB1 input
PB1 output
A9 output
Operating mode
Mode 7
—
AE3 to AE0 in
PFCR
PB1DDR
Pin function
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0
1
PB1 input
PB1 output
Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PB0/A8
The pin function is switched as shown below according to the combination of the
operating mode, PFCR setting, bit PB1DDR.
Operating mode
Modes 4 to 6
B'0000
AE3 to AE0 in
PFCR
P30DDR
Pin function
Other than B'0000
0
1
—
PB0 input
PB0 output
A8 output
Operating mode
Mode 7
—
AE3 to AE0 in
PFCR
PB0DDR
Pin function
9.8.4
0
1
PB0 input
PB0 output
MOS Input Pull-Up Function
Port B has an on-chip MOS input pull-up function that can be controlled by software. MOS input
pull-up can be specified as on or off for individual bits.
With port input pins, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1
turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a power-on reset and in hardware standby
mode. The previous state is retained after a manual reset and in software standby mode.
Table 9.15 summarizes the MOS input pull-up states.
Table 9.15 MOS Input Pull-Up States (Port B)
Pins
Power-On
Reset
Hardware
Standby
Mode
Manual
Reset
Software
Standby
Mode
In Other
Operations
Address output, port output
OFF
OFF
OFF
OFF
OFF
Port input
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PBDDR = 0 and PBPCR = 1; otherwise off.
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Section 9 I/O Ports
9.9
Port C
9.9.1
Overview
Port C is an 8-bit I/O port. Port C pins also function as address bus outputs. The pin functions
depend on the operating mode.
Port C has an on-chip MOS input pull-up function that can be controlled by software.
Figure 9.8 shows the port C pin configuration.
Port C
Port C pins
Pin functions in modes 4 and 5
PC7/A7
A7 (output)
PC6/A6
A6 (output)
PC5/A5
A5 (output)
PC4/A4
A4 (output)
PC3/A3
A3 (output)
PC2/A2
A2 (output)
PC1/A1
A1 (output)
PC0/A0
A0 (output)
Pin functions in mode 6
Pin functions in mode 7
PC7 (input)/A7 (output)
PC7 (input/output)
PC6 (input)/A6 (output)
PC6 (input/output)
PC5 (input)/A5 (output)
PC5 (input/output)
PC4 (input)/A4 (output)
PC4 (input/output)
PC3 (input)/A3 (output)
PC3 (input/output)
PC2 (input)/A2 (output)
PC2 (input/output)
PC1 (input)/A1 (output)
PC1 (input/output)
PC0 (input)/A0 (output)
PC0 (input/output)
Figure 9.8 Port C Pin Functions
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Section 9 I/O Ports
9.9.2
Register Configuration
Table 9.16 shows the port C register configuration.
Table 9.16 Port C Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port C data direction register
PCDDR
W
H'00
H'FE3B
Port C data register
PCDR
R/W
H'00
H'FF0B
Port C register
PORTC
R
Undefined
H'FFBB
Port C MOS pull-up control register
PCPCR
R/W
H'00
H'FE42
Note: * Lower 16 bits of the address.
(1) Port C Data Direction Register (PCDDR)
Bit
:
7
6
5
4
3
2
1
0
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.
Setting a PCDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit
to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section 2.10.4, Access Methods for
Registers with Write-Only Bits.
PCDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode. The OPE bit in SBYCR is used
to select whether the address output pins retain their output state or become high-impedance when
a transition is made to software standby mode.
(a) Modes 4 and 5
Port C pins are address outputs regardless of the PCDDR settings.
(b) Mode 6
Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while
clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports
(c) Mode 7
Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing
the bit to 0 makes the pin an input port.
(2) Port C Data Register (PCDR)
Bit
:
7
6
5
4
3
2
1
0
PC7DR
PC6DR
PC5DR
PC4DR
PC3DR
PC2DR
PC1DR
PC0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value :
R/W
:
PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to
PC0).
PCDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(3) Port C Register (PORTC)
Bit
:
7
6
5
4
3
2
1
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Initial value :
—*
—*
—*
—*
—*
—*
—*
—*
R/W
R
R
R
R
R
R
R
R
:
Note: * Determined by the state of pins PC7 to PC0.
PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port C pins (PC7 to PC0) must always be performed on PCDR.
If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C
read is performed while PCDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTC contents are determined by the pin
states, as PCDDR and PCDR are initialized. PORTC retains its previous state after a manual reset
and in software standby mode.
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Section 9 I/O Ports
(4) Port C MOS Pull-Up Control Register (PCPCR)
Bit
:
7
6
5
4
3
2
1
0
PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port C on a bit-by-bit basis.
PCPCR is valid for port input (modes 6 and 7).
When a PCDDR bit is cleared to 0 (input port setting), setting the corresponding PCPCR bit to 1
turns on the MOS input pull-up for the corresponding pin.
PCPCR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
9.9.3
Pin Functions in Each Mode
(1) Modes 4 and 5
In modes 4 and 5, port C pins function as address outputs automatically. Port C pin functions in
modes 4 and 5 are shown in figure 9.9.
A7 (output)
A6 (output)
A5 (output)
Port C
A4 (output)
A3 (output)
A2 (output)
A1 (output)
A0 (output)
Figure 9.9 Port C Pin Functions (Modes 4 and 5)
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Section 9 I/O Ports
(2) Mode 6
In mode 6, port C pins function as address outputs or input ports, and input or output can be
specified bit by bit. Setting a PCDDR bit to 1 makes the corresponding port C pin an address
output, while clearing the bit to 0 makes the pin an input port.
Port C pin functions in mode 6 are shown in figure 9.10.
Port C
When PCDDR = 1
When PCDDR = 0
A7 (output)
PC7 (input)
A6 (output)
PC6 (input)
A5 (output)
PC5 (input)
A4 (output)
PC4 (input)
A3 (output)
PC3 (input)
A2 (output)
PC2 (input)
A1 (output)
PC1 (input)
A0 (output)
PC0 (input)
Figure 9.10 Port C Pin Functions (Mode 6)
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Section 9 I/O Ports
(3) Mode 7
In mode 7, port C functions as an I/O port, and input or output can be specified bit by bit. Setting a
PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0
makes the pin an input port.
Port C pin functions in mode 7 are shown in figure 9.11.
PC7 (input/output)
PC6 (input/output)
PC5 (input/output)
Port C
PC4 (input/output)
PC3 (input/output)
PC2 (input/output)
PC1 (input/output)
PC0 (input/output)
Figure 9.11 Port C Pin Functions (Mode 7)
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Section 9 I/O Ports
9.9.4
MOS Input Pull-Up Function
Port C has an on-chip MOS input pull-up function that can be controlled by software. MOS input
pull-up can be used in modes 6 and 7, and can be specified as on or off for individual bits.
With the port input pin function (modes 6 and 7), when a PCDDR bit is cleared to 0, setting the
corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a power-on reset and in hardware standby
mode. The previous state is retained after a manual reset and in software standby mode.
Table 9.17 summarizes the MOS input pull-up states.
Table 9.17 MOS Input Pull-Up States (Port C)
Hardware
Power-On Standby
Mode
Reset
Manual
Reset
Software
Standby
Mode
In Other
Operations
Address output (modes 4 and 5),
port output (modes 6 and 7)
OFF
OFF
OFF
OFF
OFF
Port input (modes 6 and 7)
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
Pins
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PCDDR = 0 and PCPCR = 1; otherwise off.
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Section 9 I/O Ports
9.10
Port D
9.10.1
Overview
Port D is an 8-bit I/O port. Port D pins also function as data bus input/output pins. The pin
functions depend on the operating mode.
Port D has an on-chip MOS input pull-up function that can be controlled by software.
Figure 9.12 shows the port D pin configuration.
Port D
Port D pin
Pin functions in modes 4 to 6
PD7/D15
D15 (input/output)
PD6/D14
D14 (input/output)
PD5/D13
D13 (input/output)
PD4/D12
D12 (input/output)
PD3/D11
D11 (input/output)
PD2/D10
D10 (input/output)
PD1/D9
D9 (input/output)
PD0/D8
D8 (input/output)
Pin functions in mode 7
PD7 (input/output)
PD6 (input/output)
PD5 (input/output)
PD4 (input/output)
PD3 (input/output)
PD2 (input/output)
PD1 (input/output)
PD0 (input/output)
Figure 9.12 Port D Pin Functions
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Section 9 I/O Ports
9.10.2
Register Configuration
Table 9.18 shows the port D register configuration.
Table 9.18 Port D Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port D data direction register
PDDDR
W
H'00
H'FE3C
Port D data register
PDDR
R/W
H'00
H'FF0C
Port D register
PORTD
R
Undefined
H'FFBC
Port D MOS pull-up control register
PDPCR
R/W
H'00
H'FE43
Note: * Lower 16 bits of the address.
(1) Port D Data Direction Register (PDDDR)
Bit
:
7
6
5
4
3
2
1
0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
Setting a PDDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit
to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section 2.10.4, Access Methods for
Registers with Write-Only Bits.
PDDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(a) Modes 4 to 6
The input/output direction settings in PDDDR are ignored, and port D pins automatically
function as data input/output pins.
(b) Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing
the bit to 0 makes the pin an input port.
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Section 9 I/O Ports
(2) Port D Data Register (PDDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PD7DR
PD6DR
PD5DR
PD4DR
PD3DR
PD2DR
PD1DR
PD0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to
PD0).
PDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(3) Port D Register (PORTD)
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Initial value :
—*
—*
—*
—*
—*
—*
—*
—*
R/W
R
R
R
R
R
R
R
R
Bit
:
:
Note: * Determined by the state of pins PD7 to PD0.
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port D pins (PD7 to PD0) must always be performed on PDDR.
If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D
read is performed while PDDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin
states, as PDDDR and PDDR are initialized. PORTD retains its previous state after a manual reset
and in software standby mode.
(4) Port D MOS Pull-Up Control Register (PDPCR)
Bit
:
7
6
5
4
3
2
1
0
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 9 I/O Ports
PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port D on a bit-by-bit basis.
PDPCR is valid for port input pins (mode 7). When a PDDDR bit is cleared to 0 (input port
setting), setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the
corresponding pin.
PDPCR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
9.10.3
Pin Functions in Each Mode
(1) Modes 4 to 6
In modes 4 to 6, port D pins function as data input/output pins automatically. Port D pin functions
in modes 4 to 6 are shown in figure 9.13.
D15 (input/output)
D14 (input/output)
D13 (input/output)
Port D
D12 (input/output)
D11 (input/output)
D10 (input/output)
D9 (input/output)
D8 (input/output)
Figure 9.13 Port D Pin Functions (Modes 4 to 6)
(2) Mode 7
In mode 7, port D functions as an I/O port, and input or output can be specified bit by bit. Setting a
PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0
makes the pin an input port.
Port D pin functions in mode 7 are shown in figure 9.14.
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Section 9 I/O Ports
PD7 (input/output)
PD6 (input/output)
PD5 (input/output)
Port D
PD4 (input/output)
PD3 (input/output)
PD2 (input/output)
PD1 (input/output)
PD0 (input/output)
Figure 9.14 Port D Pin Functions (Mode 7)
9.10.4
MOS Input Pull-Up Function
Port D has an on-chip MOS input pull-up function that can be controlled by software. MOS input
pull-up can be used in mode 7, and can be specified as on or off for individual bits.
With the port input pin function (mode 7), when a PDDDR bit is cleared to 0, setting the
corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a power-on reset and in hardware standby
mode. The previous state is retained after a manual reset and in software standby mode.
Table 9.19 summarizes the MOS input pull-up states.
Table 9.19 MOS Input Pull-Up States (Port D)
Hardware
Power-On Standby
Reset
Mode
Manual
Reset
Software
Standby
Mode
In Other
Operations
Data input/output (modes 4 to 6),
port output (mode 7)
OFF
OFF
OFF
OFF
OFF
Port input (mode 7)
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
Pins
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PDDDR = 0 and PDPCR = 1; otherwise off.
Rev.4.00 Sep. 18, 2008 Page 341 of 872
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Section 9 I/O Ports
9.11
Port E
9.11.1
Overview
Port E is an 8-bit I/O port. Port E pins also function as data bus input/output pins. The pin
functions depend on the operating mode and on whether 8-bit or 16-bit bus mode is used.
Port E has an on-chip MOS input pull-up function that can be controlled by software.
Figure 9.15 shows the port E pin configuration.
Port E
Port E pins
Pin functions in modes 4 to 6
PE7/D7
PE7 (input/output)/D7 (input/output)
PE6/D6
PE6 (input/output)/D6 (input/output)
PE5/D5
PE5 (input/output)/D5 (input/output)
PE4/D4
PE4 (input/output)/D4 (input/output)
PE3/D3
PE3 (input/output)/D3 (input/output)
PE2/D2
PE2 (input/output)/D2 (input/output)
PE1/D1
PE1 (input/output)/D1 (input/output)
PE0/D0
PE0 (input/output)/D0 (input/output)
Pin functions in mode 7
PE7 (input/output)
PE6 (input/output)
PE5 (input/output)
PE4 (input/output)
PE3 (input/output)
PE2 (input/output)
PE1 (input/output)
PE0 (input/output)
Figure 9.15 Port E Pin Functions
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Section 9 I/O Ports
9.11.2
Register Configuration
Table 9.20 shows the port E register configuration.
Table 9.20 Port E Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port E data direction register
PEDDR
W
H'00
H'FE3D
Port E data register
PEDR
R/W
H'00
H'FF0D
Port E register
PORTE
R
Undefined
H'FFBD
Port E MOS pull-up control register
PEPCR
R/W
H'00
H'FE44
Note: * Lower 16 bits of the address.
(1) Port E Data Direction Register (PEDDR)
Bit
7
:
6
5
4
3
2
1
0
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
Setting a PEDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit
to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section 2.10.4, Access Methods for
Registers with Write-Only Bits.
PEDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(a) Modes 4 to 6
When 8-bit bus mode is selected, port E functions as an I/O port. Setting a PEDDR bit to 1
makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an
input port.
When 16-bit bus mode is selected, the input/output direction settings in PEDDR are ignored,
and port E pins automatically function as data input/output pins.
For details of the 8-bit and 16-bit bus modes, see section 6, Bus Controller.
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(b) Mode 7
Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the
bit to 0 makes the pin an input port.
(2) Port E Data Register (PEDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PE7DR
PE6DR
PE5DR
PE4DR
PE3DR
PE2DR
PE1DR
PE0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to
PE0).
PEDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(3) Port E Register (PORTE)
Bit
:
7
6
5
4
3
2
1
0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Initial value :
—*
—*
—*
—*
—*
—*
—*
—*
R/W
R
R
R
R
R
R
R
R
:
Note: * Determined by the state of pins PE7 to PE0.
PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port E pins (PE7 to PE0) must always be performed on PEDR.
If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E
read is performed while PEDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin
states, as PEDDR and PEDR are initialized. PORTE retains its previous state after a manual reset
and in software standby mode.
(4) Port E MOS Pull-Up Control Register (PEPCR)
Bit
:
7
6
5
4
3
2
1
0
PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 9 I/O Ports
PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port E on a bit-by-bit basis.
PEPCR is valid for port input pins (modes 4 to 6 in 8-bit bus mode, or mode 7).
When a PEDDR bit is cleared to 0 (input port setting), setting the corresponding PEPCR bit to 1
turns on the MOS input pull-up for the corresponding pin.
PEPCR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
9.11.3
Pin Functions in Each Mode
(1) Modes 4 to 6
In modes 4 to 6, if 8-bit access space is designated and 8-bit bus mode is selected, port E functions
as an I/O port. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while
clearing the bit to 0 makes the pin an input port.
When 16-bit bus mode is selected, the input/output direction settings in PEDDR are ignored, and
port E pins function as data input/output pins.
Port E pin functions in modes 4 to 6 are shown in figure 9.16.
Port E
8-bit bus mode
16-bit bus mode
PE7 (input/output)
D7 (input/output)
PE6 (input/output)
D6 (input/output)
PE5 (input/output)
D5 (input/output)
PE4 (input/output)
D4 (input/output)
PE3 (input/output)
D3 (input/output)
PE2 (input/output)
D2 (input/output)
PE1 (input/output)
D1 (input/output)
PE0 (input/output)
D0 (input/output)
Figure 9.16 Port E Pin Functions (Modes 4 to 6)
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(2) Mode 7
In mode 7, port E functions as an I/O port, and input or output can be specified bit by bit. Setting a
PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0
makes the pin an input port.
Port E pin functions in mode 7 are shown in figure 9.17.
PE7 (input/output)
PE6 (input/output)
PE5 (input/output)
Port E
PE4 (input/output)
PE3 (input/output)
PE2 (input/output)
PE1 (input/output)
PE0 (input/output)
Figure 9.17 Port E Pin Functions (Mode 7)
9.11.4
MOS Input Pull-Up Function
Port E has an on-chip MOS input pull-up function that can be controlled by software. MOS input
pull-up can be used in modes 4 to 6 in 8-bit bus mode, or in mode 7, and can be specified as on or
off for individual bits.
With the port input pin function (modes 4 to 6 in 8-bit bus mode, or mode 7), when a PEDDR bit
is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that
pin.
The MOS input pull-up function is in the off state after a power-on reset and in hardware standby
mode. The previous state is retained after a manual reset and in software standby mode.
Table 9.21 summarizes the MOS input pull-up states.
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Section 9 I/O Ports
Table 9.21 MOS Input Pull-Up States (Port E)
Pins
Hardware
Power-On Standby
Mode
Reset
Manual
Reset
Software
Standby
Mode
In Other
Operations
Data input/output (modes 4 to 6
OFF
with 16-bit bus), port output (modes
4 to 6 with 8-bit bus, mode 7)
OFF
OFF
OFF
OFF
Port input (modes 4 to 6 with 8-bit
bus, mode 7)
OFF
ON/OFF
ON/OFF
ON/OFF
OFF
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PEDDR = 0 and PEPCR = 1; otherwise off.
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Section 9 I/O Ports
9.12
Port F
9.12.1
Overview
Port F is an 8-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and
IRQ3), bus control signal I/O pins (AS, RD, HWR, LWR, WAIT, BREQ, and BACK), and the
system clock (φ) output pin.
The interrupt input pins (IRQ2 and IRQ3) are Schmitt-triggered inputs.
Figure 9.18 shows the port F pin configuration.
Port F
Port F pins
Pin functions in mode 7
PF7/φ
PF7 (input)/φ (output)
PF6/AS
PF6 (input/output)
PF5/RD
PF5 (input/output)
PF4/HWR
PF4 (input/output)
PF3/LWR/IRQ3
PF3 (input/output)/IRQ3 (input)
PF2/WAIT
PF2 (input/output)
PF1/BACK
PF1 (input/output)
PF0/BREQ/IRQ2
PF0 (input/output)/IRQ2 (input)
Pin functions in modes 4 to 6
PF7 (input)/φ (output)
AS (output)
RD (output)
HWR (output)
PF3 (input/output)/LWR (output)/IRQ3 (input)
PF2 (input/output)/WAIT (input)
PF1 (input/output)/BACK (output)
PF0 (input/output)/BREQ (input)/IRQ2 (input)
Figure 9.18 Port F Pin Functions
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9.12.2
Register Configuration
Table 9.22 shows the port F register configuration.
Table 9.22 Port F Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
Port F data direction register
PFDDR
W
2
H'80/H'00*
H'FE3E
Port F data register
PFDR
R/W
H'00
H'FF0E
Port F register
PORTF
R
Undefined
H'FFBE
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode. Initialized to H'80 in modes 4 to 6, and to H'00 in
mode 7.
(1) Port F Data Direction Register (PFDDR)
Bit
:
7
6
5
4
3
2
1
0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 4 to 6 :
Initial value
:
1
0
0
0
0
0
0
0
R/W
:
W
W
W
W
W
W
W
W
Mode 7
:
Initial value
:
0
0
0
0
0
0
0
0
R/W
:
W
W
W
W
W
W
W
W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
Setting a PFDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit
to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section 2.10.4, Access Methods for
Registers with Write-Only Bits.
PFDDR is initialized to H'80 (modes 4 to 6) or H'00 (mode 7) by a power-on reset and in hardware
standby mode. It retains its previous state after a manual reset and in software standby mode. The
OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or
become high-impedance when a transition is made to software standby mode.
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(a) Modes 4 to 6
Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specification in PFDDR is ignored for pins PF6 to PF3, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
Pins PF2 to PF0 are made bus control input/output pins (WAIT, BACK, and BREQ) by bus
controller settings. Otherwise, setting a PFDDR bit to 1 makes the corresponding pin an output
port, while clearing the bit to 0 makes the pin an input port.
(b) Mode 7
Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in
the case of pin PF7, the φ output pin. Clearing the bit to 0 makes the pin an input port.
(2) Port F Data Register (PFDR)
7
6
5
4
3
2
1
0
PF7DR
PF6DR
PF5DR
PF4DR
PF3DR
PF2DR
PF1DR
PF0DR
Initial value :
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
:
:
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF6 to PF0).
PFDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(3) Port F Register (PORTF)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
—*
—*
—*
—*
—*
—*
—*
—*
R
R
R
R
R
R
R
R
Note: * Determined by the state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
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Section 9 I/O Ports
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin
states, as PFDDR and PFDR are initialized. PORTF retains its previous state after a manual reset
and in software standby mode.
9.12.3
Pin Functions
Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), bus control signal I/O
pins (AS, RD, HWR, LWR, WAIT, BREQ, and BACK), and the system clock (φ) output pin. The
pin functions differ between modes 4 to 6 and mode 7. Port F pin functions are shown in table
9.23.
Table 9.23 Port F Pin Functions
Pin
Pin Functions and Selection Method
PF7/φ
The pin function is switched as shown below according to bit PF7DDR.
PF7DDR
Pin function
PF6/AS
Operating mode
Pin function
Modes 4 to 6
Mode 7
—
0
1
AS output
PF6 input
PF6 output
The pin function is switched as shown below according to the operating mode and bit
PF5DDR.
Operating mode
PF5DDR
Pin function
PF4/HWR
1
φ output
The pin function is switched as shown below according to the operating mode and bit
PF6DDR.
PF6DDR
PF5/RD
0
PF7 input
Modes 4 to 6
Mode 7
—
0
1
RD output
PF5 input
PF5 output
The pin function is switched as shown below according to the operating mode and bit
PF4DDR.
Operating mode
PF4DDR
Pin function
Modes 4 to 6
Mode 7
—
0
1
HWR output
PF4 input
PF4 output
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Pin
Pin Functions and Selection Method
PF3/LWR/ The pin function is switched as shown below according to the operating mode, the bus
IRQ3
mode, and bit PF3DDR.
Operating mode
Modes 4 to 6
Mode 7
Bus mode
16-bit bus
mode
PF3DDR
—
0
1
LWR output
PF3 input
PF3 output
Pin function
8-bit bus mode
—
0
1
PF3 input
IRQ3 input*
PF3 output
Note: * When used as an external interrupt input pin, do not use as an I/O pin for
another function.
PF2/WAIT The pin function is switched as shown below according to the operating mode, bit
WAITE, and bit PF2DDR.
Operating mode
Modes 4 to 6
WAITE
PF2DDR
Pin function
0
Mode 7
1
—
0
1
—
0
1
PF2 input
PF2 output
WAIT input
PF2 input
PF2 output
PF1/BACK/ The pin function is switched as shown below according to the operating mode, bit
BUZZ
BRLE, bit BUZZE in PFCR, and bit PF1DDR.
Operating mode
Modes 4 to 6
BRLE
PF1DDR
Pin function
0
0
Mode 7
1
1
—
PF1 output BACK output
PF1
input
—
0
1
PF1
input
PF1 output
PF0/BREQ/ The pin function is switched as shown below according to the operating mode, bit
IRQ2
BRLE, and bit PF0DDR.
Operating mode
Modes 4 to 6
BRLE
PF0DDR
Pin function
0
0
PF0 input
Mode 7
1
1
—
PF0 output BREQ input
IRQ2 input*
—
0
1
PF0 input
PF0 output
Note: * When used as an external interrupt input pin, do not use as an I/O pin for
another function.
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Section 9 I/O Ports
9.13
Port G
9.13.1
Overview
Port G is a 5-bit I/O port. Port G pins also function as external interrupt input pins (IRQ6 and
IRQ7) and bus control signal output pins (CS0 to CS3).
The interrupt input pins (IRQ6 and IRQ7) are Schmitt-triggered inputs.
Figure 9.19 shows the port G pin configuration.
Port G
Port G pins
Pin functions in modes 4 to 6
PG4/ CS0
PG4 (input)/CS0 (output)
PG3/ CS1
PG3 (input)/CS1 (output)
PG2/ CS2
PG2 (input)/CS2 (output)
PG1/ CS3/ IRQ7
PG1 (input)/CS3 (output)/IRQ7 (input)
PG0/ IRQ6
PG0 (input/output)/ IRQ6 (input)
Pin functions in mode 7
PG4 (input/output)
PG3 (input/output)
PG2 (input/output)
PG1 (input/output)/ IRQ7 (input)
PG0 (input/output)/ IRQ6 (input)
Figure 9.19 Port G Pin Functions
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Section 9 I/O Ports
9.13.2
Register Configuration
Table 9.24 shows the port G register configuration.
Table 9.24 Port G Registers
Name
Abbreviation
R/W
2
1
Initial Value* Address*
Port G data direction register
PGDDR
W
3
H'10/H'00*
Port G data register
PGDR
R/W
H'00
H'FF0F
Port G register
PORTG
R
Undefined
H'FFBF
H'FE3F
Notes: 1. Lower 16 bits of the address.
2. Value of bits 4 to 0.
3. Initial value depends on the mode. Initialized to H'10 in modes 4 and 5, and to H'00 in
modes 6 and 7.
(1) Port G Data Direction Register (PGDDR)
Bit
:
7
6
5
—
—
—
4
3
2
1
0
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
Modes 4 and 5 :
Initial value
: Undefined Undefined Undefined
R/W
:
—
—
—
1
0
0
0
0
W
W
W
W
W
0
0
0
0
0
W
W
W
W
W
Modes 6 and 7 :
Initial value
: Undefined Undefined Undefined
R/W
:
—
—
—
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port G. PGDDR cannot be read. Also, bits 7 to 5 are reserved, and will return an undefined
value if read.
Setting a PGDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit
to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit
manipulation instructions to write to this register. See section 2.10.4, Access Methods for
Registers with Write-Only Bits.
Bit PG4DDR is initialized to 1 (modes 4 and 5) or 0 (modes 6 and 7) by a power-on reset and in
hardware standby mode. PGDDR retains its previous state after a manual reset and in software
standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain
their output state or become high-impedance when a transition is made to software standby mode.
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Section 9 I/O Ports
(a) Modes 4 to 6
Pins PG4 to PG1 function as bus control signal output pins (CS0 to CS3) when the
corresponding PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.
Pin PG0 functions as an output port when the corresponding PGDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
(b) Mode 7
Setting a PGDDR bit to 1 makes the corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
(2) Port G Data Register (PGDR)
Bit
:
7
6
5
—
—
—
Initial value : Undefined Undefined Undefined
R/W
:
—
—
—
4
3
2
PG4DR PG3DR PG2DR
1
0
PG1DR PG0DR
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to
PG0).
Bits 7 to 5 are reserved; these bits cannot be modified and will return an undefined value if read.
PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset and in hardware standby mode. It
retains its previous state after a manual reset and in software standby mode.
(3) Port G Register (PORTG)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
PG4
PG3
PG2
PG1
PG0
—*
—*
—*
—*
—*
R
R
R
R
R
Initial value : Undefined Undefined Undefined
R/W
:
—
—
—
Note: * Determined by the state of pins PG4 to PG0.
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG4 to PG0) must always be performed on PGDR.
Bits 7 to 5 are reserved; these bits cannot be modified and will return an undefined value if read.
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Section 9 I/O Ports
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin
states, as PGDDR and PGDR are initialized. PORTG retains its previous state after a manual reset
and in software standby mode.
9.13.3
Pin Functions
Port G pins also function as external interrupt input pins (IRQ6 and IRQ7) and bus control signal
output pins (CS0 to CS3). The pin functions differ between modes 4 to 6 and mode 7. Port G pin
functions are shown in table 9.25.
Table 9.25 Port G Pin Functions
Pin
Pin Functions and Selection Method
PG4/CS0
The pin function is switched as shown below according to the operating mode and bit
PG4DDR.
Operating mode
PG4DDR
Pin function
PG3/CS1
Modes 4 to 6
0
1
0
1
PG4 input
CS0 output
PG4 input
PG4 output
The pin function is switched as shown below according to the operating mode and bit
PG3DDR.
Operating mode
PG3DDR
Pin function
PG2/CS2
Mode 7
Modes 4 to 6
Mode 7
0
1
0
1
PG3 input
CS1 output
PG3 input
PG3 output
The pin function is switched as shown below according to the operating mode and bit
PG2DDR.
Operating mode
PG2DDR
Pin function
Modes 4 to 6
Mode 7
0
1
0
1
PG2 input
CS2 output
PG2 input
PG2 output
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PG1/CS3/
IRQ7
The pin function is switched as shown below according to the operating mode and bit
PG1DDR.
Operating mode
PG1DDR
Pin function
Modes 4 to 6
Mode 7
0
1
0
PG1 input
CS3 output
1
PG1 input
IRQ7 input*
PG1 output
Note: * When used as an external interrupt input pin, do not use as an I/O pin for
another function.
PG0/IRQ6 The pin function is switched as shown below according to bit PG0DDR.
PG0DDR
Pin function
0
1
PG0 input
PG0 output
IRQ6 input*
Note: * When used as an external interrupt input pin, do not use as an I/O pin for
another function.
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Section 9 I/O Ports
9.14
Handling of Unused Pins
Unused input pins must be held at either the high level or the low level.
Input pins in CMOS devices are usually high-impedance inputs. If an unused pin is operated in the
open state, it is possible that intermediate levels could be generated by induction from peripheral
noise, and through currents could occur internally. This could lead to incorrect operation. Unused
input pins must be handled as listed in table 9.26
Table 9.26 Handling of Unused Input Pins
Pin Name
Pin Handling Example
Port 1
Connect each pin, through a resistor, to either VCC (pull up) or to VSS (pull down).
Port 3
Port 4
Port 7
Port 9
Connect each pin, through a resistor, to either AVCC (pull up) or to AVSS (pull down).
Port A
Connect each pin, through a resistor, to either VCC (pull up) or to VSS (pull down).
Port B
Port C
Port D
Port E
Port F
Port G
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Section 10 16-Bit Timer Pulse Unit (TPU)
Section 10 16-Bit Timer Pulse Unit (TPU)
10.1
Overview
The H8S/2214 Group has an on-chip 16-bit timer pulse unit (TPU) comprising three 16-bit timer
channels.
10.1.1
Features
• Can input/output a maximum of 8 pulses
⎯ A total of 8 timer general registers (TGRs) are provided (four each for channel 0, and two
each for channels 1 and 2), each of which can be set independently as an output
compare/input capture register
⎯ TGRC and TGRD for channel 0 can also be used as buffer registers
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
⎯ Waveform output at compare match: Selection of 0, 1, or toggle output
⎯ Input capture function: Selection of rising edge, falling edge, or both edge detection
⎯ Counter clear operation: Counter clearing possible by compare match or input capture
⎯ Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare match and input capture possible
Register simultaneous input/output possible by counter synchronous operation
⎯ PWM mode: Any PWM output duty can be set
Maximum of 7-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channel 0
⎯ Input capture register double-buffering possible
⎯ Automatic rewriting of output compare register possible
• Phase counting mode settable independently for each of channels 1 and 2
⎯ Two-phase encoder pulse up/down-count possible
• SCI0 baud rate clock generation by channels 1 and 2
⎯ An SCI0 baud rate clock can be generated using an AND circuit for TIOCA1 output and
TIOCA2 output
• Fast access via internal 16-bit bus
⎯ Fast access is possible via a 16-bit bus interface
Rev.4.00 Sep. 18, 2008 Page 359 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
• 13 interrupt sources
⎯ For channel 0, four compare match/input capture dual-function interrupts and one overflow
interrupt can be requested independently
⎯ For channels 1 and 2 two compare match/input capture dual-function interrupts, one
overflow interrupt, and one underflow interrupt can be requested independently
• Automatic transfer of register data
⎯ Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer
controller (DTC) and DMA controller (DMAC) activation
• Module stop mode can be set
⎯ As the initial setting, TPU operation is halted. Register access is enabled by exiting module
stop mode.
Table 10.1 lists the functions of the TPU.
Rev.4.00 Sep. 18, 2008 Page 360 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.1 TPU Functions
Item
Channel 0
Channel 1
Channel 2
Count clock
φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
General registers
TGR0A
TGR0B
TGR1A
TGR1B
TGR2A
TGR2B
General registers/
buffer registers
TGR0C
TGR0D
—
—
I/O pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
Counter clear
function
TGR compare match or TGR compare match or TGR compare match or
input capture
input capture
input capture
Compare 0 output
match
1 output
output
Toggle
output
Input capture
function
Synchronous
operation
PWM mode
Phase counting
mode
—
—
Buffer operation
—
DTC activation
TGR compare match
or input capture
TGR compare match or TGR compare match or
input capture
input capture
DMAC activation
TGR0A compare
TGR1A compare match TGR2A compare match
match or input capture or input capture
or input capture
Legend:
: Possible
— : Not possible
Rev.4.00 Sep. 18, 2008 Page 361 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
Item
Channel 0
Channel 1
Channel 2
Interrupt sources
5 sources
4 sources
4 sources
• Compare match or
input capture 0A
• Compare match or
input capture 1A
• Compare match or input
capture 2A
• Compare match or
input capture 0B
• Compare match or
input capture 1B
• Compare match or input
capture 2B
• Compare match or
input capture 0C
• Overflow
• Overflow
• Underflow
• Underflow
• Compare match or
input capture 0D
• Overflow
Rev.4.00 Sep. 18, 2008 Page 362 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.1.2
Block Diagram
Bus interface
TGRD
TGRB
TGRB
TGRB
Internal data bus
TGRC
TCNT
TGRA
TCNT
TGRA
TCNT
TGRA
Module data bus
TSR
TIER
TSR
TIER
TSR
TIER
TIOR
TIOR
TIORH TIORL
Common
Control logic
TMDR
Channel 2
TCR
TMDR
Channel 1
TCR
Channel 0
Control logic for channels 0 to 2
Input/output pins
Channel 0:
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Channel 1:
TIOCB1
TIOCA2
Channel 2:
TIOCB2
TMDR
External clock: TCLKA
TCLKB
TCLKC
TCLKD
TCR
Clock input
Internal clock: φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
TSTR TSYR
Figure 10.1 shows a block diagram of the TPU.
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
SCK0 (to SCI0)
Legend:
TSTR: Timer start register
TSYR: Timer synchro register
TCR: Timer control register
TMDR: Timer mode register
TIOR (H, L):
TIER:
TSR:
TGR (A, B, C, D):
Timer I/O control registers (H, L)
Timer interrupt enable register
Timer status register
Timer general registers (A, B, C, D)
Figure 10.1 Block Diagram of TPU
Rev.4.00 Sep. 18, 2008 Page 363 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.1.3
Pin Configuration
Table 10.2 summarizes the TPU pins.
Table 10.2 TPU Pins
Channel
Name
Symbol
I/O
Function
All
Clock input A
TCLKA
Input
External clock A input pin
(Channel 1 phase counting mode A phase
input)
Clock input B
TCLKB
Input
External clock B input pin
(Channel 1 phase counting mode B phase
input)
Clock input C
TCLKC
Input
External clock C input pin
(Channel 2 phase counting mode A phase
input)
Clock input D
TCLKD
Input
External clock D input pin
(Channel 2 phase counting mode B phase
input)
Input capture/out TIOCA0
compare match A0
I/O
TGR0A input capture input/output compare
output/PWM output pin
Input capture/out TIOCB0
compare match B0
I/O
TGR0B input capture input/output compare
output/PWM output pin
Input capture/out TIOCC0
compare match C0
I/O
TGR0C input capture input/output compare
output/PWM output pin
Input capture/out TIOCD0
compare match D0
I/O
TGR0D input capture input/output compare
output/PWM output pin
Input capture/out TIOCA1
compare match A1
I/O
TGR1A input capture input/output compare
output/PWM output pin
Input capture/out TIOCB1
compare match B1
I/O
TGR1B input capture input/output compare
output/PWM output pin
Input capture/out TIOCA2
compare match A2
I/O
TGR2A input capture input/output compare
output/PWM output pin
Input capture/out TIOCB2
compare match B2
I/O
TGR2B input capture input/output compare
output/PWM output pin
0
1
2
Rev.4.00 Sep. 18, 2008 Page 364 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.1.4
Register Configuration
Table 10.3 summarizes the TPU registers.
Table 10.3 TPU Registers
Channel Name
Abbreviation
R/W
Initial Value
Address*
0
Timer control register 0
TCR0
R/W
H'00
H'FF10
Timer mode register 0
TMDR0
R/W
H'C0
H'FF11
Timer I/O control register 0H
TIOR0H
R/W
H'00
H'FF12
Timer I/O control register 0L
TIOR0L
1
2
1
R/W
H'00
H'FF13
Timer interrupt enable register 0 TIER0
R/W
H'40
H'FF14
Timer status register 0
TSR0
R/(W)*
H'C0
H'FF15
Timer counter 0
TCNT0
R/W
H'0000
H'FF16
Timer general register 0A
TGR0A
R/W
H'FFFF
H'FF18
Timer general register 0B
TGR0B
R/W
H'FFFF
H'FF1A
Timer general register 0C
TGR0C
R/W
H'FFFF
H'FF1C
Timer general register 0D
TGR0D
R/W
H'FFFF
H'FF1E
Timer control register 1
TCR1
R/W
H'00
H'FF20
Timer mode register 1
TMDR1
R/W
H'C0
H'FF21
Timer I/O control register 1
TIOR1
R/W
H'00
H'FF22
Timer interrupt enable register 1 TIER1
R/W
Timer status register 1
TSR1
R/(W)*
Timer counter 1
TCNT1
Timer general register 1A
Timer general register 1B
2
H'40
H'FF24
H'C0
H'FF25
R/W
H'0000
H'FF26
TGR1A
R/W
H'FFFF
H'FF28
TGR1B
R/W
H'FFFF
H'FF2A
2
Timer control register 2
TCR2
R/W
H'00
H'FF30
Timer mode register 2
TMDR2
R/W
H'C0
H'FF31
Timer I/O control register 2
TIOR2
R/W
H'00
H'FF32
Timer interrupt enable register 2 TIER2
R/W
H'FF34
H'FF35
H'FF36
Timer status register 2
TSR2
H'40
2
*
R/(W)
H'C0
Timer counter 2
TCNT2
R/W
H'0000
Timer general register 2A
TGR2A
R/W
H'FFFF
H'FF38
Timer general register 2B
TGR2B
R/W
H'FFFF
H'FF3A
Rev.4.00 Sep. 18, 2008 Page 365 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
Channel Name
Abbreviation
R/W
Initial Value
Address*
All
Timer start register
TSTR
R/W
H'00
H'FEB0
Timer synchro register
TSYR
R/W
H'00
H'FEB1
Module stop control register A
MSTPCRA
R/W
H'3F
H'FDE8
3
2
1
0
TPSC2
TPSC1
TPSC0
1
Notes: 1. Lower 16 bits of the address.
2. Can only be written with 0 for flag clearing.
10.2
Register Descriptions
10.2.1
Timer Control Register (TCR)
Channel 0: TCR0
Bit
7
6
5
CCLR2
CCLR1
CCLR0
:
:
CKEG1 CKEG0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value :
R/W
4
Channel 1: TCR1
Channel 2: TCR2
Bit
:
—
CCLR1
CCLR0
TPSC2
TPSC1
TPSC0
Initial value :
0
0
0
0
0
0
0
0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
CKEG1 CKEG0
The TCR registers are 8-bit registers that control the TCNT channels. The TPU has three TCR
registers, one for each of channels 0 to 2. The TCR registers are initialized to H'00 by a reset, and
in hardware standby mode.
Rev.4.00 Sep. 18, 2008 Page 366 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter
clearing source.
Bit 7
Bit 6
Bit 5
Channel
CCLR2
CCLR1
CCLR0
Description
0
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input
2
capture*
0
TCNT cleared by TGRD compare match/input
2
capture*
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operatio*
1
1
0
1
Bit 7
Bit 6
(Initial value)
Bit 5
Channel
Reserved* CCLR1
CCLR0
Description
1, 2
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
3
0
1
(Initial value)
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
3. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.
Rev.4.00 Sep. 18, 2008 Page 367 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both
edges = φ/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is
ignored and the phase counting mode setting has priority.
Bit 4
Bit 3
CKEG1
CKEG0
Description
0
0
Count at rising edge
1
Count at falling edge
—
Count at both edges
1
(Initial value)
Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected.
(Counting occurs on the falling edge of φ when φ/1 is selected.)
Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter
clock. The clock source can be selected independently for each channel. Table 10.4 shows the
clock sources that can be set for each channel.
Table 10.4 TPU Clock Sources
Internal Clock
Channel
Channel
φ/1
φ/4
φ/16
φ/64
φ/256
0
1
2
Legend:
:
Setting
Blank: No setting
Rev.4.00 Sep. 18, 2008 Page 368 of 872
REJ09B0189-0400
External Clock
φ/1024 φ/4096
TCLKA TCLKB TCLKC TCLKD
Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 2
Bit 1
Bit 0
Channel
TPSC2
TPSC1
TPSC0
Description
0
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
External clock: counts on TCLKC pin input
1
External clock: counts on TCLKD pin input
1
1
0
1
(Initial value)
Bit 2
Bit 1
Bit 0
Channel
TPSC2
TPSC1
TPSC0
Description
1
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
1
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
Internal clock: counts on φ/256
1
Setting prohibited
1
1
(Initial value)
Note: This setting is ignored when channel 1 is in phase counting mode.
Bit 2
Bit 1
Bit 0
Channel
TPSC2
TPSC1
TPSC0
Description
2
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
External clock: counts on TCLKC pin input
1
Internal clock: counts on φ/1024
1
1
0
1
(Initial value)
Note: This setting is ignored when channel 2 is in phase counting mode.
Rev.4.00 Sep. 18, 2008 Page 369 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.2.2
Timer Mode Register (TMDR)
Channel 0: TMDR0
Bit
:
7
6
5
4
3
2
1
0
—
—
BFB
BFA
MD3
MD2
MD1
MD0
Initial value :
1
1
0
0
0
0
0
0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
—
—
—
—
MD3
MD2
MD1
MD0
:
Channel 1: TMDR1
Channel 2: TMDR2
Bit
:
Initial value :
1
1
0
0
0
0
0
0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
:
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers
are initialized to H'C0 by a reset, and in hardware standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not generated.
In channels 1 and 2 which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be
modified.
Bit 5
BFB
Description
0
TGRB operates normally
1
TGRB and TGRD used together for buffer operation
Rev.4.00 Sep. 18, 2008 Page 370 of 872
REJ09B0189-0400
(Initial value)
Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not generated.
In channels 1 and 2 which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be
modified.
Bit 4
BFA
Description
0
TGRA operates normally
1
TGRA and TGRC used together for buffer operation
(Initial value)
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3
Bit 2
Bit 1
Bit 0
MD3
MD2
MD1
MD0
Description
0
0
0
0
Normal operation
1
Reserved
0
PWM mode 1
1
PWM mode 2
0
Phase counting mode 1
1
Phase counting mode 2
0
Phase counting mode 3
1
Phase counting mode 4
*
—
1
1
0
1
1
*
*
(Initial value)
Legend:
*: Don’t care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be
written to MD2.
Rev.4.00 Sep. 18, 2008 Page 371 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.2.3
Timer I/O Control Register (TIOR)
Channel 0: TIOR0H
Channel 1: TIOR1
Channel 2: TIOR2
Bit
7
6
5
4
3
2
1
0
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
Initial value :
R/W
:
Channel 0: TIOR0L
Bit
:
Initial value :
R/W
Note:
:
7
6
5
4
3
2
1
0
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR
registers, two each for channel 0, and one each for channels 1 and 2. The TIOR registers are
initialized to H'00 by a reset, and in hardware standby mode.
Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR
is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the point at which the counter is cleared to 0 is specified.
Rev.4.00 Sep. 18, 2008 Page 372 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0)
I/O Control D3 to D0 (IOD3 to IOD0):
Bits IOB3 to IOB0 specify the function of TGRB.
Bits IOD3 to IOD0 specify the function of TGRD.
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOB3 IOB2 IOB1 IOB0 Description
0
0
0
0
0
1
1
0
1
1
0
1
0
Output disabled
1
Initial output is 1
output
0
1
1
0
0
0
1
1
TGR0B is Output disabled
(Initial value)
output
Initial output is 0 0 output at compare match
compare output
1 output at compare match
register
Toggle output at compare
match
1
*
*
*
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR0B is Capture input
Input capture at rising edge
input
source is
Input capture at falling edge
capture
TIOCB0 pin
Input capture at both edges
register
Setting prohibited
Legend:
*: Don’t care
Rev.4.00 Sep. 18, 2008 Page 373 of 872
REJ09B0189-0400
Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOD3 IOD2 IOD1 IOD0 Description
0
0
0
0
0
1
1
0
TGR0D is Output disabled
(Initial value)
output
Initial output is 0 0 output at compare match
compare output
1
1 output at compare match
register*
Toggle output at compare
match
1
1
0
1
0
Output disabled
1
Initial output is 1
output
0
0
0
0
1
1
1
*
*
*
1 output at compare match
Toggle output at compare
match
1
1
0 output at compare match
TGR0D is Capture input
input
source is
capture
TIOCD0 pin
1
register*
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Setting prohibited
Legend:
*: Don’t care
Note: 1. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.4.00 Sep. 18, 2008 Page 374 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOB3 IOB2 IOB1 IOB0 Description
1
0
0
0
0
1
1
0
TGR1B is Output disabled
output
Initial output is 0
compare output
register
0
1
0
Output disabled
1
Initial output is 1
output
0
1
1
0
0
0
1
1
1
*
*
*
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR1B is Capture input
input
source is
capture
TIOCB1 pin
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Setting prohibited
Legend:
*: Don’t care
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOB3 IOB2 IOB1 IOB0 Description
2
0
0
0
0
1
1
0
TGR2B is Output disabled
output
Initial output is 0
compare output
register
0
1
0
Output disabled
1
Initial output is 1
output
0
*
0
0
1
1
*
1 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
0 output at compare match
Toggle output at compare
match
1
1
(Initial value)
TGR2B is Capture input
input
source is
capture
TIOCB2 pin
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
*: Don’t care
Rev.4.00 Sep. 18, 2008 Page 375 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0)
I/O Control C3 to C0 (IOC3 to IOC0):
IOA3 to IOA0 specify the function of TGRA.
IOC3 to IOC0 specify the function of TGRC.
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOA3 IOA2 IOA1 IOA0 Description
0
0
0
0
0
1
1
0
TGR0A is Output disabled
output
Initial output is 0
compare output
register
0
1
0
Output disabled
1
Initial output is 1
output
0
0
0
0
1
1
1
*
*
*
1 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
0 output at compare match
Toggle output at compare
match
1
1
(Initial value)
TGR0A is Capture input
Input capture at rising edge
input
source is
Input capture at falling edge
capture
TIOCA0 pin
Input capture at both edges
register
Setting prohibited
Legend:
*: Don’t care
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOC3 IOC2 IOC1 IOC0 Description
0
0
0
0
0
1
1
0
TGR0C is Output disabled
output
Initial output is 0
compare output
1
register*
0
1
0
Output disabled
1
Initial output is 1
output
0
0
0
0
1
1
1
*
*
*
1 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
0 output at compare match
Toggle output at compare
match
1
1
(Initial value)
TGR0C is Capture input
input
source is
capture
TIOCC0 pin
1
register*
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Setting prohibited
Legend:
*: Don’t care
Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOA3 IOA2 IOA1 IOA0 Description
1
0
0
0
0
1
1
0
TGR1A is Output disabled
output
Initial output is 0
compare output
register
0
1
0
Output disabled
1
Initial output is 1
output
0
0
0
0
1
1
1
*
*
*
1 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
0 output at compare match
Toggle output at compare
match
1
1
(Initial value)
TGR1A is Capture input
Input capture at rising edge
input
source is
Input capture at falling edge
capture
TIOCA1 pin
Input capture at both edges
register
Setting prohibited
Legend:
*: Don’t care
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOA3 IOA2 IOA1 IOA0 Description
2
0
0
0
0
1
1
0
TGR2A is Output disabled
output
Initial output is 0
compare output
register
0
1
0
Output disabled
1
Initial output is 1
output
0
*
0
0
1
1
*
1 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
0 output at compare match
Toggle output at compare
match
1
1
(Initial value)
TGR2A is Capture input
input
source is
capture
TIOCA2 pin
register
Legend:
*: Don’t care
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Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Section 10 16-Bit Timer Pulse Unit (TPU)
10.2.4
Timer Interrupt Enable Register (TIER)
Channel 0: TIER0
Bit
:
:
6
5
4
3
2
1
0
—
—
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
0
1
0
0
0
0
0
0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
—
—
TCIEU
TCIEV
—
—
TGIEB
TGIEA
0
1
0
0
0
0
0
0
R/W
—
R/W
R/W
—
—
R/W
R/W
Initial value :
R/W
7
Channel 1: TIER1
Channel 2: TIER2
Bit
:
Initial value :
R/W
:
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has three TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset, and in hardware standby mode.
Bit 7—Reserved: Only 0 should be written to this bit.
Bit 6—Reserved: Read-only bit, always read as 1.
Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by
the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2.
In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5
TCIEU
Description
0
Interrupt requests (TCIU) by TCFU disabled
1
Interrupt requests (TCIU) by TCFU enabled
(Initial value)
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by
the TCFV flag when the TCFV flag in TSR is set to 1.
Bit 4
TCIEV
Description
0
Interrupt requests (TCIV) by TCFV disabled
1
Interrupt requests (TCIV) by TCFV enabled
(Initial value)
Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in channel 0.
In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3
TGIED
Description
0
Interrupt requests (TGID) by TGFD bit disabled
1
Interrupt requests (TGID) by TGFD bit enabled
(Initial value)
Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in channel 0.
In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2
TGIEC
Description
0
Interrupt requests (TGIC) by TGFC bit disabled
1
Interrupt requests (TGIC) by TGFC bit enabled
(Initial value)
Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
Bit 1
TGIEB
Description
0
Interrupt requests (TGIB) by TGFB bit disabled
1
Interrupt requests (TGIB) by TGFB bit enabled
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(Initial value)
Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
Bit 0
TGIEA
Description
0
Interrupt requests (TGIA) by TGFA bit disabled
1
Interrupt requests (TGIA) by TGFA bit enabled
10.2.5
(Initial value)
Timer Status Register (TSR)
Channel 0: TSR0
Bit
:
7
6
5
4
3
2
1
0
—
—
—
TCFV
TGFD
TGFC
TGFB
TGFA
Initial value :
1
1
0
0
0
0
0
0
R/W
—
—
—
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
7
6
5
4
3
2
1
0
TCFD
—
TCFU
TCFV
—
—
TGFB
TGFA
:
Channel 1: TSR1
Channel 2: TSR2
Bit
:
Initial value :
1
1
0
0
0
0
0
0
R/W
R
—
R/(W)*
R/(W)*
—
—
R/(W)*
R/(W)*
:
Note: * Can only be written with 0 for flag clearing.
The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has three
TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in
hardware standby mode.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT
counts in channels 1 and 2.
In channel 0, bit 7 is reserved. It is always read as 1 and cannot be modified.
Bit 7
TCFD
Description
0
TCNT counts down
1
TCNT counts up
(Initial value)
Bit 6—Reserved: Read-only bit, always read as 1 and cannot be modified.
Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred
when channels 1and 2 are set to phase counting mode.
In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5
TCFU
Description
0
[Clearing condition]
•
1
(Initial value)
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
•
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred.
Bit 4
TCFV
Description
0
[Clearing condition]
•
1
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
•
When the TCNT value overflows (changes from H'FFFF to H'0000 )
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(Initial value)
Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the
occurrence of TGRD input capture or compare match in channel 0.
In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3
TGFD
Description
0
[Clearing conditions]
1
(Initial value)
•
When DTC is activated by a TGID interrupt, the DTC module MRB register DISEL
bit is 0, and furthermore the transfer counter is not 0.
•
When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
•
When TCNT = TGRD while TGRD is functioning as output compare register
•
When TCNT value is transferred to TGRD by input capture signal while TGRD is
functioning as input capture register
Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the
occurrence of TGRC input capture or compare match in channel 0.
In channels 1and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2
TGFC
Description
0
[Clearing conditions]
1
(Initial value)
•
When DTC is activated by a TGIC interrupt, the DTC module MRB register DISEL
bit is 0, and furthermore the transfer counter is not 0.
•
When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
•
When TCNT = TGRC while TGRC is functioning as output compare register
•
When TCNT value is transferred to TGRC by input capture signal while TGRC is
functioning as input capture register
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Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the
occurrence of TGRB input capture or compare match.
Bit 1
TGFB
Description
0
[Clearing conditions]
1
(Initial value)
•
When DTC is activated by a TGIB interrupt, the DTC module MRB register DISEL
bit is 0, and furthermore the transfer counter is not 0.
•
When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
•
When TCNT = TGRB while TGRB is functioning as output compare register
•
When TCNT value is transferred to TGRB by input capture signal while TGRB is
functioning as input capture register
Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the
occurrence of TGRA input capture or compare match.
Bit 0
TGFA
Description
0
[Clearing conditions]
1
(Initial value)
•
When DTC is activated by a TGIA interrupt, the DTC module MRB register DISEL
bit is 0, and furthermore the transfer counter is not 0.
•
When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1
•
When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
•
When TCNT = TGRA while TGRA is functioning as output compare register
•
When TCNT value is transferred to TGRA by input capture signal while TGRA is
functioning as input capture register
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.2.6
Timer Counter (TCNT)
Channel 0: TCNT0 (up-counter)
Channel 1: TCNT1 (up/down-counter*)
Channel 2: TCNT2 (up/down-counter*)
Bit
:
Initial value :
R/W
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: * These counters can be used as up/down-counters only in phase counting mode.
In other cases they function as up-counters.
The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel.
The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
10.2.7
Bit
Timer General Register (TGR)
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The TGR registers are 16-bit registers with a dual function as output compare and input capture
registers. The TPU has eight TGR registers, four each for channel 0 and two each for channels 1
and 2. TGRC and TGRD for channel 0 can also be designated for operation as buffer registers*.
The TGR registers are initialized to H'FFFF by a reset, and in hardware standby mode.
The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
Note: * TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.2.8
Timer Start Register (TSTR)
7
6
5
4
3
2
1
0
—
—
—
—
—
CST2
CST1
CST0
Initial value :
0
0
0
0
0
0
0
0
R/W
—
—
—
—
—
R/W
R/W
R/W
Bit
:
:
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2.
TSTR is initialized to H'00 by a reset, and in hardware standby mode.
TCNT counter operation must be halted before setting the operating mode in TMDR, or setting the
TCNT count clock in TCR.
Bits 7 to 3—Reserved: Should always be written with 0.
Bits 2 to 0—Counter Start 2 to 0 (CST2 to CST0): These bits select operation or stoppage for
TCNT.
Bit n
CSTn
Description
0
TCNTn count operation is stopped
1
TCNTn performs count operation
(Initial value)
(n = 2 to 0)
Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the
counter stops but the TIOC pin output compare output level is retained. If TIOR is written to
when the CST bit is cleared to 0, the pin output level will be changed to the set initial output
value.
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.2.9
Timer Synchro Register (TSYR)
7
6
5
4
3
2
1
0
—
—
—
—
—
SYNC2
SYNC1
SYNC0
Initial value :
0
0
0
0
0
0
0
0
R/W
—
—
—
—
—
R/W
R/W
R/W
Bit
:
:
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channels 0 to 2 TCNT counters. A channel performs synchronous operation
when the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 3—Reserved: Should always be written with 0.
Bits 2 to 0—Timer Synchro 2 to 0 (SYNC2 to SYNC0): These bits select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels* , and
2
synchronous clearing through counter clearing on another channel* are possible.
1
Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source
must also be set by means of bits CCLR2 to CCLR0 in TCR.
Bit n
SYNCn
Description
0
TCNTn operates independently (TCNT presetting/clearing is unrelated to
other channels)
(Initial value)
1
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is possible
(n = 2 to 0)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.2.10 Module Stop Control Register A (MSTPCRA)
Bit
:
7
6
5
4
3
2
1
0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
R/W
:
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRA is a 16-bit readable/writable register that performs module stop mode control.
When the MSTPA5 bit in MSTPCR is set to 1, TPU operation stops at the end of the bus cycle
and a transition is made to module stop mode. Registers cannot be read or written to in module
stop mode. For details, see section 17.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 5—Module Stop (MSTPA5): Specifies the TPU module stop mode.
Bit 5
MSTPA5
Description
0
TPU module stop mode cleared
1
TPU module stop mode set
Rev.4.00 Sep. 18, 2008 Page 388 of 872
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(Initial value)
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3
Interface to Bus Master
10.3.1
16-Bit Registers
TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these
registers can be read and written to in 16-bit units.
These registers cannot be read or written to in 8-bit units; 16-bit access must always be used.
An example of 16-bit register access operation is shown in figure 10.2.
Internal data bus
H
Bus
master
L
Module
data bus
Bus interface
TCNTH
TCNTL
Figure 10.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)]
10.3.2
8-Bit Registers
Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these
registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit
units.
Examples of 8-bit register access operation are shown in figures 10.3 to 10.5.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Internal data bus
H
Bus
master
L
Module
data bus
Bus interface
TCR
Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
Internal data bus
H
Bus
master
L
Module
data bus
Bus interface
TMDR
Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
Internal data bus
H
Bus
master
L
Module
data bus
Bus interface
TCR
TMDR
Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4
Operation
10.4.1
Overview
Operation in each mode is outlined below.
(1) Normal Operation
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, synchronous counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
(2) Synchronous Operation
When synchronous operation is designated for a channel, TCNT for that channel performs
synchronous presetting. That is, when TCNT for a channel designated for synchronous operation
is rewritten, the TCNT counters for the other channels are also rewritten at the same time.
Synchronous clearing of the TCNT counters is also possible by setting the timer synchronization
bits in TSYR for channels designated for synchronous operation.
(3) Buffer Operation
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the relevant channel is
transferred to TGR.
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transfer to TGR and the value previously
held in TGR is transferred to the buffer register.
(4) PWM Mode
In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM
waveform with a duty of between 0% and 100% can be output, according to the setting of each
TGR register.
(5) Phase Counting Mode
In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input
from the external clock input pins in channels 1 and 2. When phase counting mode is set, the
corresponding TCLK pin functions as the clock pin, and TCNT performs up- or down-counting.
Rev.4.00 Sep. 18, 2008 Page 391 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
This can be used for two-phase encoder pulse input.
10.4.2
Basic Functions
(1) Counter Operation
When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding
channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.
• Example of count operation setting procedure
Figure 10.6 shows an example of the count operation setting procedure.
[1] Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
Operation selection
Select counter clock
[1]
Periodic counter
[2] For periodic counter
operation, select the
TGR to be used as
the TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
Free-running counter
Select counter clearing source
[2]
Select output compare register
[3]
Set period
[4]
Start count operation
[5]
<Periodic counter>
[3] Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
[4] Set the periodic
counter cycle in the
TGR selected in [2].
Start count operation
<Free-running counter>
[5]
[5] Set the CST bit in
TSTR to 1 to start
the counter
operation.
Figure 10.6 Example of Counter Operation Setting Procedure
Rev.4.00 Sep. 18, 2008 Page 392 of 872
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Section 10 16-Bit Timer Pulse Unit (TPU)
• Free-running count operation and periodic count operation
Immediately after a reset, the TPU’s TCNT counters are all designated as free-running
counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000),
the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at
this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from
H'0000.
Figure 10.7 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
CST bit
TCFV
Figure 10.7 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the
relevant channel performs periodic count operation. The TGR register for setting the period is
designated as an output compare register, and counter clearing by compare match is selected
by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts
up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When
the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared
to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an
interrupt. After a compare match, TCNT starts counting up again from H'0000.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.8 illustrates periodic counter operation.
Counter cleared by TGR
compare match
TCNT value
TGR
H'0000
Time
CST bit
Flag cleared by software or
DTC activation
TGF
Figure 10.8 Periodic Counter Operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
(2) Waveform Output by Compare Match
The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare
match.
• Example of setting procedure for waveform output by compare match
Figure 10.9 shows an example of the setting procedure for waveform output by compare
match.
Output selection
Select waveform output mode
[1]
[1] Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TIOC pin until the
first compare match occurs.
[2] Set the timing for compare match generation in
TGR.
Set output timing
[2]
Start count operation
[3]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
<Waveform output>
Figure 10.9 Example Of Setting Procedure For Waveform Output By Compare Match
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Section 10 16-Bit Timer Pulse Unit (TPU)
• Examples of waveform output operation
Figure 10.10 shows an example of 0 output/1 output.
In this example TCNT has been designated as a free-running counter, and settings have been
made so that 1 is output by compare match A, and 0 is output by compare match B. When the
set level and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
TGRA
TGRB
Time
H'0000
No change
No change
1 output
TIOCA
No change
TIOCB
No change
0 output
Figure 10.10 Example of 0 Output/1 Output Operation
Figure 10.11 shows an example of toggle output.
In this example TCNT has been designated as a periodic counter (with counter clearing
performed by compare match B), and settings have been made so that output is toggled by both
compare match A and compare match B.
TCNT value
Counter cleared by TGRB compare match
H'FFFF
TGRB
TGRA
Time
H'0000
Toggle output
TIOCB
Toggle output
TIOCA
Figure 10.11 Example of Toggle Output Operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
(3) Input Capture Function
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge,
falling edge, or both edges can be selected as the detected edge.
• Example of input capture operation setting procedure
Figure 10.12 shows an example of the input capture operation setting procedure.
[1] Designate TGR as an input capture register by
means of TIOR, and select rising edge, falling
edge, or both edges as the input capture source
and input signal edge.
Input selection
Select input capture input
[1]
Start count
[2]
[2] Set the CST bit in TSTR to 1 to start the count
operation.
<Input capture operation>
Figure 10.12 Example of Input Capture Operation Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
• Example of input capture operation
Figure 10.13 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input
capture input edge, falling edge has been selected as the TIOCB pin input capture input edge,
and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB
input (falling edge)
TCNT value
H'0180
H'0160
H'0010
H'0005
Time
H'0000
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB
TGRB
H'0180
Figure 10.13 Example of Input Capture Operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.3
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten
simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared
simultaneously by making the appropriate setting in TCR (synchronous clearing).
Synchronous operation enables TGR to be incremented with respect to a single time base.
Channels 0 to 2 can all be designated for synchronous operation.
(1) Example of Synchronous Operation Setting Procedure
Figure 10.14 shows an example of the synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous presetting
Set TCNT
Synchronous clearing
[2]
Clearing
sourcegeneration
channel?
No
Yes
<Synchronous presetting>
Select counter
clearing source
[3]
Set synchronous
counter clearing
[4]
Start count
[5]
Start count
[5]
<Counter clearing>
<Synchronous clearing>
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
operation.
[2] When the TCNT counter of any of the channels designated for synchronous operation is
written to, the same value is simultaneously written to the other TCNT counters.
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare,
etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing
source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 10.14 Example of Synchronous Operation Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
(2) Example of Synchronous Operation
Figure 10.15 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous
clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this
time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed
for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle.
For details of PWM modes, see section 10.4.5, PWM Modes.
Synchronous clearing by TGR0B compare match
TCNT0 to TCNT2 values
TGR0B
TGR1B
TGR0A
TGR2B
TGR1A
TGR2A
Time
H'0000
TIOC0A
TIOC1A
TIOC2A
Figure 10.15 Example of Synchronous Operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.4
Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 10.5 shows the register combinations used in buffer operation.
Table 10.5 Register Combinations in Buffer Operation
Channel
Timer General Register
Buffer Register
0
TGR0A
TGR0C
TGR0B
TGR0D
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 10.16.
Compare match signal
Buffer register
Timer general
register
Comparator
TCNT
Figure 10.16 Compare Match Buffer Operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 10.17.
Input capture
signal
Timer general
register
Buffer register
TCNT
Figure 10.17 Input Capture Buffer Operation
(1) Example of Buffer Operation Setting Procedure
Figure 10.18 shows an example of the buffer operation setting procedure.
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
Buffer operation
[1]
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
Set buffer operation
[2]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
Start count
[3]
Select TGR function
<Buffer operation>
Figure 10.18 Example of Buffer Operation Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
(2) Examples of Buffer Operation
• When TGR is an output compare register
Figure 10.19 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details of PWM modes, see section 10.4.5, PWM Modes.
TCNT value
TGR0B
H'0520
H'0450
H'0200
TGR0A
Time
H'0000
TGR0C H'0200
H'0450
H'0520
Transfer
TGR0A
H'0200
H'0450
TIOCA
Figure 10.19 Example of Buffer Operation (1)
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Section 10 16-Bit Timer Pulse Unit (TPU)
• When TGR is an input capture register
Figure 10.20 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
Time
TIOCA
TGRA
H'0532
TGRC
H'0F07
H'09FB
H'0532
H'0F07
Figure 10.20 Example of Buffer Operation (2)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be
selected as the output level in response to compare match of each TGR.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is
output from the TIOCA and TIOCC pins at compare matches A and C, and the output
specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B
and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired
TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 4-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output specified in TIOR is performed by means of compare matches. Upon counter
clearing by a synchronization register compare match, the output value of each pin is the initial
value set in TIOR. If the set values of the cycle and duty registers are identical, the output
value does not change when a compare match occurs.
In PWM mode 2, a maximum 7-phase PWM output is possible by combined use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 10.6.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.6 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
PWM Mode 1
PWM Mode 2
0
TGR0A
TIOCA0
TIOCA0
TGR0B
TGR0C
TIOCB0
TIOCC0
TIOCC0
TIOCA1
TIOCA1
TGR0D
1
TGR1A
TIOCD0
TGR1B
2
TGR2A
TGR2B
TIOCB1
TIOCA2
TIOCA2
TIOCB2
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
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Section 10 16-Bit Timer Pulse Unit (TPU)
(1) Example of PWM Mode Setting Procedure
Figure 10.21 shows an example of the PWM mode setting procedure.
PWM mode
Select counter clock
[1]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
[2] Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Select counter clearing source
Select waveform output level
Set TGR
[2]
[3]
[4]
[3] Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
[4] Set the cycle in the TGR selected in [2], and set
the duty in the other the TGR.
[5] Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set PWM mode
[5]
Start count
[6]
[6] Set the CST bit in TSTR to 1 to start the count
operation.
<PWM mode>
Figure 10.21 Example of PWM Mode Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
(2) Examples of PWM Mode Operation
Figure 10.22 shows an example of PWM mode 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as
the duty.
TCNT value
TGRA
Counter cleared by
TGRA compare match
TGRB
H'0000
Time
TIOCA
Figure 10.22 Example of PWM Mode Operation (1)
Figure 10.23 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match
is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output
value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM
waveform.
In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as
the duty.
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Section 10 16-Bit Timer Pulse Unit (TPU)
TCNT value
Counter cleared by TGR1B
compare match
TGR1B
TGR1A
TGR0D
TGR0C
TGR0B
TGR0A
H'0000
Time
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 10.23 Example of PWM Mode Operation (2)
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Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM
mode.
TCNT value
TGRB rewritten
TGRA
TGRB
TGRB
rewritten
TGRB rewritten
H'0000
Time
0% duty
TIOCA
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB rewritten
TGRB
H'0000
Time
100% duty
TIOCA
Output does not change when cycle register and duty
register compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB
TGRB rewritten
Time
H'0000
100% duty
TIOCA
0% duty
Figure 10.24 Example of PWM Mode Operation (3)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1and 2.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 10.7 shows the correspondence between external clock pins and channels.
Table 10.7 Phase Counting Mode Clock Input Pins
External Clock Pins
Channels
A-Phase
B-Phase
When channel 1 is set to phase counting mode
TCLKA
TCLKB
When channel 2 is set to phase counting mode
TCLKC
TCLKD
(1) Example of Phase Counting Mode Setting Procedure
Figure 10.25 shows an example of the phase counting mode setting procedure.
[1] Select phase counting mode with bits MD3 to
MD0 in TMDR.
Phase counting mode
Select phase counting mode
[1]
Start count
[2]
[2] Set the CST bit in TSTR to 1 to start the count
operation.
<Phase counting mode>
Figure 10.25 Example of Phase Counting Mode Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
(2) Examples of Phase Counting Mode Operation
In phase counting mode, TCNT counts up or down according to the phase difference between two
external clocks. There are four modes, according to the count conditions.
• Phase counting mode 1
Figure 10.26 shows an example of phase counting mode 1 operation, and table 10.8
summarizes the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Up-count
Down-count
Time
Figure 10.26 Example of Phase Counting Mode 1 Operation
Table 10.8 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
Up-count
High level
Low level
Low level
High level
High level
Down-count
Low level
High level
Low level
Legend:
: Rising edge
: Falling edge
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Section 10 16-Bit Timer Pulse Unit (TPU)
• Phase counting mode 2
Figure 10.27 shows an example of phase counting mode 2 operation, and table 10.9
summarizes the TCNT up/down-count conditions.
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
TCNT value
Up-count
Down-count
Time
Figure 10.27 Example of Phase Counting Mode 2 Operation
Table 10.9 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level
Don’t care
Low level
Don’t care
Low level
Don’t care
High level
Up-count
High level
Don’t care
Low level
Don’t care
High level
Don’t care
Low level
Down-count
Legend:
: Rising edge
: Falling edge
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Section 10 16-Bit Timer Pulse Unit (TPU)
• Phase counting mode 3
Figure 10.28 shows an example of phase counting mode 3 operation, and table 10.10
summarizes the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Down-count
Up-count
Time
Figure 10.28 Example of Phase Counting Mode 3 Operation
Table 10.10 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level
Don’t care
Low level
Don’t care
Low level
Don’t care
High level
Up-count
High level
Down-count
Low level
Don’t care
High level
Don’t care
Low level
Don’t care
Legend:
: Rising edge
: Falling edge
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Section 10 16-Bit Timer Pulse Unit (TPU)
• Phase counting mode 4
Figure 10.29 shows an example of phase counting mode 4 operation, and table 10.11
summarizes the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Down-count
Up-count
Time
Figure 10.29 Example of Phase Counting Mode 4 Operation
Table 10.11 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
High level
Operation
Up-count
Low level
Low level
Don’t care
High level
High level
Down-count
Low level
High level
Don’t care
Low level
Legend:
: Rising edge
: Falling edge
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.5
Interrupts
10.5.1
Interrupt Sources and Priorities
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
Table 10.12 lists interrupt sources and DMA controller (DMAC) and data transfer controller
(DTC) activation.
Table 10.12 Interrupt Sources and DMA Controller (DMAC) and Data Transfer (DTC)
Activation
Channel
Interrupt
Source
Description
DMAC
Activation
DTC
Activation
Priority
0
TGI0A
TGR0A input capture/compare match
Possible
Possible
High
1
2
TGI0B
TGR0B input capture/compare match
Not possible
Possible
TGI0C
TGR0C input capture/compare match
Not possible
Possible
TGI0D
TGR0D input capture/compare match
Not possible
Possible
TCI0V
TCNT0 overflow
Not possible
Not possible
TGI1A
TGR1A input capture/compare match
Possible
Possible
TGI1B
TGR1B input capture/compare match
Not possible
Possible
TCI1V
TCNT1 overflow
Not possible
Not possible
TCI1U
TCNT1 underflow
Not possible
Not possible
TGI2A
TGR2A input capture/compare match
Possible
Possible
TGI2B
TGR2B input capture/compare match
Not possible
Possible
TCI2V
TCNT2 overflow
Not possible
Not possible
TCI2U
TCNT2 underflow
Not possible
Not possible
Low
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
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Section 10 16-Bit Timer Pulse Unit (TPU)
(1) Input Capture/Compare Match Interrupt
An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1
by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt
request is cleared by clearing the TGF flag to 0. The TPU has eight input capture/compare match
interrupts, four for channel 0, and two each for channels 1 and 2.
(2) Overflow Interrupt
An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to
1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing
the TCFV flag to 0. The TPU has three overflow interrupts, one for each channel.
(3) Underflow Interrupt
An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to
1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing
the TCFU flag to 0. The TPU has two overflow interrupts, one each for channels 1 and 2.
10.5.2
DTC and DMAC Activation
(1) DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For
details, see section 8, Data Transfer Controller (DTC).
A total of eight TPU input capture/compare match interrupts can be used as DTC activation
sources, four each for channel 0, and two each for channels 1 and 2.
(2) DMAC Activation
The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel.
For details, see section 7, DMA Controller (DMAC).
With the TPU, a total of three TGRA input capture/compare match interrupts can be used as
DMAC activation sources, one for each channel.
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.6
Operation Timing
10.6.1
Input/Output Timing
(1) TCNT Count Timing
Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT
count timing in external clock operation.
φ
Internal clock
Rising edge
Falling edge
TCNT
input clock
TCNT
N–1
N
N+1
N+2
Figure 10.30 Count Timing in Internal Clock Operation
φ
External clock
Falling edge
Rising edge
Falling edge
TCNT
input clock
TCNT
N–1
N
N+1
Figure 10.31 Count Timing in External Clock Operation
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N+2
Section 10 16-Bit Timer Pulse Unit (TPU)
(2) Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point
at which the count value matched by TCNT is updated). When a compare match signal is
generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
After a match between TCNT and TGR, the compare match signal is not generated until the
TCNT input clock is generated.
Figure 10.32 shows output compare output timing.
φ
TCNT
input clock
TCNT
TGR
N
N+1
N
Compare
match signal
TIOC pin
Figure 10.32 Output Compare Output Timing
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Section 10 16-Bit Timer Pulse Unit (TPU)
(3) Input Capture Signal Timing
Figure 10.33 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
TCNT
N
N+1
N+2
N
TGR
Figure 10.33 Input Capture Input Signal Timing
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N+2
Section 10 16-Bit Timer Pulse Unit (TPU)
(4) Timing for Counter Clearing by Compare Match/Input Capture
Figure 10.34 shows the timing when counter clearing by compare match occurrence is specified,
and figure 10.35 shows the timing when counter clearing by input capture occurrence is specified.
φ
Compare
match signal
Counter
clear signal
TCNT
N
TGR
N
H'0000
Figure 10.34 Counter Clear Timing (Compare Match)
φ
Input capture
signal
Counter clear
signal
TCNT
TGR
N
H'0000
N
Figure 10.35 Counter Clear Timing (Input Capture)
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Section 10 16-Bit Timer Pulse Unit (TPU)
(5) Buffer Operation Timing
Figures 10.36 and 10.37 show the timing in buffer operation.
φ
n
TCNT
n+1
Compare
match signal
TGRA,
TGRB
n
TGRC,
TGRD
N
N
Figure 10.36 Buffer Operation Timing (Compare Match)
φ
Input capture
signal
TCNT
N
TGRA,
TGRB
n
TGRC,
TGRD
N+1
N
N+1
n
N
Figure 10.37 Buffer Operation Timing (Input Capture)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.6.2
Interrupt Signal Timing
(1) TGF Flag Setting Timing in Case of Compare Match
Figure 10.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence,
and TGI interrupt request signal timing.
φ
TCNT input
clock
TCNT
N
TGR
N
N+1
Compare
match signal
TGF flag
TGI interrupt
Figure 10.38 TGI Interrupt Timing (Compare Match)
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Section 10 16-Bit Timer Pulse Unit (TPU)
(2) TGF Flag Setting Timing in Case of Input Capture
Figure 10.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and
TGI interrupt request signal timing.
φ
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 10.39 TGI Interrupt Timing (Input Capture)
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Section 10 16-Bit Timer Pulse Unit (TPU)
(3) TCFV Flag/TCFU Flag Setting Timing
Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and
TCIV interrupt request signal timing.
Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
TCIU interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
H'FFFF
H'0000
Overflow
signal
TCFV flag
TCIV interrupt
Figure 10.40 TCIV Interrupt Setting Timing
φ
TCNT
input clock
TCNT
(underflow)
H'0000
H'FFFF
Underflow
signal
TCFU flag
TCIU interrupt
Figure 10.41 TCIU Interrupt Setting Timing
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Section 10 16-Bit Timer Pulse Unit (TPU)
(4) Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or
DMAC is activated, the flag is cleared automatically. Figure 10.42 shows the timing for status flag
clearing by the CPU, and figure 10.43 shows the timing for status flag clearing by the DTC or
DMAC.
TSR write cycle
T1
T2
φ
TSR address
Address
Write signal
Status flag
Interrupt
request
signal
Figure 10.42 Timing for Status Flag Clearing by CPU
DTC/DMAC
read cycle
T1
T2
DTC/DMAC
write cycle
T1
T2
φ
Address
Source address
Destination
address
Status flag
Interrupt
request
signal
Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC Activation
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.7
Usage Notes
Note that the kinds of operation and contention described below occur during TPU operation.
(1) Module Stop Mode Settings
The TPU module operation disabled/enabled state can be set with the module stop control register.
The initial value of this register sets the TPU module to the stopped state. Register access becomes
possible when module stop mode is cleared. See section 17, Power-Down Modes, for details.
(2) Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.44 shows the input clock
conditions in phase counting mode.
Overlap
Phase
Phase
differdifference Overlap ence
Pulse width
Pulse width
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
: 2.5 states or more
Pulse width
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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Section 10 16-Bit Timer Pulse Unit (TPU)
(3) Caution on Period Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
φ
f=
Where
(N + 1)
f: Counter frequency
φ: Operating frequency
N: TGR set value
(4) Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 10.45 shows the timing in this case.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
Counter clear
signal
N
TCNT
H'0000
Figure 10.45 Contention between TCNT Write and Clear Operations
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Section 10 16-Bit Timer Pulse Unit (TPU)
(5) Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 10.46 shows the timing in this case.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 10.46 Contention between TCNT Write and Increment Operations
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Section 10 16-Bit Timer Pulse Unit (TPU)
(6) Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is inhibited. A compare match does not occur even if the same value
as before is written.
Figure 10.47 shows the timing in this case.
TGR write cycle
T2
T1
φ
TGR address
Address
Write signal
Compare
match signal
Prohibited
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 10.47 Contention between TGR Write and Compare Match
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Section 10 16-Bit Timer Pulse Unit (TPU)
(7) Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 10.48 shows the timing in this case.
TGR write cycle
T2
T1
φ
Buffer register
address
Address
Write signal
Compare
match signal
Buffer register write data
Buffer
register
TGR
N
M
N
Figure 10.48 Contention between Buffer Register Write and Compare Match
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Section 10 16-Bit Timer Pulse Unit (TPU)
(8) Contention between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data after input capture transfer.
Figure 10.49 shows the timing in this case.
TGR read cycle
T2
T1
φ
TGR address
Address
Read signal
Input capture
signal
TGR
X
M
M
Internal
data bus
Figure 10.49 Contention between TGR Read and Input Capture
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Section 10 16-Bit Timer Pulse Unit (TPU)
(9) Contention between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 10.50 shows the timing in this case.
TGR write cycle
T2
T1
φ
TGR address
Address
Write signal
Input capture
signal
TCNT
TGR
M
M
Figure 10.50 Contention between TGR Write and Input Capture
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Section 10 16-Bit Timer Pulse Unit (TPU)
(10) Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation
takes precedence and the write to the buffer register is not performed.
Figure 10.51 shows the timing in this case.
Buffer register write cycle
T1
T2
φ
Buffer register
address
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
N
M
N
M
Figure 10.51 Contention between Buffer Register Write and Input Capture
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Section 10 16-Bit Timer Pulse Unit (TPU)
(11) Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter
clear signal
TGF
Prohibited
TCFV
Figure 10.52 Contention between Overflow and Counter Clearing
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Section 10 16-Bit Timer Pulse Unit (TPU)
(12) Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set .
Figure 10.53 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T1
T2
φ
TCNT address
Address
Write signal
TCNT
TCNT write data
H'FFFF
M
Prohibited
TCFV flag
Figure 10.53 Contention between TCNT Write and Overflow
(13) Multiplexing of I/O Pins
In the H8S/2214 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the
TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and
the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match
output should not be performed from a multiplexed pin.
(14) Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source, DTC activation source, or DMAC activation source. Interrupts
should therefore be disabled before entering module stop mode.
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Section 11 Watchdog Timer (WDT)
Section 11 Watchdog Timer (WDT)
11.1
Overview
The H8S/2214 Group has an on-chip watchdog timer/watch timer with one channel. The watchdog
timer can generate an internal interrupt or an internal reset signal if a system crash prevents the
CPU from writing to the counter, allowing it to overflow.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer mode, an interval timer interrupt is generated each time the counter overflows.
11.1.1
Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
• Internal reset or internal interrupt generated when watchdog timer mode
Choice of whether or not an internal reset (power-on reset or manual reset selectable) is
effected when the counter overflows
• Interrupt generation in interval timer mode
⎯ An interval timer interrupt is generated when the counter overflows
• Choice of 8 counter input clocks
⎯ Maximum WDT interval: system clock period × 131072 × 256
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Section 11 Watchdog Timer (WDT)
11.1.2
Block Diagram
Figure 11.1 shows block diagrams of WDT.
Clock
Internal reset
signal*
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Overflow
Interrupt
control
Clock
select
Reset
control
RSTCSR
Internal clock
TCNT
TCSR
Module bus
Bus
interface
WDT
Legend:
TCSR:
Timer control/status register
TCNT:
Timer counter
RSTCSR: Reset control/status register
Note: * The internal reset signal can be generated by means of a register setting.
Either a power-on reset or a manual reset can be selected.
Figure 11.1 Block Diagram of WDT
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Internal bus
WOVI0
(interrupt request
signal)
Section 11 Watchdog Timer (WDT)
11.1.3
Register Configuration
The WDT has three registers, as summarized in table 11.1. These registers control clock selection,
WDT mode switching, the reset signal, etc.
Table 11.1 WDT Registers
Address*
1
Name
Abbreviation R/W
Timer control/status register
TCSR0
R/(W)*
Timer counter
TCNT0
R/W
RSTCSR0
R/(W)*
Reset control/status register
3
3
Initial Value
Write*
H'00
H'FF74
H'FF74
H'00
H'FF74
H'FF75
H'1F
H'FF76
H'FF77
2
Read
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 11.2.4, Notes on Register Access.
3. Only 0 can be written in bit 7, to clear the flag.
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Section 11 Watchdog Timer (WDT)
11.2
Register Descriptions
11.2.1
Timer Counter (TCNT)
:
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
R/W
:
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF flag in TCSR is set to 1.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see
section 11.2.4, Notes on Register Access.
11.2.2
Bit
Timer Control/Status Register (TCSR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
—
—
CKS2
CKS1
CKS0
0
0
0
1
1
0
0
0
R/(W)*
R/W
R/W
—
—
R/W
R/W
R/W
Note: * Only 0 can be written, to clear the flag.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCSR0 is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
section 11.2.4, Notes on Register Access.
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Section 11 Watchdog Timer (WDT)
Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF
to H'00.
Bit 7
OVF
Description
0
[Clearing condition]
•
1
(Initial value)
Read TCSR* when OVF = 1, then write 0 in OVFA
[Setting condition]
•
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF
is cleared automatically by the internal reset.
Note: * When the interval timer interrupt is disabled and OVF is polled, read the state of OVF = 1
twice or more.
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. If WDT is used in watchdog timer mode, it can generate a reset when TCNT
overflows. If WDT is used in interval timer mode, it generates a WOVI interrupt request to the
CPU when TCNT overflows.
Bit 6
WT/IT
Description
0
Interval timer mode: Interval timer interrupt (WOVI) request is sent to
CPU when TCNT overflows
(Initial value)
Watchdog timer mode: Internal reset can be selected when TCNT overflows*
1
Note: * For details of the case where TCNT overflows in watchdog timer mode, see section
11.2.3, Reset Control/Status Register (RSTCSR).
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME
Description
0
TCNT is initialized to H'00 and count operation is halted
1
TCNT counts
(Initial value)
WDT0 TCSR bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
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Section 11 Watchdog Timer (WDT)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source,
obtained by dividing the system clock (φ) for input to TCNT.
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
Clock
Overflow Period* (when φ = 10 MHz)
0
0
0
φ/2 (Initial value)
51.2 µs
1
φ/64
1.6 ms
0
φ/128
3.2 ms
1
φ/512
13.2 ms
0
φ/2048
52.4 ms
1
φ/8192
209.8 ms
0
φ/32768
838.8 ms
1
φ/131072
3.36 s
1
1
0
1
Description
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until
overflow occurs.
11.2.3
Bit
Reset Control/Status Register (RSTCSR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
WOVF
RSTE
RSTS
—
—
—
—
—
0
0
0
1
1
1
1
1
R/(W)*
R/W
R/W
—
—
—
—
—
Note: * Only 0 can be written, to clear the flag.
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the internal reset
signal caused by a WDT overflow.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
see section 11.2.4, Notes on Register Access.
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Section 11 Watchdog Timer (WDT)
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (from H'FF to
H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF
Description
0
[Clearing condition]
1
[Setting condition]
(Initial value)
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
When TCNT overflows (from H'FF to H'00) in watchdog timer mode
Bit 6—Reset Enable (RSTE): Specifies whether or not an internal reset signal is generated if
TCNT overflows in watchdog timer mode.
Bit 6
RSTE
Description
0
No internal reset when TCNT overflows*
1
Internal reset is generated when TCNT overflows
(Initial value)
Note: * The chip is not reset internally, but TCNT and TCSR in WDT0 are reset.
Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows in
watchdog timer mode.
For details of the types of resets, see section 4, Exception Handling.
Bit 5
RSTS
Description
0
Power-on reset
1
Manual reset
(Initial value)
Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.
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Section 11 Watchdog Timer (WDT)
11.2.4
Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
(1) Writing to TCNT and TCSR
These registers must be written to by a word transfer instruction. They cannot be written to with
byte transfer instructions.
Figure 11.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the written word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
TCNT write
15
8 7
H'5A
Address: H'FF74
0
Write data
TCSR write
15
Address: H'FF74
8 7
H'A5
0
Write data
Figure 11.2 Format of Data Written to TCNT and TCSR (Example of WDT0)
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Section 11 Watchdog Timer (WDT)
(2) Writing to RSTCSR
RSTCSR must be written to by a word transfer to address H'FF76. It cannot be written to with
byte instructions.
Figure 11.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF
bit differs from that for writing to the RSTE and RSTS bits.
To write 0 to the WOVF bit, the upper byte of the written word must contain H'A5 and the lower
byte must contain H'00. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS
bits. To write to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte
must contain the write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE
and RSTS bits, but has no effect on the WOVF bit.
Writing 0 to WOVF bit
15
8 7
H'A5
Address: H'FF76
0
H'00
Writing to RSTE and RSTS bits
15
Address: H'FF76
8 7
H'5A
0
Write data
Figure 11.3 Format of Data Written to RSTCSR (Example of WDT0)
(3) Reading TCNT, TCSR, and RSTCSR
These registers are read in the same way as other registers. The read addresses are H'FF74 for
TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR.
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Section 11 Watchdog Timer (WDT)
11.3
Operation
11.3.1
Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must
prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. This ensures that TCNT does not overflow while the system is operating
normally.
In this way, TCNT will not overflow while the system is operating normally, but if TCNT is not
rewritten and overflows because of a system crash or other error, in the case of WDT, if the RSTE
bit in RSTCSR is set to 1 beforehand, a signal is generated that effects an internal chip reset.
Either a power-on reset or a manual reset can be selected with the RSTS bit in RSTCSR. The
internal reset signal is output for 518 states. This is illustrated in figure 11.4.
If a reset caused by an input signal from the RES pin and a reset caused by WDT overflow occur
simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0.
TCNT value
Overflow
H'FF
Time
H'00
WT/IT = 1
TME = 1
H'00 written
to TCNT
WOVF = 1
WT/IT = 1 H'00 written
TME = 1 to TCNT
Internal reset
generated
Internal reset signal*
518 states (WDT0)
Legend:
WT/IT: Timer mode select bit
TME: Timer enable bit
Note: * With WDT, the internal reset signal is generated only when the RSTE bit is set to 1.
Figure 11.4 Operation in Watchdog Timer Mode
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Section 11 Watchdog Timer (WDT)
11.3.2
Interval Timer Operation
To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1.
An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the
WDT is operating as an interval timer, as shown in figure 11.5. This function can be used to
generate interrupt requests at regular intervals.
TCNT count
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WT/IT = 0
TME = 1
WOVI
WOVI
WOVI
WOVI
Legend:
WOVI: Interval timer interrupt request generation
Figure 11.5 Operation in Interval Timer Mode
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Section 11 Watchdog Timer (WDT)
11.3.3
Timing of Setting of Overflow Flag (OVF)
The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an
interval timer interrupt (WOVI) is requested. This timing is shown in figure 11.6.
φ
TCNT
H'FF
Overflow signal
(internal signal)
H'00
φ1
φ1
φ1
OVF
Figure 11.6 Timing of OVF Setting
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Section 11 Watchdog Timer (WDT)
11.3.4
Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
With WDT, the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode. If
TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated
for the entire chip. This timing is illustrated in figure 11.7.
φ
TCNT
H'FF
H'00
Overflow signal
(internal signal)
WOVF
Internal reset
signal
518 states (WDT)
Figure 11.7 Timing of WOVF Setting
11.4
Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
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Section 11 Watchdog Timer (WDT)
11.5
Usage Notes
11.5.1
Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 11.8 shows this operation.
TCNT write cycle
T1
T2
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 11.8 Contention between TCNT Write and Increment
11.5.2
Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
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Section 11 Watchdog Timer (WDT)
11.5.3
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
11.5.4
Internal Reset in Watchdog Timer Mode
If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally if
TCNT overflows, but TCNT and TCSR in WDT will be reset.
TCNT, TCSR, and RSTCR cannot be written to for a 132-state interval after overflow occurs, and
a read of the WOVF flag is not recognized during this time. It is therefore necessary to wait for
132 states after overflow occurs before writing 0 to the WOVF flag to clear it.
11.5.5
OVF Flag Clear Operation in Interval Timer Mode
In interval timer mode, if a contention between an OVF flag set and an OVF flag read occurs,
there are cases where even though the OVF = 1 state was read, the flag is not cleared when it is set
to 0. In cases such as when the interval timer interrupt is disabled and the OVF flag is polled, that
is, in cases where contention between an OVF flag set and an OVF flag read may occur, the
application should read the OVF = 1 state at least twice and then set OVF to 0.
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Section 11 Watchdog Timer (WDT)
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Section 12 Serial Communication Interface (SCI)
Section 12 Serial Communication Interface (SCI)
12.1
Overview
The H8S/2214 Group is equipped with mutually independent serial communication interface (SCI)
channels. The SCI can handle both asynchronous and clocked synchronous serial communication.
A function is also provided for serial communication between processors (multiprocessor
communication function).
SCI0 allows a choice of 720 kbps, 460.784 kbps, or 115.192 kbps at 16-MHz operation.
12.1.1
Features
SCI features are listed below.
• Choice of asynchronous or clocked synchronous serial communication mode
Asynchronous mode
⎯ Serial data communication executed using asynchronous system in which synchronization
is achieved character by character
Serial data communication can be carried out with standard asynchronous communication
chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous
Communication Interface Adapter (ACIA)
⎯ A multiprocessor communication function is provided that enables serial data
communication with a number of processors
⎯ Choice of 12 serial data transfer formats
Data length
: 7 or 8 bits
Stop bit length
: 1 or 2 bits
Parity
: Even, odd, or none
Multiprocessor bit
: 1 or 0
⎯ Receive error detection
: Parity, overrun, and framing errors
⎯ Break detection
: Break can be detected by reading the RxD pin level directly in
case of a framing error
⎯ Average transfer rate generator (SCI0): 720 kbps, 460.784 kbps, or 115.192 kbps can be
selected at 16 MHz
⎯ A transfer rate clock can be input from the TPU (SCI0)
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Section 12 Serial Communication Interface (SCI)
Clocked Synchronous mode
⎯ Serial data communication synchronized with a clock
Serial data communication can be carried out with other chips that have a synchronous
communication function
⎯ One serial data transfer format
Data length
⎯ Receive error detection
: 8 bits
: Overrun errors detected
⎯ SCI select function (SCI0 : TxD0 = high-impedance and SCK0 = fixed high-level input
can be selected when IRQ7 = 1)
• Full-duplex communication capability
⎯ The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
⎯ Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
• Choice of LSB-first or MSB-first transfer
⎯ Can be selected regardless of the communication mode* (except in the case of
asynchronous mode 7-bit data)
Note: * Descriptions in this section refer to LSB-first transfer.
• On-chip baud rate generator allows any bit rate to be selected
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
• Four interrupt sources
⎯ Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive
error — that can issue requests independently
⎯ The transmit-data-empty interrupt and receive data full interrupts can activate the data
transfer controller (DTC) or DMA controller (DMAC) to execute data transfer
• Module stop mode can be set
⎯ As the initial setting, SCI operation is halted. Register access is enabled by exiting module
stop mode.
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Section 12 Serial Communication Interface (SCI)
12.1.2
Block Diagram
Bus interface
Figures 12.1 and 12.2 show block diagrams of the SCI.
Module data bus
RxD0
RDR
TDR
RSR
TSR
SCMR
SSR
SCR
SMR
SEMR
Internal
data bus
BRR
φ
φ/4
φ/16
φ/64
Baud rate
generator
Transmit/
receive control
TxD0
Parity
generation
Parity check
Clock
TEI
TxI
RxI
ERI
PG1/IRQ7
Average transfer
rate generator
C/A
CKE1
SSE
External clock
SCK0
at 10.667 MHz
• 115.152 kbps
• 460.606 kbps
at 16 MHz
• 115.192 kbps
• 460.784 kbps
• 720 kbps
SCI0
TIOCA1
TCLKA
TIOCA2
Legend:
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR:
SSR:
SCMR:
BRR:
SEMR:
TPU
Serial control register
Serial status register
Serial card mode register
Bit rate register
Serial extended mode register
Figure 12.1 Block Diagram of SCI0
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Bus interface
Section 12 Serial Communication Interface (SCI)
Module data bus
RDR
RxD
TxD
RSR
TDR
SCMR
SSR
SCR
SMR
TSR
BRR
φ
φ/4
Baud rate
generator
φ/16
Transmission/
reception control
Parity generation
Parity check
SCK
Legend:
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
SCMR: Smart card mode register
BRR: Bit rate register
φ/64
Clock
External clock
TEI
TXI
RXI
ERI
Figure 12.2 Block Diagram of SCI1 and SCI2
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Internal
data bus
Section 12 Serial Communication Interface (SCI)
12.1.3
Pin Configuration
Table 12.1 shows the serial pins for each SCI channel.
Table 12.1 SCI Pins
Channel
Pin Name
Symbol
I/O
Function
0
Serial clock pin 0
SCK0
I/O
SCI0 clock input/output
Receive data pin 0
RxD0
Input
SCI0 receive data input
Transmit data pin 0
TxD0
Output
SCI0 transmit data output
1
2
Serial clock pin 1
SCK1
I/O
SCI1 clock input/output
Receive data pin 1
RxD1
Input
SCI1 receive data input
Transmit data pin 1
TxD1
Output
SCI1 transmit data output
Serial clock pin 2
SCK2
I/O
SCI2 clock input/output
Receive data pin 2
RxD2
Input
SCI2 receive data input
Transmit data pin 2
TxD2
Output
SCI2 transmit data output
Note: Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel
designation.
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Section 12 Serial Communication Interface (SCI)
12.1.4
Register Configuration
The SCI has the internal registers shown in table 12.2. These registers are used to specify
asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control
transmitter/receiver.
Table 12.2 SCI Registers
Channel Name
Abbreviation R/W
Initial Value Address*
0
SMR0
H'00
1
2
All
Serial mode register 0
R/W
1
H'FF78
Bit rate register 0
BRR0
R/W
H'FF
H'FF79
Serial control register 0
SCR0
R/W
H'00
H'FF7A
Transmit data register 0
TDR0
R/W
H'FF7B
Serial status register 0
SSR0
H'FF
2
*
R/(W)
H'84
Receive data register 0
RDR0
R
H'00
H'FF7D
Smart card mode register 0
SCMR0
R/W
H'F2
H'FF7E
Serial expansion mode register 0
SEMR0
R/W
H'00
H'FDF8
Serial mode register 1
SMR1
R/W
H'00
H'FF80
Bit rate register 1
BRR1
R/W
H'FF
H'FF81
Serial control register 1
SCR1
R/W
H'00
H'FF82
Transmit data register 1
TDR1
Serial status register 1
SSR1
R/W
H'FF
2
R/(W)* H'84
H'FF84
Receive data register 1
RDR1
R
H'00
H'FF85
Smart card mode register 1
SCMR1
R/W
H'F2
H'FF86
Serial mode register 2
SMR2
R/W
H'00
H'FF88
Bit rate register 2
BRR2
R/W
H'FF
H'FF89
H'FF7C
H'FF83
Serial control register 2
SCR2
R/W
H'00
H'FF8A
Transmit data register 2
TDR2
R/W
H'FF
H'FF8B
Serial status register 2
SSR2
2
R/(W)* H'84
H'FF8C
Receive data register 2
RDR2
R
H'00
H'FF8D
Smart card mode register 2
SCMR2
R/W
H'F2
H'FF8E
Module stop control register B
MSTPCRB
R/W
H'FF
H'FDE9
Notes: 1. Lower 16 bits of the address.
2. Can only be written with 0 for flag clearing.
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Section 12 Serial Communication Interface (SCI)
12.2
Register Descriptions
12.2.1
Receive Shift Register (RSR)
Bit
:
7
6
5
4
3
2
1
0
R/W
:
—
—
—
—
—
—
—
—
RSR is a register used to receive serial data.
The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to RDR automatically.
RSR cannot be directly read or written to by the CPU.
12.2.2
Bit
Receive Data Register (RDR)
:
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
:
RDR is a register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received serial data from RSR to
RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled.
Since RSR and RDR function as a double buffer in this way, enables continuous receive
operations to be performed.
RDR is a read-only register, and cannot be written to by the CPU.
RDR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, and subsleep
mode or module stop mode.
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Section 12 Serial Communication Interface (SCI)
12.2.3
Transmit Shift Register (TSR)
Bit
:
7
6
5
4
3
2
1
0
R/W
:
—
—
—
—
—
—
—
—
TSR is a register used to transmit serial data.
To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then
sends the data to the TxD pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from TDR to
TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not
performed if the TDRE bit in SSR is set to 1.
TSR cannot be directly read or written to by the CPU.
12.2.4
Bit
Transmit Data Register (TDR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDR is an 8-bit register that stores data for serial transmission.
When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and
starts serial transmission. Continuous serial transmission can be carried out by writing the next
transmit data to TDR during serial transmission of the data in TSR.
TDR can be read or written to by the CPU at all times.
TDR is initialized to H'FF by a reset, in standby mode, watch mode, subactive mode, and subsleep
mode or module stop mode.
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Section 12 Serial Communication Interface (SCI)
12.2.5
Bit
Serial Mode Register (SMR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate
generator clock source.
SMR can be read or written to by the CPU at all times.
SMR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in
module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
Bit 7—Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode
as the SCI operating mode.
Bit 7
C/A
Description
0
Asynchronous mode
1
Clocked synchronous mode
(Initial value)
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR
Description
0
8-bit data
7-bit data*
1
(Initial value)
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not
possible to choose between LSB-first or MSB-first transfer.
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Section 12 Serial Communication Interface (SCI)
Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In clocked synchronous mode
with a multiprocessor format, parity bit addition and checking is not performed, regardless of the
PE bit setting.
Bit 5
PE
Description
0
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
1
(Initial value)
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode,
when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor
format is used.
Bit 4
O/E
Description
0
Even parity*
2
Odd parity*
1
1
(Initial value)
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is odd.
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the
STOP bit setting is invalid since stop bits are not added.
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Section 12 Serial Communication Interface (SCI)
Bit 3
STOP
Description
0
1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end
of a transmit character before it is sent.
1
2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit
character before it is sent.
(Initial value)
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in clocked synchronous mode.
For details of the multiprocessor communication function, see section 12.3.3, Multiprocessor
Communication Function.
Bit 2
MP
Description
0
Multiprocessor function disabled
1
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the
baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 12.2.8, Bit Rate Register (BRR).
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
φ clock
1
φ/4 clock
0
φ/16 clock
1
φ/64 clock
1
(Initial value)
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Section 12 Serial Communication Interface (SCI)
12.2.6
Bit
Serial Control Register (SCR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in
module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1.
Bit 7
TIE
Description
0
Transmit data empty interrupt (TXI) requests disabled*
1
Transmit data empty interrupt (TXI) requests enabled
(Initial value)
Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then
clearing it to 0, or clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI)
request and receive error interrupt (ERI) request generation when serial receive data is transferred
from RSR to RDR and the RDRF flag in SSR is set to 1.
Bit 6
RIE
Description
0
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
disabled*
(Initial value)
1
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
enabled
Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF
flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to
0.
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Section 12 Serial Communication Interface (SCI)
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5
TE
Description
0
Transmission disabled*
2
Transmission enabled*
1
1
(Initial value)
Notes: 1. The TDRE flag in SSR is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR and the
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transfer format before setting the TE bit
to 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4
RE
Description
0
1
Reception disabled*
2
Reception enabled*
1
(Initial value)
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in clocked synchronous mode.
SMR setting must be performed to decide the transfer format before setting the RE bit
to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1.
The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.
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Section 12 Serial Communication Interface (SCI)
Bit 3
MPIE
Description
0
Multiprocessor interrupts disabled (normal reception performed)
(Initial value)
[Clearing conditions]
•
When the MPIE bit is cleared to 0
•
1
When MPB= 1 data is received
Multiprocessor interrupts enabled*
Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR,
receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not
performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to
1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts
(when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is
enabled.
Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt
(TEI) request generation when there is no valid transmit data in TDR in MSB data transmission.
Bit 2
TEIE
Description
0
Transmit end interrupt (TEI) request disabled*
Transmit end interrupt (TEI) request enabled*
1
(Initial value)
Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing
it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or
the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case
of external clock operation (CKE1 = 1). Note that the SCI’s operating mode must be decided using
SMR after setting the CKE1 and CKE0 bits.
For details of clock source selection, see table 12.9.
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Section 12 Serial Communication Interface (SCI)
Bit 1
Bit 0
CKE1
CKE0
Description
0
0
Asynchronous mode
1
Internal clock/SCK pin functions as I/O port*
Clocked synchronous
mode
Internal clock/SCK pin functions as serial clock
output
Asynchronous mode
Internal clock/SCK pin functions as clock output*
Clocked synchronous
mode
Internal clock/SCK pin functions as serial clock
output
Asynchronous mode
External clock/SCK pin functions as clock input*
Clocked synchronous
mode
Asynchronous mode
External clock/SCK pin functions as serial clock
input
3
External clock/SCK pin functions as clock input*
Clocked synchronous
mode
External clock/SCK pin functions as serial clock
input
1
1
0
1
2
3
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
12.2.7
Bit
Serial Status Register (SSR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
1
0
0
0
0
1
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Note: * Only 0 can be written, to clear the flag.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR is initialized to H'84 by a reset, in standby mode, watch mode, subactive mode, and subsleep
mode or module stop mode.
Rev.4.00 Sep. 18, 2008 Page 467 of 872
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Section 12 Serial Communication Interface (SCI)
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 7
TDRE
Description
0
[Clearing conditions]
1
Note:
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
*
(Initial value)
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR and data can be written to TDR
This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not
0.
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6
RDRF
Description
0
[Clearing conditions]
1
(Initial value)
•
When 0 is written to RDRF after reading RDRF = 1
•
When the DMAC or DTC* is activated by an RXI interrupt and reads data from
RDR
[Setting condition]
•
When serial reception ends normally and receive data is transferred from RSR to
RDR
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
* This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not
0.
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Section 12 Serial Communication Interface (SCI)
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5
ORER
Description
0
[Clearing condition]
1
[Setting condition]
•
•
1
(Initial value)*
When 0 is written to ORER after reading ORER = 1
When the next serial reception is completed while RDRF = 1*
2
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. The receive data prior to the overrun error is retained in RDR, and the data received
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be
continued, either.
Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Bit 4
FER
Description
0
[Clearing condition]
•
1
(Initial value)*
1
When 0 is written to FER after reading FER = 1
[Setting condition]
•
When the SCI checks whether the stop bit at the end of the receive data when
2
reception ends, and the stop bit is 0 *
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit
is not checked. If a framing error occurs, the receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial reception cannot be continued while the
FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be
continued, either.
Rev.4.00 Sep. 18, 2008 Page 469 of 872
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Section 12 Serial Communication Interface (SCI)
Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity
addition in asynchronous mode, causing abnormal termination.
Bit 3
PER
Description
0
[Clearing condition]
•
1
(Initial value)*
1
When 0 is written to PER after reading PER = 1
[Setting condition]
•
When, in reception, the number of 1 bits in the receive data plus the parity bit does
2
not match the parity setting (even or odd) specified by the O/E bit in SMR*
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In clocked synchronous mode, serial transmission cannot be continued, either.
Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2
TEND
Description
0
[Clearing conditions]
1
Note:
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
*
(Initial value)
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not
0.
Rev.4.00 Sep. 18, 2008 Page 470 of 872
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Section 12 Serial Communication Interface (SCI)
Bit 1—Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in
asynchronous mode, MPB stores the multiprocessor bit in the receive data.
MPB is a read-only bit, and cannot be modified.
Bit 1
MPB
Description
0
[Clearing condition]
1
[Setting condition]
•
•
(Initial value)*
When data with a 0 multiprocessor bit is received
When data with a 1 multiprocessor bit is received
Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor
format.
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting,
and in clocked synchronous mode.
Bit 0
MPBT
Description
0
Data with a 0 multiprocessor bit is transmitted
1
Data with a 1 multiprocessor bit is transmitted
(Initial value)
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Section 12 Serial Communication Interface (SCI)
12.2.8
Bit
Bit Rate Register (BRR)
:
7
6
5
4
3
2
1
0
Initial value :
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset and in hardware standby mode. It retains its previous state in
module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 12.3 shows sample BRR settings in asynchronous mode, and table 12.4 shows sample BRR
settings in clocked synchronous mode.
Rev.4.00 Sep. 18, 2008 Page 472 of 872
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Section 12 Serial Communication Interface (SCI)
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
φ = 2 MHz
φ = 2.097152 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
110
1
141
0.03
1
148
150
1
103
0.16
1
108
300
0
207
0.16
0
600
0
103
0.16
1200
0
51
2400
0
4800
0
9600
φ = 2.4576 MHz
N
Error
(%)
–0.04 1
174
0.21
1
127
217
0.21
0
0
108
0.21
0
0.16
0
54
25
0.16
0
12
0.16
0
—
—
—
19200
—
—
31250
0
38400
—
φ = 3 MHz
N
Error
(%)
–0.26 1
212
0.03
0.00
1
155
0.16
255
0.00
1
77
0.16
127
0.00
0
155
0.16
–0.70 0
63
0.00
0
77
0.16
26
1.14
0
31
0.00
0
38
0.16
13
–2.48 0
15
0.00
0
19
–2.34
0
6
–2.48 0
7
0.00
0
9
–2.34
—
—
—
—
0
3
0.00
0
4
–2.34
1
0.00
—
—
—
—
—
—
0
2
0.00
—
—
—
—
—
0
1
0.00
—
—
—
φ = 3.6864 MHz
n
φ = 4 MHz
n
φ = 4.9152 MHz
φ = 5 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
64
0.70
2
70
0.03
2
86
0.31
2
88
–0.25
150
1
191
0.00
1
207
0.16
1
255
0.00
2
64
0.16
300
1
95
0.00
1
103
0.16
1
127
0.00
1
129
0.16
600
0
191
0.00
0
207
0.16
0
255
0.00
1
64
0.16
1200
0
95
0.00
0
103
0.16
0
127
0.00
0
129
0.16
2400
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
–1.36
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
19200
0
5
0.00
—
—
—
0
7
0.00
0
7
1.73
31250
—
—
—
0
3
0.00
0
4
–1.70 0
4
0.00
38400
0
2
0.00
—
—
—
0
3
0.00
3
1.73
0
Rev.4.00 Sep. 18, 2008 Page 473 of 872
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Section 12 Serial Communication Interface (SCI)
φ = 6 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
110
2
106
150
2
300
φ = 6.144 MHz
φ = 7.3728 MHz
N
Error
(%)
n
N
Error
(%)
–0.44 2
108
0.08
2
130
77
0.16
2
79
0.00
2
1
155
0.16
1
159
0.00
600
1
77
0.16
1
79
1200
0
155
0.16
0
2400
0
77
0.16
0
4800
0
38
0.16
9600
0
19200
φ = 8 MHz
N
Error
(%)
–0.07 2
141
0.03
95
0.00
2
103
0.16
1
191
0.00
1
207
0.16
0.00
1
95
0.00
1
103
0.16
159
0.00
0
191
0.00
0
207
0.16
79
0.00
0
95
0.00
0
103
0.16
0
39
0.00
0
47
0.00
0
51
0.16
19
–2.34 0
19
0.00
0
23
0.00
0
25
0.16
0
9
–2.34 0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.40
—
—
—
0
7
0.00
38400
0
4
–2.34 0
4
0.00
0
5
0.00
—
—
—
n
φ = 9.8304 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
110
2
174
150
2
300
φ = 10 MHz
N
Error
(%)
–0.26 2
177
127
0.00
2
1
255
0.00
600
1
127
1200
0
2400
0
4800
n
φ = 12 MHz
φ = 12.288 MHz
N
Error
(%)
n
N
Error
(%)
–0.25 2
212
0.03
2
217
0.08
129
0.16
2
155
0.16
2
159
0.00
2
64
0.16
2
77
0.16
2
79
0.00
0.00
1
129
0.16
1
155
0.16
1
159
0.00
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
–1.36 0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
–2.34 0
19
0.00
31250
0
9
–1.70 0
9
0.00
0
11
0.00
11
2.40
38400
0
7
0.00
7
1.73
0
9
–2.34 0
9
0.00
n
0
Rev.4.00 Sep. 18, 2008 Page 474 of 872
REJ09B0189-0400
n
0
Section 12 Serial Communication Interface (SCI)
φ = 14 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
110
2
248
150
2
300
φ = 14.7456 MHz
φ = 16 MHz
N
Error
(%)
n
N
Error
(%)
–0.17 3
64
0.70
3
70
0.03
181
0.16
2
191
0.00
2
207
0.16
2
90
0.16
2
95
0.00
2
103
0.16
600
1
181
0.16
1
191
0.00
1
207
0.16
1200
1
90
0.16
1
95
0.00
1
103
0.16
2400
0
181
0.16
0
191
0.00
0
207
0.16
4800
0
90
0.16
0
95
0.00
0
103
0.16
9600
0
45
–0.93 0
47
0.00
0
51
0.16
19200
0
22
–0.93 0
23
0.00
0
25
0.16
31250
0
13
0.00
0
14
–1.70 0
15
0.00
38400
—
—
—
0
11
0.00
12
0.16
n
0
Note: Example when ABCS in SEMR0 is cleared to 0. The bit rate is 2× if ABCS is set to 1.
Rev.4.00 Sep. 18, 2008 Page 475 of 872
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Section 12 Serial Communication Interface (SCI)
Table 12.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
φ = 2 MHz
φ = 4 MHz
Bit Rate
(bit/s)
n
N
n
N
110
3
70
—
—
250
2
124
2
500
1
249
2
1k
1
124
2.5 k
0
5k
φ = 6 MHz
φ = 16 MHz
N
n
N
n
N
249
3
124
—
—
3
249
124
2
249
—
—
3
124
1
249
2
124
—
—
2
249
199
1
99
1
149
1
199
1
249
2
99
0
99
0
199
1
74
1
99
1
124
1
199
10 k
0
49
0
99
0
149
0
199
0
249
1
99
25 k
0
19
0
39
0
59
0
79
0
99
0
159
50 k
0
9
0
19
0
29
0
39
0
49
0
79
100 k
0
4
0
9
0
14
0
19
0
24
0
39
250 k
0
1
0
3
0
5
0
7
0
9
0
15
0
0*
0
1
0
2
0
3
0
4
0
7
0
0*
0
1
0
3
0
0*
0
0*
1M
N
φ = 10 MHz
n
500 k
n
φ = 8 MHz
2.5 M
4M
Legend:
Blank: Cannot be set.
—:
Can be set, but there will be a degree of error.
*:
Continuous transfer is not possible.
Rev.4.00 Sep. 18, 2008 Page 476 of 872
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Section 12 Serial Communication Interface (SCI)
The BRR setting is found from the following formulas.
Mode
ABCS
Asynchronous
mode
0
Bit Rate
B=
φ × 106
64 × 22n-1 × (N + 1)
Error (%) =
φ × 106
– 1 × 100
B × 64 × 22n-1 × (N + 1)
B=
φ × 106
32 × 22n-1 × (N + 1)
Error (%) =
φ × 106
– 1 × 100
B × 32 × 22n-1 × (N + 1)
B=
φ × 106
8 × 22n-1 × (N + 1)
1
Clocked
synchronous
mode
Error
X
⎯
Legend: B:
N:
φ:
n:
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
X: Don’t care
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
Rev.4.00 Sep. 18, 2008 Page 477 of 872
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Section 12 Serial Communication Interface (SCI)
Table 12.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 12.6
and 12.7 show the maximum bit rates with external clock input.
When the ABCS bit in SCI0's serial expansion mode register 0 (SEMR0) is set to 1 in
asynchronous mode, the maximum bit rates are twice those shown in tables 12.5 and 12.6.
Table 12.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode, when ABCS = 0)
φ (MHz)
Maximum Bit Rate (bit/s)
n
N
2
62500
0
0
2.097152
65536
0
0
2.4576
76800
0
0
3
93750
0
0
3.6864
115200
0
0
4
125000
0
0
4.9152
153600
0
0
5
156250
0
0
6
187500
0
0
6.144
192000
0
0
7.3728
230400
0
0
8
250000
0
0
9.8304
307200
0
0
10
312500
0
0
12
375000
0
0
12.288
384000
0
0
14
437500
0
0
14.7456
460800
0
0
16
500000
0
0
Rev.4.00 Sep. 18, 2008 Page 478 of 872
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Section 12 Serial Communication Interface (SCI)
Table 12.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode,
when ABCS = 0)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
2
0.5000
31250
2.097152
0.5243
32768
2.4576
0.6144
38400
3
0.7500
46875
3.6864
0.9216
57600
4
1.0000
62500
4.9152
1.2288
76800
5
1.2500
78125
6
1.5000
93750
6.144
1.5360
96000
7.3728
1.8432
115200
8
2.0000
125000
9.8304
2.4576
153600
10
2.5000
156250
12
3.0000
187500
12.288
3.0720
192000
14
3.5000
218750
14.7456
3.6864
230400
16
4.0000
250000
Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
2
0.3333
333333.3
4
0.6667
666666.7
6
1.0000
1000000.0
8
1.3333
1333333.3
10
1.6667
1666666.7
12
2.0000
2000000.0
14
2.3333
2333333.3
16
2.6667
2666666.7
Rev.4.00 Sep. 18, 2008 Page 479 of 872
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Section 12 Serial Communication Interface (SCI)
12.2.9
Smart Card Mode Register (SCMR)
7
6
5
4
3
2
1
0
—
—
—
—
SDIR
SINV
—
—
Initial value :
1
1
1
1
0
0
1
0
R/W
—
—
—
—
R/W
R/W
—
R/W
Bit
:
:
SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous
mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication
mode
SCMR is initialized to H'F2 by a reset and in hardware standby mode. It retains its previous state
in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
This bit is valid when 8-bit data is used as the transmit/receive format.
Bit 3
SDIR
Description
0
TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
1
TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
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(Initial value)
Section 12 Serial Communication Interface (SCI)
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV
bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the
O/E bit in SMR.
Bit 2
SINV
Description
0
TDR contents are transmitted without modification
Receive data is stored in RDR without modification
1
TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
(Initial value)
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Reserved: This bit can be read or written to, but only 0 should be written.
12.2.10 Serial Extended Mode Register 0 (SEMR0)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
SSE
—
—
—
ABCS
ACS2
ACS1
ACS0
0
0
0
0
R/W
R/W
R/W
R/W
0
R/W
Undefined Undefined Undefined
—
—
—
SEMR0 is an 8-bit register that extends the functions of SCI0.
SEMR0 enables selection of the SCI0 select function in synchronous mode, base clock setting in
asynchronous mode, and also clock source selection and automatic transfer rate setting.
SEMR0 is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in module stop mode and software standby mode.
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Section 12 Serial Communication Interface (SCI)
Bit 7—SCI0 Select Enable (SSE): Allows selection of the SCI0 select function when an external
clock is input in synchronous mode. When the SCI0 select function is enabled, if 1 is input to the
PG1/IRQ7 pin, TxD0 output goes to the high-impedance state, SCK0 input is fixed high inside the
chip, and SCI0 data transmission/reception is halted.
The SSE setting is valid when external clock input is used (CKE1 = 1 in SCR) in synchronous
mode (C/A = 1 in SMR). When an internal clock is selected (CKE1 = 0 in SCR) in synchronous
mode, or when the chip is in asynchronous mode (C/A = 0 in SMR), the SCI0 select function is
disabled even if SSE is set to 1.
Bit 7
SSE
Description
0
SCI0 select function disabled
1
SCI0 select function enabled
When PG1/IRQ7 pin input = 1, TxD0 output goes to high-impedance state and SCK0
clock input is fixed high
(Initial value)
Bits 6 to 4—Reserved: Write 0 to these bits.
Bit 3—Asynchronous Base Clock Select (ABCS): Selects the 1-bit-interval base clock in
asynchronous mode.
The ABCS setting is valid in asynchronous mode (C/A = 0 in SMR). It is invalid in synchronous
mode (C/A = 1 in SMR).
Bit 3
ABCS
Description
0
SCI0 operates on base clock with frequency of 16 times transfer rate
1
SCI0 operates on base clock with frequency of 8 times transfer rate
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(Initial value)
Section 12 Serial Communication Interface (SCI)
Bits 2 to 0—Asynchronous Clock Source Select 2 to 0 (ACS2 to ACS0): These bits select the
clock source in asynchronous mode.
When an average transfer rate is selected, the base clock is set automatically regardless of the
ABCS value. Note that average transfer rates are not supported for operating frequencies other
than 10.667 MHz and 16 MHz.
The setting in bits ACS2 to ACS0 is valid when external clock input is used (CKE1 = 1 in SCR) in
asynchronous mode (C/A = 0 in SMR). The setting in ACS2 to ACS0 is invalid when an internal
clock is selected (CKE1 = 0 in SCR) in asynchronous mode, or when the chip is in synchronous
mode (C/A = 1 in SMR).
Bit 2
Bit 1
Bit 0
ACS2
ACS1
ACS0
0
0
0
External clock input
1
115.152 kbps average transfer rate (for φ = 10.667 MHz only)
is selected (SCI0 operates on base clock with frequency of
16 times transfer rate)
0
460.606 kbps average transfer rate (for φ = 10.667 MHz only)
is selected (SCI0 operates on base clock with frequency of 8
times transfer rate)
1
Reserved
0
TPU clock input (AND of TIOCA1 and TIOCA2)
1
115.196 kbps average transfer rate (for φ = 16 MHz only) is
selected (SCI0 operates on base clock with frequency of 16
times transfer rate)
0
460.784 kbps average transfer rate (for φ = 16 MHz only) is
selected (SCI0 operates on base clock with frequency of 16
times transfer rate)
1
720 kbps average transfer rate (for φ = 16 MHz only) is
selected (SCI0 operates on base clock with frequency of 8
times transfer rate)
1
1
0
1
Description
(Initial value)
Figures 12.3 and 12.4 show examples of the internal base clock when an average transfer rate is
selected.
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1
1
2
2
4
5
1.8424 MHz
4 5
6
1
1
2
2
8
7
4
5
6
3
7
8
13 14
15 16
7
Average transfer rate = 3.6848 MHz/8 = 460.606 kbps
Average error = -0.043%
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1
1 bit = base clock × 8*
3.6848 MHz
4 5
6
5.333 MHz
3
10 11 12
Average transfer rate = 1.8424 MHz/16= 115.152 kbps
Average error = -0.043%
8 9
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1
1 bit = base clock × 16*
3
7
Note: * As the base clock synchronization varies, so does the length of one bit.
3.6848 MHz (average)
5.333 MHz × (38/55) =
10.667 MHz/2 = 5.333 MHz
Base clock
6
2.667 MHz
3
Base clock with 460.606 kbps average transfer rate
1.8424 MHz (average)
2.667 MHz × (38/55) =
10.6677 MHz/4 = 2.667 MHz
Base clock
Base clock with 115.152 kbps average transfer rate
When φ = 10.667 MHz
2
2
3 4
3 4
Section 12 Serial Communication Interface (SCI)
Figure 12.3 Examples of Base Clock when Average Transfer Rate Is Selected (1)
1
1
2
2
3
3
4
5
Base clock
1
1
2
2
3
3
4
Base clock
1
1
2
2
1 bit = base clock × 16*
9 10 11 12
13 14 15 16
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1
8
4
5
6
7
5.76 MHz
4 5
8 MHz
6
8
2
3 4
5
6
7 8
9 10 11 12
13 14 15 16
7
Average transfer rate = 5.76 MHz/8 = 720 kbps
Average error = 0%
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
1 bit = base clock × 16*
7.3725 MHz
5 6 7 8
7
Average transfer rate = 7.3725 MHz/16 = 460.784 kbps
Average error = -0.004%
4
6
1 bit = base clock × 8*
3
3
8
Note: * As the base clock synchronization varies, so does the length of one bit.
(average)
8 MHz × (18/25) = 5.76 MHz
16 MHz/2 = 8 MHz
5
8 MHz
Base clock with 720 kbps average transfer rate
(average)
8 MHz × (47/51) = 7.3725 MHz
16 MHz/2 = 8 MHz
7
1.8431 MHz
5 6 7 8
6
Average transfer rate = 1.8431 MHz/16 = 115.196 kbps
Average error = -0.004%
4
2 MHz
Base clock with 460.784 kbps average transfer rate
(average)
2 MHz × (47/51) = 1.8431 MHz
16 MHz/8 = 2 MHz
Base clock
Base clock with 115.196 kbps average transfer rate
When φ = 16 MHz
Section 12 Serial Communication Interface (SCI)
Figure 12.4 Examples of Base Clock when Average Transfer Rate Is Selected (2)
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Section 12 Serial Communication Interface (SCI)
12.2.11 Module Stop Control Register B (MSTPCRB)
Bit
:
7
6
5
4
3
2
0
1
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
Initial value :
R/W
:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRB is an 8-bit readable/writable register that performs module stop mode control.
When one of bits MSTPB7 to MSTPB5 is set to 1, SCI0, SCI1, or SCI2 respectively, stops
operation at the end of the bus cycle, and enters module stop mode. For details, see section 17.5,
Module Stop Mode.
MSTPCRB is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Module Stop (MSTPB7): Specifies the SCI0 module stop mode.
Bit 7
MSTPB7
Description
0
SCI0 module stop mode is cleared
1
SCI0 module stop mode is set
(Initial value)
Bit 6—Module Stop (MSTPB6): Specifies the SCI1 module stop mode.
Bit 6
MSTPB6
Description
0
SCI1 module stop mode is cleared
1
SCI1 module stop mode is set
(Initial value)
Bit 5—Module Stop (MSTPB5): Specifies the SCI2 module stop mode.
Bit 5
MSTPB5
Description
0
SCI2 module stop mode is cleared
1
SCI2 module stop mode is set
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(Initial value)
Section 12 Serial Communication Interface (SCI)
12.3
Operation
12.3.1
Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and clocked synchronous mode in which
synchronization is achieved with clock pulses.
Selection of asynchronous or clocked synchronous mode and the transmission format is made
using SMR as shown in table 12.8. The SCI clock is determined by a combination of the C/A bit
in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 12.9.
(1) Asynchronous Mode
• Data length: Choice of 7 or 8 bits
• Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the
combination of these parameters determines the transfer format and character length)
• Detection of framing, parity, and overrun errors, and breaks, during reception
• Choice of internal or external clock as SCI clock source
⎯ When internal clock is selected:
The SCI operates on the baud rate generator clock and a clock with the same frequency as
the bit rate can be output
⎯ When external clock is selected:
A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate
generator is not used)
(2) Clocked Synchronous Mode
• Transfer format: Fixed 8-bit data
• Detection of overrun errors during reception
• Choice of internal or external clock as SCI clock source
⎯ When internal clock is selected:
The SCI operates on the baud rate generator clock and a serial clock is output off-chip
⎯ When external clock is selected:
The on-chip baud rate generator is not used, and the SCI operates on the input serial clock
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Section 12 Serial Communication Interface (SCI)
Table 12.8 SMR Settings and Serial Transfer Format Selection
SMR Settings
SCI Transfer Format
Bit 7
Bit 6
Bit 2
Bit 5
Bit 3
C/A
CHR
MP
PE
STOP
Mode
0
0
0
0
0
Asynchronous
mode
1
1
Data
Length
Multi
Processor
Bit
Parity
Bit
Stop Bit
Length
8-bit data
No
No
1 bit
Yes
1 bit
2 bits
0
1
1
0
2 bits
0
7-bit data
No
1
1
0
—
0
—
1
—
0
—
1
—
—
2 bits
Yes
1
0
1
1
1
—
—
1 bit
1 bit
2 bits
Asynchronous
mode (multiprocessor format)
8-bit data
Yes
No
1 bit
2 bits
7-bit data
1 bit
2 bits
Clocked
synchronous mode
8-bit data
No
None
Table 12.9 SMR and SCR Settings and SCI Clock Source Selection
SMR
SCR Setting
SCI Transmit/Receive Clock
Bit 7
Bit 1
Bit 0
C/A
CKE1
CKE0
Mode
0
0
0
Asynchronous
mode
1
1
0
Clock
Source
SCK Pin Function
Internal
SCI does not use SCK pin
Outputs clock with same frequency as bit
rate
External
Inputs clock with frequency of 16 times
the bit rate
Internal
Outputs serial clock
External
Inputs serial clock
1
1
0
0
1
1
Clocked
synchronous
mode
0
1
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Section 12 Serial Communication Interface (SCI)
Table 12.10 SMR0, SCR0, SEMR0 Settings and SCI Clock Source Selection (SCI0 Only)
SMR0
SCR0 Setting
SEMR0 Setting
SCI Transmit/Receive Clock
Bit 7
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
C/A
CKE1
CKE0
ACS2
ACS1
ACS0
Mode
Clock Source
SCK Pin Function
0
0
0
*
*
*
Asynchronous
mode
Internal
SCI does not use SCK
pin
1
1
*
Outputs clock with some
frequency as bit rate
0
0
1
1
0
1
1
0
0
1
1
0
*
*
0
External
1
Average transfer SCI does not use SCK
pin
rate generator
(115.152 kbps
at 10.667 MHz)
0
Average transfer SCI does not use SCK
pin
rate generator
(460.606 kbps
at 10.667 MHz)
1
—
—
0
TPU (AND of
T10CA1 and
T10CA2)
SCI does not use SCK
pin
1
Average transfer SCI does not use SCK
pin
rate generator
(115.196 kbps
at 16 MHz)
0
Average transfer SCI does not use SCK
pin
rate generator
(460.784 kbps
at 16 MHz)
1
Average transfer SCI does not use SCK
pin
rate generator
(720 kbps at
16 MHz)
*
Clocked
Internal
synchronous
mode
External
Inputs clock with
frequency of 16 or 8
times the bit rate
Outputs serial clock
Input serial clock
1
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Section 12 Serial Communication Interface (SCI)
12.3.2
Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and stop bits indicating the end of communication. Serial communication
is thus carried out with synchronization established on a character-by-character basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 12.5 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally stop bits (high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the
length of one bit, so that the transfer data is latched at the center of each bit.
When the ABCS bit in SEMR0 is set to 1, SCI0 samples the data on the 4th pulse of a clock with a
frequency of 8 times the length of one bit.
Idle state
(mark state)
1
Serial
data
LSB
0
D0
1
MSB
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
0/1
Parity
bit
1 bit,
or none
1
1
Stop bit
1 or
2 bits
One unit of transfer data (character or frame)
Figure 12.5 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
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Section 12 Serial Communication Interface (SCI)
(1) Data Transfer Format
Table 12.11 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting.
Table 12.11 Serial Transfer Formats (Asynchronous Mode)
SMR Settings
Serial Transfer Format and Frame Length
CHR
PE
MP
STOP
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
Legend:
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
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Section 12 Serial Communication Interface (SCI)
(2) Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table
12.9.
When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate
used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 12.6.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 12.6 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode)
(3) Data Transfer Operations
(a) SCI initialization (asynchronous mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
When an external clock is used the clock should not be stopped during operation, including
initialization, since operation is uncertain.
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Section 12 Serial Communication Interface (SCI)
Figure 12.7 shows a sample SCI initialization flowchart.
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if an
external clock is used.
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE* bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
<Transfer completion>
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
[4]
Note: * The RE bit must be set when
the RxD pin is in the 1 state. If
the RE bit is set t 1 with the
RxD pin in the 0 state, this
event may be mistakenly
recognized as a start bit.
Figure 12.7 Sample SCI Initialization Flowchart
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Section 12 Serial Communication Interface (SCI)
(b) Serial data transmission (asynchronous mode)
Figure 12.8 shows a sample flowchart for serial transmission.
The following procedure should be used for serial data transmission.
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
No
TDRE = 1
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes
[3]
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
Yes
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
<End>
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[4]
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC or
DTC* is activated by a transmit
data empty interrupt (TXI) request,
and date is written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Note: * The TDRE flag check and clear
operations are performed
automatically
by DTC only when the DTC
DISEL bit is 0 and furthermore
the transfer counter is not 0.
Therefore the CPU must clear
the TDRE flag when either
DISEL is 1 or when DISEL is 0
and furthermore the transfer
counter is 0.
Figure 12.8 Sample Serial Transmission Flowchart
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Section 12 Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below.
[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
The serial transmit data is sent from the TxD pin in the following order.
[a] Start bit:
One 0-bit is output.
[b] Transmit data:
8-bit or 7-bit data is output in LSB-first order.
[c] Parity bit or multiprocessor bit:
One parity bit (even or odd parity), or one multiprocessor bit is output.
A format in which neither a parity bit nor a multiprocessor bit is output can also be
selected.
[d] Stop bit(s):
One or two 1-bits (stop bits) are output.
[e] Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
[3] The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent,
and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
“mark state” is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at
this time, a TEI interrupt request is generated.
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Section 12 Serial Communication Interface (SCI)
Figure 12.9 shows an example of the operation for transmission in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and
request generated TDRE flag cleared to 0 in
TXI interrupt service routine
TXI interrupt
request generated
TEI interrupt
request generated
1 frame
Figure 12.9 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev.4.00 Sep. 18, 2008 Page 496 of 872
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Section 12 Serial Communication Interface (SCI)
(c) Serial data reception (asynchronous mode)
Figures 12.10 and 12.11 show a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
Initialization
[1]
Start reception
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error processing and
break detection:
Read ORER, PER, and
If a receive error occurs, read the
[2]
FER flags in SSR
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
Yes
processing, ensure that the
PER ∨ FER ∨ ORER = 1
ORER, PER, and FER flags are
[3]
all cleared to 0. Reception cannot
No
Error processing
be resumed if any of these flags
(Continued on next page) are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
[4]
Read RDRF flag in SSR
the input port corresponding to
the RxD pin.
No
RDRF = 1
[4] SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
[5] Serial reception continuation
procedure:
To continue serial reception,
Yes
before the stop bit for the current
frame is received, read the
Clear RE bit in SCR to 0
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
<End>
flag is cleared automatically
when DMAC or DTC* is
Note: * The RDRF flag is cleared automatically by DTC
activated by an RXI interrupt and
only when the DTC DISEL bit is 0 and
the RDR value is read.
furthermore the transfer counter is not 0.
Therefore the CPU must clear the RDRF flag
when either DISEL is 1 or when DISEL is 0 and
furthermore the transfer counter is 0.
All data received?
[5]
Figure 12.10 Sample Serial Reception Data Flowchart (1)
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Section 12 Serial Communication Interface (SCI)
[3]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
No
Break?
Yes
Framing error processing
Clear RE bit in SCR to 0
No
PER = 1
Yes
Parity error processing
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 12.11 Sample Serial Reception Data Flowchart (2)
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Section 12 Serial Communication Interface (SCI)
In serial reception, the SCI operates as described below.
[1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal
synchronization and starts reception.
[2] The received data is stored in RSR in LSB-to-MSB order.
[3] The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks.
[a] Parity check:
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/E bit in SMR.
[b] Stop bit check:
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
[c] Status check:
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred from RSR to RDR.
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
RDR.
If a receive error* is detected in the error check, the operation is as shown in table 12.12.
Note: * Subsequent receive operations cannot be performed when a receive error has occurred.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be
cleared to 0.
[4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive error interrupt (ERI) request is generated.
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Section 12 Serial Communication Interface (SCI)
Table 12.12 Receive Errors and Conditions for Occurrence
Receive Error
Abbreviation
Occurrence Condition
Data Transfer
Overrun error
ORER
When the next data reception is Receive data is not
completed while the RDRF flag transferred from RSR to
RDR.
in SSR is set to 1
Framing error
FER
When the stop bit is 0
Parity error
PER
When the received data differs Receive data is transferred
from the parity (even or odd) set from RSR to RDR.
in SMR
Receive data is transferred
from RSR to RDR.
Figure 12.12 shows an example of the operation for reception in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
RDRF
FER
RXI interrupt
request
generated
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
ERI interrupt request
generated by framing
error
1 frame
Figure 12.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
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Section 12 Serial Communication Interface (SCI)
12.3.3
Multiprocessor Communication Function
The multiprocessor communication function performs serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous
mode. Use of this function enables data transfer to be performed among a number of processors
sharing transmission lines.
When multiprocessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two component cycles: an ID transmission cycle
which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used
to differentiate between the ID transmission cycle and the data transmission cycle.
The transmitting station first sends the ID of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added.
The receiving station skips the data until data with a 1 multiprocessor bit is sent.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this
way, data communication is carried out among a number of processors.
Figure 12.13 shows an example of inter-processor communication using the multiprocessor
format.
(1) Data Transfer Format
There are four data transfer formats.
When the multiprocessor format is specified, the parity bit specification is invalid.
For details, see table 12.11.
(2) Clock
See the section on asynchronous mode.
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Section 12 Serial Communication Interface (SCI)
Transmitting
station
Serial transmission line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'AA
H'01
(MPB = 1)
ID transmission cycle =
receiving station
specification
(MPB = 0)
Data transmission cycle =
Data transmission to
receiving station specified by ID
Legend:
MPB: Multiprocessor bit
Figure 12.13 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
(3) Data Transfer Operations
(a) Multiprocessor serial data transmission
Figure 12.14 shows a sample flowchart for multiprocessor serial data transmission.
The following procedure should be used for multiprocessor serial data transmission.
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Section 12 Serial Communication Interface (SCI)
[1] [1] SCI initialization:
Initialization
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
Yes
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
[3]
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DMAC or DTC* is activated by a
transmit data empty interrupt
(TXI) request, and data is written
to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
[4]
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Yes
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
<End>
Note: * The TDRE flag is cleared
automatically by DTC only
when the DTC DISEL bit is 0
and furthermore the transfer
counter is not 0. Therefore
the CPU must clear the
TDRE flag when either DISEL
is 1 or when DISEL is 0 and
furthermore the transfer
counter is 0.
Figure 12.14 Sample Multiprocessor Serial Transmission Flowchart
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Section 12 Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below.
[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
The serial transmit data is sent from the TxD pin in the following order.
[a] Start bit:
One 0-bit is output.
[b] Transmit data:
8-bit or 7-bit data is output in LSB-first order.
[c] Multiprocessor bit
One multiprocessor bit (MPBT value) is output.
[d] Stop bit(s):
One or two 1-bits (stop bits) are output.
[e] Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
[3] The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and
then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this
time, a transmission end interrupt (TEI) request is generated.
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Section 12 Serial Communication Interface (SCI)
Figure 12.15 shows an example of SCI operation for transmission using the multiprocessor format.
1
Start
bit
0
Multiprocessor Stop
bit
bit
Data
D0
D1
D7
0/1
1
Start
bit
0
Multiproces- Stop
1
sor bit bit
Data
D0
D1
D7
0/1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
request generated
Data written to TDR
and TDRE flag cleared to
0 in TXI interrupt service
routine
TXI interrupt
request generated
TEI interrupt
request generated
1 frame
Figure 12.15 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
(b) Multiprocessor serial data reception
Figures 12.16 and 12.17 show a sample flowchart for multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
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Section 12 Serial Communication Interface (SCI)
Initialization
[1]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2]
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
Start reception
Read MPIE bit in SCR
Read ORER and FER flags in SSR
FER ∨ ORER = 1
[3] SCI status check, ID reception
and comparison:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
compare it with this station’s ID.
If the data is not this station’s ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0.
If the data is this station’s ID,
clear the RDRF flag to 0.
Yes
No
Read RDRF flag in SSR
[3]
No
RDRF = 1
Yes
[4] SCI status check and data
reception:
Read SSR and check that the
RDRF flag is set to 1, then read
the data in RDR.
Read receive data in RDR
No
This station’s ID?
Yes
[5] Receive error processing and
break detection:
If a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After
performing the appropriate error
processing, ensure that the
ORER and FER flags are all
cleared to 0.
Reception cannot be resumed if
either of these flags is set to 1.
In the case of a framing error, a
break can be detected by reading
the RxD pin value.
Read ORER and FER flags in SSR
FER ∨ ORER = 1
Yes
No
Read RDRF flag in SSR
[4]
No
RDRF = 1
Yes
Read receive data in RDR
No
All data received?
[5]
Error processing
Yes
Clear RE bit in SCR to 0
(Continued on
next page)
<End>
Figure 12.16 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 12 Serial Communication Interface (SCI)
[5]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCR to 0
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 12.17 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 12 Serial Communication Interface (SCI)
Figure 12.18 shows an example of SCI operation for multiprocessor format reception.
1
Start
bit
0
Data (ID1)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data1)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
RXI interrupt
request
(multiprocessor
interrupt)
generated
MPIE = 0
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
service routine
If not this station’s ID, RXI interrupt request is
MPIE bit is set to 1
not generated, and RDR
again
retains its state
(a) Data does not match station’s ID
1
Start
bit
0
Data (ID2)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data2)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID2
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt service routine
(b) Data matches station’s ID
Figure 12.18 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Data2
MPIE bit set to 1
again
Section 12 Serial Communication Interface (SCI)
12.3.4
Operation in Clocked Synchronous Mode
In clocked synchronous mode, data is transmitted or received in synchronization with clock
pulses, making it suitable for high-speed serial communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication by use of a common clock. Both the transmitter and the receiver also have a
double-buffered structure, so that data can be read or written during transmission or reception,
enabling continuous data transfer.
Figure 12.19 shows the general format for clocked synchronous serial communication.
One unit of transfer data (character or frame)
*
*
Serial
clock
LSB
Serial
data
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Don’t care
Note: * High except in continuous transfer
Figure 12.19 Data Format in Synchronous Communication
In clocked synchronous serial communication, data on the transmission line is output from one
falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of
the serial clock.
In clocked serial communication, one character consists of data output starting with the LSB and
ending with the MSB. After the MSB is output, the transmission line holds the MSB state.
In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the
serial clock.
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Section 12 Serial Communication Interface (SCI)
(1) Data Transfer Format
A fixed 8-bit data format is used.
No parity or multiprocessor bits are added.
(2) Clock
Either an internal clock generated by the on-chip baud rate generator or an external serial clock
input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1
and CKE0 bits in SCR. For details of SCI clock source selection, see table 12.9.
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive operations are performed, however, the
serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to
perform receive operations in units of one character, you should select an external clock as the
clock source.
(3) Data Transfer Operations
(a) SCI initialization (clocked synchronous mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Figure 12.20 shows a sample SCI initialization flowchart.
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Section 12 Serial Communication Interface (SCI)
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
[2] Set the data transfer format in SMR
and SCMR.
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
Wait
No
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
[4]
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
Figure 12.20 Sample SCI Initialization Flowchart
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Section 12 Serial Communication Interface (SCI)
(b) Serial data transmission (clocked synchronous mode)
Figure 12.21 shows a sample flowchart for serial transmission.
The following procedure should be used for serial data transmission.
[1]
Initialization
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SSR
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC* is activated by a transmit data
empty interrupt (TXI) request, and data
is written to TDR.
No
TEND = 1
Yes
Clear TE bit in SCR to 0
<End>
Note: * The TDRE flag is cleared
automatically by DTC only when
the DTC DISEL bit is 0 and
furthermore the transfer counter is
not 0. Therefore the CPU must
clear the TDRE flag when either
DISEL is 1 or when DISEL is 0 and
furthermore the transfer counter is
0.
Figure 12.21 Sample Serial Transmission Flowchart
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Section 12 Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below.
[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI)
is generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an
external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with
the MSB (bit 7).
[3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the
TxD pin maintains its state.
If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.
[4] After completion of serial transmission, the SCK pin is fixed.
Figure 12.22 shows an example of SCI operation in transmission.
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Section 12 Serial Communication Interface (SCI)
Transfer direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request generated
Data written to TDR
TXI interrupt
and TDRE flag
request generated
cleared to 0 in TXI
interrupt service routine
TEI interrupt
request generated
1 frame
Figure 12.22 Example of SCI Operation in Transmission
(c) Serial data reception (clocked synchronous mode)
Figure 12.23 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
When changing the operating mode from asynchronous to clocked synchronous, be sure to check
that the ORER, PER, and FER flags are all cleared to 0.
The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive
operations will be possible.
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Section 12 Serial Communication Interface (SCI)
[1]
Initialization
Start reception
[2]
Read ORER flag in SSR
Yes
[3]
ORER = 1
No
Error processing
(Continued below)
Read RDRF flag in SSR
[4]
No
RDRF = 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[1]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
processing, clear the ORER flag
to 0. Transfer cannot be resumed
if the ORER flag is set to 1.
[4] SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DMAC or
DTC* is activated by a receive
data full interrupt (RXI) request
and the RDR value is read.
<End>
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
<End>
Note: * The RDRF flag is cleared
automatically by DTC only
when the DTC DISEL bit is 0
and furthermore the transfer
counter is not 0. Therefore
the CPU must clear the
RDRF flag when either
DISEL is 1 or when DISEL is
0 and furthermore the
transfer counter is 0.
Figure 12.23 Sample Serial Reception Flowchart
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Section 12 Serial Communication Interface (SCI)
In serial reception, the SCI operates as described below.
[1] The SCI performs internal initialization in synchronization with serial clock input or output.
[2] The received data is stored in RSR in LSB-to-MSB order.
After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be
transferred from RSR to RDR.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a
receive error is detected in the error check, the operation is as shown in table 12.12.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
[3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error
interrupt (ERI) request is generated.
Figure 12.24 shows an example of SCI operation in reception.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt request
generated
RDR data read and
RDRF flag cleared to 0
in RXI interrupt service
routine
RXI interrupt request
generated
ERI interrupt request
generated by overrun
error
1 frame
Figure 12.24 Example of SCI Operation in Reception
(d) Simultaneous serial data transmission and reception (clocked synchronous mode)
Figure 12.25 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations.
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Section 12 Serial Communication Interface (SCI)
Initialization
[1] SCI initialization:
[1]
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
Start transmission/reception
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0
to 1 can also be identified by a TXI
interrupt.
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
processing, clear the ORER flag to
0. Transmission/reception cannot be
resumed if the ORER flag is set to
1.
Read ORER flag in SSR
ORER = 1
No
Read RDRF flag in SSR
Yes
[3]
Error processing
[4] SCI status check and receive data
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[4]
No
RDRF = 1
Yes
[5] Serial transmission/reception
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
<End>
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to
0, then set both these bits to 1 simultaneously.
* The TDRE flag and RDRF flag clear operations are performed
automatically by DTC only when the corresponding DTC transfer
DISEL bit is 0 and furthermore the transfer counter is not 0.
Therefore the CPU must clear the corresponding flag when
either the corresponding DTC transfer DISEL is 1 or when the
corresponding DTC transfer DISEL is 0 and furthermore the
transfer counter is 0.
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC is activated by a transmit data
empty interrupt (TXI) request and
data is written to TDR. Also, the
RDRF flag is cleared automatically
when the DMAC or DTC* is
activated by a receive data full
interrupt (RXI) request and the RDR
value is read.
Figure 12.25 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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Section 12 Serial Communication Interface (SCI)
12.4
SCI Interrupts
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request. Table 12.13 shows the interrupt sources and their relative priorities. Individual interrupt
sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of
interrupt request is sent to the interrupt controller independently.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DMAC or
DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is
performed by the DMAC or DTC*. The DMAC or DTC cannot be activated by a TEI interrupt
request.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DMAC or DTC to perform data transfer. The RDRF flag is cleared to 0 automatically
when data transfer is performed by the DMAC or DTC*. The DMAC or DTC cannot be activated
by an ERI interrupt request.
Note : * The flag is cleared when DISEL is 0 and furthermore the transfer counter is not 0.
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Section 12 Serial Communication Interface (SCI)
Table 12.13 SCI Interrupt Sources
Channel
Interrupt
Source
Description
DMAC
Activation
DTC
Activation
Priority*
0
ERI
Interrupt due to receive error
(ORER, FER, or PER)
Not possible
Not possible
High
RXI
Interrupt due to receive data full
state (RDRF)
Possible
Possible
TXI
Interrupt due to transmit data
empty state (TDRE)
Possible
Possible
TEI
Interrupt due to transmission
end (TEND)
Not possible
Not possible
ERI
Interrupt due to receive error
(ORER, FER, or PER)
Not possible
Not possible
RXI
Interrupt due to receive data full
state (RDRF)
Possible
Possible
TXI
Interrupt due to transmit data
empty state (TDRE)
Possible
Possible
TEI
Interrupt due to transmission
end (TEND)
Not possible
Not possible
ERI
Interrupt due to receive error
(ORER, FER, or PER)
Not possible
Not possible
RXI
Interrupt due to receive data full
state (RDRF)
Possible
Not possible
TXI
Interrupt due to transmit data
empty state (TDRE)
Possible
Not possible
TEI
Interrupt due to transmission
end (TEND)
Not possible
Not possible
1
2
Low
Note: * This table shows the initial state immediately after a reset. Relative priorities among
channels can be changed by means of the interrupt controller.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance,
with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be
accepted in this case.
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Section 12 Serial Communication Interface (SCI)
12.5
Usage Notes
The following points should be noted when using the SCI.
(1) Module Stop Mode Settings
The SCI module operation disabled/enabled state can be set with the module stop control register.
The initial value of this register sets the SCI module to the stopped state. Register access becomes
possible when module stop mode is cleared. See section 17, Power-Down Modes, for details.
(2) Relation between Writes to TDR and the TDRE Flag
The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.
(3) Operation when Multiple Receive Errors Occur Simultaneously
If a number of receive errors occur at the same time, the state of the status flags in SSR is as
shown in table 12.14. If there is an overrun error, data is not transferred from RSR to RDR, and
the receive data is lost.
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Section 12 Serial Communication Interface (SCI)
Table 12.14 State of SSR Status Flags and Transfer of Receive Data
SSR Status Flags
RDRF
ORER
FER
PER
Receive Data Transfer
RSR to RDR
Receive Error Status
1
1
0
0
X
Overrun error
0
0
1
0
Framing error
0
0
0
1
Parity error
1
1
1
0
X
Overrun error + framing error
1
1
0
1
X
Overrun error + parity error
0
0
1
1
1
1
1
1
Framing error + parity error
X
Overrun error + framing error +
parity error
Legend:
: Receive data is transferred from RSR to RDR.
X: Receive data is not transferred from RSR to RDR.
(4) Break Detection and Processing (Asynchronous Mode Only)
When framing error (FER) detection is performed, a break can be detected by reading the RxD pin
value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set,
and the parity error flag (PER) may also be set.
Note that, since the SCI continues the receive operation after receiving a break, even if the FER
flag is cleared to 0, it will be set to 1 again.
(5) Sending a Break (Asynchronous Mode Only)
The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by
DR and DDR. This can be used to send a break.
Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced
by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1).
Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1.
To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission
state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.
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Section 12 Serial Communication Interface (SCI)
(6) Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
(7) Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer
rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
basic clock. This is illustrated in figure 12.26.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal basic
clock
Receive data
(RxD)
Start bit
D0
Synchronization
sampling timing
Data sampling
timing
Figure 12.26 Receive Data Sampling Timing in Asynchronous Mode
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D1
Section 12 Serial Communication Interface (SCI)
Thus the reception margin in asynchronous mode is given by formula (1) below.
1
M = | (0.5 –
Where M:
N:
D:
L:
F:
2N
) – (L – 0.5) F –
| D – 0.5 |
N
(1 + F) | × 100%
........... Formula (1)
Reception margin (%)
Ratio of bit rate to clock (N = 16)
Clock duty (D = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by
formula (2) below.
When D = 0.5 and F = 0,
M = (0.5 –
1
2 × 16
) × 100%
= 46.875%
........... Formula (2)
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
(8) Restrictions on Use of DMAC or DTC
(a) When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 φ clock cycles after TDR is updated by the DMAC or DTC. Misoperation
may occur if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 12.27)
(b) When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant
SCI reception end interrupt (RXI).
(c) During data transfers, flags are cleared automatically by DTC only when the DTC DISEL bit is
0 and furthermore the transfer counter is not 0. Therefore the CPU must clear the flags when
either DISEL is 1 or when DISEL is 0 and furthermore the transfer counter is 0. In particular,
note that during transmission, data will not be transmitted correctly unless the CPU clears the
TDRE flag.
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Section 12 Serial Communication Interface (SCI)
SCK
t
TDRE
LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
D7
Note: When operating on an external clock, set t > 4 clocks.
Figure 12.27 Example of Clocked Synchronous Transmission by DTC
(9) Operation in Case of Mode Transition
(a) Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop
mode, software standby mode, or subsleep mode transition. TSR, TDR, and SSR are reset. The
output pin states in module stop mode, software standby mode, or subsleep mode depend on the
port settings, and becomes high-level output after the relevant mode is cleared. If a transition is
made during transmission, the data being transmitted will be undefined. When transmitting
without changing the transmit mode after the relevant mode is cleared, transmission can be started
by setting TE to 1 again, and performing the following sequence: SSR read -> TDR write ->
TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the
procedure must be started again from initialization. Figure 12.28 shows a sample flowchart for
mode transition during transmission. Port pin states are shown in figures 12.29 and 12.30.
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition
from transmission by DTC transfer to module stop mode, software standby mode, or subsleep
mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting
TE and TIE to 1 will set the TXI flag and start DTC transmission.
(b) Reception
Receive operation should be stopped (by clearing RE to 0) before making a module stop mode,
software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR,
and SSR are reset. If a transition is made without stopping operation, the data being received will
be invalid.
To continue receiving without changing the reception mode after the relevant mode is cleared, set
RE to 1 before starting reception. To receive with a different receive mode, the procedure must be
started again from initialization.
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Section 12 Serial Communication Interface (SCI)
Figure 12.31 shows a sample flowchart for mode transition during reception.
<Transmission>
No
All data
transmitted?
[1]
Yes
Read TEND flag in SSR
No
TEND = 1
Yes
TE = 0
[2] If TIE and TEIE are set to 1, clear
them to 0 in the same way.
[2]
Transition to software
standby mode, etc.
[3]
Exit from software
standby mode, etc.
Change
operating mode?
[1] Data being transmitted is
interrupted. After exiting software
standby mode, etc., normal CPU
transmission is possible by setting
TE to 1, reading SSR, writing TDR,
and clearing TDRE to 0, but note
that if the DTC has been activated,
the remaining data in DTCRAM will
be transmitted when TE and TIE
are set to 1.
[3] Includes module stop mode, watch
mode, subactive mode, and
subsleep mode.
No
Yes
Initialization
TE = 1
<Start of transmission>
Figure 12.28 Sample Flowchart for Mode Transition during Transmission
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Section 12 Serial Communication Interface (SCI)
End of
transmission
Start of transmission
Transition
to software
standby
Exit from
software
standby
TE bit
Port input/output
SCK output pin
TxD output pin
Port input/output
High output
Port
Start
Stop
Port input/output
Port
SCI TxD output
High output
SCI TxD
output
Figure 12.29 Asynchronous Transmission Using Internal Clock
Start of transmission
End of
transmission
Transition
to software
standby
Exit from
software
standby
TE bit
Port input/output
SCK output pin
TxD output pin Port input/output
Last TxD bit held
Marking output
Port
SCI TxD output
Port input/output
Port
Note: * Initialized by software standby.
Figure 12.30 Synchronous Transmission Using Internal Clock
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High output*
SCI TxD
output
Section 12 Serial Communication Interface (SCI)
<Reception>
Read RDRF flag in SSR
RDRF = 1
No
[1]
[1] Receive data being received
becomes invalid.
[2]
[2] Includes module stop mode, watch
mode, subactive mode, and
subsleep mode.
Yes
Read receive data in RDR
RE = 0
Transition to software
standby mode, etc.
Exit from software
standby mode, etc.
Change
operating mode?
No
Yes
Initialization
RE = 1
<Start of reception>
Figure 12.31 Sample Flowchart for Mode Transition during Reception
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Section 12 Serial Communication Interface (SCI)
(10) Switching from SCK Pin Function to Port Pin Function
(a) Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0,
CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
1. End of serial data transmission
2. TE bit = 0
3. C/A bit = 0 ... switchover to port output
4. Occurrence of low-level output (see figure 12.32)
Half-cycle low-level output
SCK/port
1. End of transmission
Data
TE
Bit 6
4. Low-level output
Bit 7
2. TE = 0
C/A
3. C/A = 0
CKE1
CKE0
Figure 12.32 Operation when Switching from SCK Pin Function to Port Pin Function
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Section 12 Serial Communication Interface (SCI)
(b) Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily
places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an
external circuit.
With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following
settings in the order shown.
1. End of serial data transmission
2. TE bit = 0
3. CKE1 bit = 1
4. C/A bit = 0 ... switchover to port output
5. CKE1 bit = 0
High-level outputTE
SCK/port
1. End of transmission
Data
TE
Bit 6
Bit 7
2. TE = 0
4. C/A = 0
C/A
3. CKE1 = 1
CKE1
5. CKE1 = 0
CKE0
Figure 12.33 Operation when Switching from SCK Pin Function to Port Pin Function
(Example of Preventing Low-Level Output)
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Section 12 Serial Communication Interface (SCI)
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Section 13 D/A Converter
Section 13 D/A Converter
13.1
Overview
The H8S/2214 Group includes a one-channel D/A converter.
13.1.1
Features
D/A converter features are listed below
• 8-bit resolution
• One output channel
• Maximum conversion time of 10 µs (with 20 pF load)
• Output voltage of 0 V to Vref
• D/A output hold function in software standby mode
• Module stop mode can be set
⎯ As the initial setting, D/A converter operation is halted. Register access is enabled by
exiting module stop mode.
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Section 13 D/A Converter
13.1.2
Block Diagram
Module data bus
Bus interface
Figure 13.1 shows a block diagram of the D/A converter.
8-bit D/A
DA0
DACR
AVCC
DADR0
Vref
AVSS
Control circuit
Figure 13.1 Block Diagram of D/A Converter
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Internal data bus
Section 13 D/A Converter
13.1.3
Pin Configuration
Table 13.1 summarizes the input and output pins of the D/A converter.
Table 13.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Analog power pin
AVCC
Input
Analog power source
Analog ground pin
AVSS
Input
Analog ground and reference voltage
Analog output pin 0
DA0
Output
Channel 0 analog output
Reference voltage pin
Vref
Input
Analog reference voltage
13.1.4
Register Configuration
Table 13.2 summarizes the registers of the D/A converter.
Table 13.2 D/A Converter Registers
Name
Abbreviation
R/W
Initial Value
Address*
D/A data register 0
DADR0
R/W
H'00
H'FDAC
D/A control register
DACR
R/W
H'1F
H'FDAE
Module stop control register C
MSTPCRC
R/W
H'FF
H'FDEA
Note: * Lower 16 bits of the address.
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Section 13 D/A Converter
13.2
Register Descriptions
13.2.1
D/A Data Register 0 (DADR0)
:
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
R/W
:
D/A data register 0 (DADR0) is an 8-bit readable/writable registers that stores data for conversion.
Whenever output is enabled, the value in the D/A data register is converted and output from the
analog output pin.
DADR0 is initialized to H'00 by a reset and in hardware standby mode.
13.2.2
Bit
D/A Control Register (DACR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
—
DAOE0
—
—
—
—
—
—
0
0
0
1
1
1
1
1
R/W
R/W
R/W
—
—
—
—
—
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a reset and in hardware standby mode.
Bit 7—Reserved: Only 0 should be written to this bit.
Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.
Bit 6
DAOE0
Description
0
Analog output DA0 is disabled
1
Channel 0 D/A conversion is enabled; analog output DA0 is enabled
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(Initial value)
Section 13 D/A Converter
Bit 5—Reserved: Only 0 should be written to this bit.
If the H8S/2214 Group enters software standby mode when D/A conversion is enabled, the D/A
output is held and the analog power current is the same as during D/A conversion. When it is
necessary to reduce the analog power current in software standby mode, clear the DAOE0 bit to 0
to disable D/A output.
Bits 4 to 0—Reserved: Read-only bits, always read as 1.
13.2.3
Bit
Module Stop Control Register C (MSTPCRC)
:
7
6
5
4
3
2
0
1
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value :
R/W
:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPC5 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus
cycle and a transition is made to module stop mode. Registers cannot be read or written to in
module stop mode. For details, see section 17.5, Module Stop Mode.
MSTPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 5—Module Stop (MSTPC5): Specifies the D/A converter module stop mode.
Bit 5
MSTPC5
Description
0
D/A converter module stop mode cleared
1
D/A converter module stop mode set
(Initial value)
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Section 13 D/A Converter
13.3
Operation
D/A conversion is performed continuously while enabled by DACR. If either DADR0 is written
to, the new data is immediately converted. The conversion result is output by setting the
corresponding DAOE0 bit to 1.
The operation example described in this section concerns D/A conversion on channel 0. Figure
13.2 shows the timing of this operation.
[1] Write the conversion data to DADR0.
[2] Set the DAOE0 bit in DACR to 1. D/A conversion is started and the DA0 pin becomes an
output pin. The conversion result is output after the conversion time has elapsed. The output
value is expressed by the following formula:
DADR contents
× Vref
256
The conversion results are output continuously until DADR0 is written to again or the DAOE0
bit is cleared to 0.
[3] If DADR0 is written to again, the new data is immediately converted. The new conversion
result is output after the conversion time has elapsed.
[4] If the DAOE0 bit is cleared to 0, the DA0 pin becomes an input pin.
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Section 13 D/A Converter
DADR0
write cycle
DACR
write cycle
DADR0
write cycle
DACR
write cycle
φ
Address
Conversion data 1
DADR0
Conversion data 2
DAOE0
DA0
Conversion
result 2
Conversion
result 1
High-impedance state
tDCONV
tDCONV
Legend:
tDCONV: D/A conversion time
Figure 13.2 Example of D/A Converter Operation
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Section 13 D/A Converter
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Section 14 RAM
Section 14 RAM
14.1
Overview
The H8S/2214 Group has 12 kbytes of on-chip high-speed static RAM. The RAM is connected to
the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word
data. This makes it possible to perform fast word data transfer.
The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the
system control register (SYSCR).
14.1.1
Block Diagram
Figure 14.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFC000
H'FFC001
H'FFC002
H'FFC003
H'FFC004
H'FFC005
H'FFEFBE
H'FFEFBF
H'FFFFC0
H'FFFFC1
H'FFFFFE
H'FFFFFF
Figure 14.1 Block Diagram of RAM
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Section 14 RAM
14.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 14.1 shows the address and initial value of
SYSCR.
Table 14.1 RAM Register
Name
Abbreviation
R/W
Initial Value
Address*
System control register
SYSCR
R/W
H'01
H'FDE5
Note: * Lower 16 bits of the address.
14.2
Register Descriptions
14.2.1
System Control Register (SYSCR)
Bit
:
7
6
5
4
3
2
1
0
—
—
INTM1
INTM0
NMIEG
MRESE
—
RAME
Initial value :
0
0
0
0
0
0
0
1
R/W
—
—
R/W
R/W
R/W
R/W
—
R/W
:
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Rev.4.00 Sep. 18, 2008 Page 540 of 872
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(Initial value)
Section 14 RAM
14.3
Operation
When the RAME bit is set to 1, accesses to addresses H'FFC000 to H'FFEFBF and H'FFFFC0 to
H'FFFFFF in the H8S/2214 Group is directed to the on-chip RAM. When the RAME bit is cleared
to 0, the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to
and read in byte or word units. Each type of access can be performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
14.4
Usage Note
DTC register information can be located in addresses H'FFEBC0 to H'FFEFBF. When the DTC is
used, the RAME bit must not be cleared to 0.
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Section 14 RAM
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Section 15 ROM
Section 15 ROM
15.1
Overview
The H8S/2214 Group has 128 kbytes of on-chip ROM (flash memory or masked ROM). The
ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word
data in one state, making possible rapid instruction fetches and high-speed processing.
The on-chip ROM is enabled or disabled by setting the mode pins (MD2, MD1, and MD0).
The flash memory versions can be erased and programmed on-board as well as with a PROM
programmer.
15.1.1
Block Diagram
Figure 15.1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000001
H'000002
H'000003
H'01FFFE
H'01FFFF
Figure 15.1 Block Diagram of ROM
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Section 15 ROM
15.1.2
Register Configuration
The H8S/2214’s on-chip ROM is controlled by the mode pins. The register configuration is shown
in table 15.1.
Table 15.1 ROM Register
Name
Abbreviation
R/W
Initial Value
Address*
Mode control register
MDCR
R/W
Undefined
H'FDE7
Note: * Lower 16 bits of the address.
15.2
Register Descriptions
15.2.1
Mode Control Register (MDCR)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
—
MDS1
—*
MDS0
—*
R
R
Initial value :
1
0
0
0
0
MDS2
—*
R/W
—
—
—
—
—
R
:
Note: * Determined by pins MD2 to MD0.
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2214
Group.
Bit 7—Reserved: Read-only bit, always read as 1.
Bits 6 to 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to
MD0. MDS2 to MDS0 are read-only bits, and cannot be written to. The mode pin (MD2 to MD0)
input levels are latched into these bits when MDCR is read. These latches are canceled by a
power-on reset, but are retained after a manual reset.
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Section 15 ROM
15.3
Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can
be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to
the lower 8 bits. Word data must start at an even address.
The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0).
These settings are shown in table 15.2.
Table 15.2 Operating Modes and ROM Area
(F-ZTAT Version and Masked ROM Version)
Mode Pin
Operating Mode
FWE
MD2
MD1
Mode 0
0
0
0
—
Mode 1
On-Chip ROM
0
—
1
Mode 2
1
Mode 3
0
1
Mode 4
Advanced expanded mode with on-chip
ROM disabled
Mode 5
Advanced expanded mode with on-chip
ROM disabled
Mode 6
Advanced expanded mode with on-chip
ROM enabled
Mode 7
Advanced single-chip mode
Mode 8
—
1
0
0
Disabled
1
1
1
0
0
Mode 9
0
Enabled (128 kbytes)*1
1
Enabled (128 kbytes)*1
0
—
1
Mode 10
Boot mode (advanced expanded mode
with on-chip ROM enabled)*1
Mode 11
Boot mode (advanced single-chip
mode)*2
Mode 12
—
0
Enabled (128 kbytes)*2
1
Enabled (128 kbytes)*2
0
0
—
1
0
Enabled (128 kbytes)*1
1
Enabled (128 kbytes)*1
1
1
Mode 13
1
Mode 14
User program mode (advanced expanded
mode with on-chip ROM enabled)*1
Mode 15
User program mode (advanced singlechip mode)*2
Notes:
MD0
1. Apart from the fact that flash memory can be erased and programmed, operation is the same as in
advanced expanded mode with on-chip ROM enabled.
2. Apart from the fact that flash memory can be erased and programmed, operation is the same as in
advanced single-chip mode.
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Section 15 ROM
15.4
Overview of Flash Memory
15.4.1
Features
The HD64F2214 has 128 kbytes of on-chip flash memory. The features of the flash memory are
summarized below.
• Four flash memory operating modes
⎯ Program mode
⎯ Erase mode
⎯ Program-verify mode
⎯ Erase-verify mode
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can
be performed. To erase multiple blocks, each block must be erased in turn. In block erasing, 1kbyte, 8-kbyte, 16-kbyte, 28-kbyte, and 32-kbyte block units can be set as required.
• Programming/erase times
The flash memory programming time is 40 ms (typ.) for simultaneous 128-byte programming,
equivalent to 312.5 µs (typ.) per byte, and the erase time is 20 ms/block (typ.).
• Reprogramming capability
The flash memory can be reprogrammed a minimum of 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
⎯ Boot mode
⎯ User program mode
• Automatic bit rate adjustment
With data transfer in boot mode, the LSI’s bit rate can be automatically adjusted to match the
transfer bit rate of the host.
• Flash memory emulation in RAM
Flash memory programming can be emulated in real time by overlapping a part of RAM onto
flash memory.
• Protect modes
There are two protect modes, hardware and software, which allow protected status to be
designated for flash memory program/erase/verify operations.
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
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Section 15 ROM
15.4.2
Block Diagram
Internal address bus
Module bus
Internal data bus (16 bits)
FLMCR1
FLMCR2
EBR1
Bus interface/controller
Operating
mode
FWE pin
Mode pin
EBR2
RAMER
Flash memory
(128 kbytes)
Legend:
FLMCR1:
FLMCR2:
EBR1:
EBR2:
RAMER:
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM emulation register
Note: These registers are for use exclusively by the flash memory version.
Reads to the corresponding addresses in the masked ROM version will return
an undefined value, and writes to these addresses are invalid.
Figure 15.2 Block Diagram of Flash Memory
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Section 15 ROM
15.4.3
Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the
microcomputer enters an operating mode as shown in figure 15.3. Transitions between user mode
and user program mode should only be made when the CPU is not accessing the flash memory.
The boot, user program and programmer modes are provided as modes to write and erase the flash
memory.
MD1 = 1,
MD2 = 1,
FWE = 0
*1
RES = 0
User mode
(on-chip ROM
enabled)
FWE = 1
Reset state
RES = 0
MD1 = 1,
MD2 = 1,
FWE = 1
FWE = 0
RES = 0
MD1 = 1,
MD2 = 0,
FWE = 1
*2
RES = 0
Programmer
mode
*1
User
program mode
Boot mode
On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. RAM emulation possible
2. MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, PF0 = 1, PE3 = 1
Figure 15.3 Flash Memory State Transitions
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Section 15 ROM
15.4.4
On-Board Programming Modes
(1) Boot Mode
1. Initial state
The old program version or data remains written
in the flash memory. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
the H8S/2214 (originally incorporated in the chip)
is started and the programming control program
in the host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically transferred
to the RAM boot program area.
Host
Host
Programming control
program
New application
program
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
SCI
Boot program
Flash memory
RAM
RAM
Boot program area
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, total flash
memory erasure is performed, without regard to
blocks.
Programming control
program
4. Writing new application program
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into the
flash memory.
Host
Host
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
Flash memory
Boot program area
Flash memory
preprogramming
erase
Programming control
program
SCI
Boot program
RAM
Boot program area
New application
program
Programming control
program
Program execution state
Figure 15.4 Boot Mode
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Section 15 ROM
(2) User Program Mode
1. Initial state
The FWE assessment program that confirms that
user program mode has been entered, and the
program that will transfer the programming/erase
control program from flash memory to on-chip
RAM should be written into the flash memory by
the user beforehand. The programming/erase
control program should be prepared in the host or
in the flash memory.
2. Programming/erase control program transfer
When user program mode is entered, user
software confirms this fact, executes transfer
program in the flash memory, and transfers the
programming/erase control program to RAM.
Host
Host
Programming/
erase control program
New application
program
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
SCI
Boot program
RAM
Flash memory
FWE assessment
program
FWE assessment
program
Transfer program
Transfer program
Programming/
erase control program
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Host
Host
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
FWE assessment
program
SCI
Boot program
Flash memory
RAM
FWE assessment
program
Transfer program
Transfer program
Programming/
erase control program
Flash memory
erase
Programming/
erase control program
New application
program
Program execution state
Figure 15.5 User Program Mode
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Section 15 ROM
15.4.5
Flash Memory Emulation in RAM
Emulation should be performed in user mode or user program mode. When the emulation block
set in RAMER is accessed while the emulation function is being executed, data written in the
overlap RAM is read.
SCI
Flash memory
RAM
Emulation block
Overlap RAM
(emulation is performed
on data written in RAM)
Application program
Execution state
Figure 15.6 Reading Overlap RAM Data in User Mode or User Program Mode
When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and
writes should actually be performed to the flash memory.
When the programming control program is transferred to RAM, ensure that the transfer destination
and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.
Rev.4.00 Sep. 18, 2008 Page 551 of 872
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Section 15 ROM
SCI
RAM
Flash memory
Programming data
Overlap RAM
(programming data)
Application program
Programming control
program execution state
Figure 15.7 Writing Overlap RAM Data in User Program Mode
15.4.6
Differences between Boot Mode and User Program Mode
Table 15.3 Differences between Boot Mode and User Program Mode
Total erase
Boot Mode
User Program Mode
Yes
Yes
Block erase
No
Yes
Programming control program*
(2)
(1) (2) (3)
(1) Erase/erase-verify
(2) Program/program-verify
(3) Emulation
Note: * To be provided by the user, in accordance with the recommended algorithm.
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Section 15 ROM
15.4.7
Block Divisions
The flash memory is divided into two 32-kbyte blocks, one 28-kbyte block, one 16-kbyte block,
two 8-kbyte blocks, and four 1-kbyte blocks.
Address H'00000
1 kbyte × 4
28 kbytes
128 kbytes
16 kbytes
8 kbytes
8 kbytes
32 kbytes
32 kbytes
Address H'1FFFF
Figure 15.8 Flash Memory Blocks
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Section 15 ROM
15.5
Pin Configuration
The flash memory is controlled by means of the pins shown in table 15.4.
Table 15.4 Pin Configuration
Pin Name
Abbreviation
I/O
Function
Reset
RES
Input
Reset
Flash write enable
FWE
Input
Flash program/erase protection by hardware
Mode 2
MD2
Input
Sets LSI operating mode
Mode 1
MD1
Input
Sets LSI operating mode
Mode 0
MD0
Input
Sets LSI operating mode
Port F3
PF3
Input
Sets LSI operating mode when MD2 =
MD1 = MD0 = 0
Port F0
PF0
Input
Sets LSI operating mode when MD2 =
MD1 = MD0 = 0
Port 16
P16
Input
Sets LSI operating mode when MD2 =
MD1 = MD0 = 0
Port 14
P14
Input
Sets LSI operating mode when MD2 =
MD1 = MD0 = 0
Transmit data
TxD2
Output
Serial transmit data output
Receive data
RxD2
Input
Serial receive data input
Rev.4.00 Sep. 18, 2008 Page 554 of 872
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Section 15 ROM
15.6
Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 15.5.
In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER,
SCRX).
Table 15.5 Register Configuration
Initial Value
Address*
H'00*
H'FFA8
1
Register Name
Abbreviation
R/W
Flash memory control register 1
Flash memory control register 2
FLMCR1*
5
FLMCR2*
R/W*
2
R*
H'00
H'FFA9
Erase block register 1
5
EBR1*
2
R/W*
4
H'00*
H'FFAA
Erase block register 2
5
EBR2*
2
R/W*
4
H'00*
H'FFAB
RAM emulation register
5
RAMER*
R/W
H'00
H'FEDB
Serial control register X
SCRX
R/W
H'00
H'FDB4
5
2
3
Notes: 1. Lower 16 bits of the address.
2. To access these registers, set the FLSHE bit to 1 in serial control register X. Even if
FLSHE is set to 1, if the chip is in a mode in which the on-chip flash memory is
disabled, a read will return H'00 and writes are invalid. Writes are also invalid when the
FWE bit in FLMCR1 is not set to 1.
3. When a high level is input to the FWE pin, the initial value is H'80.
4. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in
FLMCR1 is not set, these registers are initialized to H'00.
5. FLMCR1, FLMCR2, EBR1, EBR2, and RAMER are 8-bit registers.
Only byte access can be used on these registers, with the access requiring two states.
These registers are for use exclusively by the flash memory version. Reads to the
corresponding addresses in the masked ROM version will return an undefined value,
and writes to these addresses are invalid.
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Section 15 ROM
15.7
Register Descriptions
15.7.1
Flash Memory Control Register 1 (FLMCR1)
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
FWE
—*
SWE1
ESU1
PSU1
EV1
PV1
E1
P1
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Determined by the state of the FWE pin.
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode for addresses H'00000 to H'1FFFF is entered by setting SWE1 bit to 1 when
FWE = 1, then setting the PV1 or EV1 bit. Program mode for addresses H'00000 to H'1FFFF is
entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the
P1 bit. Erase mode for addresses H'00000 to H'1FFFF is entered by setting SWE1 bit to 1 when
FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a
power-on reset, and in hardware standby mode and software standby mode. Its initial value is H'80
when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash
memory is disabled, a read will return H'00, and writes are invalid.
Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled when
FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when
FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 when FWE = 1, SWE1 = 1, and PSU1 = 1.
Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7
FWE
Description
0
When a low level is input to the FWE pin (hardware-protected state)
1
When a high level is input to the FWE pin
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Section 15 ROM
Bit 6—Software Write Enable Bit 1 (SWE1): Enables or disables flash memory programming
and erasing. Set this bit when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2.
Bit 6
SWE1
Description
0
Writes disabled
1
Writes enabled
(Initial value)
[Setting condition]
•
When FWE = 1
Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode. Set this bit to 1 before
setting the E1 bit in FLMCR1 to 1. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the
same time.
Bit 5
ESU1
Description
0
Erase setup cleared
1
Erase setup
(Initial value)
[Setting condition]
•
When FWE = 1 and SWE1 = 1
Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode. Set this bit to 1
before setting the P1 bit in FLMCR1 to 1. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at
the same time.
Bit 4
PSU1
Description
0
Program setup cleared
1
Program setup
(Initial value)
[Setting condition]
•
When FWE = 1 and SWE1 = 1
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Section 15 ROM
Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing. Do not set the
SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time.
Bit 3
EV1
Description
0
Erase-verify mode cleared
1
Transition to erase-verify mode
(Initial value)
[Setting condition]
•
When FWE = 1 and SWE1 = 1
Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing. Do not set
the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time.
Bit 2
PV1
Description
0
Program-verify mode cleared
1
Transition to program-verify mode
(Initial value)
[Setting condition]
•
When FWE = 1 and SWE1 = 1
Bit 1—Erase 1 (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1,
PSU1, EV1, PV1, or P1 bit at the same time.
Bit 1
E1
Description
0
Erase mode cleared
1
Transition to erase mode
(Initial value)
[Setting condition]
•
When FWE = 1, SWE1 = 1, and ESU1 = 1
Bit 0—Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1,
PSU1, ESU1, EV1, PV1, or E1 bit at the same time.
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Section 15 ROM
Bit 0
P1
Description
0
Program mode cleared
1
Transition to program mode
(Initial value)
[Setting condition]
•
15.7.2
When FWE = 1, SWE1 = 1, and PSU1 = 1
Flash Memory Control Register 2 (FLMCR2)
Bit:
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Note: FLMCR2 is a read-only register, and should not be written to.
FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is
initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode.
When on-chip flash memory is disabled, a read will return H'00.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state.
Bit 7
FLER
Description
0
Flash memory is operating normally
(Initial value)
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
•
1
Power-on reset or hardware standby mode
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
•
See section 15.10.3, Error Protection
Bits 6 to 0—Reserved: These bits always read 0.
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Section 15 ROM
15.7.3
Erase Block Register 1 (EBR1)
Bit:
Initial value:
R/W:
7
EB7
0
R/W
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
0
EB0
0
R/W
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,
when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the
SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be
erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can
be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be
automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and
writes are invalid.
The flash memory block configuration is shown in table 15.6.
15.7.4
Erase Block Register 2 (EBR2)
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
EB9
EB8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,
when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is
not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the
corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1
and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both
EBR1 and EBR2 to be automatically cleared to 0. Bits 7 to 2 are reserved and must only be
written with 0. When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
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Section 15 ROM
The flash memory block configuration is shown in table 15.6.
Table 15.6 Flash Memory Erase Blocks
Block (Size)
Addresses
EB0 (1 kbyte)
H'000000 to H'0003FF
EB1 (1 kbyte)
H'000400 to H'0007FF
EB2 (1 kbyte)
H'000800 to H'000BFF
EB3 (1 kbyte)
H'000C00 to H'000FFF
EB4 (28 kbytes)
H'001000 to H'007FFF
EB5 (16 kbytes)
H'008000 to H'00BFFF
EB6 (8 kbytes)
H'00C000 to H'00DFFF
EB7 (8 kbytes)
H'00E000 to H'00FFFF
EB8 (32 kbytes)
H'010000 to H'017FFF
EB9 (32 kbytes)
H'018000 to H'01FFFF
15.7.5
RAM Emulation Register (RAMER)
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
RAMS
—
RAM1
RAM0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R/W
R/W
R/W
R/W
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER initialized to H'00 by a power-on reset and in
hardware standby mode. It is not initialized by a manual reset and in software standby mode.
RAMER settings should be made in user mode or user program mode.
Flash memory area divisions are shown in table 15.7. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bits 7 to 5—Reserved: These bits always read 0.
Bit 4—Reserved: Only 0 may be written to these bits.
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Section 15 ROM
Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 3
RAMS
Description
0
Emulation not selected
(Initial value)
Program/erase-protection of all flash memory blocks is disabled
1
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
Bit 2—Reserved: Only 0 should be written to this bit.
Bits 1 and 0—Flash Memory Area Selection: These bits are used together with bit 3 to select the
flash memory area to be overlapped with RAM. (See table 15.7)
Table 15.7 Flash Memory Area Divisions
Addresses
Block Name
RAMS
RAM1
RAM0
H'FFD000 to H'FFD3FF
RAM area 1 kbyte
0
*
*
H'000000 to H'0003FF
EB0 (1 kbyte)
1
0
0
H'000400 to H'0007FF
EB1 (1 kbyte)
1
0
1
H'000800 to H'000BFF
EB2 (1 kbyte)
1
1
0
H'000C00 to H'000FFF
EB3 (1 kbyte)
1
1
1
Legend:
*: Don’t care
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Section 15 ROM
15.7.6
Serial Control Register X (SCRX)
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
—
—
—
—
FLSHE
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCRX is an 8-bit readable/writable register that performs register access control, and on-chip flash
memory control (including the F-ZTAT version).
SCRX is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4—Reserved: Only 0 should be written to these bits.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1
enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash
memory control registers are deselected. In this case, the flash memory control register contents
are retained. When the FLSHE bit is set to 1, the flash memory control registers can be read and
written to. When FLSHE is cleared to 0, the flash memory control registers are deselected. In this
case, the contents of the flash memory control registers are retained.
Bit 3
FLSHE
Description
0
Flash control registers deselected in area H'FFFFA8 to H'FFFFAC
1
Flash control registers selected in area H'FFFFA8 to H'FFFFAC
(Initial value)
Bits 2 to 0—Reserved: Only 0 should be written to these bits.
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Section 15 ROM
15.8
On-Board Programming Modes
When pins are set to on-board programming mode and a reset-start is executed, a transition is
made to the on-board programming state in which program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
15.8. For a diagram of the transitions to the various flash memory modes, see figure 15.3.
Table 15.8 Setting On-Board Programming Modes
Mode
Boot mode
Expanded mode
FWE
MD2
MD1
MD0
1
0
1
0
0
1
1
1
1
1
0
1
1
1
Single-chip mode
User program mode
Expanded mode
Single-chip mode
15.8.1
Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The SCI channel to be used is set to asynchronous mode.
When a reset-start is executed after the LSI’s pins have been set to boot mode, the boot program
built into the LSI is started and the programming control program prepared in the host is serially
transmitted to the LSI via the SCI. In the LSI, the programming control program received via the
SCI is written into the programming control program area in on-chip RAM. After the transfer is
completed, control branches to the start address of the programming control program area and the
programming control program execution state is entered (flash memory programming is
performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as
an erase error indication, and the erase operation and subsequent operations are halted. When a
transition is made to boot mode, or from boot mode to another mode, mode switching must be
carried out by means of RES input. The states of ports with multiplexed address functions and bus
control output signals (AS, RD, WR) change during the switchover period (while a low level is
being input at the RES pin), and therefore these pins should not be used for output signals during
this period.
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Section 15 ROM
The system configuration in boot mode is shown in figure 15.9, and the boot mode execution
procedure in figure 15.10.
HD64F2214
Flash memory
Host
Write data reception
Verify data transmission
RXD2
SCI2
TXD2
On-chip RAM
Figure 15.9 System Configuration in Boot Mode
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Section 15 ROM
Start
Set pins to boot mode
and execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
HD64F2214 measures low period
of H'00 data transmitted by host
HD64F2214 calculates bit rate and
sets value in bit rate register
After bit rate adjustment,
HD64F2214 transmits one H'00
data byte to host to indicate end
of adjustment
Host confirms normal reception
of bit rate adjustment end
indication (H'00), and transmits
one H'55 data byte
After receiving H'55,
HD64F2214 transmits one H'AA
data byte to host
Host transmits number
of programming control program
bytes (N), upper byte followed
by lower byte
HD64F2214 transmits received
number of bytes to host as verify
data (echo-back)
n=1
Host transmits programming control
program sequentially in byte units
HD64F2214 transmits received
programming control program to
host as verify data (echo-back)
n+1→n
Transfer received programming
control program to on-chip RAM
No
n = N?
Yes
End of transmission
Check flash memory data, and
if data has already been written,
erase all blocks
After confirming that all flash
memory data has been erased,
HD64F2214 transmits one H'AA
data byte to host
Execute programming control
program transferred to on-chip RAM
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Figure 15.10 Boot Mode Execution Procedure
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Section 15 ROM
(1) Automatic SCI Bit Rate Adjustment
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Low period (9 bits) measured (H'00 data)
Stop
bit
High period
(1 or more bits)
Figure 15.11 Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the LSI measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the LSI’s system clock frequency, there will be
a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 4,800,
9,600, or 19,200 bps to operate the SCI properly.
Table 15.9 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of the LSI bit rate is possible. The boot program should be executed within this system
clock range.
Table 15.9 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is
Possible
Host Bit Rate
System Clock Frequency for Which Automatic Adjustment
of LSI Bit Rate is Possible
4,800 bps
2 MHz to 16 MHz
9,600 bps
4 MHz to 16 MHz
19,200 bps
8 MHz to 16 MHz
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Section 15 ROM
(2) On-Chip RAM Area Divisions in Boot Mode
In boot mode, the RAM area is divided into an area used by the boot program and an area to which
the programming control program is transferred via the SCI, as shown in figure 15.12. The boot
program area cannot be used until the execution state in boot mode switches to the programming
control program transferred from the host.
H'FFC000
Programming
control program area
(8 kbytes)
H'FFDFFF
H'FFE000
Boot program area
(4 kbytes)
H'FFEFBF
Note:
The boot program area cannot be used until a transition is made to the execution state
for the programming control program transferred to RAM. Note also that the boot program
remains in this area of the on-chip RAM even after control branches to the programming
control program.
Figure 15.12 RAM Areas in Boot Mode
(3) Notes on Use of Boot Mode
• When the chip comes out of reset in boot mode, it measures the low-level period of the input at
the SCI’s RxD2 pin. The reset should end with RxD2 high. After the reset ends, it takes
approximately 100 states before the chip is ready to measure the low-level period of the RxD2
pin.
• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
• Interrupts cannot be used while the flash memory is being programmed or erased.
• The RxD2 and TxD2 pins should be pulled up on the board.
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Section 15 ROM
• Before branching to the programming control program (RAM area H'FFC000), the chip
terminates transmit and receive operations by the on-chip SCI (channel 2) (by clearing the RE
and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data
output pin, TxD2, goes to the high-level output state (PA1DDR = 1, PA1DR = 1).
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area
must be specified for use by the programming control program.
Initial settings must also be made for all other on-chip registers.
• Boot mode can be entered by making the pin settings shown in table 15.8 and executing a
reset-start.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
1
the FWE pin and mode pins, and executing reset release* . Boot mode can also be cleared by a
WDT overflow reset.
Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low
while the boot program is being executed or while flash memory is being programmed or
2
erased* .
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR)
3
will change according to the change in the microcomputer’s operating mode* .
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins during a reset, or to prevent collision with signals outside the microcomputer.
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS =
200 ns) with respect to the reset release timing.
2. For further information on FWE application and disconnection, see section 15.15,
Flash Memory Programming and Erasing Precautions.
3. See appendix D, Pin States.
15.8.2
User Program Mode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing on-board means of FWE control and supply of
programming data, and storing a program/erase control program in part of the program area as
necessary.
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Section 15 ROM
To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7),
and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash
memory operate as they normally would in modes 6 and 7.
The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or
erasing, so the control program that performs programming and erasing should be run in on-chip
RAM or external memory.
Figure 15.13 shows the procedure for executing the program/erase control program when
transferred to on-chip RAM.
Write the FWE assessment program and
transfer program (and the program/erase
control program if necessary) beforehand
MD2, MD1, MD0 = 110, 111
Reset-start
Transfer program/erase control
program to RAM
Branch to program/erase control
program in RAM area
FWE = high*
Execute program/erase control
program (flash memory rewriting)
Clear FWE*
Branch to flash memory application
program
Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin
only when the flash memory is programmed or erased. Also, while a high level is
applied to the FWE pin, the watchdog timer should be activated to prevent
overprogramming or overerasing due to program runaway, etc.
* For further information on FWE application and disconnection, see section 15.15,
Flash Memory Programming and Erasing Precautions.
Figure 15.13 User Program Mode Execution Procedure
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Section 15 ROM
15.9
Programming/Erasing Flash Memory
A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by
setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1 for addresses H'000000 to
H'01FFFF.
The flash memory cannot be read while it is being written or erased. Install the program to control
flash memory programming and erasing (programming control program) in the on-chip RAM, in
external memory, and execute the program from there.
Notes: 1. Operation is not guaranteed if bits SWE1, ESU1, PSU1, EV1, PV1, E1, and P1 of
FLMCR1 are set/reset by a program in flash memory in the corresponding address
areas.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Programming should be performed in the erased state. Do not perform additional
programming on previously programmed addresses.
15.9.1
Program Mode
Follow the procedure shown in the program/program-verify flowchart in figure 15.10 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a
time.
For the wait times (tsswe, tspsu, tsp10, tsp30, tsp200, tcp, tcpsu, tspv, tspvr, tcpv, tcswe) after bits are set or cleared in
flash memory control register 1 (FLMCR1) and the maximum number of programming operations
(N), see section 18.6, Flash Memory Characteristics.
Following the elapse of tsswe µs or more after the SWE1 bit is set to 1 in flash memory control
register 1 (FLMCR1), 128-byte data is stored in the program data area and reprogram data area,
and the 128-byte data in the program data area in RAM is written consecutively to the write
addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive
byte data transfers are performed. The program address and program data are latched in the flash
memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this
case, H'FF data must be written to the extra addresses.
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Section 15 ROM
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a value greater than (tspsu + tsp200 + tcp + tcpsu) µs as the WDT overflow period. After this,
preparation for program mode (program setup) is carried out by setting the PSU1 bit in FLMCR1,
and after the elapse of tspsu µs or more, the operating mode is switched to program mode by
setting the P1 bit in FLMCR1. The time during which the P1 bit is set is the flash memory
programming time. Set the programming time according to the table in the programming
flowchart.
15.9.2
Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P1 bit in
FLMCR1 is cleared, then the PSU1 bit is cleared at least tcp µs later). The watchdog timer is
cleared after the elapse of tcpsu µs or more, and the operating mode is switched to program-verify
mode by setting the PV1 bit in FLMCR1. Before reading in program-verify mode, a dummy write
of H'FF data should be made to the addresses to be read. The dummy write should be executed
after the elapse of tspv µs or more. When the flash memory is read in this state (verify data is read in
16-bit units), the data at the latched address is read. Wait at least tspvr µs after the dummy write
before performing this read operation. Next, the originally written data is compared with the verify
data, and reprogram data is computed (see figure 15.14) and transferred to the reprogram data
area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least tcpv µs,
then clear the SWE1 bit in FLMCR1 to 0. If reprogramming is necessary, set program mode again,
and repeat the program/program-verify sequence as before. However, ensure that the
program/program-verify sequence is not repeated more than (N) times on the same bits.
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Section 15 ROM
Subroutine: Write Pulse
Start of subroutine
Start
Enable WDT
Set SWE1 bit in FLMCR1
Data writes must be performed
in the memory-erased state.
Do not write additional data to
an address to which data is
already written.
Set PSU1 bit in FLMCR1
Wait 1 μs: tSSWE
Wait 50 μs: tSPSU
Store 128 bytes program data in program
data area and reprogram data area
*4
Set P1 bit in FLMCR1
n=1
Wait: tSP10, tSP30 or tSP200
*5
m=0
Clear P1 bit in FLMCR1
Successively write 128-byte data from
reprogram data area in RAM to flash memory *1
Wait 5 μs: tCP
Clear PSU1 bit in FLMCR1
Subroutine call
See Note 6 for pulse width
Write Pulse (tSP30 or tSP200)
Wait 5 μs: tCPSU
Set PV1 bit in FLMCR1
Disable WDT
Wait 4 μs: tSPV
Return
Perform H'FF dummy-write to verify address
Note: 6. Write Pulse Width
Number of Writes n Write Time (tSP30/tSP200) µs
1
tSP30
tSP30
2
tSP30
3
tSP30
4
tSP30
5
tSP30
6
tSP200
7
tSP200
8
tSP200
9
tSP200
10
tSP200
11
tSP200
12
tSP200
13
.
.
.
.
.
.
tSP200
998
tSP200
999
tSP200
1000
Note: Use a tSP10 write pulse for additional programming.
Wait 2 μs: tSPVR
Increment
address
RAM
Read verify data
n←n+1
*2
Write data =
verify data?
No
m=1
Yes
No
6 ≥ n?
Yes
Compute additional-programming data
Transfer additional-programming data
to additional-programming data area
*4
Compute reprogram data
*3
Transfer reprogram data to reprogram
data area
*4
128 byte data
verify complete?
No
Program data storage area
(128 bytes)
Yes
Clear PV1 bit in FLMCR1
Reprogram data storage area
(128 bytes)
Wait 2 μs: tCPV
Additional program data
storage area (128 bytes)
No
6 ≥ n?
Yes
Notes: 1. Transfer data in byte units. The lower eight bits of the start
address to which data is written must be H'00 or H'80.
Transfer 128-byte data even when writing fewer than 128 bytes.
In this case, set H'FF in unused addresses.
2. Read verify data in longword form (32 bits).
3. Even for bits to which data is already written, an additional write
should be performed if their verify result is NG.
4. A 128-byte area for storing program data, a 128-byte area for
storing reprogram data, and a 128-byte area for storing additional
program data must be provided in RAM. The reprogram and
additional program data contents are modified as programming
proceeds.
5. A write pulse of tSP30 or tSP200 is applied according to the
progress of the programming operation. See Note 6 for the pulse
widths. When writing of the additional program data is executed,
a tSP10 write pulse should be applied. Reprogram data X' means
reprogram data when the pulse is applied.
Successively write 128-byte data
from additional-programming data area
in RAM to flash memory
Reprogram Data Computation Table
Original Data Verify Data Reprogram Data
Comments
(V)
(D)
(X)
0
0
1
Programming complete.
Programming is incomplete;
0
1
0
reprogramming should be performed.
1
0
1
—
1
1
1
Left in the erased state.
*1
Subroutine call
Write Pulse (tSP10)
No
m = 0?
n ≥ 1000?
Yes
No
Yes
Clear SWE1 bit in FLMCR1
Clear SWE1 bit in FLMCR1
Wait 100 μs: tCSWE
Wait 100 μs: tCSWE
Programming end
Programming failure
Additional-Programming Data Computation Table
Reprogram Data Verify Data Additional-Programming
Comments
(V)
Data (Y)
(X')
Additional programming executed
0
0
0
Additional programming not executed
0
1
1
Additional programming not executed
1
0
1
Additional programming not executed
1
1
1
Figure 15.14 Program/Program-Verify Flowchart
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Section 15 ROM
15.9.3
Erase Mode
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart shown in figure 15.15.
For the wait times (tsswe, tsesu, tse, tce, tcesu, tsev, tsevr, tcev, tcswe) after bits are set or cleared in flash memory
control register 1 (FLMCR1) and the maximum number of erase operations (N), see section 18.6,
Flash Memory Characteristics.
To perform data or program erasure, make a 1-bit setting for the flash memory area to be erased in
erase block register 1 or 2 (EBR1 or EBR2) at least tsswe µs after setting the SWE1 bit to 1 in flash
memory control register 1 (FLMCR1). Next, set up the watchdog timer to prevent overerasing in
the event of program runaway, etc. Set a value greater than (tsesu + tse + tce + tcesu) µs as the WDT
overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the
ESU1 bit in FLMCR1, and after the elapse of tsesu µs or more, the operating mode is switched to
erase mode by setting the E1 bit in FLMCR1. The time during which the E1 bit is set is the flash
memory erase time. Ensure that the erase time does not exceed tse ms.
Note: With flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is
not necessary before starting the erase procedure.
15.9.4
Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the E1 bit in FLMCR1 is cleared to 0, then
the ESU1 bit is cleared to 0 at least tce µs later), the watchdog timer is cleared after the elapse of
tcesu µs or more, and the operating mode is switched to erase-verify mode by setting the EV1 bit in
FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to
the addresses to be read. The dummy write should be executed after the elapse of tsev µs or more.
When the flash memory is read in this state (verify data is read in 16-bit units), the data at the
latched address is read. Wait at least tsevr µs after the dummy write before performing this read
operation. If the read data has been erased (all 1), execute a dummy write to the next address, and
perform an erase-verify. If the read data has not been erased, set erase mode again and repeat the
erase/erase-verify sequence as before. However, ensure that the erase/erase-verify sequence is not
repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait
for at least tcev µs. If erasure has been completed on all the erase blocks, clear the SWE1 bit in
Rev.4.00 Sep. 18, 2008 Page 574 of 872
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Section 15 ROM
FLMCR1. If there are any unerased blocks, make a 1-bit setting for the flash memory block to be
erased, and repeat the erase/erase-verify sequence as before.
Start
*1
Erasing must be performed in
block units.
Set SWE1 bit in FLMCR1
tSSWE : Wait 1 µs
n=1
Set EBR1 (2)
*3
Enable WDT
Set ESU1 bit in FLMCR
tSESU : Wait 100 µs
Start erase
Set E1 bit in FLMCR1
tSE : Wait 10 ms
Clear E1 bit in FLMCR1
Halt erase
tCE : Wait 10 µs
Clear ESU1 bit in FLMCR1
tCESU : Wait 10 µs
Disable WDT
n←n+1
Set EV1 bit in FLMCR1
tSEV : Wait 20 µs
Set block start address to verify address
H'FF dummy write to verify address
tSEVR : Wait 2 µs
Read verify data
Increment
address
Verify data = all "1"?
*2
NG
OK
NG
NG
Notes: 1.
2.
3.
4.
Last address of block?
OK
Clear EV1 bit in FLMCR1
Clear EV1 bit in FLMCR1
Wait 4 µs: tCEV
Wait 4 µs: tCEV
*4
End of
erasing of all erase
blocks?
n ≥ 100?
OK
Clear SWE1 bit in FLMCR1
OK
Clear SWE1 bit in FLMCR1
Wait 100 µs: tCSWE
Wait 100 µs: tCSWE
End of erasing
Erase failure
NG
Preprogramming (setting erase block data to all "0") is not necessary.
Verify data is read in 32-bit (longword) units.
Set only one bit in EBR1 (2). More than one bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Figure 15.15 Erase/Erase-Verify Flowchart
Rev.4.00 Sep. 18, 2008 Page 575 of 872
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Section 15 ROM
15.10
Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
15.10.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control register 1
(FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase
block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the
error-protected state. (See table 15.10)
Table 15.10 Hardware Protection
Functions
Item
Description
Program
Erase
FWE pin protection
•
When a low level is input to the FWE pin,
FLMCR1, FLMCR2, (except bit FLER)
EBR1, and EBR2 are initialized, and the
program/erase-protected state is entered.
Yes
Yes
Reset/standby
protection
•
In a power-on reset (including a WDT
power-on reset) and in standby mode,
FLMCR1, FLMCR2, EBR1, and EBR2 are
initialized, and the program/eraseprotected state is entered.
Yes
Yes
•
In a reset via the RES pin, the reset state
is not entered unless the RES pin is held
low until oscillation stabilizes after
powering on. In the case of a reset during
operation, hold the RES pin low for the
RES pulse width specified in the AC
Characteristics section.
Rev.4.00 Sep. 18, 2008 Page 576 of 872
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Section 15 ROM
15.10.2 Software Protection
Software protection can be implemented by setting the SWE1 bit in FLMCR1, erase block register
1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register
(RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control
register 1 (FLMCR1), does not cause a transition to program mode or erase mode. (See table
15.11.)
Table 15.11 Software Protection
Functions
Item
Description
Program
Erase
SWE bit protection
•
Setting bit SWE1 in FLMCR1 to 0 will
place area H'000000 to H'01FFFF in the
program/erase-protected state. (Execute
the program in the on-chip RAM, external
memory)
Yes
Yes
Block specification
protection
•
Erase protection can be set for individual
blocks by settings in erase block register 1
(EBR1) and erase block register 2 (EBR2).
—
Yes
•
Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
Yes
Yes
Emulation protection •
Setting the RAMS bit to 1 in the RAM
emulation register (RAMER) places all
blocks in the program/erase-protected
state.
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Section 15 ROM
15.10.3 Error Protection
In error protection, an error is detected when LSI runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the LSI malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P1 or E1 bit.
However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
1. When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
2. Immediately after exception handling (excluding a reset) during programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the CPU releases the bus to the DTC during programming/erasing.
Error protection is released only by a power-on reset and in hardware standby mode.
Rev.4.00 Sep. 18, 2008 Page 578 of 872
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Section 15 ROM
Figure 15.16 shows the flash memory state transition diagram.
Program mode
Erase mode
Reset or standby
(hardware protection)
RES = 0 or HSTBY = 0
RD VF PR ER FLER = 0
RD VF PR ER FLER = 0
Error occurrence
(software standby)
RES = 0 or
HSTBY = 0
Error
occurrence
RES = 0 or
HSTBY = 0
Error protection mode
RD VF PR ER FLER = 1
Software
standby mode
Software standby
mode release
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
Error protection mode
(software standby)
RD VF PR ER FLER = 1
FLMCR1, FLMCR2, (except bit FLER)
EBR1, EBR2 initialization state
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD:
VF:
PR:
ER:
Memory read not possible
Verify-read not possible
Programming not possible
Erasing not possible
Figure 15.16 Flash Memory State Transitions
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Section 15 ROM
15.11
Flash Memory Emulation in RAM
Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped
onto the flash memory area so that data to be written to flash memory can be emulated in RAM in
real time. After the RAMER setting has been made, accesses can be made from the flash memory
area or the RAM area overlapping flash memory. Emulation can be performed in user mode and
user program mode. Figure 15.17 shows an example of emulation of real-time flash memory
programming.
Start of emulation program
Set RAMER
Write tuning data to overlap
RAM
Execute application program
No
Tuning OK?
Yes
Clear RAMER
Write to flash memory emulation
block
End of emulation program
Figure 15.17 Flowchart for Flash Memory Emulation in RAM
Rev.4.00 Sep. 18, 2008 Page 580 of 872
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Section 15 ROM
This area can be accessed
from both the RAM area
and flash memory area
H'000000
EB0
H'000400
EB1
H'000800
EB2
H'000C00
EB3
H'001000
Flash memory
EB4 to EB9
H'FFD000
H'FFD3FFF
On-chip RAM
H'01FFFF
Figure 15.18 Example of RAM Overlap Operation
Example in which Flash Memory Block Area EB0 is Overlapped
1. Set bits RAMS, RAM1 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the
area (EB0) for which real-time programming is required.
2. Real-time programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB0).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
regardless of the value of RAM1 to RAM0 (emulation protection). In this state, setting
the P1 or E1 bit in flash memory control register 1 (FLMCR1), will not cause a
transition to program mode or erase mode. When actually programming or erasing a
flash memory area, the RAMS bit should be cleared to 0.
2. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm while flash memory emulation in RAM is being used.
3. Block area EB0 contains the vector table. When performing RAM emulation, the
vector table is needed in the overlap RAM.
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Section 15 ROM
15.12
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI interrupt is disabled when flash memory is being programmed or
erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot
1
mode* , to give priority to the program or erase operation. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the interrupt exception handling sequence during programming or erasing, the vector would
2
not be read correctly* , possibly resulting in MCU runaway.
3. If interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupt, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All requests, including NMI interrupt, must
therefore be restricted inside and outside the MCU when programming or erasing flash memory.
NMI interrupt is also disabled in the error-protection state while the P1 or E1 bit remains set in
FLMCR1.
Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming
control program has completed programming.
2. The vector may not be read correctly in this case for the following two reasons:
15.13
•
If flash memory is read while being programmed or erased (while the P1 or E1 bit
is set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
•
If the interrupt entry in the vector table has not been programmed yet, interrupt
exception handling will not be executed correctly.
Flash Memory Programmer Mode
Programs and data can be written and erased in programmer mode as well as in the on-board
programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and
status read mode, a status polling procedure is used, and in status read mode, detailed internal
signals are output after execution of an auto-program or auto-erase operation.
In programmer mode, set the mode pins to programmer mode (see table 15.12) and input a 12
MHz input clock.
Rev.4.00 Sep. 18, 2008 Page 582 of 872
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Section 15 ROM
Table 15.12 shows the pin settings for programmer mode. For the pin names in programmer mode,
see section 1.3.2, Pin Functions in Each Operating Mode.
Table 15.12 Programmer Mode Pin Settings
Pin Names
Settings
Mode pins: MD2, MD1, MD0
Low level input to MD2, MD1, and MD0.
Mode setting pins: PF3, PF0, P16, P14
High level input to PF3, PF0, low level input to P16 and
P14
FWE pin
High level input (in auto-program and auto-erase
modes)
RES pin
Power-on reset circuit
XTAL, EXTAL pins
Oscillator circuit
15.13.1 Socket Adapter Pin Correspondence Diagram
Connect the socket adapter to the chip as shown in figure 15.20. This will enable conversion to a
40-pin arrangement. The on-chip ROM memory map is shown in figure 15.19, and the socket
adapter pin correspondence diagram in figure 15.20.
Addresses in
MCU mode
Addresses in
programmer mode
H'000000
H'00000
On-chip ROM space
128 kbytes
H'01FFFF
H'1FFFF
Figure 15.19 On-Chip ROM Memory Map
Rev.4.00 Sep. 18, 2008 Page 583 of 872
REJ09B0189-0400
Section 15 ROM
HN27C4096HG (40 Pins)
H8S/2214
Pin No.
Pin Name
TFP-100B, TFP-100G
TBP-112
Socket Adapter
(Conversion to 40-Pin
Arrangement)
Pin No.
Pin Name
13
F1
A0
21
A0
15
G1
A1
22
A1
16
G2
A2
23
A2
17
G3
A3
24
A3
18
H1
A4
25
A4
19
G4
A5
26
A5
20
H2
A6
27
A6
21
J1
A7
28
A7
22
H3
A8
29
A8
23
J2
A9
31
A9
24
K1
A10
32
A10
25
J3
A11
33
A11
26
K2
A12
34
A12
27
L2
A13
35
A13
28
H4
A14
36
A14
29
K3
A15
37
A15
30
L3
A16
38
A16
31
J4
A17
39
A17
32
K4
A18
10
A18
4
C2
D0
19
I/O0
5
C1
D1
18
I/O1
6
D3
D2
17
I/O2
7
D2
D3
16
I/O3
8
D1
D4
15
I/O4
9
E4
D5
14
I/O5
10
E3
D6
13
I/O6
11
E1
D7
12
I/O7
3
D4
CE
2
CE
1
B2
OE
20
OE
2
B1
WE
3
WE
66
E10
FWE
4
FWE
12, 53, 54, 58, 60,
61, 62, 75, 99, 72
E2, F3, H8, C9, F9, G9,
G10, J10, G11, H11, D9
VCC
1,40
VCC
11,30
VSS
14, 38, 40, 42, 55, 56, A2, F2, F4, J6, K6, K7,
L7, F8, E9, H9, F10, J11
64, 67, 100
VSS
59
G8
RES
63
F11
XTAL
65
E11
EXTAL
Other than the above
Other than the above
NC (OPEN)
Power-on
reset circuit
Oscillator circuit
5,6,7
NC
8
A20
9
A19
Legend:
FWE:
I/O7 to I/O0:
A18 to A0:
CE:
OE:
WE:
Flash write enable
Data input/output
Address input
Chip enable
Output enable
Write enable
Figure 15.20 Socket Adapter Pin Correspondence Diagram
Rev.4.00 Sep. 18, 2008 Page 584 of 872
REJ09B0189-0400
Section 15 ROM
15.13.2 Programmer Mode Operation
Table 15.13 shows how the different operating modes are set when using programmer mode, and
table 15.14 lists the commands used in programmer mode. Details of each mode are given below.
(1) Memory Read Mode
Memory read mode supports byte reads.
(2) Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
(3) Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to
confirm the end of auto-programming.
(4) Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the I/O6 signal. In status read mode, error information is output if an error
occurs.
Table 15.13 Settings for Various Operating Modes In Programmer Mode
Pin Names
Mode
FWE
CE
OE
WE
I/O7 to I/O0
A18 to A0
Read
H or L
L
L
H
Data output
Ain
Output disable
H or L
L
H
H
Hi-Z
X
Command write
H or L
L
H
L
Data input
*Ain
Chip disable
H or L
H
X
X
Hi-Z
X
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
2. *Ain indicates that there is also address input in auto-program mode.
3. For command writes in auto-program and auto-erase modes, input a high level to the
FWE pin.
Rev.4.00 Sep. 18, 2008 Page 585 of 872
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Section 15 ROM
Table 15.14 Programmer Mode Commands
1st Cycle
2nd Cycle
Command Name
Number
of Cycles
Mode
Address Data
Mode
Address Data
Memory read mode
1+n
Write
X
H'00
Read
RA
Dout
Auto-program mode
129
Write
X
H'40
Write
WA
Din
Auto-erase mode
2
Write
X
H'20
Write
X
H'20
Status read mode
2
Write
X
H'71
Write
X
H'71
Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous
128-byte write.
2. In memory read mode, the number of cycles depends on the number of address write
cycles (n).
15.13.3 Memory Read Mode
1. After completion of auto-program/auto-erase/status read operations, a transition is made to the
command wait state. When reading memory contents, a transition to memory read mode must
first be made with a command write, after which the memory contents are read.
2. In memory read mode, command writes can be performed in the same way as in the command
wait state.
3. Once memory read mode has been entered, consecutive reads can be performed.
4. After powering on, memory read mode is entered.
Table 15.15 AC Characteristics in Transition to Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min.
Command write cycle
tnxtc
20
Max.
Unit
µs
CE hold time
tceh
0
ns
CE setup time
tces
0
ns
Data hold time
tdh
50
ns
Data setup time
tds
50
ns
Write pulse width
twep
70
ns
WE rise time
tr
30
ns
WE fall time
tf
30
ns
Rev.4.00 Sep. 18, 2008 Page 586 of 872
REJ09B0189-0400
Notes
Section 15 ROM
Command write
Memory read mode
Address stable
A18 to A0
tces
tceh
tnxtc
CE
OE
twep
tf
tr
WE
tds
tdh
I/O7 to I/O0
Note: Data is latched on the rising edge of WE.
Figure 15.21 Timing Waveforms for Memory Read after Memory Write
Table 15.16 AC Characteristics in Transition from Memory Read Mode to Another Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min.
Max.
Unit
Command write cycle
tnxtc
20
µs
CE hold time
tceh
0
ns
CE setup time
tces
0
ns
Data hold time
tdh
50
ns
Data setup time
tds
50
ns
Write pulse width
twep
70
ns
WE rise time
tr
30
ns
WE fall time
tf
30
ns
Notes
Rev.4.00 Sep. 18, 2008 Page 587 of 872
REJ09B0189-0400
Section 15 ROM
Memory read mode
A18 to A0
Other mode command write
Address stable
tnxtc
tces
tceh
CE
OE
twep
tf
tr
WE
tds
tdh
I/O7 to I/O0
Note: Do not enable WE and OE at the same time.
Figure 15.22 Timing Waveforms in Transition from Memory Read Mode to Another Mode
Table 15.17 AC Characteristics in Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min.
Max.
Unit
Access time
tacc
20
µs
CE output delay time
tce
150
ns
OE output delay time
toe
150
ns
Output disable delay time
tdf
100
ns
Data output hold time
toh
Rev.4.00 Sep. 18, 2008 Page 588 of 872
REJ09B0189-0400
5
ns
Notes
Section 15 ROM
Address stable
A18 to A0
CE
VIL
OE
VIL
WE
VIH
Address stable
tacc
tacc
toh
toh
I/O7 to I/O0
Figure 15.23 CE and OE Enable State Read Timing Waveforms
Address stable
A18 to A0
Address stable
tce
tce
CE
toe
toe
OE
WE
VIH
tacc
tacc
toh
tdf
toh
tdf
I/O7 to I/O0
Figure 15.24 CE and OE Clock System Read Timing Waveforms
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REJ09B0189-0400
Section 15 ROM
15.13.4 Auto-Program Mode
1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers.
2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this
case, H'FF data must be written to the extra addresses.
3. The lower 7 bits of the transfer address must be low. If a value other than an effective address
is input, processing will switch to a memory write operation but a write error will be flagged.
4. Memory address transfer is performed in the second cycle (figure 15.25). Do not perform
transfer after the third cycle.
5. Do not perform a command write during a programming operation.
6. Perform one auto-program operation for a 128-byte block for each address. Two or more
additional programming operations cannot be performed on a previously programmed address
block.
7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode
can also be used for this purpose (I/O7 status polling uses the auto-program operation end
decision pin).
8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
Rev.4.00 Sep. 18, 2008 Page 590 of 872
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Section 15 ROM
Table 15.18 AC Characteristics in Auto-Program Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min.
Max.
Unit
Command write cycle
tnxtc
20
µs
CE hold time
tceh
0
ns
CE setup time
tces
0
ns
Data hold time
tdh
50
ns
Data setup time
tds
50
ns
Write pulse width
twep
70
ns
Status polling start time
twsts
1
ms
Status polling access time
tspa
Address setup time
tas
0
ns
Address hold time
tah
60
ns
Memory write time
twrite
1
Write setup time
tpns
100
ns
Write end setup time
tpnh
100
ns
150
Notes
ns
3000
ms
WE rise time
tr
30
ns
WE fall time
tf
30
ns
FWE
tpnh
Address
stable
A18 to A0
tpns
tces
tceh
tnxtc
tnxtc
CE
OE
tf
twep
tr
tas
tah
twsts
tspa
WE
tds
tdh
Data transfer
1 to 128 bytes
twrite
I/O7
Write operation end decision signal
I/O6
Write normal end decision signal
I/O5 to I/O0
H'40
H'00
Figure 15.25 Auto-Program Mode Timing Waveforms
Rev.4.00 Sep. 18, 2008 Page 591 of 872
REJ09B0189-0400
Section 15 ROM
15.13.5 Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing.
2. Do not perform a command write during auto-erasing.
3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also
be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin).
4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
Table 15.19 AC Characteristics in Auto-Erase Mode
Conditions: VCC = 3.3 V ±3.0 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min.
Command write cycle
tnxtc
20
µs
CE hold time
tceh
0
ns
CE setup time
tces
0
ns
Data hold time
tdh
50
ns
Data setup time
tds
50
ns
Write pulse width
twep
70
ns
Status polling start time
tests
1
ms
Status polling access time
tspa
Memory erase time
terase
100
Erase setup time
tens
100
ns
Erase end setup time
tenh
100
ns
WE rise time
tr
30
ns
WE fall time
tf
30
ns
Rev.4.00 Sep. 18, 2008 Page 592 of 872
REJ09B0189-0400
Max.
Unit
150
ns
40000
ms
Notes
Section 15 ROM
FWE
tpnh
A18 to A0
tens
tces
tceh
tnxtc
tnxtc
CE
OE
tf
twep
tr
tests
tspa
WE
tds
terase
tdh
I/O7
Erase end
decision signal
I/O6
I/O5 to I/O0
Erase normal
end
decision signal
H'20
H'20
H'00
Figure 15.26 Auto-Erase Mode Timing Waveforms
Rev.4.00 Sep. 18, 2008 Page 593 of 872
REJ09B0189-0400
Section 15 ROM
15.13.6 Status Read Mode
1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an
abnormal end occurs in auto-program mode or auto-erase mode.
2. The return code is retained until a command write other than a status read mode command
write is executed.
Table 15.20 AC Characteristics in Status Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min.
Read time after command write
tnxtc
20
Max.
Unit
Notes
µs
CE hold time
tceh
0
ns
CE setup time
tces
0
ns
Data hold time
tdh
50
ns
Data setup time
tds
50
ns
Write pulse width
twep
70
ns
OE output delay time
toe
150
ns
Disable delay time
tdf
100
ns
CE output delay time
tce
150
ns
WE rise time
tr
30
ns
WE fall time
tf
30
ns
A18 to A0
tces
tceh
tnxtc tces
tceh
tnxtc
tnxtc
CE
tce
OE
twep
tf
tr
twep
tf
tr
toe
WE
tds
I/O7 to I/O0
tdh
H'71
tds
tdh
H'71
Note: I/O2 and I/O3 are undefined.
Figure 15.27 Status Read Mode Timing Waveforms
Rev.4.00 Sep. 18, 2008 Page 594 of 872
REJ09B0189-0400
tdf
Section 15 ROM
Table 15.21 Status Read Mode Return Commands
Pin Name I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
Attribute
Normal
end
decision
Command
error
Programming error
Erase
error
—
—
ProgramEffective
ming or
address error
erase count
exceeded
Initial
value
0
0
0
0
0
0
0
—
Count
Effective
exceeded: 1 address
Otherwise: 0 error: 1
Indications Normal
end: 0
Command
error: 1
ProgramErasing
—
ming
error: 1
Otherwise: 0 error: 1
Otherwise: 0
Otherwise: 0
Abnormal
end: 1
I/O0
0
Otherwise: 0
Note: I/O2 and I/O3 are undefined.
15.13.7 Status Polling
1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode.
2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase
mode.
Table 15.22 Status Polling Output Truth Table
Pin Name
During Internal
Operation
Abnormal End
—
Normal End
I/O7
0
1
0
1
I/O6
0
0
1
1
I/O0 to I/O5
0
0
0
0
Rev.4.00 Sep. 18, 2008 Page 595 of 872
REJ09B0189-0400
Section 15 ROM
15.13.8 Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 15.23 Stipulated Transition Times to Command Wait State
Item
Symbol
Min.
Standby release (oscillation
stabilization time)
tosc1
30
ms
Programmer mode setup time
tbmv
10
ms
VCC hold time
tdwn
0
ms
tosc1
tbmv
Max.
Memory read
mode
Command
Auto-program mode
wait state
Auto-erase mode
Unit
Notes
Command wait state
Normal/abnormal
end decision
tdwn
VCC
RES
FWE
Note: When using other than the automatic write mode and automatic erase mode, drive the FWE
input pin low.
Figure 15.28 Oscillation Stabilization Time, Boot Program Transfer Time, and
Power-Down Sequence
Rev.4.00 Sep. 18, 2008 Page 596 of 872
REJ09B0189-0400
Section 15 ROM
15.13.9 Notes on Memory Programming
1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming.
2. When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas.
For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
Additional programming cannot be performed on previously programmed address
blocks.
15.14
Flash Memory and Power-Down States
In addition to its normal operating state, the flash memory has power-down states in which power
consumption is reduced by halting part or all of the internal power supply circuitry.
There are three flash memory operating states:
(1) Normal operating mode: The flash memory can be read and written to.
(2) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or
written to.
State (2) is flash memory power-down state. Table 15.24 shows the correspondence between the
operating states of the LSI and the flash memory.
Table 15.24 Flash Memory Operating States
LSI Operating State
Flash Memory Operating State
High-speed mode
Normal mode (read/write)
Medium-speed mode
Sleep mode
Software standby mode
Standby mode
Hardware standby mode
Rev.4.00 Sep. 18, 2008 Page 597 of 872
REJ09B0189-0400
Section 15 ROM
15.14.1 Note on Power-Down States
When the flash memory is in a power-down state, part or all of the internal power supply circuitry
is halted. Therefore, a power supply circuit stabilization period must be provided when returning
to normal operation. When the flash memory returns to its normal operating state from a powerdown state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 100 µs
(power supply stabilization time), even if an oscillation stabilization period is not necessary.
15.15
Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming mode, the RAM emulation function, and
PROM mode are summarized below.
(1) Use the specified voltages and timing for programming and erasing
Applied voltages in excess of the rating can permanently damage the device. Use a PROM
programmer that supports the Renesas microcomputer device type with 256-kbyte on-chip flash
memory (FZTAT256V3A).
Do not select the HN27C4096 setting for the PROM programmer, and only use the specified
socket adapter. Failure to observe these points may result in damage to the device.
(2) Powering on and off (See figures 15.29 to 15.31)
Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low
before turning off VCC.
When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in
the hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a power
failure and subsequent recovery.
(3) FWE application/disconnection (See figures 15.29 to 15.31)
FWE application should be carried out when MCU operation is in a stable condition. If MCU
operation is not stable, fix the FWE pin low and set the protection state.
The following points must be observed concerning FWE application and disconnection to prevent
unintentional programming or erasing of flash memory:
• Apply FWE when the VCC voltage has stabilized within its rated voltage range.
• In boot mode, apply and disconnect FWE during a reset.
Rev.4.00 Sep. 18, 2008 Page 598 of 872
REJ09B0189-0400
Section 15 ROM
• In user program mode, FWE can be switched between high and low level regardless of the
reset state. FWE input can also be switched during execution of a program in flash memory.
• Do not apply FWE if program runaway has occurred.
• Disconnect FWE only when the SWE1, ESU1, PSU1, EV1, PV1, P1, and E bits in FLMCR1
are cleared.
Make sure that the SWE1, ESU1, PSU1, EV1, PV1, P1, and E bits are not set by mistake when
applying or disconnecting FWE.
(4) Do not apply a constant high level to the FWE pin
Apply a high level to the FWE pin only when programming or erasing flash memory. A system
configuration in which a high level is constantly applied to the FWE pin should be avoided. Also,
while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent
overprogramming or overerasing due to program runaway, etc.
(5) Use the recommended algorithm when programming and erasing flash memory
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting the P1
or E1 bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against
program runaway, etc.
(6) Do not set or clear the SWE1 bit during execution of a program in flash memory
Wait for at least 100 µs after clearing the SWE1 bit before executing a program or reading data in
flash memory. When the SWE1 bit is set, data in flash memory can be rewritten, but access flash
memory only for verify operations (verification during programming/erasing). Also, do not clear
the SWE1 bit during programming, erasing, or verifying.
Similarly, when using emulation by RAM with a high level applied to the FWE pin, the SWE1 bit
should be cleared before executing a program or reading data in flash memory. However,
read/write accesses can be performed in the RAM area overlapping the flash memory space
regardless of whether the SWE1 bit is set or cleared.
(7) Do not use interrupts while flash memory is being programmed or erased
All interrupt requests, including NMI, should be disabled during FWE1 application to give priority
to program/erase operations.
Rev.4.00 Sep. 18, 2008 Page 599 of 872
REJ09B0189-0400
Section 15 ROM
(8) Do not perform additional programming. Erase the memory before reprogramming
In on-board programming, perform only one programming operation on a 128-byte programming
unit block. In programmer mode, too, perform only one programming operation on a 128-byte
programming unit block. Programming should be carried out with the entire programming unit
block erased.
(9) Before programming, check that the chip is correctly mounted in the PROM
programmer
Overcurrent damage to the device can result if the index marks on the PROM programmer socket,
socket adapter, and chip are not correctly aligned.
(10) Do not touch the socket adapter or chip during programming
Touching either of these can cause contact faults and write errors.
(11) The reset state must be entered after powering on
Apply the reset signal for at least 100 µs during the oscillation settling period.
(12) When a reset is applied during operation, this should be done while the SWE1 pin is
low
Wait at least 100 µs after clearing the SWE1 bit before applying the reset.
Rev.4.00 Sep. 18, 2008 Page 600 of 872
REJ09B0189-0400
Section 15 ROM
Wait time: x
Programming/
erasing
possible
Wait time: 100 μs
φ
Min. 0 μs
tOSC1
VCC
tMDS*3
FWE
Min. 0 μs
MD2 to MD0*1
tMDS*3
RES
SWE set
SWE cleared
SWE bit
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until
power-off by pulling the pins up or down.
2. See section 18.6, Flash Memory Characteristics.
3. Mode programming setup time tMDS (min.) = 200 ns
Figure 15.29 Power-On/Off Timing (Boot Mode)
Rev.4.00 Sep. 18, 2008 Page 601 of 872
REJ09B0189-0400
Section 15 ROM
Wait time: x
Programming/
erasing
possible
Wait time: 100 μs
φ
Min. 0 μs
tOSC1
VCC
FWE
MD2 to MD0*1
tMDS*3
RES
SWE set
SWE cleared
SWE bit
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until
power-off by pulling the pins up or down.
2. See section 18.6, Flash Memory Characteristics.
3. Mode programming setup time tMDS (min.) = 200 ns
Figure 15.30 Power-On/Off Timing (User Program Mode)
Rev.4.00 Sep. 18, 2008 Page 602 of 872
REJ09B0189-0400
Wait time: 100 μs
Wait time: x
Programming/erasing
possible
Wait time: 100 μs
Wait time: x
Programming/erasing
possible
Wait time: 100 μs
Wait time: x
Programming/erasing
possible
Wait time: 100 μs
Wait time: x
Programming/erasing
possible
Section 15 ROM
ø
tOSC1
VCC
Min. 0 μs
FWE
tMDS
tMDS*2
MD2 to MD0
tMDS
tRESW
RES
SWE1 bit
SWE
set
Mode
change*1
SWE
cleared
Boot
mode
Mode
User
change*1 mode
User program mode
User
mode
User program
mode
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)*3
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be
carried out by means of RES input. The state of ports with multiplexed address functions and bus control output
pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is
low), and therefore these pins should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, a mode programming setup time tMDS (min.) of 200
ns is necessary with respect to RES clearance timing.
3. See section 18.6, Flash Memory Characteristics.
Figure 15.31 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode)
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REJ09B0189-0400
Section 15 ROM
15.16
Note on Switching from F-ZTAT Version to Masked ROM Version
The masked ROM version does not have the internal registers for flash memory control that are
provided in the F-ZTAT version. Table 15.25 lists the registers that are present in the F-ZTAT
version but not in the masked ROM version. If a register listed in table 15.25 is read in the masked
ROM version, an undefined value will be returned. Therefore, if application software developed
on the F-ZTAT version is switched to a masked ROM version product, it must be modified to
ensure that the registers in table 15.25 have no effect.
Table 15.25 Registers Present in F-ZTAT Version but Absent in Masked ROM Version
Register
Abbreviation
Address
Flash memory control register 1
FLMCR1
H'FFA8
Flash memory control register 2
FLMCR2
H'FFA9
Erase block register 1
EBR1
H'FFAA
Erase block register 2
EBR2
H'FFAB
RAM emulation register
RAMER
H'FEDB
Serial control register X
SCRX
H'FDB4
Rev.4.00 Sep. 18, 2008 Page 604 of 872
REJ09B0189-0400
Section 16 Clock Pulse Generator
Section 16 Clock Pulse Generator
16.1
Overview
The H8S/2214 Group has an on-chip clock pulse generator (CPG) that generates the system clock
(φ), the bus master clock, and internal clocks.
The clock pulse generator consists of a system clock oscillator, duty adjustment circuit, mediumspeed clock divider, and bus master clock selection circuit.
16.1.1
Block Diagram
Figure 16.1 shows a block diagram of the clock pulse generator.
SCKCR
SCK2 to SCK0
LPWRCR
RFCUT
EXTAL
XTAL
System
clock
oscillator
Mediumspeed
clock divider
Duty
adjustment
circuit
φ/2 to
φ/32
Bus
master
clock
selection
circuit
φ
System clock
to φ pin
Internal clock to
supporting modules
Bus master clock
to CPU, DTC,
and DMAC
Legend:
LPWRCR: Low-power control register
SCKCR: System clock control register
Figure 16.1 Block Diagram of Clock Pulse Generator
Rev.4.00 Sep. 18, 2008 Page 605 of 872
REJ09B0189-0400
Section 16 Clock Pulse Generator
16.1.2
Register Configuration
The clock pulse generator is controlled by SCKCR and LPWRCR. Table 16.1 shows the register
configuration.
Table 16.1 Clock Pulse Generator Register
Name
Abbreviation
R/W
Initial Value
Address*
System clock control register
SCKCR
R/W
H'00
H'FDE6
Low-power control register
LPWRCR
R/W
H'00
H'FDEC
Note: * Lower 16 bits of the address.
16.2
Register Descriptions
16.2.1
System Clock Control Register (SCKCR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PSTOP
—
—
—
—
SCK2
SCK1
SCK0
0
0
0
0
0
0
0
0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
SCKCR is an 8-bit readable/writable register that performs φ clock output control and mediumspeed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Description
Bit 7
PSTOP
High–Speed Mode
Medium-Speed Mode
Sleep Mode
Software Standby Hardware
Mode, Watch
Standby Mode
0
φ output (initial value)
φ output
Fixed high
High impedance
1
Fixed high
Fixed high
Fixed high
High impedance
Bits 6 and 3—Reserved: This bit can be read or written to, but only 0 should be written.
Rev.4.00 Sep. 18, 2008 Page 606 of 872
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Section 16 Clock Pulse Generator
Bits 5 and 4—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock
used in high-speed mode and medium-speed mode.
Bit 2
Bit 1
Bit 0
SCK2
SCK1
SCK0
Description
0
0
0
Bus master is in high-speed mode
1
Medium-speed clock is φ/2
0
Medium-speed clock is φ/4
1
Medium-speed clock is φ/8
0
Medium-speed clock is φ/16
1
Medium-speed clock is φ/32
—
—
1
1
0
1
16.2.2
Bit
Low-Power Control Register (LPWRCR)
:
Initial value :
R/W
(Initial value)
:
7
6
5
4
3
2
1
0
—
—
—
—
RFCUT
—
STC1
STC0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bits 7 to 4—Reserved: These bits can be read or written to, but only 0 should be written.
Bit 3—On-chip Feedback Resistor Control (RFCUT): Selects whether the oscillator’s on-chip
feedback resistor and duty adjustment circuit are used with external clock input. Do not access this
bit when a crystal oscillator is used.
After this bit is set when using external clock input, a transition should intially be made to
software standby mode. Switching between use and non-use of the oscillator’s on-chip feedback
resistor and duty adjustment circuit is performed when the transition is made to software standby
mode.
Rev.4.00 Sep. 18, 2008 Page 607 of 872
REJ09B0189-0400
Section 16 Clock Pulse Generator
Bit 3
RFCUT
Description
0
System clock oscillator’s on-chip feedback resistor and duty adjustment
circuit are used
(Initial value)
1
System clock oscillator’s on-chip feedback resistor and duty adjustment circuit are not
used
Bit 2—Reserved: This bit can be read or written to, but should only be written with 0.
Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the
frequency multiplication factor of the PLL circuit incorporated into the evaluation chip. The
specified frequency multiplication factor is valid after a transition to software standby mode.
With the LSI, STC1 and STC0 must both be set to 1. After a reset, STC1 and STC0 are both
cleared to 0, and so must be set to 1.
Bit 1
Bit 0
STC1
STC0
Description
0
0
×1
1
×2 (Setting prohibited)
0
×4 (Setting prohibited)
1
PLL is bypassed
1
Rev.4.00 Sep. 18, 2008 Page 608 of 872
REJ09B0189-0400
(Initial value)
Section 16 Clock Pulse Generator
16.3
System Clock Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
16.3.1
Connecting a Crystal Resonator
(1) Circuit Configuration
A crystal resonator can be connected as shown in the example in figure 16.2. Select the damping
resistance Rd according to table 16.2. An AT-cut parallel-resonance crystal should be used.
CL1
EXTAL
XTAL
Rd
CL2
CL1 = CL2 = 10 to 22 pF
Figure 16.2 Connection of Crystal Resonator (Example)
Table 16.2 Damping Resistance Value
Frequency (MHz) 2
4
6
8
10
12
16
Rd (Ω)
500
300
200
100
0
0
1k
(2) Crystal Resonator
Figure 16.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has
the characteristics shown in table 16.3 and the same resonance frequency as the system clock (φ).
CL
L
Rs
XTAL
EXTAL
C0
AT-cut parallel-resonance type
Figure 16.3 Crystal Resonator Equivalent Circuit
Rev.4.00 Sep. 18, 2008 Page 609 of 872
REJ09B0189-0400
Section 16 Clock Pulse Generator
Table 16.3 Crystal Resonator Parameters
Frequency (MHz)
2
4
6
8
10
12
16
RS max (Ω)
500
120
100
80
60
60
50
C0 max (pF)
7
7
7
7
7
7
7
(3) Note on Board Design
When a crystal resonator is connected, the following points should be noted:
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 16.4.
When designing the board, place the crystal resonator and its load capacitors as close as possible
to the XTAL and EXTAL pins.
Avoid
Signal A Signal B
CL2
H8S/2214 Group
XTAL
EXTAL
CL1
Figure 16.4 Example of Incorrect Board Design
Rev.4.00 Sep. 18, 2008 Page 610 of 872
REJ09B0189-0400
Section 16 Clock Pulse Generator
16.3.2
External Clock Input
(1) Circuit Configuration
An external clock signal can be input as shown in the examples in figure 16.5. If the XTAL pin is
left open, make sure that stray capacitance is no more than 10 pF.
In example (b), make sure that the external clock is held high in standby mode, subactive mode,
subsleep mode, and watch mode.
EXTAL
XTAL
External clock input
Open
(a) XTAL pin left open
EXTAL
External clock input
XTAL
(b) Complementary clock input at XTAL pin
Figure 16.5 External Clock Input (Examples)
(2) External Clock
The external clock signal should have the same frequency as the system clock (φ).
Table 16.4 and figure 16.6 show the input conditions for the external clock.
Rev.4.00 Sep. 18, 2008 Page 611 of 872
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Section 16 Clock Pulse Generator
Table 16.4 External Clock Input Conditions
Item
Symbol
Min.
Max.
Unit
Test Conditions
External clock input lowpulse width
tEXL
25
—
ns
Figure 16.6
External clock input high pulse width
tEXH
25
—
ns
External clock rise time
tEXr
—
6.25
ns
External clock fall time
tEXf
—
6.25
ns
Clock low pulse width level
tCL
0.4
0.6
tcyc
φ ≥ 5 MHz Figure 18.3
80
—
ns
φ < 5 MHz
0.4
0.6
tcyc
φ ≥ 5 MHz
80
—
ns
φ < 5 MHz
Clock high pulse width level
tCH
The external clock input conditions when the duty adjustment circuit is not used are shown in
table 16.5 and figure 16.6. When the duty adjustment circuit is not used, the φ output waveform
depends on the external clock input waveform, and so no restrictions apply.
Table 16.5 External Clock Input Conditions when the Duty Adjustment Circuit Is not Used
Item
Symbol
Min.
Max.
Unit
Test Conditions
External clock input low pulse width
tEXL
31.25
—
ns
Figure 16.6
External clock input high pulse width
tEXH
31.25
—
ns
External clock rise time
tEXr
—
6.25
ns
External clock fall time
tEXf
—
6.25
ns
Note: When duty adjustment circuit is not used, the maximum frequency decreases according to
the input waveform. (Example: When tEXL = tEXH = 50 ns, and tEXr = tEXf = 10 ns, clock cycle
time = 120 ns; therefore, maximum operating frequency = 8.3 MHz)
tEXH
tEXL
EXTAL
VCC × 0.5
tEXr
tEXf
Figure 16.6 External Clock Input Timing
Rev.4.00 Sep. 18, 2008 Page 612 of 872
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Section 16 Clock Pulse Generator
(3) Note on Switchover of External Clock
When two or more external clocks (e.g. 10 MHz and 2 MHz) are used as the system clock,
switchover of the input clock should be carried out in software standby mode.
An example of an external clock switching circuit is shown in figure 16.7, and an example of the
external clock switchover timing in figure 16.8.
H8S/2214 Group
Port output
External clock
switchover request
External interrupt signal
External clock
switchover signal
External clock 1
External clock 2
Selector
Control
circuit
External
interrupt
EXTAL
Figure 16.7 Example of External Clock Switching Circuit
Rev.4.00 Sep. 18, 2008 Page 613 of 872
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Section 16 Clock Pulse Generator
External
clock 1
External
clock 2
Operation
Clock switchover
request
SLEEP instruction
execution
Interrupt exception handling
(5)
(1)
Port setting
(2)
External clock
switchover
signal
(3)
EXTAL
Internal
clock ø
Wait time
External
interrupt
200 ns or more (4)
Active (external clock 2)
Software standby mode
Active (external clock 1)
(1)
(2)
(3)
(4)
Port setting (clock switchover)
Software standby mode transition
External clock switchover
External interrupt generation
(Input interrupt at least 200 ns after transition to software standby mode.)
(5) Interrupt exception handling
Figure 16.8 Example of External Clock Switchover Timing
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Section 16 Clock Pulse Generator
16.4
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
16.5
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
16.6
Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/2, φ/4, or φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings
of the SCK2 to SCK0 bits in SCKCR.
16.7
Note on Crystal Resonator
Since various characteristics related to the crystal resonator are closely linked to the user’s board
design, thorough evaluation is necessary on the user’s part, for both the mask versions, and FZTAT versions, using the resonator connection examples shown in this section as a guide. As the
resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting
circuit, the ratings should be determined in consultation with the resonator manufacturer. The
design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator
pin.
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Section 16 Clock Pulse Generator
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Section 17 Power-Down Modes
Section 17 Power-Down Modes
17.1
Overview
In addition to the normal program execution state, the H8S/2214 Group has power-down modes in
which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip supporting modules, and
so on.
The H8S/2214 Group operating modes are as follows:
(1) High-speed mode
(2) Medium-speed mode
(3) Sleep mode
(4) Module stop mode
(5) Software standby mode
(6) Hardware standby mode
Of these, (2) to (6) are power-down modes. Sleep mode is CPU mode, medium-speed mode is a
CPU and bus master mode, and module stop mode is an on-chip supporting module mode
(including bus masters other than the CPU). Certain combinations of these modes can be set.
After a reset, the MCU is in high-speed mode.
Table 17.1 shows the internal chip states in each mode, and table 17.2 shows the conditions for
transition to the various modes. Figure 17.1 shows a mode transition diagram.
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Section 17 Power-Down Modes
Table 17.1 LSI Internal States in Each Mode
Function
MediumHigh-Speed Speed
Sleep
Software
Module Stop Standby
Hardware
Standby
System clock oscillator
Functioning
Functioning
Functioning
Functioning
Halted
Halted
Subclock oscillator
Functioning
Functioning
Functioning
Functioning
Functioning/ Halted
Halted
CPU
operation
Functioning
Mediumspeed
Halted
Functioning
Halted
Halted
Retained
Undefined
Instructions
Registers
Retained
RAM
Functioning
Functioning
Functioning
(DTC)
Functioning
Retained
Retained
I/O
Functioning
Functioning
Functioning
Functioning
Retained
High
impedance
External
interrupts
Functioning
Functioning
Functioning
Functioning
Functioning
Halted
On-chip
DMAC
supporting
DTC
module
operation
WDT0
Functioning
Mediumspeed
Functioning
Functioning/ Halted
(retained)
halted
(retained)
Functioning
TPU
SCI
Halted
(reset)
Functioning
Functioning/
halted
(retained)
D/A
Note: “Halted (retained)” means that internal register values are retained. The internal state is
operation suspended.
“Halted (reset)” means that internal register values and internal states are initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
: Operating state
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Section 17 Power-Down Modes
Program-halted state
Reset state
STBY pin = low
Manual
reset state
Power-on
reset state
MRES = high
STBY pin = high,
RES pin = low
Hardware
standby mode
RES pin = high
Program
execution state
SSBY = 0
High-speed
mode
(main clock)
SCK2 to
SCK0 = 0
SCK2 to
SCK0 ≠ 0
Medium-speed
mode
(main clock)
SLEEP
instruction
Sleep mode
(main clock)
All interrupt
SLEEP
instruction
External
interrupt*
: Transition after exception handling
SSBY = 1
Software
standby mode
: Power-down mode
Notes: * NMI, IRQ0 to IRQ7
• When a transition is made between modes by means of an interrupt, transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting
the interrupt request.
• From any state except hardware standby mode, a transition to the power-on reset state occurs
whenever RES goes low. From any state except hardware standby mode and the power-on reset
state, a transition to the manual reset state occurs whenever MRES goes low.
• From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 17.1 Mode Transitions
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Section 17 Power-Down Modes
17.1.1
Register Configuration
The power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and
MSTPCR registers. Table 17.2 summarizes these registers.
Table 17.2 Power-Down Mode Registers
Name
Abbreviation
R/W
Initial Value
Address*
Standby control register
SBYCR
R/W
H'08
H'FDE4
System clock control register
SCKCR
R/W
H'00
H'FDE6
Module stop control register
MSTPCRA
R/W
H'3F
H'FDE8
MSTPCRB
R/W
H'FF
H'FDE9
MSTPCRC
R/W
H'FF
H'FDEA
Note: * Lower 16 bits of the address.
17.2
Register Descriptions
17.2.1
Standby Control Register (SBYCR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
OPE
—
—
—
0
0
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
—
—
—
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Software Standby (SSBY): Specifies a transition to software standby mode. The SSBY
setting is not changed by a mode transition due to an interrupt, etc.
Bit 7
SSBY
Description
0
Transition to sleep mode after execution of SLEEP instruction
1
Transition to software standby mode after execution of SLEEP instruction
(Initial value)
Transition to subsleep mode after execution of SLEEP instruction in subactive mode
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Section 17 Power-Down Modes
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU
waits for the clock to stabilize when software standby mode is cleared and a transition is made to
high-speed mode or medium-speed mode by means of a specific interrupt or instruction. With
crystal oscillation, refer to table 17.4 and make a selection according to the operating frequency so
that the standby time is at least 8 ms (the oscillation stabilization time). With an external clock,
any selection can be made*.
Note: * In the F-ZTAT version, a 16-state standby time cannot be used with an external clock.
Use 2048 states or more.
Bit 6
Bit 5
Bit 4
STS2
STS1
STS0
Description
0
0
0
Standby time = 8192 states
1
Standby time = 16384 states
1
1
0
1
0
Standby time = 32768 states
1
Standby time = 65536 states
0
Standby time = 131072 states
1
Standby time = 262144 states
0
Standby time = 2048 states
Standby time = 16 states*
1
(Initial value)
Note: * Cannot be used in the F-ZTAT version.
Bit 2 to 0—Reserved: This bit cannot be modified and is always read as 0.
Bit 3—Output Port Enable (OPE): Specifies whether the address bus and bus control signals
(CS0 to CS7, AS, RD, HWR, and LWR) retain their output state or go to the high-impedance state
in software standby mode.
Bit 3
OPE
Description
0
In software standby mode, address bus and bus control signals are high-impedance
1
In software standby mode, address bus and bus control signals retain their output
state
(Initial value)
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Section 17 Power-Down Modes
17.2.2
System Clock Control Register (SCKCR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PSTOP
—
—
—
—
SCK2
SCK1
SCK0
0
0
0
0
0
0
0
0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
SCKCR is an 8-bit readable/writable register that performs φ clock output control and mediumspeed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Description
Bit 7
PSTOP
High–Speed Mode
Medium-Speed Mode
Sleep Mode
Software Standby Hardware
Mode, Watch
Standby Mode
0
φ output (initial value)
φ output
Fixed high
High impedance
1
Fixed high
Fixed high
Fixed high
High impedance
Bits 6 and 3—Reserved: These bits can be read or written to, but should only be written with 0.
Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus
master in high-speed mode and medium-speed mode.
Bit 2
Bit 1
Bit 0
SCK2
SCK1
SCK0
Description
0
0
0
Bus master is in high-speed mode
1
Medium-speed clock is φ/2
0
Medium-speed clock is φ/4
1
Medium-speed clock is φ/8
0
Medium-speed clock is φ/16
1
Medium-speed clock is φ/32
—
—
1
1
0
1
Rev.4.00 Sep. 18, 2008 Page 622 of 872
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(Initial value)
Section 17 Power-Down Modes
17.2.3
Module Stop Control Register (MSTPCR)
MSTPCRA
Bit
:
7
6
5
4
3
2
1
0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
R/W
:
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
MSTPCRB
Bit
:
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
1
1
1
1
1
1
1
1
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
7
6
5
4
3
2
1
0
Initial value :
R/W
MSTPCRC
Bit
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value :
R/W
:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRA, MSTPCRB, and MSTPCRC are 8-bit readable/writable registers that perform module
stop mode control.
MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. MSTPCRB and
MSTPCRC are initialized to H'FF. They are not initialized in software standby mode.
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Section 17 Power-Down Modes
MSTPCRA, MSTPCRB, and MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0, and MSTPC7 to MSTPC0): These bits specify module stop mode. See
table 17.3 for the method of selecting on-chip supporting modules.
MSTPCRA, MSTPCRB, and MSTPCRC
Bits 7 to 0
MSTPA7 to MSTPA0, MSTPB7 to
MSTPB0, and MSTPC7 to MSTPC0
Description
0
Module stop mode is cleared
(Initial value of MSTPA7, MSTPA6)
1
Module stop mode is set
(Initial value of except MSTPA7 to MSTPA6)
17.3
Medium-Speed Mode
When the SCK2 to SCK0 bits in SCKCR are set to 1 in high-speed mode, the operating mode
changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU
operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits.
The bus master other than the CPU (the DMAC and DTC) also operates in medium-speed mode.
On-chip supporting modules other than the bus masters always operate on the high-speed clock
(φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY is cleared to 0, a transition is made to sleep
mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made
to software standby mode. When software standby mode is cleared by an external interrupt,
medium-speed mode is restored.
When the RES pin and MRES pin is driven low, a transition is made to the reset state, and
medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the
watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
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Section 17 Power-Down Modes
Figure 17.2 shows the timing for transition to and clearance of medium-speed mode.
Medium-speed mode
φ,
supporting module
clock
Bus master clock
Internal address
bus
SBYCR
SBYCR
Internal write signal
Figure 17.2 Medium-Speed Mode Transition and Clearance Timing
17.4
Sleep Mode
17.4.1
Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters
sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers
are retained. Other supporting modules do not stop.
17.4.2
Clearing Sleep Mode
Sleep mode is cleared by all interrupts, or with the RES pin, MRES pin or STBY pin.
(1) Clearing with an Interrupt
When an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is
started. Sleep mode will not be cleared if interrupts are disabled, or if interrupts other than NMI
have been masked by the CPU.
(2) Clearing with the RES Pin and MRES Pin
When the RES pin and MRES pin is driven low, the reset state is entered. When the RES pin and
MRES pin is driven high after the prescribed reset input period, the CPU begins reset exception
handling.
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Section 17 Power-Down Modes
(3) Clearing with the STBY Pin
When the STBY pin is driven low, a transition is made to hardware standby mode.
17.5
Module Stop Mode
17.5.1
Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 17.3 shows MSTP bits and the corresponding on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating again at the end of the bus cycle. In module stop mode, the internal states of
modules are retained.
After reset release, all modules other than the DMAC and DTC are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
When a transition is made to sleep mode with all modules stopped (MSTPCR = H'FFFFFF), the
bus controller and I/O ports also stop operating, enabling current dissipation to be further reduced.
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Section 17 Power-Down Modes
Table 17.3 MSTP Bits and Corresponding On-Chip Supporting Modules
Register
MSTPCRA
Bit
Module
MSTPA7
DMA controller (DMAC)
MSTPA6
Data transfer controller (DTC)
MSTPA5
16-bit timer pulse unit (TPU)
—*
MSTPA4
MSTPA3
MSTPA2
MSTPA0
—*
—*
MSTPB7
Serial communication interface 0 (SCI0)
MSTPB6
Serial communication interface 1 (SCI1)
MSTPB5
Serial communication interface 2 (SCI2)
—*
—*
MSTPA1
MSTPCRB
MSTPB4
MSTPB3
MSTPB2
MSTPB1
MSTPB0
MSTPCRC
—*
—*
—*
—*
MSTPC7
External module expansion function
—*
MSTPC6
—*
MSTPC5
D/A converter
—*
MSTPC4
MSTPC3
MSTPC2
MSTPC1
MSTPC0
—*
—*
—*
—*
Note: * Reserved.
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Section 17 Power-Down Modes
17.5.2
Usage Notes
(1) DMAC and DTC Module Stop Mode
Depending on the operating status of the DMAC and DTC, the MSTPA7 and MSTPA6 bits may
not be set to 1. Setting of the DTC module stop mode should be carried out only when the DTC is
not activated.
For details, section 7, DMA Controller (DMAC) and section 8, Data Transfer Controller (DTC).
(2) On-Chip Supporting Module Interrupts
Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module
stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU
interrupt source, DMAC, or DTC activation source. Interrupts should therefore be disabled before
setting module stop mode.
(3) Writing to MSTPCR
MSTPCR should be written to only by the CPU.
17.6
Software Standby Mode
17.6.1
Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in
software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and
oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states
of on-chip supporting module, and of the I/O ports, are retained. The address bus and bus control
signals are placed in the high-impedance state.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
Rev.4.00 Sep. 18, 2008 Page 628 of 872
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Section 17 Power-Down Modes
17.6.2
Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ7), or by
means of the RES pin, MRES pin or STBY pin.
(1) Clearing with an Interrupt
When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and after
the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire
H8S/2214 chip, software standby mode is cleared, and interrupt exception handling is started.
When software standby mode is cleared with an IRQ0 to IRQ7 interrupt, set the corresponding
enable bit to 1 and ensure that an interrupt of higher priority than interrupts IRQ0 to IRQ7 is not
generated. Software standby mode cannot be cleared if the interrupt has been masked by the CPU
side or has been designated as a DTC activation source.
(2) Clearing with the RES Pin and MRES Pin
When the RES pin and MRES pin are driven low, clock oscillation is started. At the same time as
clock oscillation starts, clocks are supplied to the entire H8S/2214 chip. Note that the RES pin and
MRES pin must be held low until clock oscillation stabilizes. When the RES pin and MRES pin
go high, the CPU begins reset exception handling.
(3) Clearing with the STBY Pin
When the STBY pin is driven low, a transition is made to hardware standby mode.
17.6.3
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
(1) Using a Crystal Oscillator
Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time).
Table 17.4 shows the standby times for different operating frequencies and settings of bits STS2 to
STS0.
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Section 17 Power-Down Modes
Table 17.4 Oscillation Stabilization Time Settings
STS2 STS1 STS0 Standby Time 16 MHz 13 MHz 10 MHz 8 MHz
6 MHz
4 MHz
2 MHz
Unit
0
4.1
ms
0
1
1
0
1
0
8192 states
0.51
0.63
0.82
1.0
1.4
2.0
1
16384 states
1.0
1.3
1.6
2.0
2.7
4.1
0
32768 states
2.0
2.5
3.3
4.1
5.5
1
65536 states
4.1
5.0
6.6
0
131072 states
1
262144 states
16.4
20.2
0
2048 states
0.13
1
16 states
1.0
8.2
10.1
13.1
8.2
10.9
8.2
8.2
16.4
16.4
32.8
16.4
21.8
32.8
65.5
26.2
32.8
43.7
65.5
131.1
0.16
0.20
0.26
0.34
0.51
1.0
1.2
1.6
2.0
2.7
4.0
8.0
µs
: Recommended time setting
(2) Using an External Clock
Any value can be set. Normally, use of the minimum time is recommended.
Note: In the F-ZTAT version, a 16-state standby time cannot be used with an external clock. Use
2048 states or more.
17.6.4
Software Standby Mode Application Example
Figure 17.3 shows an example in which a transition is made to software standby mode at the
falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.
Rev.4.00 Sep. 18, 2008 Page 630 of 872
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Section 17 Power-Down Modes
Oscillator
φ
NMI
NMIEG
SSBY
NMI
exception
handling
NMIEG = 1
SSBY = 1
Software standby mode
(power-down mode)
Oscillation
stabilization
time (tOSC2)
NMI exception
handling
SLEEP instruction
Figure 17.3 Software Standby Mode Application Example
17.6.5
Usage Notes
(1) I/O Port States
In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus
and bus control signal output is also retained. Therefore, there is no reduction in current
dissipation for the output current when a high-level signal is output.
(2) Current Dissipation During the Oscillation Stabilization Wait Period
Current dissipation increases during the oscillation stabilization wait period.
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Section 17 Power-Down Modes
17.7
Hardware Standby Mode
17.7.1
Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low.
Do not change the state of the mode pins (MD2 to MD0) while the H8S/2214 is in hardware
standby mode.
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY
pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.
Ensure that the RES pin is held low until the clock oscillation stabilizes (at least tosc1 —the
oscillation stabilization time—when using a crystal oscillator). When the RES pin is subsequently
driven high, a transition is made to the program execution state via the reset exception handling
state.
17.7.2
Hardware Standby Mode Timing
Figure 17.4 shows an example of hardware standby mode timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting
for the oscillation stabilization time, then changing the RES pin from low to high.
Rev.4.00 Sep. 18, 2008 Page 632 of 872
REJ09B0189-0400
Section 17 Power-Down Modes
Oscillator
RES
STBY
Oscillation
stabilization
time (tOSC1)
Reset exception
handling
Figure 17.4 Hardware Standby Mode Timing (Example)
17.8
φ Clock Output Disabling Function
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR and the
corresponding DDR bit. When the PSTOP bit is set to 1, the φ clock is stopped at the end of the
bus cycle, and φ output goes high. φ clock output is enabled when PSTOP bit is cleared to 0. When
DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is
set. Table 17.5 shows the state of the φ pin in each processing mode.
Table 17.5 φ Pin State in Each Processing Mode
DDR
0
1
1
PSTOP
Hardware standby mode
—
0
1
High impedance
High impedance High impedance
Software standby mode
High impedance
Fixed high
Fixed high
Sleep mode
High impedance
φ output
Fixed high
High-speed mode, medium-speed mode
High impedance
φ output
Fixed high
Rev.4.00 Sep. 18, 2008 Page 633 of 872
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Section 17 Power-Down Modes
Rev.4.00 Sep. 18, 2008 Page 634 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
Section 18 Electrical Characteristics
18.1
Absolute Maximum Ratings
Table 18.1 lists the absolute maximum ratings.
Table 18.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +4.6
V
Input voltage (except port 9)
Vin
–0.3 to VCC +0.3
V
Input voltage (port 9)
Vin
–0.3 to AVCC +0.3
V
Reference voltage
Vref
–0.3 to AVCC +0.3
V
Analog power supply voltage
AVCC
–0.3 to +4.6
V
Operating temperature
Topr
Regular specifications: –20 to +75*
°C
Wide-range specifications: –40 to +85*
°C
–55 to +125
°C
Storage temperature
Tstg
Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.
Note: * The operating temperature ranges for flash memory programming/erasing are Ta = –20 to
+75°C.
Rev.4.00 Sep. 18, 2008 Page 635 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
18.2
Power Supply Voltage and Operating Frequency Range
Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 18.1.
(1) Power Supply Voltage and Oscillation Frequency Range
f (MHz)
16.0
System clock
10.0
2.0
0
2.7
3.0
3.6 Vcc (V)
• Active (high-speed/medium-speed) mode
• Sleep mode
(2) Power Supply Voltage and Instruction Execution Time Range
(ns)
62.5
System clock
100
500
0
2.7
3.0
3.6 Vcc (V)
• Active (high-speed/medium-speed) mode
Figure 18.1 Power Supply Voltage and Operating Ranges
Rev.4.00 Sep. 18, 2008 Page 636 of 872
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Section 18 Electrical Characteristics
18.3
DC Characteristics
Tables 18.2 to 18.4 list the DC characteristics. Table 18.5 lists the permissible output currents.
Table 18.2 DC Characteristics (1)
Condition:
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC,
VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)*
Item
Symbol
Min.
Typ.
Max.
Unit
VCC × 0.2
—
—
V
—
—
VCC × 0.8
V
Test Conditions
Schmitt
trigger input
voltage
IRQ7 to IRQ0, VT
+
EXIRQ0 to
VT
EXIRQ7
+
–
VT – VT
VCC × 0.05 —
—
V
Input high
voltage
RES, STBY, VIH
NMI, MD2
to MD0, FWE
VCC × 0.9
—
VCC + 0.3
V
EXTAL,
ports 1, 3, 4,
7, A to G
VCC × 0.8
—
VCC + 0.3
V
Port 9
VCC × 0.8
—
AVCC + 0.3 V
–0.3
—
VCC × 0.1
V
NMI, EXTAL,
ports 1, 3, 4,
7, 9, A to G
–0.3
—
VCC × 0.2
V
Output high
voltage
All output pins VOH
VCC – 0.5
—
—
V
VCC – 1.0
—
—
V
IOH = –1 mA
Output low
voltage
All output pins VOL
—
—
0.4
V
IOL = 0.4 mA
Input leakage
current
RES
Input low
voltage
–
RES, STBY,
FWE,
MD2 to MD0
VIL
IOH = –200 µA
—
—
0.4
V
IOL = 0.8 mA
—
—
1.0
µA
STBY, NMI,
MD2 to MD0,
port 4
—
—
1.0
µA
Vin =
0.5 to VCC – 0.5 V
Port 9
—
—
1.0
µA
| Iin |
Vin =
0.5 to AVCC – 0.5 V
Rev.4.00 Sep. 18, 2008 Page 637 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
Item
Three-state
leakage
current
(off state)
Ports 1, 3, 7,
A to G
MOS input
Ports A to E
pull-up current
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
⏐ITSI⏐
—
—
1.0
µA
Vin =
0.5 to VCC – 0.5 V
–IP
10
—
300
µA
Vin = 0 V
Note: * If the D/A converter is not used, do not leave the AVCC, Vref, and AVSS pins open. Apply a
voltage between 2.0 V and 3.6 V to the AVCC and Vref pins by connecting them to VCC, for
instance. Set Vref = AVCC.
Rev.4.00 Sep. 18, 2008 Page 638 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
Table 18.3 DC Characteristics (2)
Conditions: F-ZTAT version: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC,
VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications),
1
Ta = –40°C to +85°C (wide-range specifications)*
Item
Input
capacitance
Current
2
dissipation*
Symbol Min.
Typ.
Max.
Unit
Test Conditions
—
—
30
pF
Vin = 0 V
NMI
—
—
30
pF
f = 1 MHz
All input pins
except RES
and NMI
—
—
15
pF
Ta = 25°C
—
20
36.0
mA
VCC = 3.0 V VCC = 3.6 V
f = 16 MHz
Sleep mode
—
13
26.0
mA
VCC = 3.0 V VCC = 3.6 V
f = 16 MHz
All modules
stopped
—
14
—
mA
f = 16 MHz,
VCC = 3.0 V
(reference
values)
Medium-speed
mode (φ/32)
—
9
—
mA
f = 16 MHz,
VCC = 3.0 V
(reference
values)
µA
Ta ≤ 50°C
RES
Normal
operation
Cin
4
ICC*
Standby
3
mode*
Analog power During D/A
supply current conversion
AlCC
Idle
Reference
current
During D/A
conversion
AlCC
Idle
RAM standby voltage
VRAM
—
1.0
10
—
—
50
—
0.01
5
mA
—
0.01
5
µA
—
1.0
1.8
mA
—
0.01
5
µA
2.0
—
—
V
50°C < Ta
AVCC = 3.0 V
Vref = 3.0 V
Notes: 1. If the D/A converter is not used, do not leave the AVCC, Vref, and AVSS pins open. Apply a
voltage between 2.0 V and 3.6 V to the AVCC and Vref pins by connecting them to VCC, for
instance. Set Vref = AVCC.
2. Current dissipation values are for VIH (min.) = VCC – 0.3 V, VIL (max.) = 0.3 V with all
output pins unloaded and the on-chip pull-up resistors in the off state.
3. The values are for VRAM ≤ VCC < 2.7 V, VIH (min.) = VCC × 0.9, and VIL (max.) = 0.3 V.
Rev.4.00 Sep. 18, 2008 Page 639 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
4. ICC depends on VCC and f as follows:
ICC (max.) = 1.0 (mA) + 0.61 (mA/(MHz × V)) × VCC × f (normal operation)
ICC (max.) = 1.0 (mA) + 0.44 (mA/(MHz × V)) × VCC × f (sleep mode)
Table 18.4 DC Characteristics (3)
Conditions: Masked ROM version: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC,
VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range
1
specifications)*
Item
Input
capacitance
Current
2
dissipation*
Symbol Min.
Typ.
Max.
Unit
Test Conditions
—
—
30
pF
Vin = 0 V
NMI
—
—
30
pF
f = 1 MHz
All input pins
except RES
and NMI
—
—
15
pF
Ta = 25°C
—
20
36
mA
VCC = 3.0 V VCC = 3.6 V
f = 16 MHz
Sleep mode
—
13
26
mA
VCC = 3.0 V VCC = 3.6 V
f = 16 MHz
All modules
stopped
—
14
—
mA
f = 16 MHz,
VCC = 3.0 V
(reference
values)
Medium-speed
mode (φ/32)
—
9
—
mA
f = 16 MHz,
VCC = 3.0 V
(reference
values)
Standby
3
mode*
—
1.0
10
µA
Ta ≤ 50°C
—
—
50
—
0.01
5
mA
—
0.01
5
µA
—
1.0
1.8
mA
—
0.01
5
µA
2.0
—
—
V
RES
Normal
operation
Analog power During D/A
supply current conversion
Cin
4
ICC*
AlCC
Idle
Reference
current
During D/A
conversion
AlCC
Idle
RAM standby voltage
VRAM
Rev.4.00 Sep. 18, 2008 Page 640 of 872
REJ09B0189-0400
50°C < Ta
AVCC = 3.0 V
Vref = 3.0 V
Section 18 Electrical Characteristics
Notes: 1. If the D/A converter is not used, do not leave the AVCC, Vref, and AVSS pins open. Apply a
voltage between 2.0 V and 3.6 V to the AVCC and Vref pins by connecting them to VCC, for
instance. Set Vref = AVCC.
2. Current dissipation values are for VIH (min.) = VCC – 0.3 V, VIL (max.) = 0.3 V with all
output pins unloaded and the on-chip pull-up resistors in the off state.
3. The values are for VRAM ≤ VCC < 2.7 V, VIH (min.) = VCC × 0.9, and VIL (max.) = 0.3 V.
4. ICC depends on VCC and f as follows:
ICC (max.) = 1.0 (mA) + 0.61 (mA/(MHz × V)) × VCC × f (normal operation)
ICC (max.) = 1.0 (mA) + 0.44 (mA/(MHz × V)) × VCC × f (sleep mode)
Table 18.5 Permissible Output Currents
Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC, VSS = AVSS = 0 V,
Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)*
Item
Symbol
Min.
Typ.
Max.
Unit
Permissible output
low current (per pin)
All output
pins
VCC = 2.7 to 3.6 V
IOL
—
—
1.0
mA
Permissible output
low current (total)
Total of all
output pins
VCC = 2.7 to 3.6 V
∑ IOL
—
—
60
mA
Permissible output
All output
high current (per pin) pins
VCC = 2.7 to 3.6 V
–IOH
—
—
1.0
mA
Permissible output
high current (total)
VCC = 2.7 to 3.6 V
∑ –IOH
—
—
30
mA
Total of all
output pins
Note: * To protect chip reliability, do not exceed the output current values in table 18.5.
Rev.4.00 Sep. 18, 2008 Page 641 of 872
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Section 18 Electrical Characteristics
18.4
AC Characteristics
Figure 18.2 shows, the test conditions for the AC characteristics.
3V
RL
RL = 2.4 kΩ
RH = 12 kΩ
LSI output pin
C
C = 30 pF:
RH
I/O timing test levels
• Low level: 0.8 V
• High level: 2.0 V (VCC: 2.7 to 3.6 V)
Figure 18.2 Output Load Circuit
18.4.1
Clock Timing
Table 18.6 lists the clock timing
Table 18.6 Clock Timing
Condition:
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC, VSS = AVSS = 0 V,
φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min.
Max.
Unit
Test Conditions
Clock cycle time
tcyc
62.5
500
ns
Figure 18.3
Clock high pulse width
tCH
20
—
ns
Clock low pulse width
tCL
20
—
ns
Clock rise time
tCr
—
10
ns
Clock fall time
tCf
—
10
ns
Clock oscillator settling
time at reset (crystal)
tOSC1
20
—
ms
Figure 18.4
Clock oscillator settling time
in software standby (crystal)
tOSC2
8
—
ms
Figure 17.3
500
—
µs
Figure 18.4
External clock output stabilization tDEXT
delay time
Rev.4.00 Sep. 18, 2008 Page 642 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
tcyc
tCH
tCf
φ
tCL
tCr
Figure 18.3 System Clock Timing
EXTAL
tDEXT
tDEXT
VCC
STBY
tOSC1
tOSC1
RES
φ
Figure 18.4 Oscillator Settling Timing
Rev.4.00 Sep. 18, 2008 Page 643 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
18.4.2
Control Signal Timing
Table 18.7 lists the control signal timing.
Table 18.7 Control Signal Timing
Condition:
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC, VSS = AVSS = 0 V,
φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min.
Max.
Unit
Test Conditions
RES setup time
tRESS
250
—
ns
Figure 18.5
RES pulse width
tRESW
20
—
tcyc
MRES setup time
tMRESS
250
—
ns
MRES pulse width
tMRESW
20
—
tcyc
NMI setup time
tNMIS
250
—
ns
NMI hold time
tNMIH
10
—
NMI pulse width (exiting software tNMIW
standby mode)
200
—
ns
IRQ setup time
tIRQS
250
—
ns
IRQ hold time
tIRQH
10
—
ns
200
—
ns
IRQ pulse width (exiting software tIRQW
standby mode)
Figure 18.6
φ
tRESS
tRESS
tMRESS
tMRESS
RES
tRESW
MRES
tMRESW
Figure 18.5 Reset Input Timing
Rev.4.00 Sep. 18, 2008 Page 644 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
φ
tNMIH
tNMIS
NMI
tNMIW
IRQ
tIRQW
tIRQS
tIRQH
IRQ
Edge input
tIRQS
IRQ
Level input
Figure 18.6 Interrupt Input Timing
Rev.4.00 Sep. 18, 2008 Page 645 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
18.4.3
Bus Timing
Table 18.8 lists the bus timing.
Table 18.8 Bus Timing
Condition:
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC, VSS = AVSS = 0 V,
φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min.
Max.
Unit
Test Conditions
Address delay time
tAD
—
50
ns
Address setup time
tAS
0.5 × tcyc – 30 —
ns
Figure 18.7,
Figure 18.8,
Figure 18.10
Address hold time
tAH
0.5 × tcyc – 15 —
ns
CS delay time
tCSD
—
50
ns
Figure 18.7,
Figure 18.8
AS delay time
tASD
—
50
ns
Figure 18.7,
Figure 18.8,
Figure 18.10
RD delay time 1
tRSD1
—
50
ns
Figure 18.7,
Figure 18.8
RD delay time 2
tRSD2
—
50
ns
Figure 18.7,
Figure 18.8,
Figure 18.10
Read data setup time
tRDS
30
—
ns
Read data hold time
tRDH
0
—
ns
Figure 18.7,
Figure 18.8,
Figure 18.10
Read data access time 2
tACC2
—
1.5 × tcyc – 65 ns
Figure 18.7
Read data access time 3
tACC3
—
2.0 × tcyc – 65 ns
Figure 18.7,
Figure 18.10
Read data access time 4
tACC4
—
2.5 × tcyc – 65 ns
Figure 18.8
Read data access time 5
tACC5
—
3.0 × tcyc – 65 ns
WR delay time 1
tWRD1
—
50
ns
WR delay time 2
tWRD2
—
50
ns
Figure 18.7,
Figure 18.8
WR pulse width 1
tWSW1
1.0 × tcyc – 30 —
ns
Figure 18.7
WR pulse width 2
tWSW2
1.5 × tcyc – 30 —
ns
Figure 18.8
Rev.4.00 Sep. 18, 2008 Page 646 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
Item
Symbol
Min.
Max.
Unit
Test Conditions
Write data delay time
tWDD
—
70
ns
Figure 18.7,
Figure 18.8
Write data setup time
tWDS
0.5 × tcyc – 30 —
ns
Figure 18.8
Write data hold time
tWDH
0.5 × tcyc – 15 —
ns
Figure 18.7,
Figure 18.8
WAIT setup time
tWTS
50
—
ns
Figure 18.9
WAIT hold time
tWTH
10
—
ns
BREQ setup time
tBRQS
50
—
ns
BACK delay time
tBACD
—
50
ns
Bus-floating time
tBZD
—
80
ns
Figure 18.11
Rev.4.00 Sep. 18, 2008 Page 647 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
T1
T2
φ
tAD
A23 to A0
tCSD
tAH
tAS
CS7 to CS0
tASD
tASD
AS
tRSD1
RD
(read)
tRSD2
tACC2
tAS
tACC3
tRDS tRDH
D15 to D0
(read)
tWRD2
HWR, LWR
(write)
tWRD2
tAH
tAS
tWDD
tWSW1
tWDH
D15 to D0
(write)
Figure 18.7 Basic Bus Timing/Two-State Access
Rev.4.00 Sep. 18, 2008 Page 648 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
T1
T2
T3
φ
tAD
A23 to A0
tCSD
tAS
tAH
CS7 to CS0
tASD
tASD
AS
tRSD1
RD
(read)
tACC4
tRSD2
tAS
tRDS tRDH
tACC5
D15 to D0
(read)
tWRD1
tWRD2
HWR, LWR
(write)
tAH
tWDD tWDS
tWSW2
tWDH
D15 to D0
(write)
Figure 18.8 Basic Bus Timing/Three-State Access
Rev.4.00 Sep. 18, 2008 Page 649 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
T1
T2
TW
T3
φ
A23 to A0
CS7 to CS0
AS
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
tWTS tWTH
tWTS tWTH
WAIT
Figure 18.9 Basic Bus Timing/Three-State Access with One Wait State
Rev.4.00 Sep. 18, 2008 Page 650 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
T1
T2 or T3
T1
T2
φ
tAD
A23 to A0
tAH
tAS
CS0
tASD
tASD
AS
tRSD2
RD
(read)
tACC3
tRDS
tRDH
D15 to D0
(read)
Figure 18.10 Burst ROM Access Timing/Two-State Access
Rev.4.00 Sep. 18, 2008 Page 651 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
φ
tBRQS
tBRQS
BREQ
tBACD
tBACD
BACK
tBZD
A23 to A0,
CS7 to CS0,
AS, RD,
HWR, LWR
Figure 18.11 External Bus Release Timing
Rev.4.00 Sep. 18, 2008 Page 652 of 872
REJ09B0189-0400
tBZD
Section 18 Electrical Characteristics
18.4.4
Timing of On-Chip Supporting Modules
Table 18.9 lists the timing of on-chip supporting modules.
Table 18.9 Timing of On-Chip Supporting Modules
Condition:
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC, VSS = AVSS = 0 V,
φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min.
Max.
Unit.
Test Conditions
I/O port Output data delay time
tPWD
—
100
ns
Figure 18.12
Input data setup time
tPRS
50
—
Input data hold time
tPRH
50
—
Timer output delay time
tTOCD
—
100
ns
Figure 18.13
Timer input setup time
tTICS
40
—
Timer clock input setup time
Figure 18.14
TPU
SCI
tTCKS
40
—
ns
Timer clock
pulse width
Single edge
tTCKWH
1.5
—
tcyc
Both edges
tTCKWL
2.5
—
Input clock
cycle
Asynchronous
tScyc
4
—
6
—
Synchronous
tcyc
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
1.5
tcyc
Input clock fall time
tSCKf
—
1.5
Transmit data delay time
tTXD
—
100
ns
Receive data setup time
(synchronous)
tRXS
75
—
ns
Receive data hold time
(synchronous)
tRXH
75
—
ns
Figure 18.15
Figure 18.16
Rev.4.00 Sep. 18, 2008 Page 653 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
T1
T2
φ
tPRS
tPRH
Ports 1, 3, 4, 7, 9
A to G (read)
tPWD
Ports 1, 3, 7
A to G (write)
Figure 18.12 I/O Port Input/Output Timing
φ
tTOCD
Output compare
output*
tTICS
Input capture
input*
Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3
Figure 18.13 TPU Input/Output Timing
φ
tTCKS
tTCKS
TCLKA to TCLKD
tTCKWL
tTCKWH
Figure 18.14 TPU Clock Input Timing
Rev.4.00 Sep. 18, 2008 Page 654 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCK0 to SCK3
tScyc
Figure 18.15 SCK Clock Input Timing
SCK0 to SCK3
tTXD
TxD0 to TxD3
(transit data)
tRXS
tRXH
RxD0 to RxD3
(receive data)
Figure 18.16 SCI Input/Output Timing/Clock Synchronous Mode
Rev.4.00 Sep. 18, 2008 Page 655 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
18.4.5
DMAC Timing
Table 18.10 lists the DMAC timing.
Table 18.10 DMAC Timing
Condition:
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC, VSS = AVSS = 0 V,
φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min.
Max.
Unit
Test Conditions
DREQ setup time
tDRQS
40
—
ns
Figure 18.18
DREQ hold time
tDRQH
10
—
DREQ delay time
tTED
—
50
T1
Figure 18.17
T2 or T3
φ
tTED
tTED
TEND
Figure 18.17 DMAC TEND Output Timing
φ
tDRQS
tDRQH
DREQ
Figure 18.18 DMAC DREQ Output Timing
Rev.4.00 Sep. 18, 2008 Page 656 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
18.5
D/A Convervion Characteristics
Table 18.11 lists the D/A conversion characteristics.
Table 18.11 D/A Conversion Characteristics
Condition:
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC,VSS = AVSS = 0 V,
φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Min.
Typ.
Max.
Unit
Test Conditions
Resolution
8
8
8
bit
Conversion time
—
—
10
µs
Absolute accuracy
—
±2.0
±3.0
LSB
2-MΩ resistive load
—
—
±2.0
LSB
4-MΩ resistive load
20-pF capacitive load
Rev.4.00 Sep. 18, 2008 Page 657 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
18.6
Flash Memory Characteristics
Table 18.12 lists the flash memory characteristics.
Table 18.12 Flash Memory Characteristics
Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC, VSS = AVSS = 0 V,
VCC = 3.0 V to 3.6 V(program/erase operating voltage range),
Ta = -20°C to +75°C (program/erase operating temperature range)
Item
Symbol Min.
Typ.
Max.
Unit
Programming time*1 *2 *4
tP
—
40
200
ms/128
bytes
Erase time*1 *3 *5
tE
—
NWEC
t *8
20
1000
100*6 10000*7 —
ms/block
Rewrite time
10
—
—
Years
tsswe
1
1
—
µs
tspsu
50
50
—
µs
tsp10
8
10
12
µs
Data retention time
Programming Wait time after SWE1 bit setting*1
Wait time after PSU1 bit setting*1
Wait time after P1 bit setting*1 *4
DRP
Times
tsp30
28
30
32
µs
1≤n≤6
tsp200
198
200
202
µs
7 ≤ n ≤ 1000
Wait time after P1 bit clearing*1
tcp
5
5
—
µs
Wait time after PSU1 bit clearing*1
Wait time after PV1 bit setting*1
tcpsu
5
5
—
µs
tspv
4
4
—
µs
Wait time after H'FF dummy write*1 tspvr
Wait time after PV1 bit clearing*1
tcpv
Wait time after SWE1 bit clearing*1 t
2
2
—
µs
2
2
—
µs
100
100
Maximum number of writes*1 *4
N1
—
—
—
6*4
Times
N2
—
—
994*4 Times
cswe
Erasing
Test
Conditions
µs
Wait time after SWE1 bit setting*1
Wait time after ESU1 bit setting*1
tsswe
1
1
—
tsesu
100
100
—
µs
Wait time after E1 bit setting*1 *5
Wait time after E1 bit clearing*1
tse
10
10
100
ms
µs
tce
10
10
—
µs
tcesu
10
10
—
µs
tsev
1
*
Wait time after H'FF dummy write
tsevr
Wait time after EV1 bit clearing*1
tsev
Wait time after SWE1 bit clearing*1 t
20
20
—
µs
2
2
—
µs
4
4
—
µs
100
100
—
µs
—
—
100
Times
Wait time after ESU1 bit clearing*1
Wait time after EV1 bit setting*1
cswe
Maximum number of erases*1 *5
N
Notes: 1. Follow the program/erase algorithms when making the time settings.
Rev.4.00 Sep. 18, 2008 Page 658 of 872
REJ09B0189-0400
Section 18 Electrical Characteristics
2. Programming time per 128 bytes (Indicates the total time during which the P1 bit is set
in flash memory control register 1 (FLMCR1). Does not include the program-verify
time).
3. Time to erase one block (Indicates the time during which the E1 bit is set in FLMCR1.
Does not include the erase-verify time).
4. Maximum programming time.
tP (max.) = Wait time after P1 bit setting (tsp) × maximum number of writes (N)
= (tsp30 + tsp10) × 6 + (tsp200) × 994
5. For the maximum erase time (tE) (max.), the following relationship applies between the
wait time after E1 bit setting (tse) and the maximum number of erase (N):
tE (max.) = Wait time after E1 bit setting (tse) × maximum number of erases (N)
6. Minimum times that guarantee all characteristics after programming (The guaranteed
range is 1 to the minimum value).
7. Reference value when the temperature is 25°C (it is reference that reprogramming is
normally enabled up to this value).
8. Data hold characteristics when reprogramming is performed within the range of
specifications including the minimum value.
18.7
Usage Note
• Characteristics of the F-ZTAT and Mask ROM Versions
Although both the F-ZTAT and masked ROM versions fully meet the electrical specifications
listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the
layout patterns, there will be differences in the actual values of the electrical characteristics,
the operating margins, the noise margins, and other aspects.
Therefore, if a system is evaluated using the F-ZTAT version, a similar evaluation should also
be performed using the masked ROM version.
• General Notes on Printed Circuit Board Deign
Circuit board designs for this IC must include adequate countermeasures to minimize radiated
noise due to the transient currents that occur during IC switching.
1. The circuit board must have both a power plane and a ground plane. A multilayer board
must be used. We present a concrete noise countermeasure example below.
2. Bypass capacitors (about 0.1 µF) must be inserted between the VCC and ground pins.
Rev.4.00 Sep. 18, 2008 Page 659 of 872
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Section 18 Electrical Characteristics
Rev.4.00 Sep. 18, 2008 Page 660 of 872
REJ09B0189-0400
Appendix A Instruction Set
Appendix A Instruction Set
A.1
Instruction List
Operand Notation
Rs
General register (destination)*
1
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
MAC
2
Multiply-and-accumulate register (32-bit register)*
(EAd)
Destination operand
Rd
1
1
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Add
–
Subtract
×
Multiply
÷
Divide
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Transfer from the operand on the left to the operand on the right, or
transition from the state on the left to the state on the right
¬
Logical NOT (logical complement)
( ) < >
Contents of operand
:8/:16/:24/:32
8-, 16-, 24-, or 32-bit length
Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
2. The MAC register cannot be used in the H8S/2214.
Rev.4.00 Sep. 18, 2008 Page 661 of 872
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Appendix A Instruction Set
Condition Code Notation
Symbol
Changes according to the result of instruction
*
Undetermined (no guaranteed value)
0
Always cleared to 0
1
Always set to 1
—
Not affected by execution of the instruction
Rev.4.00 Sep. 18, 2008 Page 662 of 872
REJ09B0189-0400
MOV
B 2
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W 4
W
W
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
Operand Size
MOV.B Rs,Rd
#xx
MOV.B #xx:8,Rd
Mnemonic
Rn
2
2
@ERn
2
2
2
@(d,ERn)
8
4
8
4
@–ERn/@ERn+
2
2
@aa
6
4
2
6
4
2
— —
— —
— —
— —
— —
— —
— —
— —
Rs8→@(d:32,ERd)
Rs8→@aa:8
Rs8→@aa:16
Rs8→@aa:32
#xx:16→Rd16
Rs16→Rd16
@ERs→Rd16
— —
Rs8→@(d:16,ERd)
ERd32-1→ERd32,Rs8→@ERd
— —
— —
— —
@aa:16→Rd8
Rs8→@ERd
— —
@aa:8→Rd8
@aa:32→Rd8
— —
— —
@(d:16,ERs)→Rd8
— —
— —
@ERs→Rd8
@ERs→Rd8,ERs32+1→ERs32
— —
@(d:32,ERs)→Rd8
— —
Rs8→Rd8
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
2
1
2
4
3
2
3
5
3
2
4
3
2
3
5
3
2
1
1
Advanced
I H N Z V C
#xx:8→Rd8
Operation
No. of States*1
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
Table A.1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Data Transfer Instructions
Rev.4.00 Sep. 18, 2008 Page 663 of 872
REJ09B0189-0400
MOV
W
W
W
W
W
W
W
W
W
W
L 6
L
L
L
L
L
L
L
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,ERd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16,ERd
MOV.L @aa:32,ERd
#xx
MOV.W @(d:32,ERs),Rd
W
Operand Size
MOV.W @(d:16,ERs),Rd
Mnemonic
Rn
2
@ERn
Rev.4.00 Sep. 18, 2008 Page 664 of 872
REJ09B0189-0400
4
2
@(d,ERn)
10
6
8
4
8
4
@–ERn/@ERn+
4
2
2
@aa
8
6
6
4
6
4
— —
— —
— —
— —
— —
@aa:32→Rd16
Rs16→@ERd
Rs16→@(d:16,ERd)
Rs16→@(d:32,ERd)
— —
@(d:32,ERs)→ERd32
— —
— —
@(d:16,ERs)→ERd32
@aa:32→ERd32
— —
@ERs→ERd32
— —
— —
ERs32→ERd32
— —
— —
#xx:32→ERd32
@ERs→ERd32,ERs32+4→@ERs32
— —
Rs16→@aa:32
@aa:16→ERd32
— —
Rs16→@aa:16
ERd32-2→ERd32,Rs16→@ERd — —
— —
@aa:16→Rd16
@ERs→Rd16,ERs32+2→ERs32 — —
@(d:32,ERs)→Rd16
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
6
5
5
7
5
4
1
3
4
3
3
5
3
2
4
3
3
5
3
Advanced
0 —
I H N Z V C
— —
Operation
@(d:16,ERs)→Rd16
No. of States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
#xx
— — — — — —
(@SP→ERn32,SP+4→SP)
— — — — — —
0 —
0 —
7/9/11 [1]
7/9/11 [1]
5
3
Note: * The STM/LDM instructions may only be used with the ER0 to ER6 registers.
Repeated for each register saved
[2]
(SP-4→SP,ERn32→@SP)
Repeated for each register restored
— —
SP-4→SP,ERn32→@SP
5
MOVTPE Rs,@aa:16
4
4
— —
SP-2→SP,Rn16→@SP
0 —
6
3
MOVTPE
L
LDM @SP+,(ERm-ERn)
2
4
— —
@SP→ERn32,SP+4→SP
0 —
5
5
7
5
[2]
L
PUSH.L ERn
— —
@SP→Rn16,SP+2→SP
0 —
— —
ERs32→@aa:32
0 —
— —
ERs32→@aa:16
0 —
0 —
4
Cannot be used in the H8S/2214 Group
W
PUSH.W Rn
4
— —
ERs32→@(d:32,ERd)
0 —
0 —
Cannot be used in the H8S/2214 Group
L
POP.L ERn
2
— —
ERd32-4→ERd32,ERs32→@ERd — —
— —
ERs32→@(d:16,ERd)
Advanced
I H N Z V C
ERs32→@ERd
Operation
MOVFPE @aa:16,Rd
W
POP.W Rn
8
6
@aa
MOVFPE
L
MOV.L ERs,@aa:32
@–ERn/@ERn+
4
@(d,PC)
L
L
MOV.L ERs,@aa:16
@@aa
STM (ERm-ERn),@-SP
L
MOV.L ERs,@-ERd
10
Rn
MOV.L ERs,@(d:32,ERd) L
4
@ERn
6
L
@(d,ERn)
MOV.L ERs,@(d:16,ERd) L
MOV.L ERs,@ERd
—
STM*
LDM*
PUSH
POP
MOV
Operand Size
Mnemonic
No. of States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 665 of 872
REJ09B0189-0400
B
L
L
L
B
W
W
L
L
B
B
W 4
ADDX Rs,Rd
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
INC.B Rd
INC.W #1,Rd
INC.W #2,Rd
INC.L #1,ERd
INC.L #2,ERd
DAA Rd
SUB.B Rs,Rd
SUB.W #xx:16,Rd
DAA
SUB
INC
ADDS
ADDX
L
L 6
ADD.L #xx:32,ERd
B 2
W
ADD.W Rs,Rd
ADDX #xx:8,Rd
B
W 4
ADD.W #xx:16,Rd
B 2
ADD.B Rs,Rd
Operand Size
ADD.B #xx:8,Rd
#xx
ADD.L ERs,ERd
ADD
Rn
2
2
2
2
2
2
2
2
2
2
2
2
2
2
I H N Z V C
1
1
1
1
1
1
1
1
1
1
—— — —— —
—— — —— —
—— — —— —
—
—
—
—
—
—
ERd32+1→ERd32
ERd32+2→ERd32
ERd32+4→ERd32
—
— [3]
— [3]
— [4]
— [4]
Rd8+Rs8→Rd8
Rd16+#xx:16→Rd16
Rd16+Rs16→Rd16
ERd32+#xx:32→ERd32
ERd32+ERs32→ERd32
——
——
——
——
——
— *
Rd8+1→Rd8
Rd16+1→Rd16
Rd16+2→Rd16
ERd32+1→ERd32
ERd32+2→ERd32
Rd8 decimal adjust→Rd8
—
— [3]
Rd8-Rs8→Rd8
Rd16-#xx:16→Rd16
[5]
[5]
Rd8+Rs8+C→Rd8
—
*
2
1
1
1
3
1
2
1
—
1
Advanced
No. of States*1
Rd8+#xx:8+C→Rd8
Operation
Rd8+#xx:8→Rd8
↔ ↔
↔ ↔
Mnemonic
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔
Rev.4.00 Sep. 18, 2008 Page 666 of 872
REJ09B0189-0400
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔
↔ ↔ ↔ ↔ ↔
Table A.2
↔ ↔ ↔
—
@@aa
@(d,PC)
@aa
@–ERn/@ERn+
@(d,ERn)
@ERn
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Arithmetic Instructions
L
L
SUBS #2,ERd
SUBS #4,ERd
B
W
B
W
DAS Rd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
MULXS.B Rs,Rd
MULXS.W Rs,ERd
MULXU
MULXS
L
B
DEC.L #2,ERd
L
DEC.L #1,ERd
W
L
SUBS #1,ERd
DEC.W #2,Rd
B
SUBX Rs,Rd
B
B 2
SUBX #xx:8,Rd
W
L
SUB.L ERs,ERd
DEC.W #1,Rd
L 6
DEC.B Rd
W
SUB.L #xx:32,ERd
DAS
DEC
SUBS
SUBX
Operand Size
SUB.W Rs,Rd
Rn
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
— — — — — —
— — — — — —
— — — — — —
ERd32-2→ERd32
ERd32-4→ERd32
(signed multiplication)
Rd16×Rs16→ERd32
— —
— —
21
13
— —
— —
Rd8×Rs8→Rd16 (signed multiplication)
(unsigned multiplication)
Rd16×Rs16→ERd32
20
1
— — — — — —
1
—
* —
1
1
1
1
12
— *
Rd8 decimal adjust→Rd8
—
—
—
1
1
Rd8×Rs8→Rd16 (unsigned multiplication) — — — — — —
— —
ERd32-2→ERd32
— —
Rd16-2→Rd16
— —
— —
ERd32-1→ERd32
— —
Rd8-1→Rd8
Rd16-1→Rd16
[5]
—
1
—
ERd32-1→ERd32
[5]
3
Rd8-Rs8-C→Rd8
— [4]
ERd32-ERs32→ERd32
—
— [4]
ERd32-#xx:32→ERd32
1
Advanced
No. of States*1
Rd8-#xx:8-C→Rd8
— [3]
Rd16-Rs16→Rd16
↔ ↔
SUB
I H N Z V C
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔
Operation
↔ ↔ ↔ ↔ ↔
↔ ↔
↔ ↔
Mnemonic
Condition Code
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
@aa
@–ERn/@ERn+
@(d,ERn)
@ERn
#xx
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 667 of 872
REJ09B0189-0400
Rev.4.00 Sep. 18, 2008 Page 668 of 872
REJ09B0189-0400
EXTU
NEG
CMP
DIVXS
W 4
W
L 6
L
B
W
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
NEG.B Rd
NEG.W Rd
L
B
CMP.B Rs,Rd
EXTU.L ERd
B 2
CMP.B #xx:8,Rd
L
W
DIVXS.W Rs,ERd
W
B
DIVXS.B Rs,Rd
EXTU.W Rd
W
DIVXU.W Rs,ERd
NEG.L ERd
B
DIVXU.B Rs,Rd
Rn
2
2
2
2
2
2
2
2
4
4
2
2
1
—
—
0-Rd8→Rd8
0-Rd16→Rd16
— — 0
— [4]
ERd32-ERs32
0→(<bit 31 to 16> of ERd32)
— [4]
ERd32-#xx:32
—
— [3]
Rd16-Rs16
— — 0
— [3]
Rd16-#xx:16
0→(<bit 15 to 8> of Rd16)
—
Rd8-Rs8
0-ERd32→ERd32
—
Rd8-#xx:8
Rd: quotient) (signed division)
0 —
0 —
21
ERd32÷Rs16→ERd32 (Ed: remainder, — — [8] [7] — —
RdL: quotient) (signed division)
1
1
1
1
1
1
3
1
2
1
13
Rd16÷Rs8→Rd16 (RdH: remainder, — — [8] [7] — —
Rd: quotient) (unsigned division)
RdL: quotient) (unsigned division)
20
Advanced
ERd32÷Rs16→ERd32 (Ed: remainder, — — [6] [7] — —
I H N Z V C
12
Operation
No. of States*1
Rd16÷Rs8→Rd16 (RdH: remainder, — — [6] [7] — —
↔ ↔ ↔
↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
DIVXU
Operand Size
Mnemonic
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
@aa
@–ERn/@ERn+
@(d,ERn)
@ERn
#xx
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
CLRMAC
LDMAC ERs,MACH
LDMAC
STMAC MACL,ERd
STMAC MACH,ERd
@(d,ERn)
#xx
(<bit 7> of @ERd)
@ERd-0→CCR set, (1)→
(<bit 31 to 16> of ERd32)
(<bit 15> of ERd32)→
(<bit 15 to 8> of Rd16)
Note: * The TAS instruction may only be used with the ER0, ER1, ER4, and ER5 registers.
STMAC
LDMAC ERs,MACL
Cannot be used in the H8S/2214 Group
MAC @ERn+, @ERm+
CLRMAC
@ERn
4
MAC
2
Operation
(<bit 7> of Rd16)→
B
Rn
2
TAS @ERd*2
EXTS
Operand Size
TAS*
@–ERn/@ERn+
L
@aa
EXTS.L ERd
@(d,PC)
W
@@aa
EXTS.W Rd
—
Mnemonic
Advanced
I H N Z V C
— —
— —
— —
No. of States*1
Condition Code
1
0 —
0 —
[2]
4
1
0 —
↔
↔
↔
↔
↔
↔
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
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NOT
XOR
OR
AND
Operand Size
L
NOT.L ERd
L
XOR.L ERs,ERd
W
L 6
XOR.L #xx:32,ERd
NOT.W Rd
W
XOR.W Rs,Rd
B
W 4
XOR.W #xx:16,Rd
NOT.B Rd
B
L
OR.L ERs,ERd
B 2
L 6
OR.L #xx:32,ERd
XOR.B Rs,Rd
W
OR.W Rs,Rd
XOR.B #xx:8,Rd
W 4
OR.W #xx:16,Rd
AND.L ERs,ERd
B
AND.L #xx:32,ERd
OR.B Rs,Rd
L 6
L
AND.W Rs,Rd
B 2
W
AND.W #xx:16,Rd
OR.B #xx:8,Rd
B
W 4
AND.B Rs,Rd
B 2
#xx
AND.B #xx:8,Rd
Mnemonic
Rn
2
2
2
4
2
2
4
2
2
4
2
2
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
Rd8∧Rs8→Rd8
Rd16∧#xx:16→Rd16
Rd16∧Rs16→Rd16
ERd32∧#xx:32→ERd32
ERd32∧ERs32→ERd32
Rd8∨#xx:8→Rd8
Rd8∨Rs8→Rd8
Rd16∨#xx:16→Rd16
Rd16∨Rs16→Rd16
ERd32∨#xx:32→ERd32
ERd32∨ERs32→ERd32
Rd8⊕#xx:8→Rd8
Rd8⊕Rs8→Rd8
Rd16⊕#xx:16→Rd16
Rd16⊕Rs16→Rd16
ERd32⊕#xx:32→ERd32
ERd32⊕ERs32→ERd32
¬ Rd8→Rd8
¬ Rd16→Rd16
¬ ERd32→ERd32
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
0 —
1
1
1
2
3
1
2
1
1
2
3
1
2
1
1
2
3
1
2
1
1
Advanced
0 —
I H N Z V C
— —
Operation
Rd8∧#xx:8→Rd8
No. of States*1
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
Table A.3
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
@aa
@–ERn/@ERn+
@(d,ERn)
@ERn
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Logical Instructions
SHLL
SHAR
SHAL
L
SHAR.L ERd
B
B
W
W
L
L
SHLL.B Rd
SHLL.B #2,Rd
SHLL.W Rd
SHLL.W #2,Rd
SHLL.L ERd
SHLL.L #2,ERd
L
W
SHAR.W #2,Rd
SHAR.L #2,ERd
W
SHAR.W Rd
L
SHAL.L #2,ERd
B
L
SHAL.L ERd
SHAR.B #2,Rd
W
SHAL.W #2,Rd
B
W
SHAL.W Rd
SHAR.B Rd
B
B
SHAL.B #2,Rd
Operand Size
SHAL.B Rd
Rn
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C
C
MSB
MSB
MSB
Operation
LSB
LSB
LSB
C
0
0
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
0
0
0
0
0
0
0
0
0
0
0
0
I H N Z V C
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
Mnemonic
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Advanced
No. of States*1
Table A.4
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
@aa
@–ERn/@ERn+
@(d,ERn)
@ERn
#xx
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Shift Instructions
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ROTXR
ROTXL
SHLR
B
W
W
L
L
ROTXR.W Rd
ROTXR.W #2,Rd
ROTXR.L ERd
ROTXR.L #2,ERd
L
ROTXL.L #2,ERd
B
L
ROTXL.L ERd
ROTXR.B #2,Rd
W
ROTXL.W #2,Rd
ROTXR.B Rd
W
ROTXL.W Rd
SHLR.L #2,ERd
B
L
SHLR.L ERd
ROTXL.B #2,Rd
L
SHLR.W #2,Rd
B
W
SHLR.W Rd
ROTXL.B Rd
B
W
SHLR.B #2,Rd
B
Operand Size
SHLR.B Rd
Rn
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C
LSB
C
— —
— —
— —
— MSB
—
— —
—
—
— —
—
C
— —
—
LSB
— —
— —
—
—
— —
—
— —
— —
—
LSB
— —
—
MSB
— — 0
—
—
— — 0
— — 0
—
MSB
— — 0
—0
—
— — 0
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I H N Z V C
— — 0
Operation
—
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
Mnemonic
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
@aa
@–ERn/@ERn+
@(d,ERn)
@ERn
#xx
Addressing Mode/
Instruction Length (Bytes)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Advanced
No. of States*1
Appendix A Instruction Set
ROTR
ROTL
L
ROTR.L ERd
L
W
ROTR.W #2,Rd
ROTR.L #2,ERd
W
ROTR.W Rd
L
ROTL.L #2,ERd
B
L
ROTL.L ERd
ROTR.B #2,Rd
W
ROTL.W #2,Rd
B
W
ROTL.W Rd
ROTR.B Rd
B
B
ROTL.B #2,Rd
2
Rn
2
2
2
2
2
2
2
2
2
2
2
MSB
1
—
C
— —
—
— —
— —
— —
— —
—
— —
— —
— —
LSB
LSB
—
MSB
C
— —
— —
— —
— —
0
0
0
0
0
0
0
0
0
0
0
0
I H N Z V C
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
Operand Size
ROTL.B Rd
Operation
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
Mnemonic
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
@aa
@–ERn/@ERn+
@(d,ERn)
@ERn
#xx
Addressing Mode/
Instruction Length (Bytes)
1
1
1
1
1
1
1
1
1
1
1
1
Advanced
No. of States*1
Appendix A Instruction Set
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B
B
B
BCLR Rn,@aa:8
BCLR Rn,@aa:16
B
BCLR Rn,Rd
BCLR Rn,@ERd
B
B
BSET Rn,@aa:32
BCLR #xx:3,@aa:32
B
BSET Rn,@aa:16
B
B
BSET Rn,@aa:8
B
B
BSET Rn,@ERd
BCLR #xx:3,@aa:16
B
BSET Rn,Rd
BCLR #xx:3,@aa:8
B
BSET #xx:3,@aa:32
B
B
BSET #xx:3,@aa:16
BCLR #xx:3,@ERd
B
BSET #xx:3,@aa:8
B
B
BSET #xx:3,@ERd
BCLR #xx:3,Rd
B
Operand Size
BSET #xx:3,Rd
Rn
2
2
2
2
@ERn
4
4
4
4
@aa
6
4
8
6
4
8
6
4
8
6
4
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
(#xx:3 of @ERd)←1
(#xx:3 of @aa:8)←1
(#xx:3 of @aa:16)←1
(#xx:3 of @aa:32)←1
(Rn8 of Rd8)←1
(Rn8 of @ERd)←1
(Rn8 of @aa:8)←1
(Rn8 of @aa:16)←1
(Rn8 of @aa:32)←1
(#xx:3 of Rd8)←0
(#xx:3 of @ERd)←0
(#xx:3 of @aa:8)←0
(#xx:3 of @aa:16)←0
(#xx:3 of @aa:32)←0
(Rn8 of Rd8)←0
(Rn8 of @ERd)←0
(Rn8 of @aa:8)←0
(Rn8 of @aa:16)←0
I H N Z V C
— — — — — —
(#xx:3 of Rd8)←1
Operation
Condition Code
5
4
4
1
6
5
4
4
1
6
5
4
4
1
6
5
4
4
1
Advanced
No. of States*1
Table A.5
BCLR
BSET
Mnemonic
—
@@aa
@(d,PC)
@–ERn/@ERn+
@(d,ERn)
#xx
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Bit-Manipulation Instructions
BTST
B
B
B
B
B
BNOT Rn,@aa:32
BTST #xx:3,Rd
BTST #xx:3,@ERd
BTST #xx:3,@aa:8
BTST #xx:3,@aa:16
B
BNOT Rn,Rd
B
B
BNOT #xx:3,@aa:32
BNOT Rn,@aa:16
B
BNOT #xx:3,@aa:16
B
B
BNOT #xx:3,@aa:8
B
B
BNOT #xx:3,@ERd
BNOT Rn,@aa:8
B
BNOT #xx:3,Rd
BNOT Rn,@ERd
B
BCLR Rn,@aa:32
BNOT
Operand Size
BCLR
Mnemonic
Rn
2
2
2
@ERn
4
4
4
@aa
6
4
8
6
4
8
6
4
8
— — —
— — —
— — —
— — —
¬ (#xx:3 of Rd8)→Z
¬ (#xx:3 of @ERd)→Z
¬ (#xx:3 of @aa:8)→Z
¬ (#xx:3 of @aa:16)→Z
— —
— —
— —
4
3
3
1
6
— — — — — —
[¬ (Rn8 of @aa:32)]
(Rn8 of @aa:32)←
— —
5
— — — — — —
[¬ (Rn8 of @aa:16)]
(Rn8 of @aa:16)←
4
4
1
6
5
(Rn8 of @aa:8)←[¬ (Rn8 of @aa:8)] — — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
(Rn8 of @ERd)←[¬ (Rn8 of @ERd)] — — — — — —
(Rn8 of Rd8)←[¬ (Rn8 of Rd8)]
[¬ (#xx:3 of @aa:32)]
(#xx:3 of @aa:32)←
[¬ (#xx:3 of @aa:16)]
(#xx:3 of @aa:16)←
[¬ (#xx:3 of @aa:8)]
(#xx:3 of @aa:8)←
4
4
— — — — — —
(#xx:3 of @ERd)←
[¬ (#xx:3 of @ERd)]
6
1
Advanced
— — — — — —
I H N Z V C
No. of States*1
(#xx:3 of Rd8)←[¬ (#xx:3 of Rd8)] — — — — — —
(Rn8 of @aa:32)←0
Operation
Condition Code
↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
@–ERn/@ERn+
@(d,ERn)
#xx
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
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BST
BILD
BLD
BTST
B
B
B
B
B
B
B
B
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
B
B
BLD #xx:3,Rd
BST #xx:3,@aa:8
B
BTST Rn,@aa:32
B
B
BTST Rn,@aa:16
B
B
BTST Rn,@aa:8
BST #xx:3,@ERd
B
BTST Rn,@ERd
BST #xx:3,Rd
B
B
BTST Rn,Rd
B
Operand Size
BTST #xx:3,@aa:32
Rn
2
2
2
2
@ERn
4
4
4
4
@aa
4
8
6
4
8
6
4
8
6
4
8
— — —
— — —
— — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
¬ (Rn8 of @aa:8)→Z
¬ (Rn8 of @aa:16)→Z
¬ (Rn8 of @aa:32)→Z
(#xx:3 of Rd8)→C
(#xx:3 of @ERd)→C
(#xx:3 of @aa:8)→C
(#xx:3 of @aa:16)→C
(#xx:3 of @aa:32)→C
¬ (#xx:3 of Rd8)→C
¬ (#xx:3 of @ERd)→C
¬ (#xx:3 of @aa:8)→C
¬ (#xx:3 of @aa:16)→C
¬ (#xx:3 of @aa:32)→C
— —
— —
— —
— —
¬ (Rn8 of @ERd)→Z
— —
— — —
— — —
¬ (Rn8 of Rd8)→Z
— —
I H N Z V C
— — —
Operation
¬ (#xx:3 of @aa:32)→Z
↔ ↔ ↔ ↔ ↔ ↔
Mnemonic
Condition Code
— — — — — —
— — — — — —
— — — — — —
C→(#xx:3 of Rd8)
C→(#xx:3 of @ERd)
C→(#xx:3 of @aa:8)
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
@–ERn/@ERn+
@(d,ERn)
#xx
Addressing Mode/
Instruction Length (Bytes)
4
4
1
5
4
3
3
1
5
4
3
3
1
5
4
3
3
1
5
Advanced
No. of States*1
Appendix A Instruction Set
BOR
BIAND
BAND
BIST
BST
B
BAND #xx:3,@aa:16
B
B
B
B
B
B
B
BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
BOR #xx:3,Rd
BOR #xx:3,@ERd
B
B
BAND #xx:3,@aa:32
B
B
BIST #xx:3,@aa:32
BAND #xx:3,@aa:8
B
BIST #xx:3,@aa:16
BAND #xx:3,@ERd
B
BIST #xx:3,@aa:8
B
B
BIST #xx:3,@ERd
BAND #xx:3,Rd
B
B
BIST #xx:3,Rd
B
BST #xx:3,@aa:32
Operand Size
BST #xx:3,@aa:16
Mnemonic
Rn
2
2
2
2
@ERn
4
4
4
4
@aa
8
6
4
8
6
4
8
6
4
8
6
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
C∧(#xx:3 of @aa:32)→C
C∧[¬ (#xx:3 of Rd8)]→C
C∧[¬ (#xx:3 of @ERd)]→C
C∧[¬ (#xx:3 of @aa:8)]→C
C∧[¬ (#xx:3 of @aa:16)]→C
C∧[¬ (#xx:3 of @aa:32)]→C
C∨(#xx:3 of Rd8)→C
C∨(#xx:3 of @ERd)→C
— — — — —
C∧(#xx:3 of @aa:16)→C
— — — — — —
¬ C→(#xx:3 of @aa:32)
— — — — —
— — — — — —
¬ C→(#xx:3 of @aa:16)
— — — — —
— — — — — —
¬ C→(#xx:3 of @aa:8)
C∧(#xx:3 of @aa:8)→C
1
— — — — — —
¬ C→(#xx:3 of @ERd)
C∧(#xx:3 of @ERd)→C
6
— — — — — —
¬ C→(#xx:3 of Rd8)
— — — — —
— — — — — —
C→(#xx:3 of @aa:32)
C∧(#xx:3 of Rd8)→C
— — — — — —
C→(#xx:3 of @aa:16)
3
1
5
4
3
3
1
5
4
3
3
5
4
4
1
6
5
I H N Z V C
Advanced
No. of States*1
Operation
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
@–ERn/@ERn+
@(d,ERn)
#xx
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 677 of 872
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Rev.4.00 Sep. 18, 2008 Page 678 of 872
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BIXOR
BXOR
BIOR
BOR
B
B
B
B
B
B
B
B
B
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
B
BIOR #xx:3,@aa:32
B
B
BIOR #xx:3,@aa:16
BXOR #xx:3,@ERd
B
BIOR #xx:3,@aa:8
BXOR #xx:3,Rd
B
BIOR #xx:3,@ERd
B
BOR #xx:3,@aa:32
B
B
BOR #xx:3,@aa:16
BIOR #xx:3,Rd
B
Operand Size
BOR #xx:3,@aa:8
Mnemonic
Rn
2
2
2
@ERn
4
4
4
@aa
8
6
4
8
6
4
8
6
4
8
6
4
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
C∨(#xx:3 of @aa:16)→C
C∨(#xx:3 of @aa:32)→C
C∨[¬ (#xx:3 of Rd8)]→C
C∨[¬ (#xx:3 of @ERd)]→C
C∨[¬ (#xx:3 of @aa:8)]→C
C∨[¬ (#xx:3 of @aa:16)]→C
C∨[¬ (#xx:3 of @aa:32)]→C
C⊕(#xx:3 of Rd8)→C
C⊕(#xx:3 of @ERd)→C
C⊕(#xx:3 of @aa:8)→C
C⊕(#xx:3 of @aa:16)→C
C⊕(#xx:3 of @aa:32)→C
C⊕[¬ (#xx:3 of Rd8)]→C
C⊕[¬ (#xx:3 of @ERd)]→C
C⊕[¬ (#xx:3 of @aa:8)]→C
C⊕[¬ (#xx:3 of @aa:16)]→C
C⊕[¬ (#xx:3 of @aa:32)]→C
I H N Z V C
— — — — —
C∨(#xx:3 of @aa:8)→C
Operation
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d,PC)
@–ERn/@ERn+
@(d,ERn)
#xx
Addressing Mode/
Instruction Length (Bytes)
5
4
3
3
1
5
4
3
3
1
5
4
3
3
1
5
4
3
Advanced
No. of States*1
Appendix A Instruction Set
Bcc
—
BVC d:16
BEQ d:8
—
—
BNE d:16
—
—
BNE d:8
BVC d:8
—
BCS d:16(BLO d:16)
BEQ d:16
—
—
BCS d:8(BLO d:8)
—
—
BLS d:8
BCC d:16(BHS d:16)
—
BHI d:16
—
—
BHI d:8
—
—
BRN d:16(BF d:16)
BCC d:B(BHS d:8)
—
BRN d:8(BF d:8)
BLS d:16
—
—
BRA d:16(BT d:16)
Operand Size
BRA d:8(BT d:8)
2
@(d,PC)
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
Branching
Condition
else next;
PC←PC+d
V=0
Z=1
Z=0
C=1
C=0
C∨Z=1
C∨Z=0
Never
if condition is true then Always
Operation
3
3
— — — — — —
3
2
— — — — — —
— — — — — —
2
3
— — — — — —
2
— — — — — —
3
— — — — — —
— — — — — —
2
— — — — — —
— — — — — —
2
— — — — — —
2
3
— — — — — —
— — — — — —
2
3
— — — — — —
— — — — — —
3
— — — — — —
3
2
— — — — — —
2
— — — — — —
Advanced
No. of States*1
— — — — — —
I H N Z V C
Condition Code
Table A.6
Mnemonic
—
@@aa
@aa
@–ERn/@ERn+
@(d,ERn)
@ERn
Rn
#xx
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Branch Instructions
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Bcc
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REJ09B0189-0400
—
—
BLE d:8
BLE d:16
—
BGE d:16
—
—
BGE d:8
BGT d:16
—
BMI d:16
—
—
BMI d:8
BGT d:8
—
BPL d:16
—
—
BPL d:8
—
—
BVS d:16
BLT d:16
—
BVS d:8
BLT d:8
Operand Size
Mnemonic
@(d,PC)
4
2
4
2
4
2
4
2
4
2
4
2
4
2
—
@@aa
@aa
@–ERn/@ERn+
@(d,ERn)
@ERn
Rn
#xx
Addressing Mode/
Instruction Length (Bytes)
Operation
2
3
2
3
2
3
Z∨(N⊕V)=0 — — — — — —
— — — — — —
Z∨(N⊕V)=1 — — — — — —
— — — — — —
3
— — — — — —
2
— — — — — —
3
— — — — — —
— — — — — —
2
— — — — — —
3
— — — — — —
3
2
— — — — — —
— — — — — —
2
Advanced
— — — — — —
I H N Z V C
No. of States*1
— — — — — —
N⊕V=1
N⊕V=0
N=1
N=0
V=1
Branching
Condition
Condition Code
Appendix A Instruction Set
RTS
JSR
BSR
JMP
—
—
JSR @@aa:8
RTS
—
JSR @aa:24
—
—
JSR @ERn
BSR d:16
—
JMP @@aa:8
—
—
BSR d:8
—
JMP @aa:24
Operand Size
JMP @ERn
Mnemonic
@ERn
2
2
@aa
4
4
@(d,PC)
4
2
@@aa
2
2
— — — — — —
— — — — — —
PC→@-SP,PC←aa:24
PC→@-SP,PC←@aa:8
— — — — — —
— — — — — —
— — — — — —
PC→@-SP,PC←PC+d:8
— — — — — —
— — — — — —
PC←@aa:8
PC→@-SP,PC←ERn
— — — — — —
PC→@-SP,PC←PC+d:16
— — — — — —
PC←aa:24
I H N Z V C
Condition Code
PC←ERn
Operation
2 PC←@SP+
—
@–ERn/@ERn+
@(d,ERn)
Rn
#xx
Addressing Mode/
Instruction Length (Bytes)
5
6
5
4
5
4
5
3
2
Advanced
No. of States*1
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 681 of 872
REJ09B0189-0400
W
W
W
W
W
W
W
W
W
W
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @ERs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
LDC @aa:32,CCR
LDC @aa:32,EXR
B
LDC Rs,CCR
W
B 4
LDC #xx:8,EXR
LDC @ERs,EXR
B 2
LDC #xx:8,CCR
LDC
B
—
SLEEP
SLEEP
W
—
RTE
RTE
LDC @ERs,CCR
—
TRAPA #xx:2
TRAPA
LDC Rs,EXR
Operand Size
Mnemonic
Rn
2
2
@ERn
4
4
@(d,ERn)
10
10
6
6
@–ERn/@ERn+
4
4
@aa
8
8
6
6
Operation
2
1
2
1
1
3
3
— — — — — —
— — — — — —
— — — — — —
— — — — — —
#xx:8→CCR
#xx:8→EXR
Rs8→CCR
Rs8→EXR
@ERs→CCR
8 [9]
Transition to power-down state
Advanced
I H N Z V C
1 — — — — —
No. of States*1
5 [9]
— — — — — —
@aa:32→EXR
5
5
@aa:32→CCR
4
4
— — — — — —
@aa:16→CCR
@aa:16→EXR
4
— — — — — —
@ERs→EXR,ERs32+2→ERs32
@(d:32,ERs)→CCR
4
6
6
— — — — — —
@(d:16,ERs)→EXR
@ERs→CCR,ERs32+2→ERs32
4
— — — — — —
@(d:16,ERs)→CCR
@(d:32,ERs)→EXR
4
@ERs→EXR
PC←@SP+
EXR←@SP+,CCR←@SP+,
EXR→@-SP,<vector>→PC
PC→@-SP,CCR→@-SP,
Condition Code
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
Rev.4.00 Sep. 18, 2008 Page 682 of 872
REJ09B0189-0400
↔
↔
↔
↔
↔
↔
Table A.7
↔
↔
↔
↔
↔
↔
—
@@aa
@(d,PC)
#xx
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
System Control Instructions
NOP
XORC
ORC
ANDC
B
B
W
W
W
W
W
W
W
W
W
W
W
W
B 2
B 4
B 2
B 4
B 2
B 4
—
STC CCR,@ERd
STC EXR,@ERd
STC CCR,@(d:16,ERd)
STC EXR,@(d:16,ERd)
STC CCR,@(d:32,ERd)
STC EXR,@(d:32,ERd)
STC CCR,@-ERd
STC EXR,@-ERd
STC CCR,@aa:16
STC EXR,@aa:16
STC CCR,@aa:32
STC EXR,@aa:32
ANDC #xx:8,CCR
ANDC #xx:8,EXR
ORC #xx:8,CCR
ORC #xx:8,EXR
XORC #xx:8,CCR
XORC #xx:8,EXR
NOP
Operand Size
STC EXR,Rd
Rn
2
2
@ERn
4
4
@(d,ERn)
10
10
6
6
@–ERn/@ERn+
4
4
@aa
8
8
6
6
6
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
CCR→@ERd
EXR→@ERd
CCR→@(d:16,ERd)
EXR→@(d:16,ERd)
CCR→@(d:32,ERd)
EXR→@(d:32,ERd)
1
4
— — — — — —
— — — — — —
ERd32-2→ERd32,EXR→@ERd
CCR→@aa:16
1
—
— — — — — —
— — — — — —
EXR⊕#xx:8→EXR
2 PC←PC+2
1
2
2
CCR⊕#xx:8→CCR
1
— — — — — —
CCR∨#xx:8→CCR
EXR∨#xx:8→EXR
2
— — — — — —
EXR∧#xx:8→EXR
5
— — — — — —
EXR→@aa:32
1
5
— — — — — —
CCR→@aa:32
CCR∧#xx:8→CCR
4
— — — — — —
EXR→@aa:16
4
4
ERd32-2→ERd32,CCR→@ERd — — — — — —
6
4
4
3
3
1
— — — — — —
— — — — — —
EXR→Rd8
Advanced
CCR→Rd8
↔
#xx
STC CCR,Rd
I H N Z V C
↔
STC
Operation
No. of States*1
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
Mnemonic
Condition Code
↔
↔
↔
@@aa
@(d,PC)
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 683 of 872
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Rev.4.00 Sep. 18, 2008 Page 684 of 872
REJ09B0189-0400
—
EEPMOV.W
@@aa
@(d,PC)
@aa
@–ERn/@ERn+
@(d,ERn)
@ERn
Rn
#xx
— — — — — — 4+2n *3
4 if R4 0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4-1→R4
Until R4=0
else next;
The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory.
This instruction should be used with the ER0, ER1, ER4, or ER5 general register only.
n is the initial value of R4L or R4.
Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers.
Cannot be used in the H8S/2214.
Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
Retains its previous value when the result is zero; otherwise cleared to 0.
Set to 1 when the divisor is negative; otherwise cleared to 0.
Set to 1 when the divisor is zero; otherwise cleared to 0.
Set to 1 when the quotient is negative; otherwise cleared to 0.
One additional state is required for execution when EXR is valid.
—
Operand Size
EEPMOV.B
Advanced
— — — — — — 4+2n *3
I H N Z V C
No. of States*1
4 if R4L 0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4L-1→R4L
Until R4L=0
else next;
Operation
Condition Code
Table A.8
Notes: 1.
2.
3.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
EEPMOV
Mnemonic
—
Addressing Mode/
Instruction Length (Bytes)
Appendix A Instruction Set
Block Transfer Instructions
Bcc
BAND
ANDC
AND
L
B
B
B
B
B
B
B
—
—
—
—
ANDC #xx:8,CCR
ANDC #xx:8,EXR
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
BRN d:16 (BF d:16)
AND.B #xx:8,Rd
L
B
ADDX Rs,Rd
AND.L ERs,ERd
B
ADDX #xx:8,Rd
AND.L #xx:32,ERd
B
ADDS #4,ERd
W
L
ADDS #2,ERd
AND.W Rs,Rd
L
ADDS #1,ERd
B
L
ADD.L ERs,ERd
W
L
ADD.L #xx:32,ERd
AND.W #xx:16,Rd
L
ADD.W Rs,Rd
AND.B Rs,Rd
W
ADD.W #xx:16,Rd
1
9
A
9
B
E
rs
6
rs
9
6
6
E
7
5
4
5
4
6
6
8
1
8
0
1
0
3
C
7
A
0 erd
6
7
1
0 IMM
1
0
A
4
6
0
disp
disp
abs
0
0
0
0
0
rd
1
0
0 erd
IMM
6
F
1
rd
rd
rd
rd
0 erd
0 erd
0 erd
IMM
A
7
rd
rd
rd
0 erd
IMM
0
1
6
rd
rs
8
B
rd
0
B
7
E
0
9
0
0
0
0
7
IMM
1 ers 0 erd
rs
9
7
A
1
8
0
0
rs
rd
2nd byte
8
1st byte
6
6
7
6
6
7
0
6
3rd byte
IMM
IMM
disp
disp
abs
0 IMM
0 IMM
IMM
0
0
abs
0 ers 0 erd
IMM
IMM
4th byte
7
6
0 IMM
0
6th byte
Instruction Format
5th byte
7
6
7th byte
0 IMM
0
8th byte
9th byte
10th byte
Table A.9
ADDX
B
W
ADD.B Rs,Rd
B
Size
ADD.B #xx:8,Rd
Mnemonic
A.2
ADDS
ADD
Instruction
Appendix A Instruction Set
Instruction Codes
Table A.9 shows the instruction codes.
Instruction Codes
Rev.4.00 Sep. 18, 2008 Page 685 of 872
REJ09B0189-0400
Bcc
Instruction
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BHI d:16
BLS d:8
BLS d:16
BCC d:8 (BHS d:8)
BCC d:16 (BHS d:16)
BCS d:8 (BLO d:8)
BCS d:16 (BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
BLE d:8
BLE d:16
Size
BHI d:8
Mnemonic
Rev.4.00 Sep. 18, 2008 Page 686 of 872
REJ09B0189-0400
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
8
F
8
E
8
D
8
C
8
B
8
A
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
1st byte
F
E
D
C
B
A
9
8
7
6
5
4
3
2
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2nd byte
3rd byte
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
4th byte
6th byte
Instruction Format
5th byte
7th byte
8th byte
9th byte
10th byte
Appendix A Instruction Set
BIOR
BILD
BIAND
BCLR
Instruction
B
B
B
B
BIAND #xx:3,@aa:32
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
B
B
BIAND #xx:3,@aa:16
BIOR #xx:3,@aa:32
B
BIAND #xx:3,@aa:8
B
B
BIAND #xx:3,@ERd
BIOR #xx:3,@aa:16
B
BIAND #xx:3,Rd
B
B
BCLR Rn,@aa:32
B
B
BCLR Rn,@aa:16
BIOR #xx:3,@aa:8
B
BCLR Rn,@aa:8
BIOR #xx:3,@ERd
B
BCLR Rn,@ERd
B
B
BCLR Rn,Rd
BIOR #xx:3,Rd
B
BCLR #xx:3,@aa:32
B
B
BCLR #xx:3,@aa:16
BILD #xx:3,@aa:32
B
BCLR #xx:3,@aa:8
B
B
BCLR #xx:3,@ERd
BILD #xx:3,@aa:16
B
Size
BCLR #xx:3,Rd
Mnemonic
6
6
7
7
7
6
6
7
7
7
6
6
7
7
7
6
6
7
7
6
6
6
0 erd
D
0 erd
C
0 erd
C
0 erd
C
1
3
A
A
abs
1 IMM
4
E
0
3
A
0
0
0
rd
0
1
0
A
abs
1 IMM
7
E
0
3
A
rd
0
1
0
A
abs
1 IMM
6
E
8
3
A
rd
8
1
A
0
rd
rn
2
abs
8
3
A
F
8
1
0
A
abs
0 erd
D
7
7
F
rd
0 IMM
2
7
2nd byte
1st byte
4
4
7
7
7
7
7
6
7
6
7
2
7
2
6
2
7
6
2
7
3rd byte
rn
rn
abs
1 IMM
1 IMM
abs
1 IMM
1 IMM
abs
1 IMM
1 IMM
abs
abs
0 IMM
0 IMM
0
0
0
0
0
0
0
0
0
0
4th byte
abs
abs
abs
abs
abs
7
7
7
6
7
4
7
6
2
2
1 IMM
1 IMM
1 IMM
rn
0 IMM
0
0
0
0
0
6th byte
Instruction Format
5th byte
7
7
7
6
7
4
7
6
2
2
7th byte
1 IMM
1 IMM
1 IMM
rn
0 IMM
0
0
0
0
0
8th byte
9th byte
10th byte
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 687 of 872
REJ09B0189-0400
Rev.4.00 Sep. 18, 2008 Page 688 of 872
REJ09B0189-0400
BNOT
BLD
BIXOR
BIST
Instruction
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
BNOT #xx:3,Rd
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
BNOT #xx:3,@aa:16
BNOT #xx:3,@aa:32
BNOT Rn,Rd
BNOT Rn,@ERd
BNOT Rn,@aa:8
BNOT Rn,@aa:16
BNOT Rn,@aa:32
Size
BIST #xx:3,Rd
Mnemonic
8
8
0
0
0
0
8
8
rd
8
8
0 erd
1
3
1 IMM
0 erd
1
3
0 IMM
0 erd
1
3
0 IMM
0 erd
1
3
rn
0 erd
1
3
D
F
A
A
5
C
E
A
A
7
C
E
A
A
1
D
F
A
A
1
D
F
A
A
7
7
6
6
7
7
7
6
6
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
abs
abs
abs
abs
0
0
rd
0
rd
0
rd
0
rd
1 IMM
7
6
abs
2nd byte
1st byte
1
1
6
1
6
1
7
7
7
7
7
5
7
5
7
7
6
7
7
6
3rd byte
abs
abs
rn
rn
0 IMM
0 IMM
abs
0 IMM
0 IMM
abs
1 IMM
1 IMM
abs
1 IMM
1 IMM
0
0
0
0
0
0
0
0
0
0
4th byte
abs
abs
abs
abs
abs
6
7
7
7
6
1
1
7
5
7
rn
0 IMM
0 IMM
1 IMM
1 IMM
0
0
0
0
0
6th byte
Instruction Format
5th byte
6
7
7
7
6
1
1
7
5
7
7th byte
rn
0 IMM
0 IMM
1 IMM
1 IMM
0
0
0
0
0
8th byte
9th byte
10th byte
Appendix A Instruction Set
BTST
BST
BSR
BSET
BOR
Instruction
B
B
B
BTST Rn,Rd
BTST Rn,@ERd
B
BST #xx:3,Rd
BTST #xx:3,@aa:32
—
BSR d:16
B
—
BSR d:8
BTST #xx:3,@aa:16
B
BSET Rn,@aa:32
B
B
BSET Rn,@aa:16
B
B
BSET Rn,@aa:8
BTST #xx:3,@aa:8
B
BSET Rn,@ERd
BTST #xx:3,@ERd
B
BSET Rn,Rd
B
B
BSET #xx:3,@aa:32
BTST #xx:3,Rd
B
BSET #xx:3,@aa:16
B
B
BSET #xx:3,@aa:8
BST #xx:3,@aa:32
B
BSET #xx:3,@ERd
B
B
BSET #xx:3,Rd
BST #xx:3,@aa:16
B
BOR #xx:3,@aa:32
B
B
BOR #xx:3,@aa:16
B
B
BOR #xx:3,@aa:8
BST #xx:3,@aa:8
B
BOR #xx:3,@ERd
BST #xx:3,@ERd
B
Size
BOR #xx:3,Rd
Mnemonic
7
6
6
6
7
7
7
6
6
7
7
6
5
5
6
6
7
7
6
6
6
7
7
7
6
6
0 erd
D
0 erd
D
0 erd
C
0
rd
3
rn
0 erd
A
3
C
0
0
1
0
A
abs
0 IMM
3
E
8
3
A
rd
8
0
1
abs
0
rd
A
F
0 erd
7
D
0
0 IMM
C
disp
8
3
A
5
8
1
A
0
rd
rn
0
abs
8
3
A
F
8
1
0
A
abs
0 IMM
0
F
0
3
A
rd
0
1
0
A
abs
0 erd
C
7
7
E
rd
0 IMM
4
7
2nd byte
1st byte
6
7
3
3
3
7
7
7
6
0
6
0
6
0
6
0
7
4
7
7
4
7
3rd byte
rn
rn
abs
rn
0 IMM
0 IMM
abs
0 IMM
0 IMM
disp
abs
abs
0 IMM
0 IMM
abs
0 IMM
0 IMM
0
0
0
0
0
0
0
0
0
0
0
4th byte
abs
abs
abs
abs
abs
7
6
6
7
7
3
7
0
0
4
0 IMM
0 IMM
rn
0 IMM
0 IMM
0
0
0
0
0
6th byte
Instruction Format
5th byte
7
6
6
7
7
3
7
0
0
4
7th byte
0 IMM
0 IMM
rn
0 IMM
0 IMM
0
0
0
0
0
8th byte
9th byte
10th byte
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 689 of 872
REJ09B0189-0400
6
6
Cannot be used in the H8S/2214 Group
A
1
7
1
7
1
0
1
1
1
1
1
B
—
B
B
W
W
L
L
B
B
B
W
W
L
BXOR #xx:3,@aa:32
CLRMAC CLRMAC
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
DAA Rd
DAS Rd
DEC.B Rd
DEC.W #1,Rd
DEC.W #2,Rd
DEC.L #1,ERd
CMP
Rev.4.00 Sep. 18, 2008 Page 690 of 872
REJ09B0189-0400
DAA
DAS
DEC
1
0
0
5
5
7
7
L
B
W
B
W
—
—
DEC.L #2,ERd
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
EEPMOV EEPMOV.B
EEPMOV.W
DIVXU
DIVXS
rd
0 erd
rs
2
D
A
rs
rs
8
8
1
3
9
9
5
5
5
5
0
0
rd
0 erd
C
4
D
rs
rs
5
D
1
1
3
B
B
7
B
0 erd
rd
0 erd
D
B
F
rd
5
B
D
rd
0
A
1
rd
0
F
IMM
abs
B
rd
0
F
1 ers 0 erd
rd
2
9
F
rd
rs
C
IMM
0
3
A
rd
0
1
A
0 IMM
5
B
0 IMM
5
7
rn
IMM
abs
abs
F
F
0 erd
rd
0
0
0
4th byte
7
BXOR #xx:3,@aa:16
abs
0
E
0 erd
7
B
BXOR #xx:3,@aa:8
C
7
B
BXOR #xx:3,@ERd
rd
0 IMM
5
7
abs
B
0
3
BXOR #xx:3,Rd
BXOR
0
1
A
6
A
6
3
B
BTST
B
6
3rd byte
BTST Rn,@aa:32
abs
2nd byte
BTST Rn,@aa:16
E
1st byte
7
Size
B
Mnemonic
BTST Rn,@aa:8
Instruction
7
6
5
3
0 IMM
rn
0
0
6th byte
Instruction Format
5th byte
7
6
5
3
7th byte
0 IMM
rn
0
0
8th byte
9th byte
10th byte
Appendix A Instruction Set
LDC
JSR
JMP
INC
EXTU
EXTS
Instruction
rd
rd
0 erd
0 erd
0
0
5
D
7
F
0 ern
A
B
B
B
B
9
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @ERs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
0
B
LDC Rs,CCR
W
0
B
LDC #xx:8,EXR
LDC @ERs,EXR
0
B
LDC #xx:8,CCR
0
5
—
JSR @@aa:8
0
5
—
JSR @aa:24
B
5
—
JSR @ERn
W
5
—
JMP @@aa:8
LDC @ERs,CCR
5
—
JMP @aa:24
LDC Rs,EXR
5
INC.L #2,ERd
0
0
L
INC.L #1,ERd
L
0
W
INC.W #2,Rd
—
0
INC.W #1,Rd
JMP @ERn
0
B
W
INC.B Rd
0 ers
0 ers
0 ers
0 ers
0 ers
0 ers
0 ers
0 ers
0
0
9
9
F
F
8
8
D
D
B
B
6
6
6
6
7
7
6
6
6
6
rs
0
1
0
1
0
1
0
1
0
1
4
4
4
4
4
4
4
4
4
4
1
1
1
1
1
1
1
1
1
IMM
1
7
B
abs
abs
0
B
0
0
0
6
0
disp
6
0
disp
0
2
2
0
0
6th byte
Instruction Format
5th byte
0
0
0
4th byte
1
0
abs
abs
3rd byte
3
1
rs
0
3
IMM
4
7
1
abs
0 ern
F
E
D
B
0
rd
7
7
1
L
EXTU.L ERd
abs
rd
0 erd
5
7
1
A
0 erd
F
7
1
L
W
EXTU.W Rd
EXTS.L ERd
rd
D
7
1
2nd byte
1st byte
W
Size
EXTS.W Rd
Mnemonic
7th byte
8th byte
disp
disp
9th byte
10th byte
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 691 of 872
REJ09B0189-0400
F
0
6
6
7
6
2
6
6
6
6
7
6
3
6
6
7
0
6
6
7
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W
W
W
W
W
MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa :16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
MOV
L
—
LDMAC ERs,MACL
D
D
6
6
0
0
2
3
1
1
Rev.4.00 Sep. 18, 2008 Page 692 of 872
REJ09B0189-0400
0 ers
0 ers
8
C
1 erd
0 erd
1 erd
E
8
C
0 ers
0 ers
F
8
0
rd
rd
rd
rs
0 ers
rd
0
9
9
rs
A
A
D
rs
8
rs
0
rs
A
abs
1 erd
8
rs
rd
2
A
rs
rd
0
rd
0
rd
rd
rd
A
abs
0 ers
E
rd
0 ers
8
IMM
rs
C
rd
6
6
6
B
A
A
disp
IMM
abs
disp
abs
disp
Cannot be used in the H8S/2214 Group
MAC @ERn+,@ERm+
L
0
L
LDM.L @SP+, (ERn-ERn+3)
LDMAC ERs,MACH
0
L
LDM.L @SP+, (ERn-ERn+2)
6
0
2
A
2
7
7
7
2
B
D
6
1
1
1
4
1
0
0
L
W
LDM.L @SP+, (ERn-ERn+1)
LDC @aa:32,EXR
rd
rs
rd
abs
abs
0 ern+3
0 ern+2
0 ern+1
0
0
2
B
6
0
4
1
0
4th byte
3rd byte
2nd byte
1st byte
W
Size
LDC @aa:32,CCR
Mnemonic
MAC
LDMAC
LDM
LDC
Instruction
6th byte
Instruction Format
5th byte
disp
disp
disp
abs
abs
7th byte
8th byte
9th byte
10th byte
Appendix A Instruction Set
W
W
W
W
W
W
W
W
L
L
L
L
L
L
L
L
L
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,Rd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16 ,ERd
MOV.L @aa:32 ,ERd
MOV.L ERs,@ERd
rd
rd
rs
0
2
1 erd
1 erd
0 erd
1 erd
B
B
9
F
8
D
0 erd
0
A
9
6
0
0
1
Cannot be used in the H8S/2214 Group
0
0
5
5
B
B
B
W
B
W
MOVFPE MOVFPE @aa:16,Rd
MOVTPE MOVTPE Rs,@aa:16
MULXS.B Rs,Rd
MULXS.W Rs,ERd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
MULXS
2
0
1
1
rs
rs
0
2
5
5
0
0
rd
0 erd
C
C
rs
rs
B
6
0
0
0 erd
rd
0 ers
0 ers
8
A
B
6
0
0
1
0
L
MOV.L ERs,@aa:32
1
0
L
MOV.L ERs,@aa:16
1 erd 0 ers
D
6
0
0
1
0
L
0 erd
8
7
0
0
1
0
1 erd 0 ers
1 erd 0 ers
MOV.L ERs,@-ERd
F
B
6
0
0
1
6
2
B
6
0
0
1
0
0 erd
0
D
6
0
0
1
0
0 ers 0 erd
0 erd
0 ers
7
0
0
1
1
0 ers 0 erd
8
6
0
0 ers 0 erd
9
F
6
0
MULXU
abs
IMM
0
rs
0
A
0
abs
disp
0
B
abs
1
6
abs
4th byte
1
1 ers 0 erd
rs
B
F
rs
8
A
B
0
rs
3rd byte
0
0
0
0
0
0
0
0
0
7
6
6
6
7
6
6
6
6
rs
rd
0 ers
D
6
2nd byte
1st byte
L
MOV.L ERs,@(d:16,ERd)
W
Size
MOV.W @ERs+,Rd
Mnemonic
MOV.L ERs,@(d:32,ERd)*1 L
MOV
Instruction
6
6
B
B
abs
disp
abs
disp
A
2
disp
abs
0 ers
abs
0 erd
6th byte
Instruction Format
5th byte
7th byte
8th byte
disp
disp
9th byte
10th byte
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 693 of 872
REJ09B0189-0400
Rev.4.00 Sep. 18, 2008 Page 694 of 872
REJ09B0189-0400
6
7
0
0
0
6
W
L
L
B
B
W
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
ORC #xx:8,CCR
ORC #xx:8,EXR
POP.W Rn
ROTL
PUSH
POP
ORC
1
1
1
1
1
B
W
W
L
L
ROTL.W Rd
ROTL.W #2, Rd
ROTL.L ERd
ROTL.L #2, ERd
1
ROTL.B Rd
ROTL.B #2, Rd
0
L
B
PUSH.L ERn
6
7
W
OR.W #xx:16,Rd
0
1
B
OR.B Rs,Rd
L
C
B
OR.B #xx:8,Rd
W
1
L
NOT.L ERd
PUSH.W Rn
1
W
NOT.W Rd
POP.L ERn
1
B
NOT.B Rd
OR
0
—
NOP
1
L
NEG.L ERd
NOT
1
W
NEG.W Rd
rd
0 erd
0
1
3
0
7
7
7
rd
0 erd
0
rs
4
F
4
A
1
0
rn
0
rd
rd
rd
rd
0 erd
0 erd
0
F
0
8
C
9
D
B
F
1
1
2
2
2
2
2
2
7
D
D
1
rn
4
1
IMM
rd
4
9
4
rd
rs
4
IMM
0
rd
0
7
rd
rd
0 erd
9
B
7
rd
8
7
1
2nd byte
1st byte
B
Size
NEG.B Rd
Mnemonic
NOP
NEG
Instruction
6
6
0
6
D
D
4
4
3rd byte
IMM
F
7
0 ern
0 ern
IMM
0 ers 0 erd
IMM
4th byte
6th byte
Instruction Format
5th byte
7th byte
8th byte
9th byte
10th byte
Appendix A Instruction Set
1
B
SHAL.B Rd
1
1
1
1
1
B
W
W
L
L
SHAL.B #2, Rd
SHAL.W Rd
SHAL.W #2, Rd
SHAL.L ERd
SHAL.L #2, ERd
SHAL
5
—
RTS
RTS
rd
0 erd
0 erd
B
F
0
7
3
5
1
L
RTE
—
ROTXR.L #2, ERd
0
3
3
1
L
ROTXR.L ERd
rd
5
3
1
W
ROTXR.W #2, Rd
D
0 erd
1
3
1
W
ROTXR.W Rd
0
rd
0 erd
4
3
1
B
ROTXR.B #2, Rd
rd
rd
0
3
1
9
rd
7
2
1
L
B
ROTXR.B Rd
ROTXL.L #2, ERd
C
rd
3
2
1
L
ROTXL.L ERd
0
0 erd
5
2
1
W
ROTXL.W #2, Rd
0
rd
0 erd
1
2
1
W
ROTXL.W Rd
0
rd
4
2
1
B
ROTXL.B #2, Rd
rd
rd
0
2
1
8
rd
F
3
1
L
B
ROTXL.B Rd
ROTR.L #2, ERd
0
0 erd
B
3
1
L
ROTR.L ERd
0
rd
0 erd
D
3
1
W
ROTR.W #2, Rd
7
rd
9
3
1
ROTR.W Rd
4
rd
C
3
1
B
W
ROTR.B #2, Rd
7
rd
8
3
6
2nd byte
1st byte
1
Size
B
Mnemonic
ROTR.B Rd
RTE
ROTXR
ROTXL
ROTR
Instruction
3rd byte
4th byte
6th byte
Instruction Format
5th byte
7th byte
8th byte
9th byte
10th byte
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 695 of 872
REJ09B0189-0400
Rev.4.00 Sep. 18, 2008 Page 696 of 872
REJ09B0189-0400
6
6
6
6
7
7
6
6
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
0
rd
rd
0
1
0
1
0
1
0
1
8
C
9
D
B
F
0
4
1
5
3
7
0
4
1
5
3
7
8
0
1
4
4
4
4
4
4
4
4
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
B
W
W
STC.W EXR,@ERd
STC.W EXR,@(d:16,ERd) W
STC.W CCR,@(d:32,ERd) W
STC.W EXR,@(d:32,ERd) W
W
STC.W CCR,@ERd
STC.W CCR,@(d:16,ERd) W
W
STC.B EXR,Rd
STC.W CCR,@-ERd
STC.W EXR,@-ERd
0
1
L
—
SHLR.L #2, ERd
B
1
L
SHLR.L ERd
STC.B CCR,Rd
1
W
SHLR.W #2, Rd
STC
1
W
SHLR.W Rd
SLEEP
1
B
SHLR.B #2, Rd
SHLL.L #2, ERd
1
1
L
SHLL.L ERd
1
1
W
SHLL.W #2, Rd
L
1
W
SHLL.W Rd
B
1
B
SHLL.B #2, Rd
SHLR.B Rd
1
SHAR.L #2, ERd
1
1
L
SHAR.L ERd
L
1
W
SHAR.W #2, Rd
B
1
SHAR.W Rd
SHLL.B Rd
1
B
W
SHAR.B #2, Rd
1
1
D
D
8
8
F
F
9
9
3rd byte
2nd byte
1st byte
B
Size
SHAR.B Rd
Mnemonic
SLEEP
SHLR
SHLL
SHAR
Instruction
1 erd
1 erd
0 erd
0 erd
1 erd
1 erd
1 erd
1 erd
0
0
0
0
0
0
0
0
4th byte
6
6
B
B
disp
disp
A
A
0
0
6th byte
Instruction Format
5th byte
7th byte
8th byte
disp
disp
9th byte
10th byte
Appendix A Instruction Set
5
D
1
7
6
7
0
B
B
W
W
L
L
XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
XOR
1
B
—
B
SUBX #xx:8,Rd
1
TRAPA #x:2
L
SUBS #4,ERd
1
1
TRAPA
L
SUBS #2,ERd
0
L
SUBS #1,ERd
1
7
B
L
SUB.L ERs,ERd
B
L
SUB.L #xx:32,ERd
1
TAS @ERd *2
W
SUB.W Rs,Rd
7
1
SUBX Rs,Rd
W
L
STMAC MACH,ERd
SUB.W #xx:16,Rd
D
6
0
3
1
0
L
STM.L (ERn-ERn+3), @-SP
L
D
6
0
2
1
0
L
STM.L (ERn-ERn+2), @-SP
B
D
6
0
1
1
0
L
STM.L(ERn-ERn+1), @-SP
SUB.B Rs,Rd
B
6
1
4
1
0
W
STC.W EXR,@aa:32
STMAC MACL,ERd
B
6
0
4
1
0
W
STC.W CCR,@aa:32
rd
rd
rd
0 erd
0
rs
5
rs
5
F
9
5
A
1
0
0
5
IMM
00 IMM
7
rd
E
rs
1
E
rd
0 erd
9
B
IMM
0 erd
8
rd
0 erd
0
B
0 erd
3
A
B
rd
rs
9
1 ers 0 erd
rd
3
9
A
rd
rs
8
6
7
5
B
8
F
F
F
A
A
C
IMM
IMM
0 ern
0 ern
0 ern
0
0
0
0 ers 0 erd
IMM
0 erd
IMM
Cannot be used in the H8S/2214 Group
B
6
1
4
1
0
W
STC.W EXR,@aa:16
0
8
B
6
0
4
1
4th byte
3rd byte
0
2nd byte
1st byte
W
Size
STC.W CCR,@aa:16
Mnemonic
TAS
SUBX
SUBS
SUB
STMAC
STM
STC
Instruction
abs
abs
6th byte
Instruction Format
5th byte
abs
abs
7th byte
8th byte
9th byte
10th byte
Appendix A Instruction Set
Rev.4.00 Sep. 18, 2008 Page 697 of 872
REJ09B0189-0400
B
B
XORC #xx:8,EXR
Size
XORC #xx:8,CCR
Mnemonic
0
0
1
5
1st byte
4
IMM
1
2nd byte
0
5
3rd byte
IMM
4th byte
6th byte
Instruction Format
5th byte
7th byte
8th byte
9th byte
10th byte
Rev.4.00 Sep. 18, 2008 Page 698 of 872
REJ09B0189-0400
General
Register
ER0
ER1
•
•
•
ER7
Register
Field
000
001
•
•
•
111
Address Register
32-Bit Register
0000
0001
•
•
•
0111
1000
1001
•
•
•
1111
Register
Field
R0
R1
•
•
•
R7
E0
E1
•
•
•
E7
General
Register
16-Bit Register
The register fields specify general registers as follows.
0000
0001
•
•
•
0111
1000
1001
•
•
•
1111
Register
Field
R0H
R1H
•
•
•
R7H
R0L
R1L
•
•
•
R7L
General
Register
8-Bit Register
Notes: 1. Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0.
2. This instruction should be used with the ER0, ER1, ER4, or ER5 general register only.
Legend:
IMM:
Immediate data (2, 3, 8, 16, or 32 bits)
abs:
Absolute address (8, 16, 24, or 32 bits)
disp:
Displacement (8, 16, or 32 bits)
rs, rd, rn:
Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn)
ers, erd, ern, erm: Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand
symbols ERs, ERd, ERn, and ERm)
XORC
Instruction
Appendix A Instruction Set
1
2
BH
3
BL
BHI
BLS
XOR
BSR
BCS
AND
RTE
BNE
AND
7
BST
TRAPA
BEQ
ADD
OR
XOR
AND
MOV
E
F
SUBX
B
D
SUB
ADD
BVS
9
Table
A.11
MOV
Table
A.11
MOV
C
Note: * Cannot be used in the H8S/2214 Group.
8
BVC
MOV.B
Table
A.11
LDC
BIST
BOR
BXOR
BAND
BLD
BIXOR
BIAND
BIOR
BILD
OR
RTS
BCC
XOR
6
ANDC
CMP
BTST
DIVXU
OR
5
XORC
ADDX
BCLR
MULXU
4
ORC
Table
A.11
Table
A.11
JMP
BPL
Table
A.11
Table
A.11
A
EEPMOV
BMI
Table
A.11
Table
A.11
B
Instruction when most significant bit of BH is 1.
Instruction when most significant bit of BH is 0.
9
BNOT
DIVXU
BRN
LDC
Table STC
*
*
A.3(2)
STMAC
LDMAC
Table
Table
Table
A.11
A.11
A.11
AL
2nd byte
A
8
7
BSET
5
6
BRA
MULXU
4
3
2
Table
A.11
1
0
NOP
AL
0
AH
AH
1st byte
BSR
BGE
C
CMP
BLT
D
E
JSR
BGT
SUBX
ADDX
Table A.12
MOV
MOV
F
BLE
Table
A.11
Table
A.11
A.3
Instruction code
Appendix A Instruction Set
Operation Code Map
Tables A.10 to A.13 show the operation code map.
Table A.10 Operation Code Map (1)
Rev.4.00 Sep. 18, 2008 Page 699 of 872
REJ09B0189-0400
1
LDM
MOV
INC
ADDS
DAA
01
0A
0B
0F
Rev.4.00 Sep. 18, 2008 Page 700 of 872
REJ09B0189-0400
DAS
BRA
MOV
MOV
MOV
58
6A
79
7A
ADD
CMP
CMP
MOV
ADD
BHI
BRN
Table
A.13
2
SUB
SUB
Table
A.13
BLS
NOT
STM
3
BL
2nd byte
BH
Note: * Cannot be used in the H8S/2214 Group.
SUBS
17
1F
NOT
13
1B
ROTXR
12
DEC
ROTXL
11
1A
SHLL
SHLR
10
AH AL
AL
1st byte
AH
0
BH
Instruction code
OR
OR
MOVFPE*
BCC
ROTXR
ROTXL
SHLR
SHLL
STC
4
LDC
XOR
XOR
BCS
DEC
EXTU
INC
5
AND
AND
BNE
MAC*
6
BEQ
DEC
EXTU
ROTXR
ROTXL
SHLR
SHLL
INC
7
MOV
BVC
9
BVS
SUBS
NEG
ROTR
ROTL
SHAR
SHAL
ADDS
SLEEP
8
MOV
BPL
CLRMAC *
A
BMI
NEG
B
BGE
MOVTPE*
CMP
SUB
ROTR
ROTL
SHAR
SHAL
MOV
ADD
C
Table
A.12
D
BLT
DEC
EXTS
INC
Table
A.12
BGT
TAS
E
F
BLE
DEC
EXTS
ROTR
ROTL
SHAR
SHAL
INC
Table
A.12
Appendix A Instruction Set
Table A.11 Operation Code Map (2)
0
2
BCLR
MULXS
DIVXS
3
BSET
7Faa7 *2
BNOT
BNOT
BCLR
BCLR
Notes: 1. r is the register specification field.
2. aa is the absolute address specification.
BSET
7Faa6 *2
BTST
BCLR
BTST
BNOT
7Eaa7 *2
BSET
7Eaa6 *2
7Dr07 *1
7Dr06 *1
BTST
BNOT
DIVXS
1
XOR
5
AND
6
DL
4th byte
DH
7
BOR
BXOR
BAND
BLD
BIOR
BIXOR
BIAND
BILD
BST
BIST
BOR
BXOR
BAND
BLD
BIOR
BIXOR
BIAND
BILD
BST
BIST
OR
4
CL
3rd byte
CH
7Cr07 *1
BSET
MULXS
BL
2nd byte
BH
BTST
CL
AL
1st byte
AH
7Cr06 *1
01F06
01D05
01C05
AH AL BH BL CH
Instruction code
8
9
A
B
C
D
E
F
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
Appendix A Instruction Set
Table A.12 Operation Code Map (3)
Rev.4.00 Sep. 18, 2008 Page 701 of 872
REJ09B0189-0400
Rev.4.00 Sep. 18, 2008 Page 702 of 872
REJ09B0189-0400
BSET
0
AH
BNOT
1
AL
1st byte
BNOT
1
0
BSET
AL
AH
1st byte
BCLR
2
BH
3
3
6
DL
7
EH
EL
5th byte
5
6
DL
4th byte
DH
7
EL
5th byte
EH
BOR
BXOR
BAND
BLD
BIOR
BIXOR
BIAND
BILD
BST
BIST
4
CL
3rd byte
CH
BTST
BL
5
DH
4th byte
BOR
BXOR
BAND
BLD
BIOR
BIXOR
BIAND
BILD
BST
BIST
4
CL
3rd byte
CH
BTST
BL
2nd byte
BCLR
2
BH
2nd byte
Note: * aa is the absolute address specification.
6A38aaaaaaaa7*
6A38aaaaaaaa6*
6A30aaaaaaaa7*
6A30aaaaaaaa6*
AHALBHBL ... FHFLGH
GL
Instruction code
6A18aaaa7*
6A18aaaa6*
6A10aaaa7*
6A10aaaa6*
AHALBHBLCHCLDHDLEH
EL
Instruction code
8
8
9
FL
FH
9
FL
6th byte
FH
6th byte
A
B
HH
HL
8th byte
C
D
E
F
B
C
D
E
F
Instruction when most significant bit of HH is 0.
Instruction when most significant bit of HH is 1.
GL
7th byte
GH
A
Instruction when most significant bit of FH is 0.
Instruction when most significant bit of FH is 1.
Appendix A Instruction Set
Table A.13 Operation Code Map (4)
Appendix A Instruction Set
A.4
Number of States Required for Instruction Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8S/2000 CPU. Table A.15 indicates the number of instruction fetch, data
read/write, and other cycles occurring in each instruction. Table A.14 indicates the number of
states required for each cycle, depending on its size. The number of states required for execution
of an instruction can be calculated from these two tables as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: Advanced mode, program code and stack located in external memory, on-chip
supporting modules accessed in two states with 8-bit bus width, external devices accessed in three
states with one wait state and 16-bit bus width.
1. BSET #0, @FFFFB3:8
From table A.15:
I = L = 2, J = K = M = N = 0
From table A.14:
SI = 4, SL = 2
Number of states required for execution = 2 × 4 + 2 × 2 = 12
2. JSR @@30
From table A.15:
I = J = K = 2, L = M = N = 0
From table A.14:
SI = SJ = SK = 4
Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24
Rev.4.00 Sep. 18, 2008 Page 703 of 872
REJ09B0189-0400
Appendix A Instruction Set
Table A.14 Number of States per Cycle
Access Conditions
External Device
On-Chip Supporting
Module
Cycle
Instruction fetch
SI
8-Bit Bus
16-Bit Bus
On-Chip 8-Bit
Memory Bus
16-Bit
Bus
2-State 3-State 2-State 3-State
Access Access Access Access
1
2
4
6 + 2m
4
2
3+m
1
1
Branch address read SJ
Stack operation
SK
Byte data access
SL
2
2
3+m
Word data access
SM
4
4
6 + 2m
Internal operation
SN
1
1
1
1
1
Legend:
m: Number of wait states inserted into external device access
Rev.4.00 Sep. 18, 2008 Page 704 of 872
REJ09B0189-0400
Appendix A Instruction Set
Table A.15 Number of Cycles in Instruction Execution
Branch
Byte
Instruction Address Stack
Data
Fetch
Read
Operation Access
Word
Data
Access
Internal
Operation
M
N
Instruction
Mnemonic
I
ADD
ADD.B #xx:8,Rd
1
ADD.B Rs,Rd
1
ADD.W #xx:16,Rd
2
ADD.W Rs,Rd
1
ADD.L #xx:32,ERd
3
ADD.L ERs,ERd
1
ADDS
ADDS #1/2/4,ERd
1
ADDX
ADDX #xx:8,Rd
1
ADDX Rs,Rd
1
AND
AND.B #xx:8,Rd
1
ANDC
BAND
Bcc
AND.B Rs,Rd
1
AND.W #xx:16,Rd
2
AND.W Rs,Rd
1
AND.L #xx:32,ERd
3
AND.L ERs,ERd
2
ANDC #xx:8,CCR
1
ANDC #xx:8,EXR
2
BAND #xx:3,Rd
1
J
K
L
BAND #xx:3,@ERd
2
1
BAND #xx:3,@aa:8
2
1
BAND #xx:3,@aa:16
3
1
BAND #xx:3,@aa:32
4
1
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
Rev.4.00 Sep. 18, 2008 Page 705 of 872
REJ09B0189-0400
Appendix A Instruction Set
Branch
Byte
Instruction Address Stack
Data
Fetch
Read
Operation Access
Word
Data
Access
Internal
Operation
M
N
Instruction
Mnemonic
I
Bcc
BVS d:8
2
BPL d:8
2
BMI d:8
2
BCLR
BGE d:8
2
BLT d:8
2
J
K
L
BGT d:8
2
BLE d:8
2
BRA d:16 (BT d:16)
2
1
BRN d:16 (BF d:16)
2
1
BHI d:16
2
1
BLS d:16
2
1
BCC d:16 (BHS d:16)
2
1
BCS d:16 (BLO d:16)
2
1
BNE d:16
2
1
BEQ d:16
2
1
BVC d:16
2
1
BVS d:16
2
1
BPL d:16
2
1
BMI d:16
2
1
BGE d:16
2
1
BLT d:16
2
1
BGT d:16
2
1
BLE d:16
2
1
BCLR #xx:3,Rd
1
BCLR #xx:3,@ERd
2
2
BCLR #xx:3,@aa:8
2
2
BCLR #xx:3,@aa:16
3
2
2
BCLR #xx:3,@aa:32
4
BCLR Rn,Rd
1
BCLR Rn,@ERd
2
2
BCLR Rn,@aa:8
2
2
BCLR Rn,@aa:16
3
2
BCLR Rn,@aa:32
4
2
Rev.4.00 Sep. 18, 2008 Page 706 of 872
REJ09B0189-0400
Appendix A Instruction Set
Branch
Byte
Instruction Address Stack
Data
Fetch
Read
Operation Access
Word
Data
Access
Internal
Operation
M
N
Instruction
Mnemonic
I
BIAND
BIAND #xx:3,Rd
1
BILD
BIOR
BIST
BIXOR
BLD
J
K
L
BIAND #xx:3,@ERd
2
1
BIAND #xx:3,@aa:8
2
1
BIAND #xx:3,@aa:16
3
1
BIAND #xx:3,@aa:32
4
1
BILD #xx:3,Rd
1
BILD #xx:3,@ERd
2
1
BILD #xx:3,@aa:8
2
1
BILD #xx:3,@aa:16
3
1
BILD #xx:3,@aa:32
4
1
BIOR #xx:8,Rd
1
BIOR #xx:8,@ERd
2
1
BIOR #xx:8,@aa:8
2
1
BIOR #xx:8,@aa:16
3
1
BIOR #xx:8,@aa:32
4
1
BIST #xx:3,Rd
1
BIST #xx:3,@ERd
2
2
BIST #xx:3,@aa:8
2
2
BIST #xx:3,@aa:16
3
2
BIST #xx:3,@aa:32
4
2
BIXOR #xx:3,Rd
1
BIXOR #xx:3,@ERd
2
1
BIXOR #xx:3,@aa:8
2
1
BIXOR #xx:3,@aa:16
3
1
BIXOR #xx:3,@aa:32
4
1
BLD #xx:3,Rd
1
BLD #xx:3,@ERd
2
1
BLD #xx:3,@aa:8
2
1
BLD #xx:3,@aa:16
3
1
BLD #xx:3,@aa:32
4
1
Rev.4.00 Sep. 18, 2008 Page 707 of 872
REJ09B0189-0400
Appendix A Instruction Set
Branch
Byte
Instruction Address Stack
Data
Fetch
Read
Operation Access
Word
Data
Access
Internal
Operation
M
N
Instruction
Mnemonic
I
BNOT
BNOT #xx:3,Rd
1
BOR
BSET
BSR
BST
J
K
L
BNOT #xx:3,@ERd
2
2
BNOT #xx:3,@aa:8
2
2
BNOT #xx:3,@aa:16
3
2
BNOT #xx:3,@aa:32
4
2
BNOT Rn,Rd
1
BNOT Rn,@ERd
2
2
BNOT Rn,@aa:8
2
2
BNOT Rn,@aa:16
3
2
BNOT Rn,@aa:32
4
2
BOR #xx:3,Rd
1
BOR #xx:3,@ERd
2
1
BOR #xx:3,@aa:8
2
1
BOR #xx:3,@aa:16
3
1
BOR #xx:3,@aa:32
4
1
BSET #xx:3,Rd
1
BSET #xx:3,@ERd
2
2
BSET #xx:3,@aa:8
2
2
BSET #xx:3,@aa:16
3
2
BSET #xx:3,@aa:32
4
2
BSET Rn,Rd
1
BSET Rn,@ERd
2
2
BSET Rn,@aa:8
2
2
BSET Rn,@aa:16
3
2
BSET Rn,@aa:32
4
2
BSR d:8
2
2
BSR d:16
2
2
1
BST #xx:3,Rd
1
BST #xx:3,@ERd
2
2
BST #xx:3,@aa:8
2
2
BST #xx:3,@aa:16
3
2
BST #xx:3,@aa:32
4
2
Rev.4.00 Sep. 18, 2008 Page 708 of 872
REJ09B0189-0400
Appendix A Instruction Set
Branch
Byte
Instruction Address Stack
Data
Fetch
Read
Operation Access
Word
Data
Access
Internal
Operation
M
N
Instruction
Mnemonic
I
BTST
BTST #xx:3,Rd
1
BXOR
J
K
L
BTST #xx:3,@ERd
2
1
BTST #xx:3,@aa:8
2
1
BTST #xx:3,@aa:16
3
1
BTST #xx:3,@aa:32
4
1
BTST Rn,Rd
1
BTST Rn,@ERd
2
1
BTST Rn,@aa:8
2
1
BTST Rn,@aa:16
3
1
BTST Rn,@aa:32
4
1
BXOR #xx:3,Rd
1
BXOR #xx:3,@ERd
2
1
BXOR #xx:3,@aa:8
2
1
BXOR #xx:3,@aa:16
3
1
BXOR #xx:3,@aa:32
4
1
CLRMAC
CLRMAC
Cannot be used in the H8S/2214 Group
CMP
CMP.B #xx:8,Rd
1
CMP.B Rs,Rd
1
CMP.W #xx:16,Rd
2
CMP.W Rs,Rd
1
CMP.L #xx:32,ERd
3
CMP.L ERs,ERd
1
DAA
DAA Rd
1
DAS
DAS Rd
1
DEC
DEC.B Rd
1
DEC.W #1/2,Rd
1
DEC.L #1/2,ERd
1
DIVXS.B Rs,Rd
2
DIVXS
DIVXU
11
DIVXS.W Rs,ERd
2
19
DIVXU.B Rs,Rd
1
11
DIVXU.W Rs,ERd
1
19
Rev.4.00 Sep. 18, 2008 Page 709 of 872
REJ09B0189-0400
Appendix A Instruction Set
Instruction
EEPMOV
Mnemonic
EEPMOV.B
Branch
Byte
Instruction Address Stack
Data
Fetch
Read
Operation Access
Word
Data
Access
Internal
Operation
I
M
N
EEPMOV.W
2
EXTS.W Rd
1
EXTS.L ERd
1
EXTU
EXTU.W Rd
1
EXTU.L ERd
1
INC
INC.B Rd
1
JSR
LDC
K
INC.W #1/2,Rd
1
INC.L #1/2,ERd
1
JMP @ERn
2
JMP @aa:24
2
JMP @@aa:8
2
2n + 2*
2n + 2*2
1
2
1
JSR @ERn
2
2
JSR @aa:24
2
2
JSR @@aa:8
2
LDC #xx:8,CCR
1
LDC #xx:8,EXR
2
LDC Rs,CCR
1
L
2
2
EXTS
JMP
J
2
1
2
LDC Rs,EXR
1
LDC @ERs,CCR
2
1
LDC @ERs,EXR
2
1
LDC @(d:16,ERs),CCR
3
1
LDC @(d:16,ERs),EXR
3
1
LDC @(d:32,ERs),CCR
5
1
LDC @(d:32,ERs),EXR
5
1
LDC @ERs+,CCR
2
1
1
1
LDC @ERs+,EXR
2
1
LDC @aa:16,CCR
3
1
LDC @aa:16,EXR
3
1
LDC @aa:32,CCR
4
1
LDC @aa:32,EXR
4
1
Rev.4.00 Sep. 18, 2008 Page 710 of 872
REJ09B0189-0400
Appendix A Instruction Set
Instruction
LDM*
4
LDMAC
Branch
Byte
Instruction Address Stack
Data
Fetch
Read
Operation Access
Word
Data
Access
Internal
Operation
Mnemonic
I
M
N
LDM.L @SP+,
(ERn-ERn+1)
2
4
1
LDM.L @SP+,
(ERn-ERn+2)
2
6
1
LDM.L @SP+,
(ERn-ERn+3)
2
8
1
LDMAC ERs,MACH
Cannot be used in the H8S/2214 Group
J
K
L
LDMAC ERs,MACL
MAC
MOV
MAC @ERn+,@ERm+
Cannot be used in the H8S/2214 Group
MOV.B #xx:8,Rd
1
MOV.B Rs,Rd
1
MOV.B @ERs,Rd
1
1
MOV.B @(d:16,ERs),Rd
2
1
MOV.B @(d:32,ERs),Rd
4
1
MOV.B @ERs+,Rd
1
1
MOV.B @aa:8,Rd
1
1
MOV.B @aa:16,Rd
2
1
MOV.B @aa:32,Rd
3
1
MOV.B Rs,@ERd
1
1
MOV.B Rs,@(d:16,ERd)
2
1
MOV.B Rs,@(d:32,ERd)
4
1
MOV.B Rs,@-ERd
1
1
MOV.B Rs,@aa:8
1
1
MOV.B Rs,@aa:16
2
1
MOV.B Rs,@aa:32
3
1
MOV.W #xx:16,Rd
2
MOV.W Rs,Rd
1
1
1
MOV.W @ERs,Rd
1
1
MOV.W @(d:16,ERs),Rd
2
1
MOV.W @(d:32,ERs),Rd
4
1
MOV.W @ERs+,Rd
1
1
MOV.W @aa:16,Rd
2
1
MOV.W @aa:32,Rd
3
1
MOV.W Rs,@ERd
1
1
1
Rev.4.00 Sep. 18, 2008 Page 711 of 872
REJ09B0189-0400
Appendix A Instruction Set
Branch
Byte
Instruction Address Stack
Data
Fetch
Read
Operation Access
Word
Data
Access
Internal
Operation
M
N
Instruction
Mnemonic
I
J
K
L
MOV
MOV.W Rs,@(d:16,ERd)
2
1
MOV.W Rs,@(d:32,ERd)
4
1
MOV.W Rs,@-ERd
1
1
MOV.W Rs,@aa:16
2
1
MOV.W Rs,@aa:32
3
1
MOV.L #xx:32,ERd
3
MOV.L ERs,ERd
1
MOV.L @ERs,ERd
2
2
MOV.L @(d:16,ERs),ERd
3
2
MOV.L @(d:32,ERs),ERd
5
2
MOV.L @ERs+,ERd
2
2
MOV.L @aa:16,ERd
3
2
MOV.L @aa:32,ERd
4
2
MOV.L ERs,@ERd
2
2
MOV.L ERs,@(d:16,ERd)
3
2
1
1
MOV.L ERs,@(d:32,ERd)
5
2
MOV.L ERs,@-ERd
2
2
MOV.L ERs,@aa:16
3
2
MOV.L ERs,@aa:32
4
2
MOVFPE
MOVFPE @:aa:16,Rd
Can not be used in the H8S/2214 Group
MOVTPE
MOVTPE Rs,@:aa:16
MULXS
MULXS.B Rs,Rd
2
11
MULXS.W Rs,ERd
2
19
MULXU
MULXU.B Rs,Rd
1
11
MULXU.W Rs,ERd
1
19
NEG
NEG.B Rd
1
NEG.W Rd
1
NEG.L ERd
1
NOP
NOP
1
NOT
NOT.B Rd
1
NOT.W Rd
1
NOT.L ERd
1
Rev.4.00 Sep. 18, 2008 Page 712 of 872
REJ09B0189-0400
1
Appendix A Instruction Set
Branch
Byte
Instruction Address Stack
Data
Fetch
Read
Operation Access
Word
Data
Access
Internal
Operation
M
N
Instruction
Mnemonic
I
OR
OR.B #xx:8,Rd
1
OR.B Rs,Rd
1
OR.W #xx:16,Rd
2
OR.W Rs,Rd
1
OR.L #xx:32,ERd
3
J
K
L
OR.L ERs,ERd
2
ORC
ORC #xx:8,CCR
1
ORC #xx:8,EXR
2
POP
POP.W Rn
1
1
1
POP.L ERn
2
2
1
PUSH
PUSH.W Rn
1
1
1
PUSH.L ERn
2
2
1
ROTL
ROTL.B Rd
1
ROTL.B #2,Rd
1
ROTL.W Rd
1
ROTR
ROTXL
ROTL.W #2,Rd
1
ROTL.L ERd
1
ROTL.L #2,ERd
1
ROTR.B Rd
1
ROTR.B #2,Rd
1
ROTR.W Rd
1
ROTR.W #2,Rd
1
ROTR.L ERd
1
ROTR.L #2,ERd
1
ROTXL.B Rd
1
ROTXL.B #2,Rd
1
ROTXL.W Rd
1
ROTXL.W #2,Rd
1
ROTXL.L ERd
1
ROTXL.L #2,ERd
1
Rev.4.00 Sep. 18, 2008 Page 713 of 872
REJ09B0189-0400
Appendix A Instruction Set
Branch
Byte
Instruction Address Stack
Data
Fetch
Read
Operation Ac