HD74LV1GW57A Configurable Multiple–Function Gate REJ03D0081-0200 Rev.2.00 May 19, 2006 Description The HD74LV1GW57A has configurable multiple–function gate in a 6 pin package. The Output state is determined by eight patterns of 3–bit input. The user can choose the logic functions AND, NAND, NOR, EX–NOR. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • Supply voltage range : 1.65 to 5.5 V Operating temperature range : –40 to +85°C • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) • Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • All the logical input has hysteresis voltage for the slow transition. • Ordering Information Part Name HD74LV1GW57ACME Package Type CMPAK-6 pin Package Code (Previous Code) PTSP0006JA-A (CMPAK-6V) Taping Abbreviation (Quantity) Package Abbreviation CM E (3,000 pcs / Reel) Outline and Article Indication • HD74LV1GW57A Index band Marking W R CMPAK–6 Rev.2.00, May 19, 2006 page 1 of 8 = Control code HD74LV1GW57A Function Table Inputs IN1 L L H H L L H H IN2 L L L L H H H H Output Y H L H L L L H H IN0 L H L H L H L H H : High level L : Low level Pin Arrangement IN1 1 6 IN2 GND 2 5 VCC IN0 3 4 Y (Top view) Logic Diagram IN0 Y IN1 IN2 Rev.2.00, May 19, 2006 page 2 of 8 HD74LV1GW57A Function Selection Table Logic Function Figure No. 1 4 2, 3 2, 3 4 1 5 2–input AND 2–input AND with both inputs inverted 2–input NAND with one input inverted 2–input OR with one input inverted 2–input NOR 2–input NOR with both inputs inverted 2–input EX–NOR Logic Configurations VCC A B A B Y A 1 (IN1) (IN2) 6 B 2 (GND) (VCC) 5 Y 3 (IN0) (Y) 4 VCC Y A B Y A B Y Figure 1. 2–inputs AND Gate A 1 (IN1) (IN2) 6 B 2 (GND) (VCC) 5 3 (IN0) (Y) 4 Y Figure 2. 2–inputs NAND Gate with A input inverted VCC 1 (IN1) A B Y A B Y (IN2) 6 B 2 (GND) (VCC) 5 A 3 (IN0) (Y) 4 Y Figure 3. 2–inputs NAND Gate with B input inverted A Y 1 (IN1) (IN2) 6 B 2 (GND) (VCC) 5 3 (IN0) (Y) 4 Figure 5. 2–inputs EX–NOR Gate Rev.2.00, May 19, 2006 page 3 of 8 1 (IN1) A B Y A B Y (IN2) 6 Y B 2 (GND) (VCC) 5 A 3 (IN0) (Y) 4 Figure 4. 2–inputs NOR Gate VCC A B VCC Y HD74LV1GW57A Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 VO Input clamp current Output clamp current Continuous output current IIK IOK IO Ratings –0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±25 ICC or IGND ±50 mA PT 200 mW Tstg –65 to 150 °C Continuous current through VCC or GND Symbol VCC VI Maximum power dissipation *3 at Ta = 25°C (in still air) Storage temperature Notes: Unit V V V mA mA mA Test Conditions Output : H or L VCC : OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Recommended Operating Conditions Item Supply voltage range Input voltage range Output voltage range Symbol VCC VI VO IOL Output current IOH Input transition rise or fall rate ∆t / ∆v Operating free-air temperature Ta Min 1.65 0 0 — — — — — — — Max 5.5 5.5 VCC 1 2 6 12 –1 –2 –6 — 0 0 0 –12 300 200 100 0 –40 20 85 Note: Unused or floating inputs must be held high or low. Rev.2.00, May 19, 2006 page 4 of 8 Unit V V V mA ns / V °C Conditions VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V HD74LV1GW57A Electrical Characteristic Ta = –40 to 85°C Item Symbol VT+ Threshold voltage VT– ∆VT VOH Output voltage VOL VCC (V) * 1.65 to 1.95 2.5 3.3 5.0 1.65 to 1.95 2.5 3.3 5.0 1.65 to 1.95 2.5 3.3 5.0 Min to Max 1.65 2.3 3.0 Min — — — — VCC×0.25 0.75 0.99 1.5 0.1 0.25 0.33 0.5 VCC–0.1 1.4 2.0 2.48 Typ — — — — — — — — — — — — — — — — Max VCC×0.75 1.75 2.31 3.50 — — — — VCC×0.4 1.0 1.32 2.0 — — — — 4.5 Min to Max 1.65 2.3 3.0 3.8 — — — — — — — — — — 0.1 0.3 0.4 0.44 Unit Test condition V V Input current IIN 4.5 0 to 5.5 — — — — 0.55 ±1 µA Quiescent supply current ICC 5.5 — — 10 µA IOH = –50 µA IOH = –1 mA IOH = –2 mA IOH = –6 mA IOH = –12 mA IOL = 50 µA IOL = 1 mA IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 Output leakage IOFF 0 — — 5 µA VIN or VO = 0 to 5.5 V current Input capacitance CIN 3.3 — 3.0 — pF VIN = VCC or GND Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.2.00, May 19, 2006 page 5 of 8 HD74LV1GW57A Switching Characteristics VCC = 1.8±0.15 V Item Symbol Propagation delay time tPLH tPHL Min — — Ta = 25°C Typ 15.8 22.6 Min — — Ta = 25°C Typ 9.4 12.6 Ta = –40 to 85°C Max 29.4 40.9 Min 1.0 1.0 Max 33.0 45.0 Unit ns Test Conditions CL = 15 pF CL = 50 pF FROM (Input) TO (Output) IN Y VCC = 2.5±0.2 V Item Symbol Propagation delay time tPLH tPHL Ta = –40 to 85°C Max 17.6 22.6 Min 1.0 1.0 Max 21.0 26.5 Unit ns Test Conditions CL = 15 pF CL = 50 pF FROM (Input) TO (Output) IN Y VCC = 3.3±0.3 V Item Symbol Propagation delay time tPLH tPHL Ta = 25°C Min — — Typ 7.0 9.5 Ta = –40 to 85°C Max 11.0 14.5 Min 1.0 1.0 Max 13.0 16.5 Unit ns Test Conditions CL = 15 pF CL = 50 pF FROM (Input) TO (Output) IN Y VCC = 5.0±0.5 V Item Symbol Propagation delay time tPLH tPHL Min — — Ta = 25°C Typ 4.8 6.3 Ta = –40 to 85°C Max 6.8 8.8 Min 1.0 1.0 Max 8.0 10.0 Unit ns Test Conditions CL = 15 pF CL = 50 pF FROM (Input) TO (Output) IN Y Operating Characteristics CL = 50 pF Item Power dissipation capacitance Symbol VCC (V) CPD 3.3 5.0 Min — — Ta = 25°C Typ 8.5 10.0 Max — — Unit pF Test Circuit Measurement point CL * Note: CL includes probe and jig capacitance. Rev.2.00, May 19, 2006 page 6 of 8 Test Conditions f = 10 MHz HD74LV1GW57A • Waveforms tf tr Input VCC 90% 90% 50% 50% 10% 10% t PLH GND t PHL VOH In phase output 50% 50% VOL VOH 50% Out of phase output t PHL 50% t PLH VOL Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. 2. The output are measured one at a time with one transition per measurement. Rev.2.00, May 19, 2006 page 7 of 8 HD74LV1GW57A Package Dimensions JEITA Package Code SC-88 Package Name CMPAK-6 RENESAS Code PTSP0006JA-A D Previous Code CMPAK-6 / CMPAK-6V MASS[Typ.] 0.006g A e Q c E HE LP L A A x M L1 S A A3 b Reference Symbol e A2 y S A A1 S e1 b l1 c b2 A-A Section Rev.2.00, May 19, 2006 page 8 of 8 Pattern of terminal position areas A A1 A2 A3 b c D E e HE L L1 LP x y b2 e1 l1 Q Dimension in Millimeters Min 0.8 0 0.8 0.15 0.1 1.8 1.15 2.0 0.3 0.1 0.2 Nom 0.9 0.25 0.2 0.15 2.0 1.25 0.65 2.1 Max 1.1 0.1 1.0 0.25 0.25 2.2 1.35 2.2 0.7 0.5 0.6 0.05 0.05 0.35 1.5 0.9 0.25 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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