Infineon IFX91041EJV50 1.8a dc/dc step-down voltage regulator 5.0v, 3.3v or adjustable output voltage Datasheet

IFX91041
1.8A DC/DC Step-Down Voltage Regulator
5.0V, 3.3V or Adjustable Output Voltage
IFX91041EJV50
IFX91041EJV33
IFX91041EJV
Data Sheet
Rev. 1.01, 2009-10-19
Standard Power
1.8A DC/DC Step-Down Voltage Regulator
1
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IFX91041
Overview
1.8A step down voltage regulator
Output voltage versions: 5.0 V, 3.3 V and adjustable
± 2% output voltage tolerance (+-4% for full load current range)
Integrated power transistor
PWM regulation with feedforward
Input voltage range from 4.75V to 45V
370 kHz switching frequency
Synchronization input
Very low shutdown current consumption (<2uA)
Soft-start function
Input undervoltage lockout
Suited for industrial applications: Tj = -40 °C to +125 °C
Green Product (RoHS compliant)
PG-DSO-8-27
For automotive and transportation applications, please refer to the Infineon TLE and TLF voltage regulator series.
Description
The IFX91041 series are monolithic integrated circuits that provide all active functions for a step-down (buck)
switching voltage regulator, capable of driving up to 1.8A load current with excellent line and load regulation.
These devices are suited for use under the harsh automotive electronics environmental conditions featuring
protection functions such as current limitation and overtemperature shutdown. Versions with a fixed 5.0V and 3.3V
(IFX91041EJV50, IFX91041EJV33) output voltage as well as an adjustable device (IFX91041EJV) with 0.60V
reference feedback voltage are available. The switching frequency of 370kHz allows to use small and inexpensive
passive components. The IFX91041 features an enable function reducing the shut-down current consumption
to <2uA. The voltage mode regulation scheme of this device provides a stable regulation loop maintained by small
external compensation components. Besides the feedforward control path offers an excellent line transient
rejection. The integrated soft-start feature limits the current peak as well as voltage overshot at start-up.
Type
Package
Marking
IFX91041EJV50
PG-DSO-8-27
I9104150
IFX91041EJV33
PG-DSO-8-27
I9104133
IFX91041EJV
PG-DSO-8-27
I91041V
Data Sheet
2
Rev. 1.01, 2009-10-19
IFX91041
Block Diagram
2
Block Diagram
7
EN
8
VS
Enable
Charge Pump
Over
Temperature
Shutdown
5
BDS
Feedforward
COMP
SYNC
3
1
Buck
Converter
6
BUO
Oscillator
4
Bandgap
Reference
FB
Soft start ramp
generator
IFX91041
2
Figure 1
Data Sheet
GND
Block Diagram
3
Rev. 1.01, 2009-10-19
IFX91041
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
SYNC
1
GND
IFX91041
8
VS
2
7
EN
COMP
3
6
BUO
FB
4
5
BDS
S08_PIN.vsd
Figure 2
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol Function
1
SYNC
Synchronization Input.
Connect to an external clock signal in order to synchronize/adjust the switching frequency.
If not used connect to GND.
2
GND
Ground.
3
COMP
Compensation Input.
Frequency compensation for regulation loop stability.
Connect to compensation RC-network.
4
FB
Feedback Input.
For the adjustable output voltage versions (IFX91041EJV) connect via voltage divider to output
capacitor.
For the fixed voltage version (IFX91041EJV50, IFX91041EJV33) connect this pin directly to the
output capacitor.
5
BDS
Buck Driver Supply Input.
Connect the bootstrap capacitor between this pin and pin BUO.
6
BUO
Buck Switch Output.
Source of the integrated power-DMOS transistor. Connect directly to the cathode of the catch
diode and the buck circuit inductance.
7
EN
Enable Input.
Active-high enable input with integrated pull down resistor.
8
VS
Supply Voltage Input.
Connect to supply voltage source.
Exposed Pad
Data Sheet
Connect to heatsink area and GND by low inductance wiring.
4
Rev. 1.01, 2009-10-19
IFX91041
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings1)
Tj = -40 °C to +125 °C; all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
-0.3
5.5
V
–
6.2
V
t < 10s2)
5.5
V
–
6.2
V
t < 10s1)
-0.3
10
V
IFX91041EJV50;
IFX91041EJV33
-0.3
5.5
V
IFX91041EJV
VBUO
VBUO
V
- 0.3
+ 5.5
VBUO
VEN
VVS
-2.0
VVS + 0.3
V
-40
45
V
-0.3
45
V
Tj
Tstg
-40
150
°C
–
-55
150
°C
–
VESD
-2
2
kV
HBM 3)
Voltages
4.1.1
4.1.2
Synchronization Input
Compensation Input
VSYNC
VCOMP
-0.3
4.1.3
4.1.4
Feedback Input
VFB
4.1.5
4.1.6
Buck Driver Supply Input
4.1.7
Buck Switch Output
4.1.8
Enable Input
4.1.9
Supply Voltage Input
VBDS
Temperatures
4.1.10
Junction Temperature
4.1.11
Storage Temperature
ESD Susceptibility
4.1.12
ESD Resistivity
1) Not subject to production test, specified by design.
2) Exposure to those absolute maximum ratings for extended periods of time (t > 10s) may affect device reliability
3) ESD susceptibility HBM according to EIA/JESD 22-A 114B (1.5kΩ,100pF).
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
5
Rev. 1.01, 2009-10-19
IFX91041
General Product Characteristics
4.2
Functional Range
Pos.
Parameter
Symbol
4.2.1
Supply Voltage
4.2.2
Output Voltage adjust range
4.2.3
Buck inductor
4.2.4
Buck capacitor
4.2.5
Buck capacitor ESR
4.2.6
Junction Temperature
VS
VCC
LBU
CBU1
ESRBU1
Tj
Limit Values
Unit
Conditions
Min.
Max.
4.75
45
V
–
0.60
16
V
IFX91041EJV
18
56
µH
–
33
120
µF
–
–
0.3
Ω
– 1)
-40
150
°C
–
1) See section ““Application Information” on Page 12” for loop compensation requirements.
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Pos.
Thermal Resistance
Parameter
Symbol
1)
4.3.1
Junction to Case
4.3.2
Junction to ambient1)
RthJC
RthJA
Limit Values
Unit
Conditions
Min.
Typ.
Max.
–
–
12
K/W
–
–
52
–
K/W
2)
1) Not subject to production test, specified by design.
2) According to Jedec JESD52-1,-5,-7 at natural convection on 2s2p FR4 PCB for 1W power dissipation. PCB
76.2x114.3x1.5mm3 with 2 inner copper layers of 70µm thickness. Thermal via array conected to the first inner copper layer
under the exposed pad.
Data Sheet
6
Rev. 1.01, 2009-10-19
IFX91041
Buck Regulator
5
Buck Regulator
5.1
Description
The gate of the power switch is driven by the external capacitor connected to pin BDS (Buck Driver Supply) using
the bootstrap principle. An integrated under voltage lockout function supervising the ’bootstrap’ capacitor voltage
ensures that the device is always driven with a sufficient bootstrap voltage in order to prevent from extensive heat
up of the power transistor. An integrated charge pump supports the gate drive in case of low input supply voltage,
small differential voltage between input supply and output voltage at low current and during startup. In order to
minimize emission, the charge pump is switched off if the input voltage is sufficient for supplying the bootstrap.
The soft start function generates a defined ramp of the output voltage during the first 0.5 ms (typ.) after device
initialization. The device initialization is triggered either by the EN voltage level crossing the turn-on threshold,
rising supply voltage (during EN=H), and also when the device restarts a after thermal shutdown. The ramp starts
after the BDS external capacitor is charged.
The regulation scheme uses a voltage controlled pulse width modulation with feed forward path (the feed forward
operates for supply voltages from 8.0V to 36V) which provides a fast line transient reaction.
In order to maintain the output voltage regulation even under low duty cycle conditions (light load conditions down
to ICC=0mA, high input voltage) a pulse skipping operation mode is implemented. Pulse skipping is also used for
operation with low supply voltages, related to high duty cycles >92%
In case of a lost connection to the pin FB , an internal pull-up current prevents from a uncontrolled rise of the output
voltage (version IFX91041EJV only).
COMP
OC
Comp.
L when Overcurrent
Error
Amp.
FB
Soft start
BDS
PWM H when
Comp. Error -Signal <
Error -Signal
Error -Ramp
VRef
Output Stage
OFF when H
L when
Tj > 175 °C
=
OFF
when H
R
&
t
V low
Clock
tr tf tr
S
S
Ramp Vhigh
H = INV
Q OFF
1
Q
H=
ON
Power
D-MOS
BUO
&
Q
PWM-FF
&
Schmitt-Trigger 1
V max
V min
&
Gate Driver
Supply
Gate
Driver
L when
Output
overvoltage
Feedforward
ΔV=k X VS
Oscillator
tr tf tr
_
>1
R
Ramp
Generator
SYNC
Charge
Pump
NOR1
Error -Ramp
0.6 V
VS
=
Q
Error -FF
NAND 2
&
H when
UV at V BDS
t
BDS
UV Comp.
=
Figure 3
Data Sheet
Block Diagram Buck Regulator
7
Rev. 1.01, 2009-10-19
IFX91041
Buck Regulator
5.2
Electrical Characteristics
Electrical Characteristics: Buck Regulator
VS = 6.0 V to 40 V, Tj = -40 °C to +125 °C, all voltages with respect to ground (unless otherwise specified)
Pos.
5.2.1
Parameter
Output voltage
Symbol
VFB
Limit Values
Min.
Typ.
Max.
4.90
5.00
5.10
Unit
Conditions
V
IFX91041EJV50;
VVEN = VS
0.1A < ICC < 1.0A
VFB
5.2.2
5.2.3
Output voltage
5.2.4
VFB
4.80
5.00
5.20
V
3.23
VFB
3.17
VFB
3.30
V
V
0.588 0.60
0.612
V
VFB
0.576 0.60
0.624
V
ICC,MIN
0
–
–
mA
5.2.8
1
–
–
mA
5.2.9
1.5
Output voltage
5.2.6
5.2.7
Minimum output load requirement
3.30
3.37
3.43
5.2.5
IFX91041EJV50;
VVEN = VS;
mA
1mA < ICC < 1.8A
IFX91041EJV33;
VVEN = VS;
0.1A < ICC < 1.0A
IFX91041EJV33;
VVEN = VS;
1mA < ICC < 1.8A
IFX91041EJV;
VVEN = VS;
FB connected to VCC;
VS = 12V
0.1A < ICC < 1.0A
IFX91041EJV;
VVEN = VS;
FB connected to VCC;
VS = 12V
1mA < ICC < 1.8A
IFX91041EJV501)
IFX91041EJV331)
IFX91041EJV
VCC > 3V1)
5.2.10
5
mA
IFX91041EJV
VCC > 1.5V1)
5.2.11
10
–
–
mA
IFX91041EJV
VCC > =0.6V1)
5.2.12
FB input current
IFB
-1
-0.1
0
µA
IFX91041EJV
VFB = 0.6V
5.2.13
FB input current
IFB
–
–
900
µA
IFX91041EJV50,
IFX91041EJV33
5.2.14
Power stage on-resistance
–
–
500
mΩ
tested at 300 mA
5.2.15
Current transition rise/fall time
–
50
–
ns
5.2.16
Buck peak over current limit
2.2
–
3.6
A
ICC=1 A 2)
–
5.2.17
Bootstrap under voltage lockout,
turn-off threshold
Ron
tr
IBUOC
VBDS,off
–
V
Bootstrap voltage
decreasing
–
mA
VS = 12V;
VBUO = VBDS = GND
5.2.18
Charge pump current
Data Sheet
VBUO –
+3.3
ICP
2
8
–
Rev. 1.01, 2009-10-19
IFX91041
Buck Regulator
Electrical Characteristics: Buck Regulator
VS = 6.0 V to 40 V, Tj = -40 °C to +125 °C, all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
VBDS VBUO
Dmax
tstart
–
–
5
V
(VBDS - VBUO) increasing
–
–
100
%
3)
350
500
750
µs
VFB rising from 5% to
95% of VFB,nom
5.2.19
Charge pump switch-off threshold
5.2.20
Maximum duty cycle
5.2.21
Soft start ramp
5.2.22
Input under voltage shutdown
threshold
VS,off
3.75
–
–
V
VS decreasing
5.2.23
Input voltage startup threshold
–
–
4.75
V
VS increasing
5.2.24
Input under voltage shutdown
hysteresis
VS,on
VS,hyst
150
–
–
mV
–
1) Not subject to production test, application related parameter
2) Not subject to production test; specified by design.
3) Consider “Chapter 4.2, Functional Range”
Data Sheet
9
Rev. 1.01, 2009-10-19
IFX91041
Module Enable and Thermal Shutdown
6
Module Enable and Thermal Shutdown
6.1
Description
With the enable pin the device can be set in off-state reducing the current consumption to less than 2µA.
The enable function features an integrated pull down resistor which ensures that the IC is shut down and the power
switch is off in case the pin EN is left open.
The integrated thermal shutdown function turns the power switch off in case of overtemperature. The typ. junction
shutdown temperature is 175°C, with a min. of 160°C. After cooling down the IC will automatically restart
operation. The thermal shutdown is an integrated protection function designed to prevent IC destruction when
operating under fault conditions. It should not be used for normal operation.
6.2
Electrical Characteristics Module Enable, Bias and Thermal Shutdown
Electrical Characteristics: Enable, Bias and Thermal Shutdown
VS = 6.0 V to 40 V, Tj = -40 °C to +125 °C, all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
VEN = 0.8V;
Tj < 105°C; VS = 16V
VEN = 5.0V; ICC = 0mA;
VS = 16V
FB connected to VOUT
VEN = 5.0V; ICC = 1.8A;
VS = 16V
FB connected to VOUT1)
6.2.1
Current Consumption,
shut down mode
Iq,OFF
–
0.1
2
µA
6.2.2
Current Consumption,
active mode
Iq,ON
–
–
7
mA
6.2.3
Current Consumption,
active mode
Iq,ON
–
–
10
mA
6.2.4
VEN,lo
VEN,hi
Enable hysteresis
VEN,HY
Enable high input current
IEN,hi
Enable low input current
IEN,lo
Over temperature shutdown Tj,sd
Over temperature shutdown Tj,sd_hyst
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
Enable high signal valid
3.0
–
–
V
–
Enable low signal valid
–
–
0.8
V
–
50
200
400
mV
1)
–
–
30
µA
–
0.1
1
µA
VEN = 16V
VEN = 0.5V
160
175
190
°C
1)
–
15
–
K
1)
hysteresis
1) Specified by design. Not subject to production test.
Data Sheet
10
Rev. 1.01, 2009-10-19
IFX91041
Module Oscillator
7
Module Oscillator
7.1
Description
The oscillator turns on the power switch with a constant frequency while the buck regulating circuit turns the power
transistor off in every cycle with an appropriate time gap depending on the output and input voltage.
The internal sawtooth signal used for the PWM generation has an amplitude proportional to the input supply
voltage (feedforward).
The turn-on frequency can optionally be set externally via the ’SYNC’ pin using a TTL compatible input signal. In
this case the synchronization of the PWM-on signal refers to the falling edge of the ’SYNC’-pin input signal. In case
the synchronization to an external clock signal is not needed the ’SYNC’ pin should be connected to GND.
Leaving pin SYNC open or short-circuiting it to GND leads to normal operation with the internal switching
frequency.
7.2
Electrical Characteristics Module Oscillator
Electrical Characteristics: Buck Regulator
VS = 6.0 V to 40 V, Tj = -40 °C to +125 °C, all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
7.2.1
Oscillator frequency
7.2.2
Synchronization capture range
7.2.3
SYNC signal high level valid
7.2.4
SYNC signal low level valid
7.2.5
SYNC input internal pull-down
fosc
fsync
VSYNC,hi
VSYNC,lo
RSYNC
Limit Values
Unit
Conditions
VSYNC = 0V
Min.
Typ.
Max.
330
370
420
kHz
530
kHz
200
V
1)
0.8
V
1)
1.4
MΩ
VSYNC = 5V
2.9
0.60
1.0
1) Synchronization of PWM-on signal to falling edge.
Data Sheet
11
Rev. 1.01, 2009-10-19
IFX91041
Application Information
8
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
8.1
Frequency Compensation
The stability of the output voltage can be achieved with a simple RC connected between pin COMP and GND. The
standard configuration using the swiching frequency of the internal oscillator is a ceramic capacitor CCOMP = 22nF
and RCOMP = 22kΩ. By slight modifications to the compensation network the stability can be optimized for different
application needs, such as varying switching frequency (using the sychronizing function), different types of buck
capacitor (ceramic or tantalum) etc.
The compensation network is essential for control loop stability. Leaving pin COMP open might lead to instable
operation.
8.2
Compensating a tantalum buck capacitor CBU1
The TLE control loop is optimized for ceramic buck capacitors CBU. In order to maintain stability also for tantalum
capacitors with ESR up to 300mΩ, an additional compensation capacitance CCOMP2 at pin COMP to GND is
required. It’s value calculates:
CCOMP2 = CBU * ESR(CBU) / RCOMP ,
whereas CCOMP2 needs to stay below 5nF.
Application _C-COMP2.vsd
COMP
3
IFX91041
CCOMP
CCOMP2
2
RCOMP
GND
Figure 4
High-ESR buck capacitor compensation
8.3
Catch Diode
In order to minimize losses and for fast recovery, a schottky catch diode is required. Disconnecting the catch diode
during operation might lead to destruction of the IC.
Data Sheet
12
Rev. 1.01, 2009-10-19
IFX91041
Application Information
8.4
IFX91041EJV50, IFX91041EJV33 with fixed Output Voltage
LI
22…47µH
D1
VBatt
Ignition Key
Terminal 15
7
EN
8
VS
Enable
Charge Pump
Over
Temperature
Shutdown
5
BDS
Feedforward
COMP
3
CBOT
220nF
Buck
Converter
6
BUO
DBU
CCOMP
SYNC
1
Oscillator
4
FB
LBU
VOUT
47µH
CBU1
CBU2
100µF
220nF
RCOMP
Bandgap
Reference
Soft start ramp
generator
IFX91041EJV50
IFX91041EJV33
2
Figure 5
GND
Application Diagram IFX91041EJV50 or IFX91041EJV33
Note: This is a very simplified example of an application circuit. The function must be verified in the real application
Data Sheet
13
Rev. 1.01, 2009-10-19
IFX91041
Application Information
8.5
Adjustable Output Voltage Device
LI
22…47µH
D1
VBatt
Ignition Key
Terminal 15
7
EN
8
Biasing &
Enable
VS
Charge Pump
Over
Temperature
Shutdown
5
BDS
Feedforward
COMP
3
CBOT
Buck
Converter
220nF
6
BUO
DBU
CCOMP
SYNC
1
Oscillator
LBU
VOUT
47µH
R1
4
FB
RCOMP
Bandgap
Reference
Soft start ramp
generator
CFB
CBU1
CBU2
100µF
220nF
R2
IFX91041EJV
2
Figure 6
GND
Application Diagram IFX91041EJV
Note: This is a very simplified example of an application circuit. The function must be verified in the real application
The output voltage of the IFX91041EJV can be programmed by a voltage divider connected to the feedback pin
FB. The divider cross current should be 300 µA at minimum, therefore the maximum R2 calculates:
R2 ≤ VFB / IR2 --> R2 ≤ 0.6V / 300 µA = 2 kΩ
For the desired output voltage level VCC, R1 calculates then (neglecting the small FB input current):
V CC ⎞
R 1 = R 2 ⎛ ---------–1 .
⎝V
⎠
FB
Add a 0.5 nF capacitor close to FB pin.
Data Sheet
14
Rev. 1.01, 2009-10-19
IFX91041
Package Outlines
9
Package Outlines
0.35 x 45˚
1.27
0.41±0.09 2)
0.2
M
0.08 C
Seating Plane
C A-B D 8x
0˚...8˚
0.64 ±0.25
D
1
5
1
6 ±0.2
0.2
M
D 8x
Bottom View
3 ±0.1
A
8
0.19 +0.06
8˚ MAX.
8˚ MAX.
C
0.1 C D 2x
4
8
4
5
2.65 ±0.1
0˚...8˚
1.7 MAX.
Stand Off
(1.45)
0.2 +0
-0.1
8˚ MAX.
0.1+0
-0.1
3.9 ±0.11)
B
4.9 ±0.11)
0.1 C A-B 2x
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
3) JEDEC reference MS-012 variation BA
Figure 7
GPS01206
Outline PG-DSO-8-27
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further package information, please visit our website:
http://www.infineon.com/packages.
Data Sheet
15
Dimensions in mm
Rev. 1.01, 2009-10-19
IFX91041
Revision History
10
Revision History
Rev
Rev.1.01 2009-10-19 Overview page: Inserted reference statement to TLE/TLF series.
Rev.1.0
2009-05-04 Final data sheet
Data Sheet
16
Rev. 1.01, 2009-10-19
Edition 2009-10-19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
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