TI1 BQ27441DRZR-G1A System-side impedance track fuel gauge Datasheet

bq27441-G1
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SLUSBH1A – NOVEMBER 2013 – REVISED JANUARY 2014
System-Side Impedance Track™ Fuel Gauge
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FEATURES
APPLICATIONS
•
•
•
•
•
1
23
•
•
•
Single Series Cell Li-Ion Battery Fuel Gauge
– Resides on System Board
– Supports Embedded or Removable
Batteries
– Powered Directly from Battery with
Integrated LDO
– Supports a Low-Value External Sense
Resistor (10mΩ)
Easy to Configure Fuel Gauging Based on
Patented Impedance Track™ Technology
– Reports Remaining Capacity and State of
Charge (SOC) with Smoothing Filter
– Automatically Adjusts for Battery Aging,
Self-discharge, Temperature, and Rate
Changes
– Battery State of Health (Aging) Estimation
Microcontroller Peripheral Supports:
– 400-kHz I2C™ Serial Interface
– Configurable SOC Interrupt, or
Battery Low Digital Output Warning
– Internal Temperature Sensor, or
Host Reported Temperature
Small 12-pin 2.5 mm × 4 mm SON Package
Smartphones, Feature Phones and Tablets
Digital Still and Video Cameras
Handheld Terminals
MP3 or Multimedia Players
DESCRIPTION
The Texas Instruments bq27441-G1 is an easy to
configure microcontroller peripheral that provides
system-side fuel gauging for single-cell Li-Ion
batteries. The device requires minimal user
configuration and system microcontroller firmware
development.
The bq27441-G1 uses the patented Impedance
Track™ algorithm for fuel gauging, and provides
information such as remaining battery capacity
(mAh), state-of-charge (%), and battery voltage (mV).
Battery fuel gauging with the bq27441-G1 requires
connections only to PACK+ (P+) and PACK– (P–) for
a removable battery pack or embedded battery
circuit. The tiny 12-pin 2.5 mm × 4 mm SON package
is ideal for space constrained applications.
TYPICAL APPLICATION
SRN
SCL
I2C
Bus
VSYS
Coulomb
Counter
SDA
SRP
CPU
Battery Pack
GPOUT
BIN
PACKP
BAT
ADC
Li-Ion
Cell
VDD
bq27441
1.8V
LDO
VSS
T
Protection
IC
PACKN
NFET NFET
0.47uF
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Impedance Track is a trademark of Texas Instruments.
I2C is a trademark of NXP B.V. Corp Netherlands.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013–2014, Texas Instruments Incorporated
bq27441-G1
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
AVAILABLE OPTIONS
BATTERY
TYPE
PART NUMBER
bq27441DRZR-G1A
LiCoO2
(4.2 V max charge)
0x0128
LiMn2O4
(4.3 - 4.35 V max charge)
0x0312
bq27441DRZT-G1A
bq27441DRZR-G1B
bq27441DRZT-G1B
(1)
(2)
(3)
(4)
CHEM_ID
(1)
DM_CODE
(2)
FIRMWARE
VERSION (3)
0x48
1.09
(0x0109)
0x58
PACKAGE
(4)
12-pin,
2.5 × 4 mm
SON
See the CHEM_ID subcommand to confirm the battery chemistry type.
See the DM_CODE subcommand to confirm the Data Memory code.
See the FW_VERSION subcommand to confirm the firmware version.
For the most current package and ordering information see the Package Option Addendum at the end of this document; or, see the TI
website at www.ti.com.
THERMAL INFORMATION
THERMAL METRIC (1)
bq27441-G1
DRZ (12-PINS)
θJA
Junction-to-ambient thermal resistance
64.1
θJCtop
Junction-to-case (top) thermal resistance
59.8
θJB
Junction-to-board thermal resistance
52.7
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
28.3
θJCbot
Junction-to-case (bottom) thermal resistance
2.4
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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PIN DIAGRAM AND PACKAGE DIMENSIONS
PIN DIAGRAM
(TOP VIEW)
SDA
1
12
GPOUT
SCL
2
11
NC
VSS
3
10
BIN
NC
4
9
NC
VDD
5
8
SRP
BAT
6
7
SRN
bq27441
12-pin VSON, 2.5 x 4mmm 0.4mm pitch
PIN FUNCTIONS
PIN
NAME
NO.
TYPE
(1)
DESCRIPTION
BAT
6
PI, AI
LDO regulator input, battery voltage input, and coulomb counter input typically connected to the PACK+ terminal.
VDD
5
PO
1.8V Regulator Output. Decouple with 0.47μF ceramic capacitor to Vss. This pin is not intended to provide power
for other devices in the system.
VSS
3
PI
Ground pin.
SRP
8
AI
SRN
7
AI
Coulomb counter differential inputs expecting an external 10mΩ, 1% sense resistor. Connect SRP to BAT (CELLP)
and connect SRN to PACKP. Refer to application diagram.
GPOUT
12
DO
SDA
1
DIO
SCL
2
DIO
BIN
10
DI
Battery-insertion detection input. A logic high to low transition is detected as a battery insertion event. Recommend
using a pull-up resistor >1MΩ (1.8 MΩ typical) to VDD for reduced power consumption. An internal pull-up resistor
option is also available.
NC
4, 8, 11
--
No internal connection. May be left floating or tied to VSS.
(1)
General Purpose open-drain output. May be configured as a Battery Low indicator or perform SOC interrupt
(SOC_INT) function.
Slave I2C serial bus for communication with system (Master). Open-drain pins. Use with external 10kΩ pull-up
resistors (typical) for each pin. If the external pull-up resistors will be disconnected from these pins during normal
operation, recommend using external 1MΩ pull-down resistors to VSS at each pin to avoid floating inputs.
I/O = Digital input/output, IA = Analog input, P = Power connection
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ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
VBAT
VSR
MIN
MAX
UNIT
BAT pin input voltage range
–0.3
6
V
SRP and SRN pins input voltage range
-0.3
[VBAT + 0.3]
V
2
V
Differential voltage across SRP and SRN. ABS(SRP - SRN).
VDD
VDD pin supply voltage range (LDO ouptut)
–0.3
2
V
VIOD
Open-drain I/O pins (SDA, SCL)
–0.3
6
V
VIOPP
Push-Pull I/O pins (BIN )
–0.3
[VDD + 0.3]
V
TA
Operating free-air temperature range
–40
85
°C
TSTG
Storage temperature range
–65
150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
TA = 30°C and VREGIN = VBAT = 3.6V (unless otherwise noted)
PARAMETER
External input capacitor for internal
LDO between BAT and VSS
CBAT (1)
CLDO18
VPU
(1)
(1)
(1)
External output capacitor for internal
LDO between VDD and VSS
TEST CONDITIONS
MIN
Nominal capacitor values specified.
Recommend a 5% ceramic X5R type
capacitor located close to the device.
External pull-up voltage for opendrain pins (SDA, SCL, GPOUT )
TYP
MAX
UNIT
0.1
μF
0.47
μF
1.62
3.6
V
Specified by design. Not production tested.
SUPPLY CURRENT
TA = 30°C and VREGIN = VBAT = 3.6V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
NORMAL mode current
ILOAD > Sleep Current
(2)
ISLP
(1)
SLEEP mode current
ILOAD < Sleep Current
(2)
IHIB
(1)
HIBERNATE mode current
ILOAD < Hibernate Current
ISD
(1)
SHUTDOWN mode current
Fuel gauge in host commanded
SHUTDOWN mode.
(LDO Regulator Output Disabled.)
ICC
(1)
(2)
4
(1)
(2)
MIN
TYP
MAX
UNIT
93
μA
21
μA
9
μA
0.6
μA
Specified by design. Not production tested.
Wake Comparator Disabled.
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DIGITAL INPUT AND OUTPUT DC CHARACTERISTICS
TA = –40°C to 85°C, typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(Force Note1) (1)
PARAMETER
TEST CONDITIONS
VIH(OD)
Input voltage, high
(2)
VIH(PP)
Input voltage, high
(3)
VIL
Input voltage, low
VOL
Output voltage, low
External pullup resistor to VPU
(1)
(2)
(3)
VPU x 0.7
V
V
V
(2)
0.6
V
0.5
mA
-3
mA
5
pF
1
μA
Output sink current, low
(2)
(2)
(2) (3)
Input leakage current (I/O pins)
Ilkg
UNIT
0.6
Output source current, high
Input capacitance
MAX
(2) (3)
IOL(OD)
(1)
TYP
1.4
IOH
CIN
MIN
(2) (3)
Specified by design. Not production tested.
Open Drain pins: (SCL, SDA, GPOUT )
Push Pull pin: (BIN )
LDO REGULATOR, WAKE-UP AND AUTO-SHUTDOWN DC CHARACTERISTICS
TA = –40°C to 85°C, typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(Force Note1) (1)
PARAMETER
VBAT
BAT pin regulator input
VDD
Regulator output voltage
UVLOIT+
VBAT Under Voltage Lock Out
LDO Wake-Up Rising Threshold
UVLOIT-
VBAT Under Voltage Lock Out
LDO Auto-Shutdown Falling
Threshold
VWU+
(1)
(2)
(1)
GPOUT (input) LDO Wake-Up
rising edge threshold (2)
TEST CONDITIONS
MIN
TYP
2.45
LDO Wake-up from SHUTDOWN
mode
MAX
UNIT
4.5
V
1.8
V
2
V
1.95
V
1.2
V
Specified by design. Not production tested.
If the device is commanded to SHUTDOWN via I2C with VBAT > UVLOIT+ , a wake-up rising edge trigger is required on GPOUT .
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LDO REGULATOR, WAKE-UP AND AUTO-SHUTDOWN AC CHARACTERISTICS
TA = –40°C to 85°C, typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(Force Note1) (1)
PARAMETER
tSHDN
(1)
tSHUP (1)
tVDD
(1)
tWUVDD
tPUCD
(1)
TEST CONDITIONS
MIN
SHUTDOWN Entry Time
Time delay from SHUTDOWN
command to LDO output disable.
SHUTDOWN GPOUT Low time
Minimum low time of GPOUT (input)
in SHUTDOWN before WAKEUP
(1)
Wake-up VDD Output delay
Power-up communication delay
Time delay from rising edge of
REGIN to the Active state. Includes
firmware initialization time.
MAX
UNIT
250
ms
μs
10
Initial VDD Output delay
Time delay from rising edge of
GPOUT (input) to nominal VDD
output.
TYP
13
ms
8
ms
250
ms
Specified by design. Not production tested.
SHUTDOWN and WAKE-UP Timing
tPUCD
tSHUP
tVDD
tSHDN
tPUCD
tWUVDD
REGIN
VDD
I2C Bus
GPOUT
SHUTDOWN_
ENABLE
SHUTDOWN
*
State
Off
WAKE-UP
Active
SHUTDOWN
WAKE-UP
Active
* GPOUT is configured as an input for wake-up signaling.
Figure 1. SHUTDOWN and WAKE-UP Timing Diagram
6
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ADC (TEMPERATURE AND CELL MEASUREMENT) CHARACTERISTICS
TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted) (Force Note1) (1)
PARAMETER
VIN(BAT)
BAT pin voltage measurement
range.
tADC_CONV
Conversion time
TEST CONDITIONS
Voltage divider enabled.
MIN
2.45
Effective Resolution
(1)
TYP
MAX
4.5
UNIT
V
125
ms
15
bits
Specified by design. Not tested in production.
INTEGRATING ADC (COULOMB COUNTER) CHARACTERISTICS
TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(Force Note1) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VSR
Input voltage range from BAT to
SRX pins
tSR_CONV
Conversion time
Single conversion
1
s
Effective Resolution
Single conversion
16
bits
(1)
BAT ± 25
UNIT
mV
Assured by design. Not tested in production.
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I2C-COMPATIBLE INTERFACE COMMUNICATION TIMING CHARACTERISTICS
TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted) (Force Note1) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Standard Mode (100 kHz)
4
μs
4.7
μs
4
μs
4.7
μs
250
ns
td(STA)
Start to first falling edge of SCL
tw(L)
SCL pulse duration (low)
tw(H)
SCL pulse duration (high)
tsu(STA)
Setup for repeated start
tsu(DAT)
Data setup time
Host drives SDA
th(DAT)
Data hold time
Host drives SDA
0
ns
tsu(STOP)
Setup time for stop
4
μs
t(BUF)
Bus free time between stop and Includes Command Waiting Time
start
66
μs
tf
SCL/SDA fall time
tr
SCL/SDA rise time
fSCL
Clock frequency (2)
(1)
300
(1)
ns
300
ns
100
kHz
Fast Mode (400 kHz)
td(STA)
Start to first falling edge of SCL
600
ns
tw(L)
SCL pulse duration (low)
1300
ns
tw(H)
SCL pulse duration (high)
600
ns
tsu(STA)
Setup for repeated start
600
ns
tsu(DAT)
Data setup time
Host drives SDA
100
ns
th(DAT)
Data hold time
Host drives SDA
0
ns
tsu(STOP)
Setup time for stop
600
ns
t(BUF)
Bus free time between stop and Includes Command Waiting Time
start
66
μs
tf
SCL/SDA fall time
tr
SCL/SDA rise time
fSCL
Clock frequency (2)
(1)
(2)
(1)
300
(1)
ns
300
ns
400
kHz
Specified by design. Not production tested.
If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at
400 kHz. (Refer to I2C INTERFACE and I2C Command Waiting Time)
tSU(STA)
tw(H)
tf
tw(L)
tr
t(BUF)
SCL
SDA
td(STA)
tsu(STOP)
tf
tr
th(DAT)
tsu(DAT)
REPEATED
START
STOP
START
Figure 2. I2C-Compatible Interface Timing Diagrams
8
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GENERAL DESCRIPTION
The bq27441-G1 accurately predicts the battery capacity and other operational characteristics of a single Libased rechargeable cell. It can be interrogated by a system processor to provide cell information, such as stateof-charge (SOC).
Information is accessed through a series of commands, called Standard Commands. Further capabilities are
provided by the additional Extended Commands set. Both sets of commands, indicated by the general format
Command( ), are used to read and write information contained within the bq27441-G1 control and status
registers, as well as its data locations. Commands are sent from system to gauge using the bq27441-G1’s I2C
serial communications engine, and can be executed during application development, system manufacture, or
end-equipment operation.
The key to the bq27441-G1’s high-accuracy gas gauging prediction is Texas Instrument’s proprietary Impedance
Track™ algorithm. This algorithm uses cell measurements, characteristics, and properties to create state-ofcharge predictions that can achieve high accuracy across a wide variety of operating conditions and over the
lifetime of the battery.
The bq27441-G1 measures charge/discharge activity by monitoring the voltage across a small-value sense
resistor. When a cell is attached to the bq27441-G1, cell impedance is computed, based on cell current, cell
open-circuit voltage (OCV), and cell voltage under loading conditions.
The bq27441-G1 uses an integrated temperature sensor for estimating cell temperature. Alternatively, the host
processor can provide temperature data for the bq27441-G1.
To minimize power consumption, the bq27441-G1 has several power modes: INITIALIZATION, NORMAL,
SLEEP, and HIBERNATE. The bq27441-G1 passes automatically between these modes, depending upon the
occurrence of specific events, though a system processor can initiate some of these modes directly. More details
are found in the bq27441-G1 Technical Reference Manual (SLUUAC9).
NOTE
Formatting Conventions in this Document:
Commands: italics with parentheses( ) and no breaking spaces, for example,
RemainingCapacity( ).
Data Flash: italics, bold, and breaking spaces, for example, Design Capacity.
Register bits and flags: italics with brackets [ ], for example, [TDA]
Data flash bits: italics, bold, and brackets [ ], for example, [LED1]
Modes and states: ALL CAPITALS, for example, UNSEALED mode.
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DATA COMMANDS
STANDARD DATA COMMANDS
The bq27441-G1 uses a series of 2-byte standard commands to enable system reading and writing of battery
information. Each standard command has an associated command-code pair, as indicated in . Because each
command consists of two bytes of data, two consecutive I2C transmissions must be executed both to initiate the
command function, and to read or write the corresponding two bytes of data. Additional details are found in the
bq27441-G1 Technical Reference Manual (SLUUAC9).
Table 1. Standard Commands
NAME
COMMAND
CODE
SEALED ACCESS
Control( )
CNTL
0x00 / 0x01
N/A
R/W
Temperature( )
TEMP
0x02 / 0x03
0.1°K
R/W
VOLT
0x04 / 0x05
mV
R
FLAGS
0x06 / 0x07
N/A
R
NominalAvailableCapacity( )
0x08 / 0x09
mAh
R
FullAvailableCapacity( )
0x0a / 0x0b
mAh
R
Voltage( )
Flags( )
RemainingCapacity( )
RM
0x0c / 0x0d
mAh
R
FullChargeCapacity( )
FCC
0x0e / 0x0f
mAh
R
AverageCurrent( )
0x10 / 0x11
mA
R
StandbyCurrent( )
0x12 / 0x13
mA
R
MaxLoadCurrent( )
0x14 / 0x15
mA
R
AveragePower( )
0x18 / 0x19
mW
R
0x1c / 0x1d
%
R
0x1e / 0x1f
0.1°K
R
0x20 / 0x21
num / %
R
StateOfCharge( )
SOC
IntTemperature( )
StateOfHealth( )
10
UNITS
SOH
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Control( ): 0x00/0x01
Issuing a Control( ) command requires a subsequent 2-byte subcommand. These additional bytes specify the
particular control function desired. The Control( ) command allows the system to control specific features of the
bq27441-G1 during normal operation and additional features when the device is in different access modes, as
described in . Additional details are found in the bq27441-G1 Technical Reference Manual (SLUUAC9).
Table 2. Control( ) Subcommands
CNTL FUNCTION
CNTL DATA
SEALED ACCESS
CONTROL_STATUS
0x0000
Yes
DESCRIPTION
Reports the status of device.
DEVICE_TYPE
0x0001
Yes
Reports the device type (0x0421).
FW_VERSION
0x0002
Yes
Reports the firmware version of the device.
DM_CODE
0x0004
Yes
Reports the Data Memory Code number stored in NVM.
PREV_MACWRITE
0x0007
Yes
Returns previous MAC command code.
CHEM_ID
0x0008
Yes
Reports the chemical identifier of the Impedance Track™ configuration
BAT_INSERT
0x000c
Yes
Forces the [BAT_DET] bit set when the [BIE] bit is 0.
BAT_REMOVE
0x000d
Yes
Forces the [BAT_DET] bit clear when the [BIE] bit is 0.
SET_HIBERNATE
0x0011
Yes
Forces CONTROL_STATUS [HIBERNATE] to 1.
CLEAR_HIBERNATE
0x0012
Yes
Forces CONTROL_STATUS [HIBERNATE] to 0.
SET_CFGUPDATE
0x0013
No
Force CONTROL_STATUS [CFGUPMODE] to 1 and gauge enters
CONFIG UPDATE mode.
SHUTDOWN_ENABLE
0x001b
No
Enables device SHUTDOWN mode.
SHUTDOWN
0x001c
No
Commands the device to enter SHUTDOWN mode.
SEALED
0x0020
No
Places the device in SEALED access mode.
TOGGLE_GPOUT
0x0023
Yes
Commands the device to toggle the GPOUT pin for 1ms.
RESET
0x0041
No
Performs a full device reset.
SOFT_RESET
0x0042
No
Gauge exits CONFIG UPDATE mode.
See the bq27441-G1 Technical Reference Manual for detailed descriptions for the Standard Data Commands
and Control( ) subcommands.
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FUNCTIONAL DESCRIPTION
I2C INTERFACE
The bq27441-G1 supports the standard I2C read, incremental read, quick read, one-byte write, and incremental
write functions. The 7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as
1010101. The first 8 bits of the I2C protocol are, therefore, 0xAA or 0xAB for write or read, respectively.
Host generated
S
ADDR[6:0]
0 A
Gauge generated
CMD [7:0]
A
DATA [7:0]
A P
S
ADDR[6:0]
(a) 1-byte write
S
ADDR[6:0]
0 A
1 A
DATA [7:0]
N P
(b) quick read
CMD [7:0]
A Sr
ADDR[6:0]
1 A
DATA [7:0]
N P
(c) 1- byte read
S
ADDR[6:0]
0 A
CMD [7:0]
A Sr
ADDR[6:0]
1 A
DATA [7:0]
A ...
DATA [7:0]
N P
(d) incremental read
S
ADDR[6:0]
0 A
CMD[7:0]
A
DATA [7:0]
A
DATA [7:0]
A
...
A P
(e) incremental write
(S = Start , Sr = Repeated Start , A = Acknowledge , N = No Acknowledge , and P = Stop).
The quick read returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I2C communication engine, increments whenever data is acknowledged by the bq27441-G1 or the
I2C master. “Quick writes” function in the same manner and are a convenient means of sending multiple bytes to
consecutive command locations (such as two-byte commands that require two bytes of data).
The following command sequences are not supported:
Attempt to write a read-only address (NACK after data sent by master):
Attempt to read an address above 0x6B (NACK command):
I2C Time Out
The I2C engine releases both SDA and SCL if the I2C bus is held low for 2 seconds. If the bq27441-G1 is holding
the lines, releasing them frees them for the master to drive the lines. If an external condition is holding either of
the lines low, the I2C engine enters the low-power sleep mode.
12
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Product Folder Links: bq27441-G1
bq27441-G1
www.ti.com
SLUSBH1A – NOVEMBER 2013 – REVISED JANUARY 2014
I2C Command Waiting Time
To ensure proper operation at 400 kHz, a t(BUF) ≥ 66 μs bus-free waiting time must be inserted between all
packets addressed to the bq27441-G1. In addition, if the SCL clock frequency (fSCL) is > 100 kHz, use individual
1-byte write commands for proper data flow control. The following diagram shows the standard waiting time
required between issuing the control subcommand the reading the status result. For read-write standard
command, a minimum of 2 seconds is required to get the result updated. For read-only standard commands,
there is no waiting time required, but the host must not issue any standard command more than two times per
second. Otherwise, the gauge could result in a reset issue due to the expiration of the watchdog timer.
S
ADDR [6:0]
0 A
CMD [7:0]
A
DATA [7:0]
A P
66ms
S
ADDR [6:0]
0 A
CMD [7:0]
A
DATA [7:0]
A P
66ms
S
ADDR [6:0]
0 A
CMD [7:0]
A Sr
ADDR [6:0]
1 A
DATA [7:0]
A
DATA [7:0]
N P
66ms
N P
66ms
Waiting time inserted between two 1-byte write packets for a subcommand and reading results
(required for 100 kHz < fSCL £ 400 kHz)
S
ADDR [6:0]
0 A
CMD [7:0]
A
DATA [7:0]
S
ADDR [6:0]
0 A
CMD [7:0]
A Sr
ADDR [6:0]
A
1 A
DATA [7:0]
DATA [7:0]
A P
A
66ms
DATA [7:0]
Waiting time inserted between incremental 2-byte write packet for a subcommand and reading results
(acceptable for fSCL £ 100 kHz)
S
ADDR [6:0]
DATA [7:0]
0 A
A
CMD [7:0]
DATA [7:0]
A Sr
N P
ADDR [6:0]
1 A
DATA [7:0]
A
DATA [7:0]
A
66ms
Waiting time inserted after incremental read
I2C Clock Stretching
A clock stretch can occur during all modes of fuel gauge operation. In SLEEP and HIBERNATE modes, a short ≤
100 µs clock stretch occurs on all I2C traffic as the device must wake-up to process the packet. In the other
modes ( INITIALIZATION , NORMAL) a ≤ 4 ms clock stretching period may occur within packets addressed for
the fuel gauge as the I2C interface performs normal data flow control.
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13
bq27441-G1
SLUSBH1A – NOVEMBER 2013 – REVISED JANUARY 2014
www.ti.com
REFERENCE SCHEMATIC
VPU
R2
VPU
R3
R4
R5
U1
5.1k
5.1k
1
SDA
2
SCL
3
4
PGND
5
6
C1
SDA
GPOUT
SCL
NC
VSS
BQ27441DRZ
NC
BIN
NC
VDD
SRP
PWPD
5.1k
BAT
SRN
1.8M
GPOUT
11
10
BIN
9
8
7
13
0.47uF
12
PGND
PGND
R1
PACKP
3
BIN
2
PACKN
1
3
2
System Load/Charger
VSYS
C2
1.0uF
BIN
0.010
Note: 1% Tol.
1
J5
PGND
spacer
REVISION HISTORY
Changes from Original (November 2013) to Revision A
•
14
Page
Changed the device status From Product Preview To: Production ...................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ27441DRZR-G1A
ACTIVE
SON
DRZ
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ27
441A
BQ27441DRZR-G1B
ACTIVE
SON
DRZ
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ27
441B
BQ27441DRZT-G1A
ACTIVE
SON
DRZ
12
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ27
441A
BQ27441DRZT-G1B
ACTIVE
SON
DRZ
12
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ27
441B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ27441DRZR-G1A
SON
DRZ
12
3000
330.0
12.4
2.8
4.3
1.2
4.0
12.0
Q2
BQ27441DRZR-G1B
SON
DRZ
12
3000
330.0
12.4
2.8
4.3
1.2
4.0
12.0
Q2
BQ27441DRZT-G1A
SON
DRZ
12
250
180.0
12.4
2.8
4.3
1.2
4.0
12.0
Q2
BQ27441DRZT-G1B
SON
DRZ
12
250
180.0
12.4
2.8
4.3
1.2
4.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ27441DRZR-G1A
SON
DRZ
12
3000
367.0
367.0
35.0
BQ27441DRZR-G1B
SON
DRZ
12
3000
367.0
367.0
35.0
BQ27441DRZT-G1A
SON
DRZ
12
250
210.0
185.0
35.0
BQ27441DRZT-G1B
SON
DRZ
12
250
210.0
185.0
35.0
Pack Materials-Page 2
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