HEF4013B Dual D-type flip-flop Rev. 8 — 21 November 2011 Product data sheet 1. General description The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW and is transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs. The outputs are buffered for best system performance. The clock input’s Schmitt-trigger action makes the circuit highly tolerant of slower clock rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Applications Counters and dividers Registers Toggle flip-flops 4. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C Type number Package Name Description Version HEF4013BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 HEF4013BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4013BTT TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 HEF4013B NXP Semiconductors Dual D-type flip-flop 5. Functional diagram 1SD 1D 6 5 SD D 1 Q 1Q FF1 1CP 3 2 Q CP 1Q CD 1CD 2SD 2D 4 8 9 SD D Q 13 2Q FF2 2CP 11 Q CP 12 2Q CD 2CD 10 001aag084 Fig 1. Functional diagram CP C Q C C C C C C C D Q C C SD CD 001aag086 Fig 2. Logic diagram (one flip-flop) HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop 6. Pinning information 6.1 Pinning 1Q 1 14 VDD 1Q 2 13 2Q 1CP 3 12 2Q 1CD 4 1D 5 1SD 6 VSS 7 HEF4013B 11 2CP 10 2CD 9 2D 8 2SD 001aag085 Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description 1Q, 2Q 1, 13 true output 1Q, 2Q 2, 12 complement output 1CP, 2CP 3, 11 clock input (LOW to HIGH edge-triggered) 1CD, 2CD 4, 10 asynchronous clear-direct input (active HIGH) 1D, 2D 5, 9 data input 1SD, 2SD 6, 8 asynchronous set-direct input (active HIGH) VSS 7 ground (0 V) VDD 14 supply voltage 7. Functional description Table 3. Function table[1] Control Input Output nSD nCD nCP nD nQ nQ H L X X H L L H X X L H H H X X H H L L L L H L L H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition. HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage Conditions Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V - 10 mA input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation IIK input clamping current VI input voltage IOK output clamping current II/O P power dissipation VI < 0.5 V or VI > VDD + 0.5 V Min VO < 0.5 V or VO > VDD + 0.5 V Tamb = 40 C to +125 C DIP14 [1] - 750 mW SO14 [2] - 500 mW TSSOP14 [3] - 500 mW - 100 mW per output [1] For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K. [2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. [3] For TSSOP14 packages: above Tamb = 60 C, Ptot derates linearly with 5.5 mW/K. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD VI Min Max Unit supply voltage 3 15 V input voltage 0 VDD V Tamb ambient temperature 40 +125 C t/V input transition rise and fall rate VDD = 5 V - 3.75 s/V VDD = 10 V - 0.5 s/V VDD = 15 V - 0.08 s/V HEF4013B Product data sheet Conditions All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage IO < 1 A IDD supply current input capacitance HEF4013B Product data sheet Max Min Max Min Max Min Max - 3.5 - 3.5 - 3.5 - V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 - 1.1 mA VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - 0.1 - 0.1 - 1.0 - 1.0 A 5V - 1.0 - 1.0 - 30 - 30 A 10 V - 2.0 - 2.0 - 60 - 60 A 15 V - 4.0 - 4.0 - 120 - 120 A - - - - 7.5 - - - - pF IO < 1 A IO < 1 A input leakage current Min 3.5 LOW-level output voltage LOW-level output current Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit 5V IO < 1 A HIGH-level output current VDD 10 V HIGH-level output voltage II CI Conditions all valid input combinations; IO = 0 A All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop 11. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 C; unless otherwise specified. For test circuit see Figure 6. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions VDD nCP to nQ, nQ; see Figure 4 Extrapolation formula Min Typ Max Unit 83 + 0.55 CL - 110 220 ns 10 V 34 + 0.23 CL - 45 90 ns 15 V 22 + 0.16 CL - 30 60 ns 73 + 0.55 CL - 100 200 ns 29 + 0.23 CL - 40 80 ns 22 + 0.16 CL - 30 60 ns 73 + 0.55 CL - 100 200 ns 29 + 0.23 CL - 40 80 ns 22 + 0.16 CL - 30 60 ns 5V 5V nSD to nQ [1] [1] 10 V 15 V nCD to nQ 5V [1] 10 V 15 V tPLH LOW to HIGH propagation delay nCP to nQ, nQ; see Figure 4 68 + 0.55 CL - 95 190 ns 29 + 0.23 CL - 40 80 ns 22 + 0.16 CL - 30 60 ns 48 + 0.55 CL - 75 150 ns 10 V 24 + 0.23 CL - 35 70 ns 15 V 17 + 0.16 CL - 25 50 ns 33 + 0.55 CL - 60 120 ns 19 + 0.23 CL - 30 60 ns 12 + 0.16 CL - 20 40 ns 10 + 1.00 CL - 60 120 ns 10 V 9 + 0.42 CL - 30 60 ns 15 V 6 + 0.28 CL - 20 40 ns 5V [1] 10 V 15 V nSD to nQ 5V 5V nCD to nQ [1] [1] 10 V 15 V tt tsu th tW transition time set-up time hold time pulse width see Figure 4 5V nD to nCP; see Figure 4 nD to nCP; see Figure 4 nCP input LOW; see Figure 4 nSD input HIGH; see Figure 5 nCD input HIGH; see Figure 5 HEF4013B Product data sheet [1] 5V 40 20 - ns 10 V 25 10 - ns 15 V 15 5 - ns 5V 20 0 - ns 10 V 20 0 - ns 15 V 15 0 - ns 5V 60 30 - ns 10 V 30 15 - ns 15 V 20 10 - ns 5V 50 25 - ns 10 V 24 12 - ns 15 V 20 10 - ns 5V 50 25 - ns 10 V 24 12 - ns 15 V 20 10 - ns All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop Table 7. Dynamic characteristics …continued Tamb = 25 C; unless otherwise specified. For test circuit see Figure 6. Symbol Parameter Conditions trec nSD input; see Figure 5 recovery time VDD nCD input; see Figure 5 fclk(max) [1] maximum clock frequency see Figure 4 Extrapolation formula Min Typ Max Unit 5V +15 5 - ns 10 V 15 0 - ns 15 V 15 0 - ns 5V 40 25 - ns 10 V 25 10 - ns 15 V 25 10 - ns 5V 7 14 - MHz 10 V 14 28 - MHz 15 V 20 40 - MHz Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas. CL is given in pF. Table 8. Dynamic power dissipation VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol Parameter PD VDD dynamic power dissipation Typical formula Where 5 V PD = 850 fi + (fo CL) VDD W 2 fi = input frequency in MHz; 10 V PD = 3600 fi + (fo CL) VDD2 W fo = output frequency in MHz; 15 V PD = 9000 fi + (fo CL) VDD2 W CL = output load capacitance in pF; (fo CL) = sum of the outputs; VDD = supply voltage in V. 12. Waveforms tW 1/fclk(max) VI VM input nCP 0V tsu tsu th tf tr th VI VM input nD 0V tPLH tPHL tt VOH tt VY VM output nQ VX VOL 001aah016 Set-up and hold times are shown as positive values but may be specified as negative values. The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 9. Fig 4. Set-up time, hold time, minimum clock pulse width, propagation delays and transition times HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop VI VM input nCP 0V trec trec VI input nSD VM 0V tW VI VM input nCD 0V tW VOH output nQ 001aag088 VOL Recovery times are shown as positive values but may be specified as negative values. Measurement points are given in Table 9. Fig 5. nSD, nCD recovery time and pulse width Table 9. Measurement points Supply voltage Input Output VDD VM VM VX VY 5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD VDD VI VO G DUT CL RT 001aag182 Test and measurement data is given in Table 10; Definitions test circuit: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 6. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD 20 ns 50 pF HEF4013B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop 13. Application information D Q D FF 1 Q CP clock Fig 7. 001aag089 N-stage shift register Q D Q FF n Q CP Q D FF 2 Q CP clock Q D FF 1 Q CP T-type flip-flop Fig 8. Q FF n Q CP Q D FF 2 Q CP Q D 001aag090 Binary ripple up-counter; divide-by-2n Q D FF 1 CP Q D FF 2 Q CP Q D Q FF n Q CP Q clock 001aag091 Fig 9. Modified ring counter; divide-by-(n + 1) HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop 14. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 10. Package outline SOT27-1 (DIP14) HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT108-1 (SO14) HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 12. Package outline SOT402-1 (TSSOP14) HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4013B v.8 20111121 Product data sheet - HEF4013B v.7 Modifications: • • Legal pages updated. Changes in “General description”, “Features and benefits” and “Applications”. HEF4013B v.7 20110913 Product data sheet - HEF4013B v.6 HEF4013B v.6 20091027 Product data sheet - HEF4013B v.5 HEF4013B v.5 20090619 Product data sheet - HEF4013B v.4 HEF4013B v.4 20080515 Product data sheet - HEF4013B_CNV v.3 HEF4013B_CNV v.3 19950101 Product specification - HEF4013B_CNV v.2 HEF4013B_CNV v.2 19950101 Product specification - - HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 15 of 16 HEF4013B NXP Semiconductors Dual D-type flip-flop 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 21 November 2011 Document identifier: HEF4013B Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: HEC4013BT,112 HEC4013BT,118 HEF4013BP,652 HEF4013BT,652 HEF4013BT,653 HEF4013BTT,112 HEF4013BTT,118