bq34z950
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SLUSBF0A – APRIL 2013 – REVISED MAY 2013
SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION
ENABLED WITH IMPEDANCE TRACK™ WITH OPTIONAL DQ INTERFACE
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FEATURES
APPLICATIONS
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1
2
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Next Generation Patented Impedance Track™
Technology Accurately Measures Available
Charge in Li-Ion and Li-Polymer Batteries
– Better Than 1% Error Over the Lifetime of
the Battery
Supports the Smart Battery Specification
SBS V1.1
Optional DQ Communication Interface
Flexible Configuration for 2-Series to 4-Series
Li-Ion and Li-Polymer Cells
Powerful 8-Bit RISC CPU with Ultralow Power
Modes
Full Array of Programmable Protection
Features
– Voltage
– Current
– Temperature
Satisfies JEITA Guidelines
Added Flexibility to Handle More Complex
Charging Profiles
Drives 3-, 4-, and 5-Segment LED Display for
Battery-Pack Conditions
Supports SHA-1 Authentication
Complete Battery Protection and Gas Gauge
Solution in One Package
Available in a 44-Pin TSSOP (DBT) Package
Notebook PCs
Medical and Test Equipment
Portable Instrumentation
DESCRIPTION
The bq34z950 SBS-compliant gas gauge and
protection IC, incorporating patented Impedance
Track technology, is a single IC solution designed for
battery-pack or in-system installation. The bq34z950
measures and maintains an accurate record of
available charge in Li-Ion or Li-Polymer batteries
using its integrated high-performance analog
peripherals. The bq34z950 monitors capacity change,
battery impedance, open-circuit voltage, and other
critical parameters of the battery pack which reports
the information to the system host controller over a
serial-communication bus. SMBus and single-wire
DQ communication interfaces are both available.
Together with the integrated analog front-end (AFE)
short-circuit and overload protection, the bq34z950
maximizes functionality and safety while minimizing
external component count, cost, and size in smart
battery circuits.
The implemented Impedance Track gas gauging
technology continuously analyzes the battery
impedance, resulting in superior gas-gauging
accuracy. This enables remaining capacity to be
calculated with discharge rate, temperature, and cell
aging all accounted for during each stage of every
cycle with high accuracy.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Impedance Track is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
bq34z950
SLUSBF0A – APRIL 2013 – REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. AVAILABLE OPTIONS
PACKAGE (1)
TA
44-PIN TSSOP (DBT) Tube
–40°C to 85°C
(1)
(2)
(3)
bq34z950DBT
44-PIN TSSOP (DBT) Tape and Reel
(2)
bq34z950DBTR (3)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
A single tube quantity is 40 units.
A single reel quantity is 2000 units.
THERMAL INFORMATION
bq34z950
THERMAL METRIC (1)
44-PIN TSSOP
(DBT)
UNITS
θJA Junction-to-ambient thermal resistance
47.6
°C/W
TA≤ 25°C Power Rating
2101
mW
Derating Factor TA> 25°C
21.01
mW/°C
TA≤ 70°C Power Rating
1155
mW
TA≤ 85°C Power Rating
840
mW
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
SYSTEM PARTITIONING DIAGRAM
VSS
VCC
BAT
PACK
CHG
DSG
GPOD
ZVCHG
PMS
DQ
LED5
LED3
LED4
LED1
LED2
PACK+
RBI
DISP
LED Display
DQ
Oscillator
PreCharge FET
& GPOD Drive
N Channel FET
Drive
Power Mode
Control
MSRT
RESET
SMBD
SMB 1.1
System Control
AFE HW Control
Watchdog
ALERT
SMBC
Voltage
Measurement
Data Flash
Memory
JEITA and
Enhanced
Charging
Algorithm
SHA-1
Authentication
Over
Temperature
Protection
Over & Under
Voltage
Protection
Cell Voltage
Multiplexer
Impedance
Track™ Gas
Gauging
Cell Balancing
VCELL+
+
VC1
VC2
+
VC3
+
VC4
+
VC1
VDD
VC2
OUT
VC3
CD
VC4
GND
bq294xx
VC5
Temperature
Measurement
Over Current
Protection
HW Over
Current & Short
Circuit Protection
Coulomb
Counter
REG33
Regulators
PACK–
2
ASRN
ASRP
GSRP
GSRN
TS1
TOUT
REG25
RSNS
5 mΩ–20 mΩ typ
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SLUSBF0A – APRIL 2013 – REVISED MAY 2013
PACKAGE PINOUT DIAGRAM
bq34z950
DBT PACKAGE
(TOP VIEW)
DSG
1
44
CHG
PACK
2
43
BAT
VCC
3
42
VC1
ZVCHG
4
41
VC2
GPOD
5
40
VC3
PMS
6
39
VC4
VSS
7
38
VC5
REG33
8
37
ASRP
TOUT
9
36
ASRN
VCELL+
10
35
RESET
ALERT
11
34
VSS
NC
12
33
RBI
NC
13
32
REG25
TS1
14
31
VSS
NC
15
30
MRST
DQ
16
29
GSRN
NC
17
28
GSRP
SMBD
18
27
LED5
NC
19
26
LED4
SMBC
20
25
LED3
DISP
21
24
LED2
VSS
22
23
LED1
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TERMINAL FUNCTIONS
TERMINAL
(1)
4
I/O (1)
DESCRIPTION
NO.
NAME
1
DSG
O
2
PACK
IA, P
3
VCC
P
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to
ensure device supply either from battery stack or battery pack input.
4
ZVCHG
O
P-CH pre-charge FET gate drive
5
GPOD
OD
6
PMS
I
High side N-CH discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in
SHUTDOWN mode.
High voltage general purpose open drain output. Can be configured to be used in pre-charge
condition.
PRE-CHARGE mode setting input. Connect to PACK to enable 0-V precharge using charge FET
connected at CHG pin. Connect to VSS to disable 0 V pre-charge using charge FET connected at
CHG pin.
7
VSS
P
Negative supply voltage input. Connect all VSS pins together for operation of device.
8
REG33
P
3.3-V regulator output. Connect at least a 2.2-μF capacitor to REG33 and VSS.
9
TOUT
P
Thermistor bias supply output
10
VCELL+
—
Internal cell voltage multiplexer and amplifier output. Connect a 0.1-μF capacitor to VCELL+ and
VSS.
11
ALERT
OD
Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will
be triggered.
12
NC
—
Not used—leave floating
13
NC
—
Not used—leave floating
14
TS1
IA
1st Thermistor voltage input connection to monitor temperature
15
NC
—
16
DQ
I/OD
Not used—leave floating
17
NC
—
18
SMBD
I/OD
19
NC
—
20
SMBC
I/OD
21
DISP
I
Display control for the LEDs. This pin is typically connected to VCC via a 100-kΩ resistor and a
push button switch connected to VSS.
22
VSS
P
Negative supply voltage input. Connect all VSS pins together for operation of device.
23
LED1
I
LED1 display segment that drives an external LED depending on the firmware configuration
24
LED2
I
LED2 display segment that drives an external LED depending on the firmware configuration
25
LED3
I
LED3 display segment that drives an external LED depending on the firmware configuration
26
LED4
I
LED4 display segment that drives an external LED depending on the firmware configuration
27
LED5
I
28
GSRP
IA
Coulomb counter differential input. Connect to one side of the sense resistor.
29
GSRN
IA
Coulomb counter differential input. Connect to one side of the sense resistor.
30
MRST
I
Master reset input that forces the device into reset when held low. Must be held high for normal
operation. Connect to RESET for correct operation of device.
31
VSS
P
Negative supply voltage input. Connect all VSS pins together for operation of device.
32
REG25
P
2.5-V regulator output. Connect at least a 1-mF capacitor to REG25 and VSS.
33
RBI
P
RAM/Register backup input. Connect a capacitor to this pin and VSS to protect loss of
RAM/Register data in case of short circuit condition.
Single-wire bidirectional DQ interface
Not used—leave floating
SMBus data open-drain bidirectional pin used to transfer address and data to and from the
bq34z950
Not used—leave floating
SMBus clock open-drain bidirectional pin used to clock the data transfer to and from the bq34z950
LED5 display segment that drives an external LED depending on the firmware configuration
34
VSS
P
Negative supply voltage input. Connect all VSS pins together for operation of device.
35
RESET
O
Reset output. Connect to MSRT.
36
ASRN
IA
Short circuit and overload detection differential input. Connect to the sense resistor.
37
ASRP
IA
Short circuit and overload detection differential input. Connect to the sense resistor.
I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O (1)
DESCRIPTION
NO.
NAME
38
VC5
IA, P
Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in the
cell stack.
39
VC4
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the
negative voltage of the second lowest cell in the cell stack.
40
VC3
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in
the cell stack and the negative voltage of the second highest cell in 4-series cell applications.
41
VC2
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell
and the negative voltage of the highest cell in 4-series cell applications. Connect to VC3 in the 2series cell stack applications.
42
VC1
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell
stack in 4-series cell applications. Connect to VC2 in 3- or 2-series cell stack applications.
43
BAT
I, P
44
CHG
O
Battery stack voltage sense input
High side N-CH charge FET gate drive
ABSOLUTE MAXIMUM RATINGS
Over-operating free-air temperature (unless otherwise noted)
(1)
PIN
VSS
Supply voltage range
VIN
Input voltage range
UNIT
BAT, VCC
–0.3 V to 34 V
PACK, PMS
–0.3 V to 34 V
VC(n)–VC(n+1); n = 1, 2, 3, 4
–0.3 V to 8.5 V
VC1, VC2, VC3, VC4
–0.3 V to 34 V
VC5
–0.3 V to 1 V
DQ, SMBD, SMBC. LED1, LED2, LED3, LED4,
LED5, DISP
–0.3 V to 6 V
TS1, VCELL+, ALERT
–0.3 V to V(REG25) + 0.3 V
MRST, GSRN, GSRP, RBI
–0.3 V to V(REG25) + 0.3 V
ASRN, ASRP
–1 V to 1 V
DSG, CHG, GPOD
–0.3 V to 34 V
ZVCHG
VOUT
Output voltage range
–0.3 V to V (BAT)
TOUT, ALERT, REG33
–0.3 V to 6 V
RESET
–0.3 V to 7 V
REG25
–0.3 V to 2.75 V
ISS
Maximum combined sink current for input
pins
TA
Operating free-air temperature range
–40°C to 85°C
TF
Functional temperature
–40°C to 100°C
Tstg
Storage temperature range
–65°C to 150°C
(1)
DQ, SMBD, SMBC, LED1, LED2, LED3, LED4,
LED5
50 mA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over-operating free-air temperature range (unless otherwise noted)
PIN
MIN
VSS
Supply voltage
VCC, BAT
4.5
V(STARTUP)
Minimum startup voltage
VCC, BAT, PACK
5.5
NOM
MAX
UNIT
25
V
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RECOMMENDED OPERATING CONDITIONS (continued)
Over-operating free-air temperature range (unless otherwise noted)
PIN
VIN
Input voltage range
MIN
NOM
MAX
UNIT
V
VC(n)–VC(n+1); n = 1,2,3,4
0
5
VC1, VC2, VC3, VC4
0
VSS
V
VC5
0
0.5
V
–0.5
0.5
V
V
ASRN, ASRP
PACK, PMS
0
25
V(GPOD)
Output voltage range
GPOD
0
25
V
I(GPOD)
Drain current (1)
GPOD
1
mA
C(REG25)
2.5-V LDO capacitor
REG25
1
µF
C(REG33)
3.3-V LDO capacitor
REG33
2.2
µF
C(VCELL+)
Cell voltage output capacitor
VCELL+
0.1
µF
1
kΩ
R(PACK)
(1)
(2)
PACK input block resistor
(2)
PACK
Use an external resistor to limit the current to GPOD to 1 mA in high voltage application.
Use an external resistor to limit the in-rush current PACK pin required.
ELECTRICAL CHARACTERISTICS
Over-operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
I(NORMAL)
Firmware running
I(SLEEP)
SLEEP mode
I(SHUTDOWN)
550
µA
CHG FET on; DSG FET on
124
µA
CHG FET off; DSG FET on
90
µA
CHG FET off; DSG FET off
52
SHUTDOWN mode
0.1
µA
1
µA
1
µA
1.25
10
mV
V (WAKE) = 1 mV;
I(WAKE)= 0, RSNS1 = 0, RSNS0 = 1
–0.7
0.7
V(WAKE) = 2.25 mV;
I(WAKE) = 1, RSNS1 = 0, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0
–0.8
0.8
V(WAKE) = 4.5 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0
–1.0
1.0
V(WAKE) = 9 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1
–1.4
1.4
SHUTDOWN WAKE; TA = 25°C (unless otherwise noted)
Shutdown exit at VSTARTUP
threshold
I(PACK)
SRx WAKE FROM SLEEP; TA = 25°C (unless otherwise noted)
Positive or negative wake
threshold with 1.00 mV, 2.25
mV, 4.5-mV and 9-mV
programmable options
V(WAKE)
V(WAKE_ACR)
Accuracy of V(WAKE)
V(WAKE_TCO)
Temperature drift of V(WAKE)
accuracy
t(WAKE)
Time from application of
current and wake of
bq34z950
mV
0.5
%/°C
1
10
ms
WATCHDOG TIMER
tWDTINT
Watchdog start up detect
time
250
500
1000
ms
tWDWT
Watchdog detect time
50
100
150
µs
2.41
2.5
2.59
V
2.5-V LDO; I(REG33OUT) = 0 mA; TA = 25°C (unless otherwise noted)
V(REG25)
6
Regulator output voltage
4.5 < VCC or BAT < 25 V;
I(REG25OUT) ≤ 16 mA;
TA = –40°C to 100°C
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ELECTRICAL CHARACTERISTICS (continued)
Over-operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔV(REG25TEMP)
Regulator output change
with temperature
I(REG25OUT) = 2 mA;
TA = –40°C to 100°C
ΔV(REG25LINE)
Line regulation
5.4 < VCC or BAT < 25 V;
I(REG25OUT) = 2 mA
ΔV(REG25LOAD)
Load regulation
I(REG25MAX)
Current limit
MIN
TYP
MAX
±0.2
UNIT
%
3
10
0.2 mA ≤ I(REG25OUT) ≤ 2 mA
7
25
0.2 mA ≤ I(REG25OUT) ≤ 16 mA
25
50
5
40
75
mA
3
3.3
3.6
V
Drawing current until
REG25 = 2 V to 0 V
mV
mV
3.3-V LDO; I(REG25OUT) = 0 mA; TA = 25°C (unless otherwise noted)
V(REG33)
Regulator output voltage
4.5 < VCC or BAT < 25 V;
I(REG33OUT) ≤ 25 mA;
TA = –40°C to 100°C
ΔV(REG33TEMP)
Regulator output change
with temperature
I(REG33OUT) = 2 mA;
TA = –40°C to 100°C
ΔV(REG33LINE)
Line regulation
5.4 < VCC or BAT < 25 V;
I(REG33OUT) = 2 mA
ΔV(REG33LOAD)
Load regulation
I(REG33MAX)
Current limit
±0.2
3
%
10
0.2 mA ≤ I(REG33OUT) ≤ 2 mA
7
17
0.2 mA ≤ I(REG33OUT) ≤ 25 mA
40
100
100
145
drawing current until REG33 = 3 V
25
short REG33 to VSS, REG33 = 0 V
12
65
mV
mV
mA
THERMISTOR DRIVE
V(TOUT)
Output voltage
I(TOUT) = 0 mA; TA = 25°C
RDS(on)
TOUT pass element
resistance
I(TOUT) = 1 mA; RDS(on) = (V(REG25) – V(TOUT) )/ 1 mA; TA =
–40°C to 100°C
Output low voltage
LED1, LED2, LED3, LED4, LED5
V(REG25)
50
V
100
Ω
0.4
V
LED OUTPUTS
VOL
VCELL+ HIGH VOLTAGE TRANSLATION
V(VCELL+OUT)
V(VCELL+REF)
Translation output
VC(n) – VC(n+1) = 0 V;
TA = –40°C to 100°C
0.950
0.975
1
VC(n) – VC(n+1) = 4.5 V;
TA = –40°C to 100°C
0.275
0.3
0.375
Internal AFE reference voltage;
TA = –40°C to 100°C
0.965
0.975
0.985
V(VCELL+PACK)
Voltage at PACK pin;
TA = –40°C to 100°C
0.98 ×
V(PACK)/18
V(PACK)/18
1.02 ×
V(PACK)/18
V(VCELL+BAT)
Voltage at BAT pin;
TA = –40°C to 100°C
0.98 ×
V(BAT)/18
V(BAT)/18
1.02 ×
V(BAT)/18
CMMR
K
COMMON mode rejection
ratio
Cell scale factor
VCELL+
40
V
dB
K= {VCELL+ output (VC5=0 V; VC4=4.5 V) – VCELL+
output (VC5=0 V; VC4=0 V)}/4.5
0.147
0.150
0.153
K= {VCELL+ output (VC2=13.5 V; VC1=18 V) – VCELL+
output
(VC5=13.5 V; VC1=13.5 V)}/4.5
0.147
0.150
0.153
I(VCELL+OUT)
Drive Current to VCELL+
capacitor
VC(n) – VC(n+1) = 0 V; VCELL+ = 0 V;
TA = –40°C to 100°C
12
18
V(VCELL+O)
CELL offset error
CELL output (VC2 = VC1 = 18 V) – CELL output (VC2 =
VC1 = 0 V)
–18
–1
18
mV
IVCnL
VC(n) pin leakage current
VC1, VC2, VC3, VC4, VC5 = 3 V
–1
0.01
1
μA
RDS(on) for internal FET switch at
VDS = 2 V; TA = 25°C
200
400
600
Ω
μA
CELL BALANCING
RBAL
internal cell balancing FET
resistance
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted)
V(OL)
OL detection threshold
voltage accuracy
VOL = 25 mV (min)
15
25
35
VOL = 100 mV; RSNS = 0, 1
90
100
110
VOL = 205 mV (max)
185
205
225
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ELECTRICAL CHARACTERISTICS (continued)
Over-operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
SCC detection threshold
voltage accuracy
V(SCC)
SCD detection threshold
voltage accuracy
V(SCD)
tda
Delay time accuracy
tpd
Protection circuit
propagation delay
MIN
TYP
MAX
V(SCC) = 50 mV (min)
TEST CONDITIONS
30
50
70
V(SCC) = 200 mV; RSNS = 0, 1
180
200
220
V(SCC) = 475 mV (max)
428
475
523
V(SCD) = –50 mV (min)
–30
–50
–70
V(SCD) = –200 mV; RSNS = 0, 1
–180
–200
–220
V(SCD) = –475 mV (max)
–428
–475
–523
UNIT
mV
mV
±15.25
μs
50
μs
FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted)
V(DSGON)
DSG pin output on voltage
V(DSGON) = V(DSG) – V(PACK);
V(GS) connected to 10 MΩ; DSG and CHG on;
TA = –40°C to 100°C
8
12
16
V
V(CHGON)
CHG pin output on voltage
V(CHGON) = V(CHG) – V(BAT);
V(GS) = 10 MΩ; DSG and CHG on;
TA = –40°C to 100°C
8
12
16
V
V(DSGOFF)
DSG pin output off voltage
V(DSGOFF) = V(DSG) – V(PACK)
0.2
V
V(CHGOFF)
CHG pin output off voltage
V(CHGOFF) = V(CHG) – V(BAT)
0.2
V
V(CHG): V(PACK) ≥ V(PACK) + 4 V
400
1000
V(DSG): V(BAT) ≥V(BAT) + 4V
400
1000
V(CHG): V(PACK) + V(CHGON) ≥ V(PACK)+
1V
40
200
V(DSG): VC1 + V(DSGON) ≥ VC1 + 1 V
40
200
3.3
3.5
3.7
ALERT
60
100
200
RESET
1
3
6
tr
Rise time
CL= 4700 pF
tf
Fall time
CL= 4700pF
V(ZVCHG)
ZVCHG clamp voltage
BAT = 4.5 V
μs
μs
V
LOGIC; TA = –40°C to 100°C (unless otherwise noted)
R(PULLUP)
Internal pullup resistance
VOL
Logic low output voltage
level
ALERT
0.2
RESET; V(BAT) = 7 V; V(REG25) = 1.5 V; I(RESET) = 200 μA
0.4
GPOD; I(GPOD) = 50 μA
0.6
kΩ
V
LOGIC SMBC, SMBD, DQ, ALERT, DISP
VIH
High-level input voltage
VIL
Low-level input voltage
2.0
VOH
Output voltage high (1)
IL = –0.5 mA
VOL
Low-level output voltage
DQ, ALERT, DISP; IL = 7 mA;
CI
Input capacitance
Ilkg
Input leakage current
V
0.8
VREG25–0.5
V
V
0.4
5
V
pF
1
µA
ADC (2)
Input voltage range
TS1, using Internal Vref
–0.2
Conversion time
1
31.5
Resolution (no missing
codes)
16
Effective resolution
14
bits
15
Integral nonlinearity
Offset error drift (4)
TA = 25°C to 85°C
Full-scale error (5)
Full-scale error drift
(1)
(2)
(3)
(4)
(5)
8
bits
±0.03
Offset error (4)
V
ms
%FSR (3)
140
250
µV
2.5
18
μV/°C
±0.1%
±0.7%
50
PPM/°C
RC[0:7] bus
Unless otherwise specified, the specification limits are valid at all measurement speed modes.
Full-scale reference
Post-calibration performance and no I/O changes during conversion with SRN as the ground reference.
Uncalibrated performance. This gain error can be eliminated with external calibration.
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ELECTRICAL CHARACTERISTICS (continued)
Over-operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Effective input resistance (6)
MIN
TYP
MAX
UNIT
8
MΩ
COULOMB COUNTER
Input voltage range
–0.20
Conversion time
Single conversion
Effective resolution
Single conversion
Integral nonlinearity
Offset error
(7)
0.20
ms
15
bits
–0.1 V to 0.20 V
±0.007
–0.20 V to –0.1 V
±0.007
TA = 25°C to 85°C
±0.034
0.4
(9)
µV
0.7
µV/°C
±0.35%
Full-scale error drift
150
Effective input resistance (10)
%FSR
10
Offset error drift
Full-scale error (8)
V
250
TA = 25°C to 85°C
PPM/°C
2.5
MΩ
INTERNAL TEMPERATURE SENSOR
V(TEMP)
Temperature sensor
voltage (11)
–2.0
mV/°C
VOLTAGE REFERENCE
Output voltage
1.215
Output voltage drift
1.225
1.230
65
V
PPM/°C
HIGH FREQUENCY OSCILLATOR
f(OSC)
Operating frequency
f(EIO)
Frequency error
t(SXO)
Start-up time (14)
4.194
(12) (13)
TA = 20°C to 70°C
MHz
–3%
0.25%
3%
–2%
0.25%
2%
2.5
5
ms
LOW FREQUENCY OSCILLATOR
f(LOSC)
Operating frequency
f(LEIO)
Frequency error (13)
t(LSXO)
Start-up time (14)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
32.768
(15)
TA = 20°C to 70°C
kHz
–2.5%
0.25%
2.5%
–1.5%
0.25%
1.5%
500
µs
The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
Post-calibration performance
Reference voltage for the coulomb counter is typically Vref/3.969 at V(REG25) = 2.5 V, TA = 25°C.
Uncalibrated performance. This gain error can be eliminated with external calibration.
The CC input is a switched capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
–53.7 LSB/°C
The frequency error is measured from 4.194 MHz.
The frequency drift is included and measured from the trimmed frequency at V(REG25) = 2.5 V, TA = 25°C.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
The frequency error is measured from 32.768 kHz.
POWER-ON RESET
Over-operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
VIT–
Negative-going voltage input
VHYS
Power-on reset hysteresis
tRST
RESET active low time
TEST CONDITIONS
Active low time after power up or watchdog
reset
MIN
TYP
MAX
UNIT
1.7
1.8
1.9
V
5
125
200
mV
100
250
560
µs
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POWER ON RESET BEHAVIOR
VS
FREE-AIR TEMPERATURE
Power-On Reset Negative-Going Voltage - V
1.81
1.8
1.79
1.78
1.77
1.76
-40
-20
0
20
40
60
80
TA - Free-Air Temperature - °C
DATA FLASH CHARACTERISTICS OVER RECOMMENDED OPERATING TEMPERATURE AND
SUPPLY VOLTAGE
Typical values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Data retention
Flash programming write-cycles
t(ROWPROG)
Row programming time
See
TYP
MAX
UNIT
10
Years
20k
Cycles
(1)
t(MASSERASE) Mass-erase time
t(PAGEERASE) Page-erase time
2
ms
200
ms
20
ms
I(DDPROG)
Flash-write supply current
5
10
mA
I(DDERASE)
Flash-erase supply current
5
10
mA
V(RBI) > V(RBI)MIN , VREG25 < VIT–, TA = 85°C
1000
2500
V(RBI) > V(RBI)MIN , VREG25 < VIT–, TA = 25°C
90
220
RAM/REGISTER BACKUP
I(RB)
RB data-retention input current
V(RB)
RB data-retention input voltage (1)
(1)
1.7
nA
V
Specified by design. Not production tested.
SMBus TIMING CHARACTERISTICS
TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
TEST CONDITIONS
MIN
f(SMB)
SMBus operating frequency
PARAMETER
SLAVE mode, SMBC 50% duty cycle
10
f(MAS)
SMBus master clock frequency
MASTER mode, No clock low slave
extend
t(BUF)
Bus free time between start and stop
(see Figure 1)
t(HD:STA)
Hold time after (repeated) start (see Figure 1)
t(SU:STA)
Repeated start setup time (see Figure 1)
t(SU:STO)
Stop setup time (see Figure 1)
t(HD:DAT)
10
Data hold time (see Figure 1)
RECEIVE mode
TRANSMIT mode
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TYP
51.2
MAX
UNIT
100
kHz
kHz
4.7
µs
4
µs
4.7
µs
4
µs
0
ns
300
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SMBus TIMING CHARACTERISTICS (continued)
TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
PARAMETER
t(SU:DAT)
Data setup time (see Figure 1)
t(TIMEOUT)
Error signal/detect (see Figure 1)
t(LOW)
Clock low period (see Figure 1)
t(HIGH)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
35
µs
50
µs
250
ns
See
(1)
Clock high period (see Figure 1)
See
(2)
t(LOW:SEXT)
Cumulative clock low slave extend time
See
(3)
25
ms
t(LOW:MEXT)
Cumulative clock low master extend time
(see Figure 1)
See
(4)
10
ms
tf
Clock/data fall time
See
(5)
300
ns
tr
Clock/data rise time
See
(6)
1000
ns
(1)
(2)
(3)
(4)
(5)
(6)
25
4.7
µs
4
The bq34z950 times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq34z950 that is
in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)
Fall time tf = 0.9VDD to (VILMAX – 0.15)
tR
tSU(STO)
tF
tF
tHD(STA)
tBUF
tHIGH
SMBC
SMBC
SMBD
SMBD
P
tR
S
tLOW
tHD(DAT)
Start and Stop condition
tSU(DAT)
Wait and Hold condition
tSU(STA)
tTIMEOUT
SMBC
SMBC
SMBD
SMBD
S
Timeout condition
A.
Repeated Start condition
SCLKACK is the acknowledge-related clock pulse generated by the master.
Figure 1. SMBus Timing Diagram
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DQ 1-WIRE INTERFACE
DQ TIMING SPECIFICATIONS
VDD = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
t(CYCH)
TEST CONDITIONS
Cycle time, host to bq34z950
See
MIN
(1)
TYP
MAX
3
UNIT
ms
t(CYCB)
Cycle time, bq34z950 to host
3
t(STRH)
Start hold, host to bq34z950
5
t(STRB)
Start hold, bq34z950 to host
500
t(DSU)
Data setup
t(DH)
Data hold
750
μs
t(DV)
Data valid
1.5
ms
t(SSU)
Stop setup
t(SH)
Stop hold
700
μs
t(SV)
Stop valid
2.95
ms
t(B)
Break
3
ms
t(BR)
Break recovery
1
ms
(1)
6
ms
750
μs
ns
μs
2.25
ms
The open-drain DQ pin should be pulled to at least VCC by the host system for proper DQ operation. DQ may be left floating if the serial
interface is not used.
DQ
(R/W 1)
t(STRH)
t(STRB)
DQ
(R/W 0)
t(DSU)
t(DH)
t(DV)
t(SSU)
t(SH)
t(SV)
DQ
(BREAK)
t(CYCH), t(CYCB), t(B)
t(BR)
T0269-01
Figure 2. DQ Timing Diagram
DQ timing for this device is selectable by adjusting values in Data Flash Sub Class 0x113. See Figure 3 for an
overview of the flash values.
12
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Wr_0_to_1_Delay
Wr0_RC
Data 6
Write 0
Wr0_Lo
Wr1_RC
SlaveRsp_Delay
Wr1_Lo
Wr_0_to_1_Delay
Data 7
Write 1
Bit 7 of Address
Data 5
Data 4
Data 3
Parameter
Data 2
Time
(ms)
Data 1
Time
Counts
BR_LO
2699
2830
BR_RC
1000
1048
Wr0_Lo
1775
1861
Wr0_RC
1225
1284
Wr1_Lo
549
576
Wr1_RC
2451
2570
Rd0_Lo
1149
1205
Rd1_Lo
1100
1153
RD_TO
0
0
RD_RS
299
314
Wr_0_to_1_Delay
SlaveRsp_Delay
Data 0
99
104
3020
3166
T0270-01
Figure 3. DQ Timing Control
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FEATURE SET
Primary (First-Level) Safety Features
The bq34z950 supports a wide range of battery and system protection features that can easily be configured.
The primary safety features include:
•
•
•
•
•
Cell over/undervoltage protection
Charge and discharge overcurrent
Short circuit
Charge and discharge overtemperature
AFE watchdog
Secondary (Second-Level) Safety Features
The secondary safety features of the bq34z950 can be used to indicate more serious faults. The secondary
safety protection features include:
•
•
•
•
•
•
Safety overvoltage
Safety overcurrent in charge and discharge
Safety overtemperature in Charge and Discharge
Charge FET and 0-V charge FET fault
Discharge FET fault
AFE communication fault
Charge Control Features
The bq34z950 charge control features include:
•
•
•
•
•
•
Reports the appropriate charging current needed for constant current charging, and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.
Determines the chemical state of charge of each battery cell using Impedance Track technology, and can
reduce the charge difference of the battery cells in a fully charged state of the battery pack, gradually using
the cell balancing algorithm during charging. This prevents fully charged cells from overcharging and causing
excessive degradation, and also increases the usable pack energy by preventing premature charge
termination.
Supports precharging/zero-volt charging
Supports fast charging
Supports charge inhibit and charge suspend if the battery pack temperature is out of temperature range
Reports charging fault and also indicates charge status via charge and discharge alarms
Gas Gauging
The bq34z950 uses Impedance Track technology to measure and calculate the available charge in battery cells.
The achievable accuracy is better than 1% error over the lifetime of the battery, and there is no full charge
discharge learning cycle required.
See the Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm application note
(SLUA364) for further details.
Authentication
The bq34z950 supports authentication by the host using SHA-1.
Power Modes
The bq34z950 supports three power modes to reduce power consumption:
•
14
In NORMAL mode, the bq34z950 performs measurements, calculations, protection decisions, and data
updates in 1-s intervals. Between these intervals, the bq34z950 is in a reduced power state.
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•
•
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In SLEEP mode, the bq34z950 performs measurements, calculations, protection decisions, and data updates
in adjustable time intervals. Between these intervals, the bq34z950 is in a reduced power state. The
bq34z950 has a wake function that enables exit from SLEEP mode when current flow or failure is detected.
In SHUTDOWN mode, the bq34z950 is completely disabled.
CONFIGURATION
Oscillator Function
The bq34z950 fully integrates the system oscillators. Therefore, the bq34z950 requires no external components
for this feature.
BATTERY PARAMETER MEASUREMENTS
The bq34z950 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a
second delta-sigma ADC for individual cell and battery voltage and temperature measurement.
Charge and Discharge Counting
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SRP and SRN pins. The integrating ADC measures bipolar
signals from –0.25 V to 0.25 V. The bq34z950 detects charge activity when VSR = V(SRP) – V(SRN) is positive, and
discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq34z950 continuously integrates the signal over
time, using an internal counter. The fundamental rate of the counter is 0.65 nV/h.
Voltage
The bq34z950 updates the individual series cell voltages at 1-s intervals. The internal ADC of the bq34z950
measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate the
impedance of the cell for the Impedance Track gas gauging.
Current
The bq34z950 uses the GSRP and GSRN inputs to measure and calculate the battery charge and discharge
current using a 5-mΩ to 20-mΩ typical sense resistor.
Auto Calibration
The bq34z950 provides an autocalibration feature to cancel the voltage offset error across SRP and SRN for
maximum charge measurement accuracy. The bq34z950 performs autocalibration when the SMBus and DQ
lines stay low for a minimum of 16 s, and the DF:AutoCal_PerSleep counter has counted up to its programmed
value. The AutoCal_PerSleep counter provides a way for the user to specify the number of times the part can
enter SLEEP mode before an offset calibration is performed. This is to prohibit unnecessary calibration cycles for
battery packs that enter SLEEP mode frequently. The bq34z950 is capable of automatic offset calibration down
to 1 μV.
Temperature
The bq34z950 has an internal temperature sensor and external temperature sensor input, TS1, which can be
used to sense the environmental temperature of the batteries. The bq34z950 can be configured to use internal or
external temperature sensors. The external sensor input is used in conjunction with an NTC thermistor (default is
Semitec 103AT).
COMMUNICATIONS
The bq34z950 uses SMBus v1.1 with MASTER mode and package error checking (PEC) options per the SBS
specification. Integrated error checking is not available on the DQ interface.
SMBus/DQ On and Off States
The bq34z950 detects an SMBus/DQ off state when SMBC, SMBD, and DQ are logic-low for ≥ 2 seconds.
Clearing this state requires either SMBC or SMBD or DQ to transition high. Within 1 ms, the communication bus
is available.
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SHA-1 Over DQ
SHA-1 Overview
The host sends a randomly generated 20-byte challenge, and then reads the 20-byte response generated by the
bq34z950. The response generated by the bq34z950 is calculated using the SHA-1 hash algorithm and a shared
private key known by both parties to the transaction. The host compares the bq34z950 response to the expected
response, and if they agree, then the host concludes that the bq34z950 knows the key, and is thus
authenticated.
The 20-byte challenge/response is written/read using registers 0x1B–0x2E. The bq34z950 calculates the
response when a write of any data value is issued to register 0x2F. DQ communication is ignored when the
response is calculated, which takes approximately 22 ms.
SHA-1 Usage Procedure
Use the following two steps to implement the SHA-1 algorithm in the bq34z950:
1. Create a unique authentication key and write it to the part during assembly.
The authentication key resides in the SMBus addresses 0x63–0x66 in 4-byte strings. The four strings are
read/write accessible until the bq34z950 is sealed. When written using an SMBus string write command, they
are retained permanently in flash memory and can only be changed when the bq34z950 is unsealed. They
are
stored
in
Little
Endian
format.
The
SHA-1
authentication
key
defaults
to
0123456789abcdeffedcba9876543210 in the bq34z950. This is a default and is not intended for production.
It should be changed to a unique key prior to production to ensure that security is not compromised.
For more details, see Using SHA-1 in bq20Zxx Family of Gas Gauges (SLUA359).
The host sends a 20-byte random challenge string. This string must be written to the bq34z950 DQ registers
in Little Endian format.
Little Endian representation is as follows:
Byte00, Byte01, Byte02, Byte03, Byte04, Byte05, Byte06, Byte07, Byte08, Byte09,
Byte0A, Byte0B, Byte0C, Byte0D, Byte0E, Byte0F, Byte10, Byte11, Byte12, Byte13
Big Endian representation is as follows:
Byte13, Byte12, Byte11, Byte10, Byte0F, Byte0E, Byte0D, Byte0C, Byte0B, Byte0A,
Byte09, Byte08, Byte07, Byte06, Byte05, Byte04, Byte10, Byte03, Byte02, Byte01, Byte00
2. Implement SHA-1 in the OEM host system.
(a) The host must know the SHA-1 key defined in Step 1. This key is used in the host system to determine
what the response should be.
(b) The host must issue a random challenge: The host sends a challenge using a 20-byte string write to the
SMBus command 0x2F or to the DQ registers in Little Endian format. For SHA-1 over DQ bus, the write
of 20 bytes must be followed by a write access to register 0x2F to start the authentication. Any value can
be written. It is important that the challenge be random every time to ensure security.
(c) The host computes the response: With the known SHA-1 authentication key and random challenge, the
host computes the anticipated response from the bq34z950.
(d) bq34z950 computes the response: The bq34z950 computes the response at the same time that the host
is computing it. The bq34z950 should be given greater than 22 ms to compute the response and put it
into memory or the DQ registers for retrieval.
(e) The host must read the response: The host reads the response from the same DQ registers to which the
challenge was written. The response is a 20-byte string read in Little Endian format.
(f) The host must validate the response: The host must compare the response read from the bq34z950 to
what was computed in Step 2.c above.
(g) If the response is validated, then the battery is authenticated. Otherwise, the host can reject the pack.
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Table 2. DQ COMMAND SET SUMMARY
Loc. (hex)
Access
Equivalent SMBus
Command (see SMBus
Command Details for
further information)
Symbol
Register Name
VBATH
Battery Voltage – High byte
40
Read
VBATL
Battery Voltage – Low byte
41
Read
CELL4H
Cell 4 Voltage – High byte
42
Read
CELL4L
Cell 4 Voltage – Low byte
43
Read
CELL3H
Cell 3 Voltage – High byte
44
Read
CELL3L
Cell 3 Voltage – Low byte
45
Read
CELL2H
Cell 2 Voltage – High byte
46
Read
CELL2L
Cell 2 Voltage – Low byte
47
Read
CELL1H
Cell 1 Voltage – High byte
48
Read
CELL1L
Cell 1 Voltage – Low byte
49
Read
CYCH
Cycle Count – High byte
4A
Read
CYCL
Cycle Count – Low byte
4B
Read
MFDH
Manufacturers Date – High byte
4C
Read
MFDL
Manufacturers Date – Low byte
4D
Read
IH
Current – High byte
4E
Read
IL
Current – Low byte
4F
Read
AVIH
Average Current – High byte
50
Read
AVIL
Average Current – Low byte
51
Read
TMPH
Temperature – High byte
52
Read
TMPL
Temperature – Low byte
53
Read
SNH
Serial Number – High byte
54
Read
SNL
Serial Number – Low byte
55
Read
CHGVH
Charging Voltage – High byte
56
Read
CHGVL
Charging Voltage – Low byte
57
Read
CHGIH
Charging Current – High byte
58
Read
CHGIL
Charging Current – Low byte
59
Read
RSOC
Relative State of Charge
5A
Read
RelativeStateofCharge()
0x0D
ASOC
Absolute State of Charge
5B
Read
AbsoluteStateofCharge()
0x0E
MERH
Max Error – High byte
5C
Read
MERL
Max Error – Low byte
5D
Read
Voltage() 0x09
VCELL4() 0x3C
VCELL3() 0x3D
VCELL2() 0x3E
VCELL1() 0x3F
Cyclecount() 0x17
ManufactureDate() 0x1B
Current() 0x0A
AverageCurrent() 0x0B
Temperature() 0x08
SerialNumber() 0x1C
ChargingVoltage() 0x15
ChargingCurrent() 0x14
MaxError() 0x0C
bq34z950 DQ Command Set Summary, SHA-1
Table 3. bq34z950 DQ COMMAND SET SUMMARY, SHA-1
SYMBOL
REGISTER NAME
LOC. (hex)
ACCESS
NOTE
CB00
CB01
Challenge Byte00
1B
R/W
Least significant byte
Challenge Byte01
1C
R/W
CB02
Challenge Byte02
1D
R/W
CB03
Challenge Byte03
1E
R/W
CB04
Challenge Byte04
1F
R/W
CB05
Challenge Byte05
20
R/W
CB06
Challenge Byte06
21
R/W
CB07
Challenge Byte07
22
R/W
CB08
Challenge Byte08
23
R/W
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Table 3. bq34z950 DQ COMMAND SET SUMMARY, SHA-1 (continued)
18
SYMBOL
REGISTER NAME
LOC. (hex)
ACCESS
CB09
Challenge Byte09
24
R/W
NOTE
CB0A
Challenge Byte0A
25
R/W
CB0B
Challenge Byte0B
26
R/W
CB0C
Challenge Byte0C
27
R/W
CB0D
Challenge Byte0D
28
R/W
CB0E
Challenge Byte0E
29
R/W
CB0F
Challenge Byte0F
2A
R/W
CB10
Challenge Byte10
2B
R/W
CB11
Challenge Byte11
2C
R/W
CB12
Challenge Byte12
2D
R/W
CB13
Challenge Byte13
2E
R/W
Most significant byte
AUTHST
Start Authentication
2F
Write
A write of any value starts the authentication algorithm
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SLUSBF0A – APRIL 2013 – REVISED MAY 2013
SBS Standard Commands
Table 4. SBS STANDARD COMMANDS
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min
Value
Max
Value
Default
Value
0x00
R/W
ManufacturerAccess
Hex
2
0x0000
0xffff
—
0x01
R/W
RemainingCapacityAlarm
Unsigned int
2
0
65,535
—
mAh or
10 mWh
min
Unit
0x02
R/W
RemainingTimeAlarm
Unsigned int
2
0
65,535
—
0x03
R/W
BatteryMode
Hex
2
0x0000
0xffff
—
0x04
R/W
AtRate
Signed int
2
–32,768
32,767
—
mA or 10
mW
0x05
R
AtRateTimeToFull
Unsigned int
2
0
65,535
—
min
0x06
R
AtRateTimeToEmpty
Unsigned int
2
0
65,535
—
min
0x07
R
AtRateOK
Unsigned int
2
0
65,535
—
0x08
R
Temperature
Unsigned int
2
0
65,535
—
0.1°K
0x09
R
Voltage
Unsigned int
2
0
20,000
—
mV
0x0A
R
Current
Signed int
2
–32,768
32,767
—
mA
0x0B
R
AverageCurrent
Signed int
2
–32,768
32,767
—
mA
0x0C
R
MaxError
Unsigned int
1
0
100
—
%
0x0D
R
RelativeStateOfCharge
Unsigned int
1
0
100
—
%
0x0E
R
AbsoluteStateOfCharge
Unsigned int
1
0
100
—
%
0x0F
R/W
RemainingCapacity
Unsigned int
2
0
65,535
—
mAh or
10 mWh
0x10
R
FullChargeCapacity
Unsigned int
2
0
65,535
—
mAh or
10 mWh
0x11
R
RunTimeToEmpty
Unsigned int
2
0
65,535
—
min
0x12
R
AverageTimeToEmpty
Unsigned int
2
0
65,535
—
min
0x13
R
AverageTimeToFull
Unsigned int
2
0
65,535
—
min
0x14
R
ChargingCurrent
Unsigned int
2
0
65,535
—
mA
0x15
R
ChargingVoltage
Unsigned int
2
0
65,535
—
mV
0x16
R
BatteryStatus
Unsigned int
2
0x0000
0xffff
—
0x17
R/W
CycleCount
Unsigned int
2
0
65,535
—
0x18
R/W
DesignCapacity
Unsigned int
2
0
65,535
—
mAh or
10 mWh
mV
0x19
R/W
DesignVoltage
Unsigned int
2
7,000
16,000
14,400
0x1A
R/W
SpecificationInfo
Unsigned int
2
0x0000
0xffff
0x0031
0x1B
R/W
ManufactureDate
Unsigned int
2
0
65,535
0
0x1C
R/W
SerialNumber
Hex
2
0x0000
0xffff
—
0x20
R/W
ManufacturerName
String
11 + 1
—
—
Texas
Instruments
ASCII
0x21
R/W
DeviceName
String
7+1
—
—
bq34z950
ASCII
0x22
R/W
DeviceChemistry
String
4+1
—
—
LION
ASCII
0x23
R
ManufacturerData
String
14 + 1
—
—
—
ASCII
0x2F
R/W
Authenticate
String
20 + 1
—
—
—
ASCII
0x3C
R
CellVoltage4
Unsigned int
2
0
65,535
—
mV
0x3D
R
CellVoltage3
Unsigned int
2
0
65,535
—
mV
0x3E
R
CellVoltage2
Unsigned int
2
0
65,535
—
mV
0x3F
R
CellVoltage1
Unsigned int
2
0
65,535
—
mV
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Table 5. EXTENDED SBS COMMANDS
20
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default
Value
Unit
0x45
R
AFEData
String
11 + 1
—
—
—
ASCII
0x46
R/W
FETControl
Hex
1
0x00
0xff
—
0x4F
R
StateOfHealth
Unsigned int
1
0
100
—
0x51
R
SafetyStatus
Hex
2
0x0000
0xffff
—
0x53
R
PFStatus
Hex
2
0x0000
0xffff
—
0x54
R
OperationStatus
Hex
2
0x0000
0xffff
—
0x55
R
ChargingStatus
Hex
2
0x0000
0xffff
—
%
0x57
R
ResetData
Hex
2
0x0000
0xffff
—
0x5A
R
PackVoltage
Unsigned int
2
0
65,535
—
mV
0x5D
R
AverageVoltage
Unsigned int
2
0
65,535
—
mV
0x60
R/W
UnSealKey
Hex
4
0x0000 0000
0xffff ffff
—
0x61
R/W
FullAccessKey
Hex
4
0x0000 0000
0xffff ffff
—
0x62
R/W
PFKey
Hex
4
0x0000 0000
0xffff ffff
—
0x63
R/W
AuthenKey3
Hex
4
0x0000 0000
0xffff ffff
—
0x64
R/W
AuthenKey2
Hex
4
0x0000 0000
0xffff ffff
—
0x65
R/W
AuthenKey1
Hex
4
0x0000 0000
0xffff ffff
—
0x66
R/W
AuthenKey0
Hex
4
0x0000 0000
0xffff ffff
—
0x70
R/W
ManufacturerInfo
String
8+1
—
—
—
0x71
R/W
SenseResistor
Unsigned int
2
0
65,535
—
0x77
R/W
DataFlashSubClassID
Hex
2
0x0000
0xffff
—
0x78
R/W
DataFlashSubClassPage1
Hex
32
—
—
—
0x79
R/W
DataFlashSubClassPage2
Hex
32
—
—
—
0x7A
R/W
DataFlashSubClassPage3
Hex
32
—
—
—
0x7B
R/W
DataFlashSubClassPage4
Hex
32
—
—
—
0x7C
R/W
DataFlashSubClassPage5
Hex
32
—
—
—
0x7D
R/W
DataFlashSubClassPage6
Hex
32
—
—
—
0x7E
R/W
DataFlashSubClassPage7
Hex
32
—
—
—
0x7F
R/W
DataFlashSubClassPage8
Hex
32
—
—
—
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SLUSBF0A – APRIL 2013 – REVISED MAY 2013
APPLICATION SCHEMATICS
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SLUSBF0A – APRIL 2013 – REVISED MAY 2013
REVISION HISTORY
Changes from Original (April 2013) to Revision A
•
Page
Deleted Lifetime Data Logging from Features list ................................................................................................................ 1
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PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
BQ34Z950DBT
ACTIVE
TSSOP
DBT
44
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ34Z950
BQ34Z950DBTR
ACTIVE
TSSOP
DBT
44
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ34Z950
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ34Z950DBTR
Package Package Pins
Type Drawing
TSSOP
DBT
44
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
6.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
11.7
1.6
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ34Z950DBTR
TSSOP
DBT
44
2000
367.0
367.0
45.0
Pack Materials-Page 2
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