Sony CXD1254AQ Ccd camera synchronization and timing signal generator Datasheet

CXD1254AR/AQ
CCD Camera Synchronization and Timing Signal Generator
Description
The CXD1254AR and CXD1254AQ Ics generates
the necessary synchronization and timing signals for
camera systems employing CCD image sensors
(ICX044, ICX045, ICX046, etc.).
Features
• Supports color (NTSC) and black & white
(EIA/CCIR) systems
• On-chip electronic shutter
• On-chip horizontal (H) driver
• Timing generator for mirror images
Applications
CCD camera systems
Structure
Silicon gate CMOS IC
CXD1254AR
64 pin LQFP (Plastic)
CXD1254AQ
64 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 °C, VSS=0 V)
• Supply voltage
VSS
–0.5 to +7.0
V
• Input voltage
VSS –0.5 to VDD +0.5 V
• Output voltage
VSS –0.5 to VDD +0.5 V
• Operating temperature
–20 to +75
°C
• Storage temperature
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
4.75 to 5.25
• Operating temperature
–20 to +75
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E91845B67-TE
CXD1254AR/AQ
TEST
GENERATOR
Block Diagram (Pin No.s given for CXD1254AR)
TEST2 54
TEST3 58
1/525 or 1/625
COUNTER
RESET
GENERATOR
EXT 52
TEST1 48
FLD 49
1/65 COUNTER
1/7 or 1/6
COUNTER
V-DECODER
H-DECODER
V-CONTROL
4
D1
5
D2
6
D3
62
BF
OUTPUT CONTROL
HD
1
VD
2
V-RELATIVE
COUNTER
H-INIT
V-INIT
V-ROM
(VD1)
H-RELATIVE COUNTER
ADDRESS
COUNTER
LATCH
H-ROM
(HD2)
H-ROM
(HD3)
H-ROM
(RD1)
LATCH
LATCH
GATE
GATE
LATCH
ADDRESS
COUNTER
1/3
C KIN 11
OSCI
H-RELATIVE COUNTER
9
H-ROM
(HD1)
LATCH
1/2
H-ROM
(RD2)
OSCO 10
CL
3
LATCH
RESET
CK
GENERATION
GATE
31
28
30
XSG2
ED0 13
GATE
XSG1
PS 16
COUNTER/GATE
PHASE CONT.
SHUTTER
ROM
SERIALPARALLEL
CONVERTER
SELECT
ED1 14
ED2 15
46 41
42
XSP1
XSP2
RG
XSUB
PBLK
BFG
CLP1
CLP2
—2—
43
44
27
26
29
XV4
39
XV2
45
XV3
25
XV1
23
CLP4
36
CLP3
33 35
ID
34
XSHP
H1
21
H4
XDL2
19 20
XSHD
18
H3
38
H2
37
XDL1
ENB 12
63
CBLK
64
SYNC
CXD1254AR/AQ
VDD
ID
PBLK
CLP4
CLP3
CLP2
CLP1
VSS
BFG
XDL2
XDL1
XSP2
XSP1
XSHD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
XSHP
TEST1
Pin Configuration (1)
33
FLD
49
32
VSS
HTSG
50
31
XV4
VDD
51
30
XSG2
EXT
52
29
XV3
VSS
53
28
XSG1
TEST2
54
27
XV1
NC
55
26
XV2
VDD
56
25
XSUB
CXD1254AR
H4
NC
61
20
H3
BF
62
19
H2
CBLK
63
18
H1
SYNC
64
17
AVDD
2
3
Mode
D1
D2
D3
ENB
ED0
ED1
ED2
PS
EXT
TEST2
4
5
6
Pin No.
4
5
6
12
13
14
15
16
52
54
7
8
9
PRESET
Low
Low
Low
High
High
High
High
High
Low
Low
—3—
10
11
12
13
Low
NTSC/EIA
Normal Image
Color
Normal
14
15
16
PS
1
ED2
21
ED1
60
ED0
NC
ENB
AVSS
CKIN
22
OSCO
59
OSCI
VSS
VSS
RG
TRIG
23
D3
58
D2
TEST3
D1
VDD
CL
24
VD
57
HD
NC
High
CCIR
Mirror Image
B/W
Shutter
Shutter Speed
Serial input
Parallel input
Internal
External
Normally Low
CXD1254AR/AQ
FLD
TEST1
VDD
ID
PBLK
CLP4
CLP3
CLP2
CLP1
VSS
BFG
XDL2
XDL1
XSP2
XSP1
XSHD
XSHP
VSS
XV4
Pin Configuration (2)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
HTSG 52
32
XSG2
VDD 53
31
XV3
EXT 54
30
XSG1
VSS 55
29
XV1
TEST2 56
28
XV2
NC 57
27
XSUB
26
VDD
NC 59
25
RG
TEST3 60
24
AVSS
VSS 61
23
H4
NC 62
22
H3
NC 63
21
H2
BF 64
20
H1
VDD 58
Pin No.
6
7
8
14
15
16
17
18
54
56
PRESET
Low
Low
Low
High
High
High
High
High
Low
Low
—4—
15
ED0
Low
NTSC/EIA
Normal Image
Color
Normal
16
17
18
19
AVDD
14
PS
13
ED2
12
ED1
11
ENB
10
CKIN
9
OSCO
8
OSCI
VD
7
VSS
HD
D1
D2
D3
ENB
ED0
ED1
ED2
PS
EXT
TEST2
6
TRIG
SYNC
Mode
5
D3
4
D2
3
D1
2
CL
1
CBLK
CXD1254AQ
High
CCIR
Mirror Image
B/W
Shutter
Shutter Speed
Serial input
Parallel input
Internal
External
Normally Low
CXD1254AR/AQ
Pin Description
Pin No.
LQFP QFP
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
11
10
12
11
13
12
14
13
15
14
16
15
17
Pin
I/O
Function
HD
VD
CL
D1
D2
D3
TRIG
VSS
OSCI
OSCO
CKIN
ENB
ED0
ED1
ED2
O
O
O
I
I
I
I
—
I
O
I
I
I
I
I
Horizontal drive pulse output
Vertical drive pulse output
Clock output
NTSC/EIA: 14.318 MHz CCIR: 14.1875 MHz
Mode selection “Low”: NTSC/EIA “High”: CCIR
(Pull-down resistor)
Mode selection “Low”: Normal “High”: Mirror
(Pull-down resistor)
Mode selection “Low”: Color “High”: B/W
(Pull-down resistor)
Shutter speed setting pulse input
(Pull-up resistor)
GND for signal generator
Oscillator input
NTSC/EIA: 28.636 MHz CCIR: 28.375 MHz
Oscillator output
Input for determining oscillator duty cycle
Shutter selection “Low”: Normal “High”: Shutter
(Pull-up resistor)
Shutter speed control
(Pull-up resistor)
Shutter speed control
(Pull-up resistor)
Shutter speed control
(Pull-up resistor)
Shutter speed setting data format selection
“Low”: Serial
“High”: Parallel
(Pull-up resistor)
Independent power supply for horizontal driver
Clock output for horizontal register driver
Clock output for horizontal register driver (Leave open except for ICX046.)
Clock output for horizontal register driver (Use as H2 except for ICX046.)
Clock output for horizontal register driver (Leave open except for ICX046.)
Independent GND for horizontal driver
Reset gate pulse output
Power supply for timing generator
Sensor charge sweep output pulse output
Clock output for vertical register driver
Clock output for vertical register driver
Sensor charge readout pulse output
Clock output for vertical register driver
Sensor charge readout pulse output
Clock output for vertical register driver
GND for timing generator
∗1
Pre-charge level/sample-and-hold pulse output
∗1
Data sample-and-hold pulse output
∗1
Color separation sample-and-hold pulse output
∗1
Color separation sample-and-hold pulse output
∗1
Pulse output for delay line
∗1
Pulse output for delay line
16
18
PS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
AVDD
H1
H2
H3
H4
AVSS
RG
VDD
XSUB
XV2
XV1
XSG1
XV3
XSG2
XV4
VSS
XSHP
XSHD
XSP1
XSP2
XDL1
XDL2
BFG
VSS
I
—
O
O
O
O
—
O
—
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
Burst flag gate pulse output
GND for timing generator
—5—
CXD1254AR/AQ
Pin No.
LQFP QFP
41
43
42
44
43
45
44
46
45
47
46
48
47
49
48
50
49
51
50
52
51
53
52
54
Pin
CLP1
CLP2
CLP3
CLP4
PBLK
ID
VDD
TEST1
FLD
HTSG
VDD
EXT
I/O
O
O
O
O
O
O
—
I
I/O
I
—
I
Function
Pulse output for clamp
Pulse output for clamp
Pulse output for clamp
Pulse output for clamp
Blanking/cleaning pulse output
Line discrimination pulse output
Power supply for timing generator
Test input/H reset pulse input
Field pulse output/V reset pulse input
XSG1, 2 controller/Test input
Power supply for signal generator
Synchronization mode selection.
“Low”: Internal “High”: External
GND for signal generator
Test input (Normally open)
Used open
Power supply for signal generator
Used open
Test input (Normally fixed at “Low”)
GND for signal generator
Used open
Used open
Burst flag pulse output
Composite blanking pulse output
Composite synchronization pulse output
—
55 VSS
I
56 TEST2
—
57 NC
—
58 VDD
—
59 NC
I
60 TEST3
—
61 VSS
—
62 NC
—
63 NC
O
64 BF
CBLK
O
1
SYNC
O
2
(Note) ∗1…Output determined by mode setting.
∗2…Function determined by mode setting.
53
54
55
56
57
58
59
60
61
62
63
64
∗2
∗2
∗2
(Pull-down resistor)
(Pull-down resistor)
Outputs for Pins Determined by Mode Setting
∗1
Pin
XSHP
XSHD
XSP1
XSP2
XDL1
XDL2
Pin No.
(LQFP)
33
34
35
36
37
38
D3 (Pin 6)
O
O
O
O
O
O
Low (Color)
XSHP (
) output
XSHD (
) output
XSP1 (
) output
XSP2 (
) output
XDL1 output
XDL2 output
—6—
O
O
O
O
O
O
High (B/W)
SHP (
) output
SHD (
) output
(Out put stopped)
(Out put stopped)
(Out put stopped)
(Out put stopped)
CXD1254AR/AQ
Functions for Pins Determined by Mode Settings
∗2
TEST1
FLD
Pin No.
(LQFP)
48
49
I
O
HTSG
50
I
Pin
EXT (Pin 11)
Low (Internal)
Test input (Normally low)
FLD output
XSG1, 2 control input
(“Low” : OFF “High” : ON)
Electrical Characteristics
1) DC Characteristics
Item
Supply voltage
Input voltage
Output voltage 1
Output voltage 2
CL, RG, XSHP, XSHD, XSP1,
XSP2, XDL1, XDL2
Output voltage 3
H1, H2, H3, H4
Output voltage 4
OSC0
Feedback resistance
Pull-up resistor
Pull-down resistor
I
Test input (Normally low)
(VDD=5 V ±0.25 V, Topr= –20 to +75 °C)
Symbol
VDD
VIH1
VIL1
VOH1
VOL1
Conditions
Min.
4.75
0.7 VDD
IOH=–2 mA
IOL=4 mA
VDD–0.5
VOH2
IOH=–4 mA
VDD–0.5
VOL2
IOL=8 mA
VOH3
VOL3
VOH4
VOL4
RFB
RPU
RPD
IOH=–8 mA
IOL=8 mA
IOH=–1 mA
IOL=1 mA
VIN=VSS or VDD
VIL=0 V
VIH=VDD
Typ.
5.0
0.4
0.4
VDD–0.5
0.4
VDD/2
500 k
40 k
40 k
Min.
—7—
Typ.
Max.
9
11
11
Unit
V
V
V
V
V
V
2M
100 k
100 k
(VDD=VI=0 V, fM=1 MHz)
Symbol
CIN
COUT
CI/O
Max.
5.25
0.3 VDD
2) Input/Output Capacitance
Item
Input pin capacitance
Output pin capacitance
Input/Output pin capacitance
I
I
High (External)
H reset pulse input
V reset pulse input
Unit
pF
pF
pF
VDD/2
5M
250 k
250 k
V
V
V
V
V
Ω
Ω
Ω
CXD1254AR/AQ
Electronic Shutter Description
Pins for Shutter
PS, TRIG, ENB
Inputs for overall mode setting
XSUB
Output
ED0, ED1, ED2
Inputs for shutter speed setting
(Note)
• Regardless of shutter speed setting controlled by PS, ED0 to ED2, and TRIG, if ENB is “Low”, the shutter
will be OFF.
• The speed set by PS and ED0 to ED2 is subject to control by TRIG.
Mode Description
1. TRIG (Pull-up resistor)
• For normal shutter operation, TRIG should be either left Open or set at High.
• For continuous variable shutter operation, input a clock pulse to TRIG.
VD
HD
XSGI
TRIG
XSUB
Shutter speded
By taking out XSUB pulses between downward pulses of XSG1 and TRIG, and thus stopping XSUB pulses
from the downward pulse of TRIG to the following downward pulse of XSG1, the shutter speed is determined.
In order to increase the range of control when the TRIG pin is used to control the shutter speed, Pins ED0 to
ED2 (described in next section) must be pre-set to 1/10000 sec. (Described in later section.)
2. ED0, ED1, and ED2 (Shutter speed control)
PS (Selects between parallel/serial input)
ENB (Shutter mode selection)
2-1. PS
Selects either parallel or serial input data format to be used for determining shutter speed.
• Parallel input
Combination of the 3 bits, ED0, ED1, ED2, yields 8 possible shutter speed settings.
• Serial input
Shutter speed is determined by inputting ED0 (strobe), and ED1 (clock), and ED2
(data) to respective pins.
—8—
CXD1254AR/AQ
2-1-1. [Parallel input] (PS = H) — For high speed shutter only
Table of Shutter Settings
D1
ENB ED0 ED1 ED2
X
L
X
X
X
L
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
L
H
H
X
H
H
L
H
X
H
L
L
H
X
H
H
H
L
X
H
L
H
L
X
H
H
L
L
X
H
L
L
L
Shutter speed
Shutter OFF
1/60 (s)
1/50 (s)
1/100 (s)
1/120 (s)
1/250 (s)
1/500 (s)
1/1000 (s)
1/2000 (s)
1/4000 (s)
1/10000 (s)
2-1-2. [Serial input] (PS = L)
The combination of serial data SMD1 and SMD2 can be used to select one of four modes.
Shutter Mode
Mode
Flickerless
High-speed shutter
Low-speed shutter
SMD1
Low
Low
High
SMD2
Low
High
Low
• Flickerless
• High-speed shutter
• Low-speed shutter
• No shutter
No shutter
High
High
Mode for eliminating flicker caused by oscillation frequency of fluorescent lights.
Shutter speed faster than 1/60 sec. (NTSC/EIA) or 1/50 sec. (CCIR).
Shutter speed slower than 1/60 sec. (NTSC/EIA) or 1/50 sec. (CCIR).
Shutter operation inactive.
ED1 (CLK)
ED2 (OATA)
D0
D1
D2
D3
D4
D5
D6
D7
D8
SMD1 SMD2 Dummy
EDO (STB)
ED2 data is latched in the register on the rising edge of ED1 and the register contents are transferred during
the low period of ED0.
—9—
CXD1254AR/AQ
AC Characteristics
ED2
ts2
th2
ED1
ts1
ts0
ED0
tW0
Symbol
ts2
th2
ts2
tw0
ts0
ED2 set-up time referenced from the ED1 rising edge
ED2 hold-time referenced from the ED1 rising edge
ED1 rise set-up time referenced from the ED0 rising edge
ED0 pulse width
ED0 rise set-up time referenced from the ED1 rising edge
2-1-3. [Shutter speed calculation formula]
High-speed Shutter
• For NTSC/EIA
T= [26210 – (1FF16 – L16)] × 63.56 + 34.78 µs
• For CCIR
T= [31210 – (1FF16 – L16)] × 64 + 35.6 µs
Load value
0FA16
0FC16
10016
10816
11816
13716
17616
19616
NTSC/EIA
Shutter speed
1/10000
1/4000
1/2000
1/1000
1/500
1/250
1/125
1/100
Min.
20 ns
20 ns
20 ns
20 ns
20 ns
Max.
—
—
—
50 µs
—
• L16: Load value
Calculated value
1/10169
1/4435
1/2085
1/1012
1/499
1/252
1/125
1/100
Load value
0C816
0CA16
0CE16
0D616
0E616
10516
14316
14916
Low-speed Shutter
N = 2 × (1FF16 – L16) FLD
“1FF” cannot be used as a load value.
Load value
Shutter speed (FLD)
1FE16
2
1FD16
4
:
:
10116
508
10016
510
—10—
CCIR
Shutter speed
1/10000
1/4000
1/2000
1/1000
1/500
1/250
1/125
1/100
Calculated value
1/10040
1/4349
1/2068
1/1004
1/495
1/250
1/125
1/120
CXD1254AR/AQ
External Synchronization Mode Description
• H Reset
The reset process is started from the first falling edge of the inputted reset pulse. The next reset occurs
only when there is a divergence of at least a clock cycles (0.98 µs) from the edge.
The minimum reset pulse width is 0.98 µs.
The HD output reset position leads the H reset input by 2.45 to 2.94 µs.
1H
0.98µs and over
H reset input
HD output
HD pulse reset at the falling edge of 0.98µs and over
2.45 to 2.94µs
• V Reset
The VD output reset position leads the falling edge of the V reset input by 3.5 to 4.0 H for NTSC/EIA and by
3.0 to 3.5 H for PAL.
The minimum reset pulse width is 32 µs.
1V
32µs and over
V reset input
VD output
3.5 to 4.0H (NTSC/EIA)
3.0 to 3.5H (CCIR)
9H
—11—
—12—
BFG
ID
CLP1
CLP2
CLP3
CLP4
PBLK
XV1
XV2
XV3
XV4
XSG2
XSG1
BF
SYNC
BLK
VD
HD
FLD
Timing Chart (1) <NTSC/EIA vertical direction>
ODD Field
• For EIA (black & white), the TG system output follows the VD switching point by 1H. (for both ODD and EVEN.)
CXD1254AR/AQ
—13—
BFG
ID
CLP1
CLP2
CLP3
CLP4
PBLK
XV1
XV2
XV3
XV4
XSG2
XSG1
BF
SYNC
BLK
VD
HD
FLD
EVEN Field
CXD1254AR/AQ
—14—
BFG
ID
CLP4
CLP3
CLP2
CLP1
PBLK
XV4
XV3
XV2
XV1
XSG1
XSG2
BF (2–3)
BF (4–1)
SYNC
VD
HD
BLK
FLD
Timing Chart (2) <CCIR vertical direction>
ODD Field
CXD1254AR/AQ
—15—
BFG
ID
CLP4
CLP3
CLP2
CLP1
PBLK
XV4
XV3
XV2
XV1
XSG1
XSG2
BF (1–2)
BF (3–4)
SYNC
VD
HD
BLK
FLD
EVEN Field
CXD1254AR/AQ
—16—
XSUB
BFC
ID
CLP1
CLP2
CLP3
CLP4
PBLK
XV1
XV2
XV3
XV4
XDL1
XDL2
XSP1
XSP2
SHP
SHD
XSHP
XSHD
RG
H1
H2
H3
H4
CLK
CL
BF
HSYNC
EQ
VSYNC
HD
BLK
B/W
Color
NTSC/EIA Normal Mode H Direction Timing Chart
Timing Chart (3) <NTSC/EIA horizontal direction, normal mode>
CXD1254AR/AQ
—17—
XSUB
BFC
ID
CLP1
CLP2
CLP3
CLP4
PBLK
XV1
XV2
XV3
XV4
XDL1
XDL2
XSP1
XSP2
SHP
SHD
XSHP
XSHD
RG
H1
H2
H3
H4
CLK
CL
BF
HSYNC
EQ
VSYNC
HD
BLK
B/W
Color
NTSC/EIA Mirror Mode H Direction Timing Chart
Timing Chart (4) <NTSC/EIA horizontal direction, mirror mode>
CXD1254AR/AQ
—18—
XSUB
BFC
ID
CLP1
CLP2
CLP3
CLP4
PBLK
XV1
XV2
XV3
XV4
XDL1
XDL2
XSP1
XSP2
SHP
SHD
XSHP
XSHD
RG
H1
H2
H3
H4
CLK
CL
BF
HSYNC
EQ
VSYNC
HD
BLK
CCIR Normal Mode H Direction Timing Chart
Timing Chart (5) <CCIR horizontal direction, normal mode>
CXD1254AR/AQ
—19—
XSUB
BFC
ID
CLP1
CLP2
CLP3
CLP4
PBLK
XV1
XV2
XV3
XV4
XDL1
XDL2
XSP1
XSP2
SHP
SHD
XSHP
XSHD
RG
H1
H2
H3
H4
CLK
CL
BF
HSYNC
EQ
VSYNC
HD
BLK
CCIR Mirror Mode H Direction Timing Chart
Timing Chart (6) <CCIR horizontal direction, mirror mode>
CXD1254AR/AQ
CXD1254AR/AQ
Signal Processing
Application Circuit
(LQFP Package)
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
CCD imase sensor
47
Driver
48
25
CXD1254AR
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Shutter control
OSC NTSC/EIA
CCIR
: 28.6363MHz
: 28.375MHz
• Please use a clock crystal which
operates on a fundamental wave.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—20—
CXD1254AR/AQ
Package Outline
Unit : mm
CXD1254AR
64PIN LQFP (PLASTIC)
12.0 ± 0.2
∗
10.0 ± 0.1
48
33
32
64
17
(0.22)
0.5 ± 0.2
(11.0)
49
A
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
16
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: “∗” Dimensions do not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
LQFP-64P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
QFP064-P-1010
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
CXD1254AQ
64PIN QFP(PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
51
0.15
64
20
1
16.3
32
+ 0.4
14.0 – 0.1
52
17.9 ± 0.4
33
+ 0.2
0.1 – 0.05
1.0
0.8 ± 0.2
19
+ 0.35
2.75 – 0.15
+ 0.15
0.4 – 0.1
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP–64P–L01
LEAD TREATMENT
EIAJ CODE
∗ QFP064–P–1420
LEAD MATERIAL
SOLDER/PALLADIUM
PLATING
COPPER /42 ALLOY
PACKAGE WEIGHT
1.5g
JEDEC CODE
—21—
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