Intel LXT351 T1/e1 short haul transceiver with crystal-less jitter attenuation Datasheet

LXT351
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Datasheet
The LXT351 is a full-featured, fully-integrated transceiver for T1 and E1 short-haul
applications. The LXT351 is software switchable between T1 and E1 operation, and offers pulse
equalization settings for all short-haul T1 and E1 line interface (LIU) applications.
The LXT351 offers an Intel/Motorola compatible parallel port for microprocessor control. The
device incorporates advanced crystal-less digital jitter attenuation in either the transmit or
receive data path starting at 3 Hz. B8ZS/HDB3 encoding/decoding and unipolar or bipolar data
I/O are selectable. Loss of signal monitoring and a variety of diagnostic loopback modes can
also be selected.
Applications
■
■
SONET/SDH tributary interfaces
Digital cross connects
■
■
Public/private switching trunk line
interfaces
Microwave transmission systems
Product Features
■
■
■
■
■
■
Fully integrated transceivers for Short-Haul
T1 or E1 interfaces
Crystal-less digital jitter attenuation
— Select either transmit or receive path
— No crystal or high speed external clock
required
Meet or exceed specifications in ANSI
T1.403 and T1.408; ITU I.431, G.703,
G.736, G.775 and G.823; ETSI 300-166
and 300-233; and AT&T Pub 62411
Supports 75 Ω (E1 coax), 100 Ω (T1
twisted-pair) and 120 Ω (E1 twisted-pair)
applications
Fully restores the received signal after
transmission through a cable with
attenuation of 18dB, at 1024 kHz
Five pulse equalization settings for T1
short-haul applications
■
■
■
■
■
■
■
■
Transmit/receive performance monitors
with Driver Fail Monitor Open (DFM) and
Loss of Signal (LOS) outputs
Selectable unipolar or bipolar data I/O and
B8ZS/HDB3 encoding/decoding
QRSS generator/detector for testing or
monitoring
Output short circuit current limit protection
Local, remote and analog loopback
capability
Compatible with Intel’s LXT360/361 T1/
E1 long haul/short haul transceiver
(Universal LIU)
Multiple register parallel interface
compatible with both Intel and Motorola
microprocessors
Available in 28-pin PLCC and 44-pin
PQFP packages
As of January 15, 2001, this document replaces the Level One document
Order Number: 249030-001
LXT351 — Integrated T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation.
January 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT351 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Contents
1.0
Pin Assignments and Signal Descriptions ...................................................... 8
1.1
2.0
Mode Dependent Signals ...................................................................................... 9
Functional Description...........................................................................................13
2.1
2.2
2.3
2.4
2.5
2.6
Initialization..........................................................................................................13
2.1.1 Reset Operation .....................................................................................13
Transmitter ..........................................................................................................13
2.2.1 Transmit Digital Data Interface...............................................................13
2.2.2 Transmit Monitoring................................................................................14
2.2.3 Transmit Drivers .....................................................................................14
2.2.4 Transmit Idle Mode.................................................................................14
2.2.5 Transmit Pulse Shape ............................................................................14
Receiver ..............................................................................................................15
2.3.1 Receive Data Recovery..........................................................................15
Jitter Attenuation .................................................................................................15
Diagnostic Mode Operation.................................................................................16
2.5.1 Loopback Modes ....................................................................................16
2.5.1.1 Local Loopback .........................................................................16
2.5.1.2 Analog Loopback.......................................................................18
2.5.1.3 Remote Loopback .....................................................................18
2.5.1.4 Dual Loopback ..........................................................................19
2.5.2 Internal Pattern Generation ....................................................................19
2.5.2.1 Transmit All Ones ......................................................................19
2.5.2.2 Quasi-Random Signal Source (QRSS) .....................................20
2.5.3 Error Insertion and Detection .................................................................21
2.5.3.1 Bipolar Violation Insertion (INSBPV) .........................................21
2.5.3.2 Logic Error Insertion (INSLER)..................................................21
2.5.3.3 Bipolar Violation Detection (BPV)..............................................21
2.5.3.4 HDB3 Code Violation Detection (CODEV) ................................21
2.5.3.5 HDB3 Zero Substitution Violation Detection (ZEROV) ..............21
2.5.4 Alarm Condition Monitoring ....................................................................22
2.5.4.1 Loss of Signal ............................................................................22
2.5.4.2 Alarm Indication Signal Detection .............................................22
2.5.4.3 Driver Failure Open Mode .........................................................22
2.5.4.4 Elastic Store Overflow/Underflow ..............................................22
2.5.4.5 Built-In Self Test ........................................................................23
Parallel Microprocessor Interface........................................................................23
2.6.1 Interrupt Handling...................................................................................23
3.0
Register Definitions.................................................................................................24
4.0
Application Information .........................................................................................29
4.1
4.2
4.3
4.4
Datasheet
Transmit Return Loss ..........................................................................................29
Transformer Data ................................................................................................29
Application Circuit................................................................................................29
Line Protection ....................................................................................................29
4.4.1 LXT351 Application Circuit .....................................................................31
3
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
5.0
Test Specifications .................................................................................................. 33
6.0
Mechanical Specifications ................................................................................... 45
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
4
LXT351 Block Diagram ......................................................................................... 7
LXT351 Pin Assignments...................................................................................... 8
50% Duty Cycle Coding ...................................................................................... 14
Local Loopback ................................................................................................... 16
TAOS with LLOOP .............................................................................................. 17
Analog Loopback ................................................................................................ 18
Remote Loopback ............................................................................................... 19
Dual Loopback .................................................................................................... 19
TAOS Data Path ................................................................................................. 20
QRSS Mode ........................................................................................................ 20
Typical T1/E1 LXT351 Application ...................................................................... 32
2.048 Mbps E1 Pulse (See Table 24)................................................................. 35
1.544 Mbps T1 Pulse, DSX-1 (See Table 25) ..................................................... 36
Transmit Clock Timing ........................................................................................ 37
Receive Clock Timing ......................................................................................... 38
Intel Address/Data Bus Timing............................................................................ 40
Motorola Address/Data Bus Timing .................................................................... 41
Typical T1 Jitter Tolerance at 36 dB ................................................................... 41
Typical E1 Jitter Tolerance at 43 dB ................................................................... 42
Typical E1 Jitter Attenuation ............................................................................... 43
Typical T1 Jitter Attenuation................................................................................ 44
Plastic Leaded Chip Carrier Package Specifications .......................................... 45
Plastic Quad Flat Package Specifications........................................................... 46
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Datasheet
LXT351 Clock and Data Pin Assignments by Mode1............................................ 9
LXT351 Processor Interface Pins.......................................................................... 9
LXT351 Signal Descriptions ................................................................................10
Diagnostic Mode Summary .................................................................................16
Register Addresses .............................................................................................24
Register and Bit Summary ..................................................................................24
Control Register #1 Read/Write, Address (A7-A0) = x010000x ..........................25
Equalizer Control Input Settings.........................................................................25
Control Register #2 Read/Write, Address (A7-A0) = x010001x ..........................25
Control Register #3 Read/Write, Address (A7-A0) = x010010x ..........................26
Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x....................26
Transition Status Register Read Only, Address (A7-A0) = x010100x.................27
Performance Status Register Read Only, Address (A7-A0) = x010101x ............27
Control Register #4 Read/Write, Address (A7-A0) = x010111x ..........................28
E1 Transmit Return Loss Requirements .............................................................29
Transmit Return Loss (2.048 Mbps)....................................................................30
Transmit Return Loss (1.544 Mbps)....................................................................30
Transformer Specifications..................................................................................30
Recommended Transformers..............................................................................31
Absolute Maximum Ratings.................................................................................33
Recommended Operating Conditions .................................................................33
DC Electrical Characteristics...............................................................................34
Analog Characteristics ........................................................................................34
2.048 Mbps E1 Pulse Mask Specifications ........................................................35
1.544 Mbps T1, DSX-1 Pulse Mask Corner Point Specifications........................36
Master and Transmit Clock Timing Characteristics for T1 Operation
(See Figure 14) ...................................................................................................37
Master and Transmit Clock Timing Characteristics for E1 Operation
(See Figure 14) ...................................................................................................37
Receive Timing Characteristics for T1 Operation (See Figure 15)......................38
Receive Timing Characteristics for E1 Operation (See Figure 15) .....................38
20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 16)................39
16.78 MHz Motorola Bus Parallel I/O Timing Characteristics (See Figure 17) ...40
5
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Revision History
Revision
6
Date
Description
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Figure 1. LXT351 Block Diagram
Datasheet
7
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
1.0
Pin Assignments and Signal Descriptions
AD3
2
AD4
TCLK
3
MCLK
TPOS / TDATA / INSLER
4
AD5
TNEG / INSBPV
Figure 2. LXT351 Pin Assignments
1
28
27
26
ALE / AS
5
25
AD2
RNEG / BPV
AD1
7
23
AD0
RCLK
8
22
GND
21
VCC
20
RRING
19
RTIP
RD / DS
9
AD6
10
AD7
LXT351PE
LXT351PEXX
XXXXXX
XXXXXXXX
CS
INT
AD5
AD3
18
AD4
17
TRING
TVCC
16
MCLK
TGND
15
TCLK
14
n/c
TPOS / TDATA / INSLER
TTIP
TNEG / INSBPV
13
n/c
12
WR / R/W
11
n/c
24
AD2
6
RPOS / RDATA
44 43 42 41 40 39 38 37 36 35 34
n/c
1
33
n/c
ALE / AS
2
32
AD1
RNEG / BPV
3
31
AD0
RPOS / RDATA
4
30
n/c
RCLK
5
n/c
6
RD / DS
7
n/c
8
AD6
29
GND
28
n/c
27
VCC
26
n/c
9
25
RRING
AD7
10
24
RTIP
n/c
11
23
n/c
LXT351QE
LXT351QE
XX
XXXXXX
XXXXXXXX
n/c
INT
CS
TVCC
TRING
n/c
TTIP
TGND
n/c
n/c
8
WR / R/W
12 13 14 15 16 17 18 19 20 21 22
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
1.1
Mode Dependent Signals
As shown in Figure 2, the LXT351 has several pins that change function (and signal name)
according to the selected mode(s) of operation. These pins, associated signal names, and operating
modes are summarized in Table 1 and Table 2. LXT351 signals are described in Table 3.
LXT351 Clock and Data Pin Assignments by Mode1
Table 1.
Pin #
External Data Modes
Bipolar Mode
QRSS Modes
PLCC
QFP
Unipolar Mode
Bipolar Mode
Unipolar Mode
1
39
2
41
3
42
TPOS
TDATA
INSLER
4
43
TNEG
INSBPV
INSBPV
6
3
RNEG
BPV
7
4
RPOS
RDATA
8
5
RCLK
13
15
TTIP
16
19
TRING
19
24
RTIP
20
25
RRING
MCLK
TCLK
RNEG
BPV
RPOS
RDATA
1. Data pins change based on whether external data or internal QRSS mode is active.
Table 2.
Pin #
LXT351 Processor Interface Pins
Address/Data Bus Type
Pin #
Address/Data Bus Type
PLCC
QFP
Intel
Motorola
PLCC
QFP
Intel
Motorola
5
2
ALE
AS
25
35
AD2
9
7
RD
DS
26
36
AD3
12
13
WR
R/W
27
37
AD4
17
20
CS
28
38
AD5
18
21
INT
10
9
AD6
23
31
AD0
11
10
AD7
24
32
AD1
-
-
-
Datasheet
9
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 3.
LXT351 Signal Descriptions
Pin #
Symbol
PLCC
I/O1
Description
QFP
1
39
MCLK
DI
Master Clock. External, independent clock signal required to generate
internal clocks. For T1 applications, a 1.544 MHz clock is required; for E1,
a 2.048 MHz clock. MCLK must be jitter-free and have an accuracy better
than ± 50 ppm with a typical duty cycle of 50%. Upon Loss of Signal (LOS),
RCLK is derived from MCLK.
2
41
TCLK
DI
Transmit Clock. For T1 applications, a 1.544 MHz clock is required; for
E1, a 2.048 MHz clock. The transceiver samples TPOS and TNEG on the
falling edge of TCLK (or MCLK, if TCLK is not present).
BIPOLAR MODES:
Transmit – Positive and Negative. TPOS and TNEG are the positive and
negative sides of a bipolar input pair. Data to be transmitted onto the
twisted-pair line is input at these pins. TPOS/TNEG are sampled on the
falling edge of TCLK (or MCLK, if TCLK is not present).
UNIPOLAR MODES:
3
42
TPOS / TDATA /
INSLER
DI
4
43
TNEG / INSBPV
DI
Transmit Data. TDATA carries unipolar data to be transmitted onto the
twisted-pair line and is sampled on the falling edge of TCLK.
Transmit Insert Logic Error. In QRSS mode, a Low-to-High transition on
INSLER inserts a logic error into the transmitted QRSS data pattern. The
error follows the data flow of the active loopback mode. The LXT351
samples this pin on the falling edge of TCLK (or MCLK, if TCLK is not
present).
Transmit Insert Bipolar Violation. INSBPV is sampled on the falling edge
of TCLK (or MCLK, if TCLK is not present) to control Bipolar Violation
(BPV) insertions in the transmit data stream. A Low-to-High transition is
required to insert each BPV. In QRSS mode, the BPV is inserted into the
transmitted QRSS pattern.
Address Latch Enable. Connect to ALE signal of Intel microprocessor
5
2
ALE / AS
DI
Address Strobe Connect to AS signal of Motorola microprocessor.
Note that leaving this pin floating forces all output pins to a high impedance
state.
BIPOLAR MODES:
6
3
RNEG / BPV
DO
Receive – Negative and Positive. RPOS and RNEG are the positive and
negative sides of a bipolar output pair. Data recovered from the line
interface is output on these pins. A signal on RNEG corresponds to receipt
of a negative pulse on RTIP/RRING. A signal on RPOS corresponds to
receipt of a positive pulse on RTIP/RRING. RNEG/RPOS are Non-Returnto-Zero (NRZ). The PLCKE bit in register CR3 selects the RCLK clock
edge when RPOS /RNEG are stable and valid.
7
4
RPOS / RDATA
DO
UNIPOLAR MODES:
Receive Bipolar Violation. BPV goes High to indicate detection of a
bipolar violation from the line. This is an NRZ output, valid on the rising
edge of RCLK.
Receive Data. RDATA is the unipolar NRZ output of data recovered from
the line interface. The PLCKE bit in register CR3 selects the RCLK clock
edge when RDATA is stable and valid.
8
5
RCLK
DO
Receive Recovered Clock. The clock recovered from the line input signal
is output on this pin. Under LOS conditions, there is a smooth transition
from the RCLK signal (derived from the recovered data) to the MCLK
signal at the RCLK pin.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
10
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Table 3.
LXT351 Signal Descriptions (Continued)
Pin #
Symbol
PLCC
I/O1
Description
QFP
9
7
RD / DS
10
9
AD6
11
10
AD7
DI
DI/O
Read. On an Intel bus, driving RD Low commands a LXT351 register read
operation.
Data Strobe. On a Motorola bus, DS goes Low when data is being driven
on the address/data bus. Data is valid on the rising edge of DS.
Address/Data Bus 6 and 7. Used with AD0 - AD5 to form the address/
data bus. Conforms to Intel and Motorola multiplexed address/data bus
specifications.
Write. On an Intel bus, driving WR Low commands a LXT351 register write
operation.
12
13
WR / R/W
13
15
TTIP
16
19
TRING
14
16
TGND
-
Ground return for the transmit driver power supply TVCC.
15
18
TVCC
-
+5 VDC Power Supply for the transmit drivers. TVCC must not vary from
VCC by more than ± 0.3 V.
17
20
CS
18
21
INT
19
24
RTIP
20
25
RRING
21
27
VCC
DI
AO
DI
Read/Write. On a Motorola bus, driving R/W High commands a LXT351
register read operation; driving it Low commands a write operation.
Transmit Tip and Ring. Differential driver output pair designed to drive a
50 - 200 Ω load. The transformer and line matching resistors should be
selected to give the desired pulse height and return loss performance. See
“Application Information” on page 29.
Chip Select. During a read or write operation, CS must remain Low. See
Figure 16 and Figure 17 for timing requirements.
In the case of a single processor controlling several chips, this line is used
to select a specific transceiver.
DO
Interrupt. INT goes Low to flag the host when LOS, AIS, QRSS, DFMS or
DFMO bits changes state, or when an elastic store overflow or underflow
occurs. To identify the specific interrupt, read the Performance Status
Register (PSR). To clear or mask an interrupt, write a one to the
appropriate bit in the Interrupt Clear Register (ICR). To re-enable the
interrupt, write a zero. INT is an open drain output that must be
connected to VCC through a pull-up resistor.
AI
Receive Tip and Ring. The Alternate Mark Inversion (AMI) signal received
from the line is applied at these pins. A 1:1 transformer is required. Data
and clock recovered from RTIP/RRING are output on the RPOS/RNEG (or
RDATA in Unipolar mode), and RCLK pins.
-
+5 VDC Power Supply for all circuits except the transmit drivers. Transmit
drivers are supplied by TVCC.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
Datasheet
11
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 3.
LXT351 Signal Descriptions (Continued)
Pin #
Symbol
I/O1
29
GND
-
23
31
AD0
24
32
AD1
25
35
AD2
26
36
AD3
27
37
AD4
28
38
AD5
-
8, 11,
12, 14,
17, 22,
23, 26,
28, 30,
33, 34,
40, 44
n/c
PLCC
QFP
22
DI/O
-
Description
Ground return for VCC.
Address/Data Bus 0 - 5. Used with AD6 and AD7 to form the address/
data bus. Conforms to Intel and Motorola multiplexed address/data bus
specifications.
Not Connected
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
12
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
2.0
Functional Description
The LXT351 is a fully integrated, PCM transceiver for short-haul, 1.544 Mbps (T1) or 2.048 Mbps
(E1) applications allowing full-duplex transmission of digital data over existing twisted-pair
installations. It interfaces with two twisted-pair lines (one pair each for transmit and receive)
through standard pulse transformers and appropriate resistors.
The figure on the front page of this data sheet shows a block diagram of the LXT351. Control of
the chip is via the 8-bit parallel microprocessor port. Stand-alone operation is not supported.
The LXT351 provides a high-precision, crystal-less jitter attenuator (JA). The user may place the
JA in the transmit or receive path, or bypass it completely.
The transceiver meets or exceeds FCC, ANSI, and AT&T specifications for CSU and DSX-1
applications, as well as ITU and ETSI requirements for E1 ISDN PRI applications.
2.1
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 3 V.
Upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the Phase Lock
Loops (PLL). The transceiver uses a reference clock to calibrate the PLLs: the transmitter reference
is TCLK, and the receiver reference clock is MCLK. MCLK is mandatory for chip operation and
must be independent, free running, and jitter free.
2.1.1
Reset Operation
A reset operation initializes the status and state machines for the LOS, AIS and QRSS blocks.
Writing a 1 to the bit CR2.RESET commands a reset which clears all registers to 0. Allow 32 ms
for the device to settle.
2.2
Transmitter
2.2.1
Transmit Digital Data Interface
Input data for transmission onto the line is clocked serially into the device at the TCLK rate. TPOS
and TNEG are the bipolar data inputs. In Unipolar mode, the TDATA pin accepts unipolar data.
Input data may pass through either the Jitter Attenuator or B8ZS/HDB3 encoder or both. Setting
CR1.ENCENB = 1 enables B8ZS/HDB3 encoding. With zero suppression enabled, Control
Register #1 (CR1) bits EC1 through EC3 determine the coding scheme as listed in Table 8 on
page 25.
TCLK supplies input synchronization. See the Figure 14 on page 37 for the transmit timing
requirements for TCLK and the Master Clock (MCLK).
Datasheet
13
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
2.2.2
Transmit Monitoring
The transmitter includes a short circuit limiter that limits the current sourced into a low impedance
load. The limiter automatically resets when the load current drops below the limit. The current is
determined by the interface circuitry (total resistance on transmit side).
The Performance Status Register (PSR) flags open circuits in bit PSR.DFMO. A transition of
DFMO can provide an interrupt, and its transition sets bit TSR.DFMO = 1. Writing a 1 in bit
ICR.CDFMO clears the interrupt; leaving a 1 in the bit masks that interrupt.
2.2.3
Transmit Drivers
The transceiver transmits data as a 50% line code as shown in Figure 3. To reduce power
consumption, the line driver is active only during transmission of marks, and is disabled during
transmission of spaces. Biasing of the transmit DC level is on-chip.
Figure 3. 50% Duty Cycle Coding
Bit Cell
1
2.2.4
0
1
Transmit Idle Mode
Transmit Idle mode allows multiple transceivers to be connected to a single line for redundant
applications. When TCLK is not present, Transmit Idle mode becomes active, and TTIP and
TRING change to the high impedance state. Remote or Dual Loopback, TAOS or any internal
transmit patterns temporarily disable the high impedance state.
2.2.5
Transmit Pulse Shape
As shown in Table 8 on page 25, the transmitted pulse shape is established by bits EC1 through
EC3 of Control Register #1 (CR1).
The transceiver produces DSX-1 pulses for short-haul T1 applications (settings from 0 dB to +6.0
dB of cable) or G.703 pulses for E1 applications. Shaped pulses are applied to the AMI line driver
for transmission onto the line at TTIP and TRING. Refer to the Test Specifications section for
pulse mask specifications.
14
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
2.3
Receiver
A 1:1 transformer provides the interface to the twisted-pair line. Recovered data is output at RPOS/
RNEG (RDATA in Unipolar mode), and the recovered clock is output at RCLK. Refer to Table 28
and Table 28 on page 38 for receiver timing specifications.
2.3.1
Receive Data Recovery
The transceiver filters the equalized signal and applies it to the peak detector and data slicers. The
peak detector samples the inputs and determines the maximum value of the received signal. The
data slicers are set at 50% of the peak value to ensure optimum signal-to-noise performance.
After processing through the data slicers, the received signal goes to the data and timing recovery
section, then to the B8ZS/HDB3 decoder (if selected) and to the receive monitor. The data and
timing recovery circuits provide input jitter tolerance significantly better than required by AT&T
Pub 62411 and ITU G.823. See the “Test Specifications” section for details.
Recovered data is routed to the Loss of Signal (LOS) Monitor and through the Alarm Indication
Signal (AIS, Blue Alarm) Monitor. The jitter attenuator (JA) may be enabled or disabled in the
receive data path or the transmit path. Received data may be routed to either the B8ZS or HDB3
decoder or neither. Finally, the device may send the digital data to the framer as either unipolar or
bipolar data.
When transmitting unipolar data to the framer, the device reports reception of bipolar violations by
driving the BPV pin High. During E1 operation, the device can report HDB3 code violations and
Zero Substitution Violations on the BPV pin.
2.4
Jitter Attenuation
A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides jitter attenuation as shown in
the Test Specifications section. The JAL requires no special circuitry, such as an external quartz
crystal or high-frequency clock (higher than the line rate). Its timing reference is MCLK.
Bit CR1.JASEL0 enables or disables the JA circuit. With bit CR1.JASEL0 = 1, bit CR1.JASEL1
controls the JA circuit placement (see Table 7 on page 25). The ES can be either a 32 x 2-bit or 64
x 2-bit register depending on the value of bit CR3.ES64 (see Table 10 on page 26.)
The device clocks data into the ES using either TCLK or RCLK depending on whether the JA
circuitry is in the transmit or receive data path, respectively. Data is shifted out of the elastic store
using the dejittered clock from the JAL. When the FIFO is within two bits of overflowing or
underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average
delay of 16 bits (or 32 bits, with the 64-bit ES option selected) in the associated data path. When
the Jitter Attenuator is in the receive path, the output RCLK transitions smoothly to MCLK in the
event of a LOS condition.
The Transition Status Register bits TSR.ESOVR and TSR.ESUNF indicate an elastic store
overflow or underflow, respectively. Note that these are sticky bits that once set to 1, remain set
until the host reads the register. The ES can also provide a maskable interrupt on either overflow or
underflow.
Datasheet
15
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
2.5
Diagnostic Mode Operation
The LXT351 offers multiple diagnostic modes as listed in Table 4. The diagnostic modes are
selected by setting the appropriate register bits as described in the following paragraphs.
2.5.1
Loopback Modes
2.5.1.1
Local Loopback
See Figure 4 and Figure 5. Local loopback is selected by setting CR2.ELLOOP to 1. LLOOP
inhibits the receiver circuits. The transmit clock and data inputs (TCLK and TPOS/TNEG or
TDATA) loop back through the jitter attenuator (if enabled) and show up at RCLK and RPOS/
RNEG or RDATA. Note that during LLOOP, the JASEL input is strictly an Enable/Disable control;
it does not affect the placement of the JAL. If JA is enabled, it is active in the loopback circuit. If
JA is bypassed, it is not active in the loopback circuit.
The transmitter circuits are unaffected by LLOOP. LXT351 transmits the TPOS/TNEG or TDATA
inputs (or a stream of 1s if TAOS is asserted) normally. When used in this mode, the transceiver
can function as a stand-alone jitter attenuator.
Figure 4. Local Loopback
Table 4.
Diagnostic Mode Summary
Diagnostic Mode
Interrupt
Maskable
Loopback Modes
16
Local Loopback (LLOOP)
No
Analog Loopback (ALOOP)
No
Remote Loopback (RLOOP)
No
Dual Loopback (DLOOP)
No
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Table 4.
Diagnostic Mode Summary
Diagnostic Mode
Interrupt
Maskable
Internal Data Pattern Generation
Transmit All Ones (TAOS)
No
Quasi-Random Signal Source (QRSS)
Yes
Error Insertion and Detection
Bipolar Violation Insertion (INSBPV)
No
Logic Error Insertion (INSLER)
No
Bipolar Violation Detection (BPV)
No
HDB3 Code Violation Detection (CODEV)
No
HDB3 Zero violation Detection (ZEROV)
No
Alarm Condition Monitoring
Receive Loss of Signal (LOS) Monitoring
Yes
Receive Alarm Indication Signal (AIS)
Monitoring
Yes
Transmit Driver Failure Monitoring Open
(DFMO)
Yes
Elastic Store Overflow and Underflow
Monitoring
Yes
Built-In Self Test (BIST)
Yes
Figure 5. TAOS with LLOOP
Datasheet
17
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
2.5.1.2
Analog Loopback
See Figure 6. Analog loopback (ALOOP) exercises the maximum number of functional blocks.
ALOOP operation disconnects the RTIP/RRING inputs from the line and routes the transmit
outputs back into the receive inputs. This tests the encoders/decoders, jitter attenuator, transmitter,
receiver and timing recovery sections. Writing a 1 to bit CR2.EALOOP enables the ALOOP mode.
Note that ALOOP will override all other loopback modes.
Figure 6. Analog Loopback
2.5.1.3
Remote Loopback
See Figure 7. In Remote loopback (RLOOP) mode, the device ignores the transmit data and clock
inputs (TCLK and TPOS/TNEG or TDATA), and bypasses the in-line encoders/decoders. The
RPOS/RNEG or RDATA outputs loop back through the transmit circuits to TTIP and TRING at the
RCLK frequency. The RLOOP command does not affect the receiver circuits which continue to
output the RCLK and RPOS/RNEG or RDATA signals received from the twisted-pair line.
RLOOP is selected by writing a 1 to bit CR2.ERLOOP.
18
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Figure 7. Remote Loopback
2.5.1.4
Dual Loopback
See Figure 8. To select Dual loopback (DLOOP) set bits CR2.ERLOOP and CR2.ELLOOP to 1. In
DLOOP mode, the transmit clock and data inputs (TCLK and TPOS/TNEG or TDATA) loop back
through the Jitter Attenuator (unless disabled) to RCLK and RPOS/RNEG or RDATA. The data
and clock recovered from the twisted-pair line loop back through the transmit circuits to TTIP and
TRING without jitter attenuation.
Figure 8. Dual Loopback
2.5.2
Internal Pattern Generation
2.5.2.1
Transmit All Ones
See Figure 9. In Transmit All Ones (TAOS) mode, the transceiver ignores the TPOS and TNEG
inputs and transmits a continuous stream of 1s at the TCLK frequency. (With no TCLK, the TAOS
output clock is MCLK.) This can be used as the Alarm Indication Signal (AIS–also called the Blue
Alarm). TAOS is commanded by writing a 1 to bit CR2.ETAOS. Both TAOS and Local loopback
can occur simultaneously as shown in Figure 4, however, Remote loopback inhibits TAOS. When
both TAOS and LLOOP are active, TCLK and TPOS/TNEG loop back to RCLK and RPOS/RNEG
through the jitter attenuator (if enabled), and an all ones pattern goes to TTIP/TRING.
Datasheet
19
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 9. TAOS Data Path
2.5.2.2
Quasi-Random Signal Source (QRSS)
See Figure 10. For T1 operation, the Quasi-Random Signal Source (QRSS) is a 220-1 pseudorandom bit sequence (PRBS) with no more than 14 consecutive zeros. For E1 operation, QRSS is
215-1 PRBS with inverted output. Setting bits CR2.EPAT0 = 0 and CR2.EPAT1 = 1 enables this
function.
The QRSS pattern is normally locked to TCLK; but if there is no TCLK, MCLK is the clock
source. Bellcore Pub 62411 defines the T1 QRSS transmit format and ITU G.703 defines the E1
format.
Figure 10. QRSS Mode
* If Enabled
INT*
With QRSS transmission enabled, it is possible to insert a logic error into the transmit data stream
by causing a Low-to-High transition on INSLER. However, if no logic or bit errors are to be
inserted into the QRSS pattern, INSLER must remain Low. Logic Error insertion waits until the
next bit if the current bit is “jammed”. When there are more than 14 consecutive 0s, the output is
jammed to a 1.
Furthermore, a bipolar violation in the QRSS pattern is possible by causing a Low-to-High
transition on the INSBPV pin, regardless of whether the device is in Bipolar or Unipolar mode.
Choosing QRSS mode also enables the QRSS Pattern Detection in the receive path. The QRSS
pattern is synchronized when there are fewer than four errors in 128 bits. The PSR.QRSS bit
provides an indication of QRSS pattern synchronization. This bit goes Low when no QRSS pattern
detected (i.e., when there are more than four errors in 128 bits). The TQRSS bit in the Transition
Status Register indicates that QRSS status has changed since the last QRSS Interrupt Clear
command.
The LXT351 can generate an interrupt to indicate that QRSS detection has occurred, or that
synchronization is lost. The interrupt is enabled when ICR.CQRSS = 0.
20
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
2.5.3
Error Insertion and Detection
2.5.3.1
Bipolar Violation Insertion (INSBPV)
Bipolar violation insertion is available In Unipolar mode. Choosing Unipolar mode configures the
INSBPV pin. To insert bipolar violation (BPV), a Low-to-High transition on the INSBPV is
required. Sampling occurs on the falling edge of TCLK. When INSBPV goes High a BPV is
inserted on the next available mark except in the four following situations:
• Zero suppression (HDB3 or B8ZS) is not violated
• If LLOOP and TAOS are both active, the BPV is looped back to RNEG/BPV indicator and the
line driver transmits all ones with no violation
• BPV insertion is disabled with RLOOP active
With the LXT351 configured to transmit internally generated data patterns, a BPV can be inserted
into the transmit pattern regardless of whether the device is in the Unipolar or Bipolar mode of
operation.
2.5.3.2
Logic Error Insertion (INSLER)
When configured to transmit internally generated data patterns, a logic error is inserted into the
transmit data pattern when the INSLER pin transitions Low-to-High. Note that in QRSS mode,
there is no logic error insertion on a jammed bit (i.e., a bit forced to one to suppress transmission of
more than 14 consecutive zeros). The transceiver routes data patterns the same way it routes data
applied to TPOS/TNEG. Therefore, the inserted logic error will follow the data flow path of the
active loopback mode.
2.5.3.3
Bipolar Violation Detection (BPV)
When the internal encoders/decoders are disabled or when configured in Unipolar mode, bipolar
violations are reported at the BPV pin. BPV goes High for a full clock cycle to indicate receipt of a
BPV. When the encoders/decoders are enabled, the LXT351 does not report bipolar violations due
to the line coding scheme.
2.5.3.4
HDB3 Code Violation Detection (CODEV)
An HDB3 code violation (CODEV) occurs when two consecutive bipolar violations of the same
polarity are received (refer to ITU O.161). When CODEV detection is enabled, the BPV pin goes
High for a full RCLK cycle to report a CODEV violation. Note that bipolar violations and zero
substitution violations will also be reported on the BPV pin if these options are enabled.
HDB3 code violation detection is enabled when the HDB3 encoders/decoders are enabled. This
requires that CR1.ENCENB = 1, also CR1.EC3:1 = 000, which establishes E1 operation. To select
CODEV detection, set bit CR4.CODEV = 1.
2.5.3.5
HDB3 Zero Substitution Violation Detection (ZEROV)
An HDB3 ZEROV is the receipt of four or more consecutive zeros. This does not occur with
correctly encoded HDB3 data unless there are transmission errors. The BPV pin goes High for a
full RCLK cycle to report a ZEROV. Note that when ZEROV detection enabled, the BPV pin will
also indicate received BPVs and CODEVs, if these detection options are enabled.
Datasheet
21
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
ZEROV detection is enabled when the HDB3 encoders/decoders are enabled. This requires
CR1.ENCENB = 1, also CR1.EC3:1 = 000, which establishes E1 operation. To select ZEROV
detection, set bit CR4.ZEROV = 1.
2.5.4
Alarm Condition Monitoring
2.5.4.1
Loss of Signal
The LXT351 Loss of Signal (LOS) monitor function is compatible with ITU G.775 and ETSI
300233. The receiver LOS monitor loads a digital counter at the RCLK frequency. The count
increments with each received 0 and the counter resets to 0 on receipt of a 1. When the count
reaches “n” 0s, bit PSR.LOS is set to ‘1’, and the MCLK replaces the recovered clock at the RCLK
output in a smooth transition. For T1 operations, the number of 0s, n = 175, and for E1 operations,
n = 32. For both T1 and E1 operation, “n” can be set to 2048 by setting bit CR4.LOS2048 = 1.
For T1 operation, when the received signal has 12.5% 1s (16 marks in a sliding 128-bit period, with
fewer than 100 consecutive 0s), bit PSR.LOS = 0 and the recovered clock replaces MCLK at the
RCLK output in another smooth transition.
For E1 operation, the LOS condition is cleared when the received signal has 12.5% 1s density (four
1s in a sliding 32-bit window with fewer than 16 consecutive 0s). In E1 operation, the out-of-LOS
criterion can be modified from 12.5% marks density to 32 consecutive marks by setting bit
CR4.COL32CM = 1.
During LOS, the device sends received data to the RPOS/RNEG pins (or RDATA in Unipolar
mode). Bit PSR.LOS = 1 to indicate LOS condition, and can generate an interrupt to the host
controller if so programmed.
2.5.4.2
Alarm Indication Signal Detection
The receiver detects an AIS pattern when it receives fewer than three 0s in any string of 2048 bits.
The device clears the AIS condition when it receives three or more 0s in a string of 2048 bits.
The AIS bit in the Performance Status Register indicates AIS detection. Whenever the AIS status
changes, bit TSR.TAIS =1. Unless masked, a change of AIS status generates an interrupt.
2.5.4.3
Driver Failure Open Mode
The DFM Open (DFMO) bit is available in the Performance Status Register to indicate an open
condition on the lines. DFMO can generate an INT to the host controller. The Transition Status
Register bit TDFMO indicates a transition in the status of the bit. Writing a 1 to ICR.CDFMO will
clear or mask the interrupt.
2.5.4.4
Elastic Store Overflow/Underflow
When the bit count in the Elastic Store (ES) is within two bits of overflowing or underflowing the
ES adjusts the output clock by 1/8 of a bit period. The ES provides an indication of overflow and
underflow via bits TRS.ESOVR and TSR.ESUNF. These are sticky bits and will stay set to 1 until
the host controller reads the register. These interrupts can be cleared or masked by writing a 1 to the
bits ICR.CESO and ICR.CESU, respectively.
22
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
2.5.4.5
Built-In Self Test
LXT351 provides a Built-In Self Test (BIST) capability. The BIST exercises the internal circuits by
providing an internal QRSS pattern, running it through the encoders and the transmit drivers then
looping it back through the receive equalizer, jitter attenuator and decoders to the QRSS pattern
detection circuitry. If all the blocks in this data path function correctly, the receive pattern detector
locks onto the pattern. It then pulls INT Low and sets the following bits:
• TSR.TQRSS = 1
• PSR.QRSS = 1
• PSR.BIST = 1
Note that during BIST, the TPOS/TNEG inputs must remain at logic level = 0
The most reliable test will result when a separate TCLK and MCLK are applied.
2.6
Parallel Microprocessor Interface
The LXT351 multiplexed address/data bus and timing/control signals are compatible with both the
Intel and Motorola microprocessors. See Figure 16 and Figure 17 for the I/O timing diagram for
each bus. The LXT351 detects and distinguishes between Intel and Motorola timing and then
automatically selects the appropriate bus timing. The maximum recommended processor speed for
an Intel device is 20 MHz; for a Motorola device, 16.78 MHz. See “Test Specifications” on
page 33 for microprocessor interface timing details.
The LXT351 contains five read/write and two read-only registers for control and status purposes.
Table 6 on page 24 is a summary of the registers. Table 7 through Table 14 identify and explain the
function of the register bits.
2.6.1
Interrupt Handling
The LXT351 provides a latched interrupt output pin (INT). When enabled, a change in any of the
Performance Status Register bits will generate an interrupt. An interrupt can also be generated
when the elastic store overflows (TSR.ESOVR) or underflows (TSR.ESUNF). When an interrupt
occurs, the INT output pin is pulled Low. Note that the output stage of the INT pin has internal
pull-down only. Therefore, each device that shares the INT line requires an external pull-up
resistor.
The interrupt is cleared when the interrupt condition no longer exists, and the host processor writes
a 1 to the respective interrupt causing bit(s) in the Interrupt Clear Register (ICR). Leaving a 1 in
any of the ICR bits masks that interrupt. To re-enable an interrupt bit, write a 0.
Datasheet
23
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
3.0
Register Definitions
The LXT351 contains five read/write and two read-only registers that are accessible via the parallel
port. Table 5 lists the LXT351 register addresses. Only bits A6 through A1 of the address byte are
valid (the address decoder ignores bits A7 and A0) while A0 functions as the read/write (R/W) bit.
Table 6 identifies the name of each register bit. Table 7 through Table 14 describe the function of
the bits in each register.
Note that upon power-up or reset, all registers are cleared to 0.
Table 5.
Register Addresses
Register
Address1, 2
A7 - A1
Name
Abbr
Control #1
CR1
x010000
Control #2
CR2
x010001
Control #3
CR3
x010010
Interrupt Clear
ICR
x010011
Transition Status
TSR
x010100
Performance Status
PSR
x010101
Control #4
CR4
x010111
1. x = don’t care
2. Address A0 is the read/write (R/W) bit.
Table 6.
Register and Bit Summary
Register
Name
Control #1
Control #2
Control #3
CR1
CR2
CR3
Bit
Type
7
6
5
4
3
R/W
JASEL1
JASEL0
ENCENB
UNIENB
reserved1
R/W
R/W
RESET
JA6HZ
EPAT1
reserved
EPAT0
1
SBIST
ETAOS
EQZMON
2
1
0
EC3
EC2
EC1
reserved
1
EALOOP
ELLOOP
ERLOOP
reserved
1
ES64
ESCEN
ESJAM
2
CQRSS
CAIS
reserved
2
CLOS
Interrupt Clear
ICR
R/W
CESU
CESO
CDFMO
reserved
Transition
Status
TSR
R
ESUNF
ESOVR
TDFMO
reserved1
TQRSS
TAIS
reserved1
TLOS
Performance
Status
PSR
R
reserved1
BIST
DFMO
reserved1
QRSS
AIS
reserved1
LOS
Control #4
CR4
R/W
reserved1
reserved1
reserved1
reserved1
COL32CM
LOS2048
ZEROV
CODEV
1. In writable registers, bits labeled reserved should be set to 0 (except as in note 2 below) for normal operation and ignored in
read only registers.
2. Write a 1 to this bit for normal operation.
24
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Table 7.
Control Register #1 Read/Write, Address (A7-A0) = x010000x
Jitter Attenuator
Bit
Name
0
Function
JASEL0
JASEL1
Position
1
0
Transmit
1
1
Receive
0
X
Disabled
EC1
Sets mode (T1 or E1) and equalizer
(see Table 8 below for control codes).
1
EC2
2
EC3
3
-
4
UNIENB
5
ENCENB
Reserved, set this bit to 0, ignore when reading.
1 = Enable Unipolar I/O mode and allow insertion/detection of BPVs.
0 = Enable Bipolar I/O mode
1 = Enable B8ZS/HDB3 encoders/decoders and force Unipolar I/O
mode.
0 = Disable B8ZS/HDB3 encoders/decoders
6
JASEL0
7
JASEL1
Table 8.
Select jitter attenuation circuitry position in data path or disables the
JA. See right hand section of table for codes.
Ñ
Equalizer Control Input Settings
EC3
EC2
EC1
Function
Pulse
Cable
Coding1
0
0
0
E1
ITU Rec G.703
75 Ω Coax/120 Ω TP
HDB3
0
1
1
T1
0-133 ft / 0.6 dB
100 Ω TP
B8ZS
1
0
0
T1
133-266 ft / 1.2 dB
100 Ω TP
B8ZS
1
0
1
T1
266-399 ft / 1.8 dB
100 Ω TP
B8ZS
1
1
0
T1
399-533 ft / 2.4 dB
100 Ω TP
B8ZS
1
1
1
T1
533-655 ft / 3.0 dB
100 Ω TP
B8ZS
1. When enabled.
Table 9.
Control Register #2 Read/Write, Address (A7-A0) = x010001x
Pattern
Bit
Name
0
ERLOOP1
1
ELLOOP1
2
EALOOP
3
-
Function
1 = Enable Remote loopback mode
0 = Disable Remote loopback mode
1 = Enable Local loopback mode
0 = Disable Local loopback mode
1 = Enable Analog loopback mode
0 = Disable Analog loopback mode
Reserved, set to 0, ignore when reading.
EPAT0
EPAT1
Selected
0
0
Transmit TPOS/TNEG
0
1
Detect and transmit QRSS
1
0
In-band Loop Up Code
00001
1
1
In-band Loop Down Code
001
1. To enable Dual loopback (DLOOP), set both ERLOOP = 1 and ELLOOP = 1.
Datasheet
25
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 9.
Control Register #2 Read/Write, Address (A7-A0) = x010001x
Pattern
Bit
Name
Function
EPAT0
4
ETAOS
5
EPAT0
6
EPAT1
7
RESET
EPAT1
Selected
1 = Enable Transmit All Ones
0 = Disable Transmit All Ones
Selects internal data pattern transmission. See
right hand section of table for codes.
Ñ
1 = Reset device states and clear all registers.
0 = Reset complete.
1. To enable Dual loopback (DLOOP), set both ERLOOP = 1 and ELLOOP = 1.
Table 10. Control Register #3 Read/Write, Address (A7-A0) = x010010x
Bit
Name
0
ESJAM
1
ESCEN
2
ES64
3
-
4
EQZMON
5
SBIST
6
-
7
JA6HZ
Description
1 = Disable jamming of Elastic Store read out clock (1/8 bit-time adjustment for over/underflow).
0 = Enable jamming of Elastic Store read out clock
1 = Center ES pointer for a difference of 16 or 32, depending on depth (clears automatically).
0 = Centering completed
1 = Set elastic store depth to 64 bits.
0 = Set elastic store depth to 32 bits.
Reserved. Set to 0 for normal operation.
1 = Configure receiver equalizer for monitor mode application (DSX-1 monitor).
0 = Configure receiver equalizer for normal mode application
1 = Start Built-In Self Test.
0 = Built-In Self Test complete.
Reserved. Set to 0 for normal operation.
1 = Set bandwidth of jitter attenuation loop to 6 Hz.
0 = Set bandwidth of jitter attenuation loop to 3 Hz.
Table 11. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit
Name
0
CLOS
1
-
2
CAIS
3
CQRSS
4
-
Function1
1 = Clear/Mask Loss of Signal interrupt.
0 = Enable Loss of Signal interrupt.
Reserved. Set to 1 for normal operation.
1 = Clear/Mask Alarm Indication Signal interrupt.
0 = Enable Alarm Indication Signal interrupt.
1 = Clear/Mask Quasi-Random Signal Source interrupt.
0 = Enable Quasi-Random Signal Source interrupt.
Reserved. Set to 1 for normal operation.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
26
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Table 11. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit
Name
5
CDFMO
6
CESO
7
CESU
Function1
1 = Clear/Mask Driver Failure Monitor Open interrupt.
0 = Enable Driver Failure Monitor Open interrupt.
1 = Clear/Mask Elastic Store Overflow interrupt.
0 = Enable Elastic Store Overflow interrupt.
1 = Clear/Mask Elastic Store Underflow interrupt.
0 = Enable Elastic Store Underflow interrupt.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
Table 12. Transition Status Register Read Only, Address (A7-A0) = x010100x
Bit
Name
0
TLOS
1
-
2
TAIS
3
TQRSS
4
-
5
TDFMO
6
ESOVR
7
ESUNF
Function
1 = Loss of Signal (LOS) has changed since last clear LOS interrupt occurred.
0 = No change in status.
Reserved. Ignore.
1 = AIS has changed since last clear AIS interrupt occurred.
0 = No change in status.
1 = QRSS has changed since last clear QRSS interrupt occurred1.
0 = No change in status.
Reserved. Ignore.
1 = DFMO has changed since last clear DFMS interrupt occurred.
0 = No change in status.
1 = ES overflow status sticky bit2.
0 = No change in status.
1 = ES underflow status sticky bit2.
0 = No change in status.
1. A QRSS transition indicates receive QRSS pattern sync or loss. A simple error in QRSS pattern is not reported as a
transition.
2. Tripping the overflow or underflow indicator in the ES sets the ESOVR/ESUNF status bit(s). Reading the Transition Status
Register clears these bits. Setting CESO and CESU in the Interrupt Clear Register masks these interrupts.
Table 13. Performance Status Register Read Only, Address (A7-A0) = x010101x
Bit
Name
0
LOS
1
-
2
AIS
3
QRSS
4
-
Datasheet
Function
1 = Loss of Signal occurred.
0 = Loss of Signal did not occur.
Reserved. Ignore.
1 = Alarm Indicator Signal detected.
0 = Alarm Indicator Signal not detected.
1 = Quasi-Random Signal Source pattern detected.
0 = Quasi-Random Signal Source pattern not detected.
Reserved. Ignore.
27
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 13. Performance Status Register Read Only, Address (A7-A0) = x010101x
Bit
Name
5
DFMO
6
BIST
7
-
Function
1 = Driver Failure Monitor Open detected.
0 = Driver Failure Monitor Open not detected.
1 = Built-In Self Test passed.
0 = Built-In Self Test did not pass (or was not run).
Reserved. Ignore.
Table 14. Control Register #4 Read/Write, Address (A7-A0) = x010111x
Bit
Name
Function
0
CODEV
1 = Enable detection of HDB3 code violations at the BPV pin along with bipolar violations and Zero
Substitution Violations (if enabled).
0 = Disable detection of HDB3 code violations
1
ZEROV
1 = Enable detection of HDB3 Zero Substitution Violations (four consecutive zeros). Note that Zero
Substitution Violations are reported at the BPV pin.
0 = Disable detection of HDB3 Zero Substitution Violations.
1 = Set LOS detection threshold to 2048 consecutive zeros.
28
2
LOS2048
3
COL32CM
4
-
Reserved. Set to 0 for normal operation, ignore when reading
5
-
Reserved. Set to 0 for normal operation, ignore when reading
6
-
Reserved. Set to 0 for normal operation, ignore when reading
7
-
Reserved. Set to 0 for normal operation, ignore when reading
0 = Set LOS detection threshold to 32 consecutive zeros (for E1 operation) or to 175 consecutive
zeros (for T1 operation).
1 = Set LOS clear condition criterion to receipt of 32 consecutive marks (E1 operation).
0 = Set LOS clear condition criterion to 12.5% mark density (E1 operation).
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
4.0
Application Information
4.1
Transmit Return Loss
Table 15 shows the specification for transmit return loss in E1 applications. The G.703/CH PTT
specification is a Swiss Telecommunications Ministry specification.
Table 16 and Table 17 show the transmit return loss values for E1 and T1 applications.
4.2
Transformer Data
Specifications for transformers are listed in Table 18. A list of transformers recommended for use
with the LXT351 are specified in Table 19.
4.3
Application Circuit
Figure 11 shows a typical LXT351 application.
4.4
Line Protection
On the receive side, 1 kΩ series resistors protect the receiver against current surges coupled into
the device. Due to the high receiver impedance (40 kΩ typical) the resistors do not affect the
receiver sensitivity. On the transmit side, Schottky diodes D1-D4 protect the output driver. While
not mandatory for normal operation, these protection elements are strongly recommended to
improve the design robustness
Table 15. E1 Transmit Return Loss Requirements
Return Loss
Frequency Band
Datasheet
ETS 300 166
G.703/CH PTT
51-102 kHz
6 dB
8 dB
102-2048 kHz
8 dB
14 dB
2048 - 3072 kHz
8 dB
10 dB
29
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 16. Transmit Return Loss (2.048 Mbps)
EC3-1
Xfrmr/Rt
R L (Ω )
CL (pF)
Return Loss
(dB)
0
14
470
16
0
12
470
13
0
13
470
16
75
1:2/
9.1 Ω
000
120
1:2.3/9.1
Ω
120
Table 17. Transmit Return Loss (1.544 Mbps)
EC3-1
Xfrmr/Rt
RL ( Ω)
1:2/
9.1 Ω
100
0112
1
1:1.15 /
0.0 Ω
CL (pF)
Return Loss
(dB)
0
16
470
17
0
2
470
2
100
1. A 1:1.15 transmit transformer keeps the total transceiver
power dissipation at a low level, a 0.47 µF DC blocking
capacitor must be placed on TTIP or TRING.
2. Refer to Table 8.
Table 18. Transformer Specifications
Tx/Rx
Tx
Rx
Frequency
MHz
Turns
Ratio
Primary
Inductance
µH (minimum)
Leakage
Inductance
µH
(max)
Interwinding
Capacitance
pF
(max)
1.544
1:1.15
600
0.80
60
2.048
1:2.3
600
0.80
60
1.544/2.048
1:2
600
0.80
1.544/2.048
1:1
600
1.10
DCR
Ω
(maximum)
0.90 pri
1.70 sec
Dielectric1
Breakdown
V
(minimum)
1500 VRMS
1.20 sec
1500 VRMS2
(3000 VRMS)
60
1.0 pri
1.70 sec
1500 VRMS2
(3000 VRMS)
60
1.10 pri
1.10 sec
1500 VRMS2
(3000 VRMS)
0.70 pri
1. Some ETSI applications may require a 2.3 kV dielectric breakdown voltage.
2. Some applications require transformers to guarantee performance in extended temperature range (-40° to +85° C) ETSI
applications require a dielectric breakdown voltage of 3000 VRMS.
30
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Table 19. Recommended Transformers
Tx/Rx
Turns Ratio
Part Number
Manufacturer
PE-65388
Pulse Engineering
1:1.15
PE-65770
16Z5952
Vitec
PE-65351
Pulse Engineering
PE-65771
0553-5006-IC
Tx
Bell-Fuse
66Z-1308
Fil-Mag
671-5832
Midcom
67127370
1:2
1:2.3
Schott Corp
67130850
TD61-1205D
HALO (combination Tx/Rx set)
TG26-1205NI
HALO (surface mount dual transformer 1CT:2CT
& 1CT:2CT)
TG48-1205NI
HALO (surface mount dual transformer 1CT:2CT
& 1:1)
16Z5946
Vitec
PE-65558
Pulse Engineering
FE 8006-155
Fil-Mag
671-5792
Midcom
PE-64936
Pulse Engineering
Rx
1:1
PE-65778
67130840
Schott Corp
67109510
TD61-1205D
4.4.1
HALO (combination Tx/Rx set)
LXT351 Application Circuit
Figure 11 shows a typical application using the LXT351. See Table 16 and Table 17 to select the
transformers (T1 and T2), resistors (Rt and RL) and capacitors (CL) needed for this application.
Note:
Datasheet
If the application includes surge protection, such as a varistor or sidactor on the TTIP/TRING lines,
it may also require reducing the value of the capacitor CL or eliminating it completely.
31
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 11. Typical T1/E1 LXT351 Application
VCC
22 kΩ
2.048 MHz/
1.544 MHz
MCLK
INT
ALE/AS
TCLK
RD/DS
TCLK
TPOS
TPOS
T1/E1 TNEG
Framer
TNEG
RCLK
RCLK
RPOS
RPOS
RNEG
RNEG
µP
(Intel or
Motorola)
WR/R/W
CS
LXT351
AD0-7
TTIP
1:21
Rt1
CL1
TVCC
VCC
0.1 µF
68 µF
TRING
Rt1
RTIP
TGND
RL2
GND
RRING
1:1
NOTES:
1. See Table 16 and Table 17 for CL, Rt and Transformer selection.
2. RL = 100 Ω for T1
RL = 120 Ω for E1/120 Ω twisted pair
RL = 75 Ω for E1/75 Ω coax
32
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
5.0
Test Specifications
Note:
Table 20 through Table 31 and Figure 12 through Figure 21 represent the performance
specifications of the LXT350/351 and are guaranteed by test except, where noted, by design. The
minimum and maximum values listed in Table 22 through Table 31 are guaranteed over the
recommended operating conditions specified in Table 21.
Table 20. Absolute Maximum Ratings
Parameter
DC supply (reference to GND)
Sym
Min
Max
Unit
VCC, TVCC
–
6.0
V
Input voltage, any pin
1
VIN
GND - 0.3 V
VCC + 0.3 V
V
Input current, any pin
2
IIN
- 10
10
mA
TSTG
-65
150
°C
Storage Temperature
Caution: Exceeding these values may cause permanent damage.
Caution: Functional operation under these conditions is not implied.
Caution: Exposure to maximum rating conditions for extended periods may affect device reliability.
1. TVCC and VCC must not differ by more than 0.3 V during operation. TGND and GND must not differ by more than 0.3 V
during operation.
2. Transient currents of up to 100 mA will not cause SCR latch-up. TTIP, TRING, TVCC, and TGND can withstand continuous
currents of up to 100 mA.
Table 21. Recommended Operating Conditions
Parameter
DC supply 2
Ambient operating temperature
Sym
Min
Typ1
Max
Unit
VCC,TVCC
4.75
5.0
5.25
V
TA
- 40
25
85
°C
PD
–
310
380
mW
100% mark density
PD
–
225
295
mW
50% mark density
PD
–
275
330
mW
100% mark density
PD
–
215
270
mW
50% mark density
Test Conditions
T1
Total power dissipation3
E1
1. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. TVCC and VCC must not differ by more than 0.3 V.
3. Power dissipation while driving 75 Ω load over operating range for T1 operation or 60 Ω load for E1 operation. Includes
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacitive load.
Datasheet
33
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 22. DC Electrical Characteristics
Parameter
Sym
Min
Typ1
Max
Unit
Test Conditions
Digital I/O pins
High level input voltage 2 (pins 1-5, 9-12, 17, 23-28)3
Low level input voltage
2
VIH
2.0
–
–
V
3
VIL
–
–
0.8
V
2
3
VOH
2.4
–
–
V
IOUT = -400 µA
2
3
VOL
–
–
0.4
V
IOUT = 1.6 mA
ILL
–
–
±10
µA
(pins 1-5, 9-12, 17, 23-28)
High level output voltage (pins 6-8, 10, 11,23, 28)
Low level output voltage (pins 6-8, 10, 11,23, 28)
Input leakage current
1. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Output drivers will output CMOS logic levels into CMOS loads.
3. Listed pins are for the PLCC package. Refer to “Pin Assignments and Signal Descriptions” on page 8 for the 44-pin QFP
package.
Table 23. Analog Characteristics
Min
Typ1
Max
Unit
50
–
200
Ω
T1
2.4
3.0
3.6
V
RL = 100 Ω
E1
2.7
3.0
3.3
V
RL = 120 Ω
Parameter
Recommended output load on TTIP/TRING
AMI output pulse amplitudes
10 Hz - 8 kHz
Jitter added by the
transmitter2
3
–
–
0.02
UI
8 kHz - 40 kHz
3
–
–
0.025
UI
10 Hz - 40 kHz
3
–
–
0.025
UI
–
–
0.05
UI
0
–
18
dB
160
175
190
–
Broad Band
Receiver sensitivity
Allowable consecutive zeros before LOS (T1)
Allowable consecutive zeros before LOS (E1)
Test Conditions
@ 1024 kHz
1.431
–
32
–
–
10 kHz - 100 kHz
0.4
–
–
UI
1 Hz3
138
–
–
UI
10 kHz - 100 kHz
0.2
–
–
UI
37
–
–
UI
0 dB line
ITU (G.823)
Jitter attenuation curve corner frequency 4
–
3
–
Hz
selectable in data port
Driver output impedance
–
3
–
Ω
–
40
–
kΩ
20
22
–
dB
20
28
–
dB
25
30
–
dB
Input jitter tolerance (T1)
Input jitter tolerance (E1)
1 Hz
3
Receiver input impedance
51 kHz - 102 kHz
Receive return loss (E1)
3
102 kHz - 2.048 MHz3
3
2.048 MHz - 3.072 MHz
1.
2.
3.
4.
34
0 dB line
AT&T Pub 62411
RTIP to RRING
Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Input signal to TCLK is jitter-free. The Jitter Attenuator is in the receive path or disabled.
Guaranteed by characterization; not subject to production testing.
Circuit attenuates jitter at 20 dB/decade above the corner frequency.
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Figure 12. 2.048 Mbps E1 Pulse (See Table 24)
20%
345 ns
20%
V = 100%
10% 10%
478 ns
NOMINAL PULSE
50%
434 ns
10% 10%
0%
10% 10%
390 ns
20%
870 ns
Table 24. 2.048 Mbps E1 Pulse Mask Specifications
Parameter
TPW
Coax
Unit
Test load impedance
120
75
Ω
Nominal peak mark voltage
3.0
2.37
V
Nominal peak space voltage
0 ±0.30
0 ±0.237
V
244
244
ns
Ratio of positive and negative pulse amplitudes at center of pulse
95-105
95-105
%
Ratio of positive and negative pulse amplitudes at nominal half amplitude
95-105
95-105
%
Nominal pulse width
Datasheet
35
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 13. 1.544 Mbps T1 Pulse, DSX-1 (See Table 25)
1.5
Normalized Amplitude
1.0
0.5
0.5
-0.5
0.0
1.0
1.5
Time
(in Unit Intervals)
-0.5
0
Table 25. 1.544 Mbps T1, DSX-1 Pulse Mask Corner Point Specifications
DSX-1 Template (per ANSI T1. 102-1993)
Minimum Curve
36
Maximum Curve
Time (UI)
Amplitude
Time (UI)
Amplitude
-0.77
-0.05
-0.77
0.05
-0.23
-0.05
-0.39
0.05
-0.23
0.50
-0.27
0.80
-0.15
0.95
-0.27
1.15
0.0
0.95
-0.12
1.15
0.15
0.90
0.0
1.05
0.23
0.50
0.27
1.05
0.23
-0.45
0.35
-0.07
0.46
-0.45
0.93
0.05
0.66
-0.20
1.16
0.05
0.93
-0.05
-
-
1.16
-0.05
-
-
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Table 26. Master and Transmit Clock Timing Characteristics for T1 Operation
(See Figure 14)
Sym
Min
Typ1
Max
Unit
Master clock frequency
MCLK
–
1.544
–
MHz
Master clock tolerance
MCLKt
–
±32
–
ppm
Master clock duty cycle
MCLKd
40
–
60
%
Transmit clock frequency
TCLK
–
1.544
–
MHz
Transmit clock tolerance
TCLKt
–
–
±100
ppm
Transmit clock duty cycle
TCLKd
10
–
90
%
TPOS/TNEG to TCLK setup time
tSUT
50
–
–
ns
TCLK to TPOS/TNEG hold time
tHT
50
–
–
ns
Parameter
Notes
must be supplied
1. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Table 27. Master and Transmit Clock Timing Characteristics for E1 Operation
(See Figure 14)
Sym
Min
Typ1
Max
Unit
Master clock frequency
MCLK
–
2.048
–
MHz
Master clock tolerance
MCLKt
–
±32
–
ppm
Master clock duty cycle
Parameter
MCLKd
40
–
60
%
Transmit clock frequency
TCLK
–
2.048
–
MHz
Transmit clock tolerance
TCLKt
–
–
±100
ppm
Transmit clock duty cycle
TCLKd
10
–
90
%
TPOS/TNEG to TCLK setup time
tSUT
50
–
–
ns
TCLK to TPOS/TNEG hold time
tHT
50
–
–
ns
Notes
must be supplied
1. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Figure 14. Transmit Clock Timing
Datasheet
37
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 28. Receive Timing Characteristics for T1 Operation (See Figure 15)
Typ1
Max
40
50
60
%
–
648
–
ns
tPWH
–
324
–
ns
tPWL
260
324
388
ns
RPOS/RNEG to RCLK rise time
tSUR
–
274
–
ns
RCLK rise to RPOS/RNEG hold time
tHR
–
274
–
ns
Parameter
Sym
Min
Receive clock duty cycle 2, 3
RLCKd
Receive clock pulse width 2, 3
tPW
Receive clock pulse width High
Receive clock pulse width Low
1,3
Unit
1. Typical s are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions.
3. Worst case conditions guaranteed by design only.
Table 29. Receive Timing Characteristics for E1 Operation (See Figure 15)
Parameter
Receive clock duty cycle
2, 3
2, 3
Sym
Min
Typ1
Max
Unit
RLCKd
40
50
60
%
tPW
–
488
–
ns
tPWH
–
244
–
ns
tPWL
195
244
293
ns
RPOS/RNEG to RCLK rise time
tSUR
–
194
–
ns
RCLK rise to RPOS/RNEG hold time
tHR
–
194
–
ns
Receive clock pulse width
Receive clock pulse width High
Receive clock pulse width Low
1,3
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min. RCLK duty cycles
are for worst case jitter conditions (0.4 UI clock displacement for 1.544 MHz).
3. Worst case conditions guaranteed by design only.
Figure 15. Receive Clock Timing
38
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Table 30. 20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 16)
Parameter
Sym
Min
Max
Unit
ALE pulse width
TLHLL
35
–
ns
Address valid to ALE falling edge
TAVLL
10
–
ns
ALE falling edge to address hold time
TLLAX
10
–
ns
ALE falling edge to RD falling edge
TLLRL
10
–
ns
ALE falling edge to WR falling edge
TLLWL
10
–
ns
CS falling edge to RD falling edge
TCLRL
10
–
ns
CS falling edge to WR falling edge
TCLWL
10
–
ns
RD Low pulse width
TRLRH
95
–
ns
RD falling edge to data valid
TRLDV
10
55
ns
Data hold time after RD rising edge
TRHDX
5
35
ns
RD rising edge to ALE rising edge
TRHLH
15
–
ns
RD rising edge to address valid
TRHAV
35
–
ns
CS Low hold time after RD rising edge
TRHCH
0
–
ns
WR Low pulse width
TWLWH
95
–
ns
Data setup time before WR rising edge
TDVWH
40
–
ns
Data hold time after WR rising edge
TWHDX
30
–
ns
WR rising edge to ALE rising edge
TWHLH
15
–
ns
CS Low hold time after WR rising edge
TWHCH
15
–
ns
Datasheet
Test Conditions
39
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 16. Intel Address/Data Bus Timing
0ns
50ns
100ns
150ns
TCLWL
TCLRL
CS
200ns
TWHCH
TRHCH
TLLRL
TLLWL
TLHLL
TLLAX
TRHLH
TWHLH
ALE
TAVLL
TRLRH
RD
TRHAV
TRHDX
TRLDV
AD0-7_R
TWLWH
TDVWH
WR
TWHDX
AD0-7_W
Table 31. 16.78 MHz Motorola Bus Parallel I/O Timing Characteristics (See Figure 17)
Parameter
Sym
Min
Max
Unit
DS rising edge to AS rising edge
TDSHASH
15
–
ns
AS High pulse width
TASHASL
35
–
ns
Address valid setup time at AS falling edge
TAVASL
10
–
ns
AS falling edge to Address valid hold time
Taslax
10
–
ns
AS falling edge to DS falling edge
TASLDSL
20
–
ns
CS falling edge to DS falling edge
TCSLDSL
10
–
ns
DS Low pulse width
TDSLDSH
95
–
ns
DS falling edge to data valid
TDSLDV
10
55
ns
Data hold time after DS rising edge
TDSHDX
5
35
ns
R/W falling edge to DS falling edge
TRWLDSL
10
–
ns
Data setup time before DS rising edge
TDVDSH
40
–
ns
Data hold time after DS rising edge
Tdxdsh
30
–
ns
R/W Low hold time after DS rising edge
TDSHRWH
15
–
ns
CS Low hold time after DS rising edge
TDSHCSH
15
–
ns
40
Test Conditions
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Figure 17. Motorola Address/Data Bus Timing
TCSLDSL
CS
TASHASL
TAVASL
AS
TDSHCSH
TASLDSL
TASLAX
TDSHASH
TDXDSH
TDSLDSH
TRWLDSL
DS
TDVDSH
TDSHRWH
R/W_Read
TDSHDX
TDSLDV
AD0-7_Read
R/W_Write
AD0-7_Write
Figure 18. Typical T1 Jitter Tolerance at 36 dB
1000 UI
Jitter
500 UI
@ 10 Hz
LXT351 Device
Typical Jitter Tolerance
Loop Mode
138 UI
100 UI
Pub 62411
28 UI
Dec 1990
10 UI
0.6 UI
@ 10 kHz
1 UI
0.4 UI
.1 UI
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
Datasheet
41
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 19. Typical E1 Jitter Tolerance at 43 dB
42
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Figure 20. Typical E1 Jitter Attenuation
Datasheet
43
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 21. Typical T1 Jitter Attenuation
44
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
6.0
Mechanical Specifications
Figure 22. Plastic Leaded Chip Carrier Package Specifications
28-Pin PLCC
• Part Number LXT351PE
• Extended Temperature Range (-40 °C to 85 °C)
CL
C
B
D1
D
D
A2
A
A1
F
Inches
Millimeters
Dim
Min
Max
Min
Max
A
0.165
0.180
4.191
4.572
A1
0.090
0.120
2.286
3.048
A2
0.062
0.083
1.575
2.108
B
.050 BSC1 (nominal)
1.27 BSC1 (nominal)
C
0.026
0.032
0.660
0.813
D
0.485
0.495
12.319
12.573
D1
0.450
0.456
11.430
11.582
F
0.013
0.021
0.330
0.533
1. BSC—Basic Spacing between Centers.
Datasheet
45
LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 23. Plastic Quad Flat Package Specifications
44-Pin PQFP
• Part Number LXT351QE
• Extended Temperature Range (-40 °C to 85 °C)
D
D1
D3
e
E1
E3
E
θ3
L1
A2
A
θ
A1
θ3
B
L
Inches
Millimeters
Dim
Min
Max
Min
Max
A
–
0.096
–
2.45
A1
0.010
–
0.25
–
A2
0.077
0.083
1.95
2.10
B
0.012
0.018
0.30
0.45
D
0.510
0.530
12.95
13.45
D1
0.390
0.398
9.90
10.10
D3
0.315 BSC1 (nominal)
8.00 BSC1 (nominal)
0.510
0.530
12.95
13.45
E1
0.390
0.398
9.90
10.10
E3
0.315 BSC1 (nominal)
8.00 BSC1 (nominal)
e
0.031 BSC1 (nominal)
0.80 BSC1 (nominal)
L
0.029
0.73
E
L1
0.041
1
0.063 BSC (nominal)
1.03
1
1.60 BSC (nominal)
q3
5°
16°
5°
16°
q
0°
7°
0°
7°
1. BSC—Basic Spacing between Centers.
46
Datasheet