AMIC A615308V-12 32k x 8 bit high speed cmos sram Datasheet

A615308 Series
Preliminary
32K X 8 BIT HIGH SPEED CMOS SRAM
Document Title
32K X 8 BIT HIGH SPEED CMOS SRAM
Revision History
Rev. No.
0.0
PRELIMINARY
History
Issue Date
Initial issue
January 17, 2001
(January, 2001, Version 0.0)
Remark
AMIC Technology, Inc.
A615308 Series
Preliminary
32K X 8 BIT HIGH SPEED CMOS SRAM
Features
n
n
n
n
n Single +5V power supply
n Access times: 12 ns (max.)
n Current: Operating: 150mA (max.)
Standby:
12mA (max.)
n Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL compatible
Common I/O using three-state output
Data retention voltage: 2V (min.)
Available in 28-pin SOJ and TSOP packages
General Description
The A615308 is a high-speed 262,144-bit static random
access memory organized as 32,768 words by 8 bits and
operates on a single 5V power supply. It is built using
high performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Minimum standby power is drawn by this device when
CE is at a high level, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n SOJ
2
WE
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CE
A0
10
19
I/O 7
I/O0
11
18
I/O 6
I/O1
12
17
I/O 5
I/O2
13
16
I/O 4
GND
14
15
I/O 3
(January, 2001, Version 0.0)
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A615308V
~
~
VCC
27
~
~
28
A615308S
1
A12
A14
PRELIMINARY
n TSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
GND
I/O 2
I/O 1
I/O 0
A0
A1
A2
AMIC Technology, Inc.
A615308 Series
Block Diagram
VCC
A0
GND
ROW
512 X 512
DECODER
MEMORY ARRAY
INPUT DATA
CIRCUIT
COLUMN I/O
A12
A13
A14
I/O0
I/O7
CE
OE
CONTROL
CIRCUIT
WE
Pin Description - SOJ
Pin Description - TSOP
Pin No.
Symbol
1 - 10, 21,
23 - 26
A0 - A14
Address Inputs
11 - 13, 15 - 19
I/O0 - I/O7
Data Inputs/Outputs
20
CE
Chip Enable
22
OE
Output Enable
27
WE
Write Enable
28
VCC
Power Supply
14
GND
Ground
PRELIMINARY
Description
(January, 2001, Version 0.0)
2
Pin No.
Symbol
Description
2 - 5, 8 - 17, 28
A0 - A14
Address Inputs
18 - 20, 22 - 26
I/O0 - I/O7
Data Inputs/Outputs
27
CE
Chip Enable
1
OE
Output Enable
6
WE
Write Enable
7
VCC
Power Supply
21
GND
Ground
AMIC Technology, Inc.
A615308 Series
Recommended DC Operating Conditions
(TA = 0°C to + 70°C)
Symbol
Parameter
VCC
Supply Voltage
GND
Ground
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
VIH
Input High Voltage
2.2
3.5
VCC + 0.5
V
VIL
Input Low (1) Voltage
-0.5
0
+0.8
V
CL
Output Load
-
-
30
pF
Absolute Maximum Ratings*
*Comments
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C
Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C
Temperature Under Bias, Tbias . . . . . . . . -10°C to +85°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics
Symbol
(TA = 0°C to + 70°C, VCC = 5V ± 10%, GND = 0V)
A615308-12
Parameter
Unit
Min.
Max.
Conditions
ILI
Input Leakage
-
2
µA
VIN = GND to VCC
ILO
Output Leakage
-
2
µA
CE = VIH or OE = VIH
VI/O = GND to VCC
Dynamic Operating
Current
-
150
mA
CE = VIL, II/O = 0 mA
Min. Cycle, Duty = 100%
-
35
mA
CE = VIH
ISB1
Standby Power
Supply Current
-
12
mA
CE ≥ VCC - 0.2V
VIN ≥ VCC -0.2V or
VIN ≤ 0.2V
VOL
Output Low Voltage
-
0.4
V
IOL = 8 mA
VOH
Output High Voltage
2.4
-
V
IOH = -4 mA
ICC1 (2)
ISB
Notes: 1. VIL = -3.0V for pulses less than 20 ns.
2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
PRELIMINARY
(January, 2001, Version 0.0)
3
AMIC Technology, Inc.
A615308 Series
Truth Table
Mode
I/O Operation
Supply Current
CE
OE
WE
Standby
H
X
X
High Z
ISB, ISB1
Output Disable
L
H
H
High Z
ICC1
Read
L
L
H
DOUT
ICC1
Write
L
X
L
DIN
ICC1
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CIN*
Input Capacitance
-
10
pF
VIN = 0V
CI/O*
Input/Output Capacitance
-
10
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0°C to +70°C, VCC = 5V ± 10%)
Symbol
A615308-12
Parameter
Unit
Min.
Max.
12
-
ns
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
-
12
ns
tACE
Chip Enable Access Time
-
12
ns
tOE
Output Enable to Output Valid
-
6
ns
tCLZ
Chip Enable to Output in Low Z
3
-
ns
tOLZ
Output Enable to Output in Low Z
0
-
ns
tCHZ
Chip Disable Output in High Z
0
6
ns
tOHZ
Output Disable to Output in High Z
0
6
ns
tOH
Output Hold from Address Change
3
-
ns
PRELIMINARY
(January, 2001, Version 0.0)
4
AMIC Technology, Inc.
A615308 Series
AC Characteristics (continued)
Symbol
A615308-12
Parameter
Unit
Min.
Max.
Write Cycle
tWC
Write Cycle Time
12
-
ns
tCW
Chip Enable to End of Write
10
-
ns
tAS
Address Setup Time of Write
0
-
ns
tAW
Address Valid to End of Write
10
-
ns
tWP
Write Pulse Width
10
-
ns
tWR
Write Recovery Time
0
-
ns
tWHZ
Write to Output in High Z
0
6
ns
tDW
Data to Write Time Overlap
6
-
ns
tDH
Data Hold from Write Time
0
-
ns
tOW
Output Active from End of Write
3
-
ns
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levles.
Timing Waveforms
Read Cycle 1(1)
tRC
Address
tAA
OE
tOE
tOH
tOLZ5
CE
tOHZ5
tCHZ5
tACE
tCLZ5
DOUT
PRELIMINARY
(January, 2001, Version 0.0)
5
AMIC Technology, Inc.
A615308 Series
Timing Waveforms (continued)
Read Cycle 2(1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 3(1, 3, 4,)
CE
tACE
tCLZ5
tCHZ5
DOUT
Notes: 1.
2.
3.
4.
5.
WE is high for Read Cycle.
Device is continuously enabled, CE = VIL.
Address valid prior to or coincident with CE transition low.
OE = VIL.
Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(January, 2001, Version 0.0)
6
AMIC Technology, Inc.
A615308 Series
Timing Waveforms (continued)
Write Cycle 1(6)
(Write Enable Controlled)
tWC
Address
tAW
tWR 3
tCW 5
CE
(4)
tAS1
tWP 2
WE
tDW
tDH
DIN
tWHZ 7
tOW 7
DOUT
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
tAW
tAS1
CE
tWR3
tCW5
(4)
tWP2
WE
tDW
tDH
DIN
tWHZ 7
DOUT
Notes: 1.
2.
3.
4.
tAS is measured from the address valid to the beginning of Write.
A Write occurs during the overlap (tWP) of a low CE and a low WE .
tWR is measured from the earliest of CE or WE going high to the end of the Write cycle
If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(January, 2001, Version 0.0)
7
AMIC Technology, Inc.
A615308 Series
AC Test Conditions
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Time
2 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 1 and 2
5V
5V
480Ω
480Ω
DATAOUT
DATA OUT
30pF
255Ω
255Ω
5pF*
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol
VDR
Parameter
VCC for Data Retention
Min.
Max.
Unit
2
5.5
V
ICCDR
Data Retention Current
-
1
mA
tCDR
Chip Disable to Data Retention
Time
0
-
ns
tR
Operation Recovery Time
Conditions
CE ≥ VCC - 0.2V
VCC = 2.0V
CE ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
See Retention Waveform
tRC*
-
ns
tRC = Read Cycle Time
PRELIMINARY
(January, 2001, Version 0.0)
8
AMIC Technology, Inc.
A615308 Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
4.5V
VCC
4.5V
tCDR
tR
VDR ≥ 2.0V
VIH
VIH
CE
CE ≥ VDR - 0.2V
Ordering Information
Access Time (ns)
Operating Current
Max. (mA)
Standby Current
Max. (mA)
A615308S-12
12
150
12
28L SOJ
A615308V-12
12
150
12
28L TSOP
Part No.
PRELIMINARY
(January, 2001, Version 0.0)
9
Package
AMIC Technology, Inc.
A615308 Series
Package Information
SOJ 28L Outline Dimensions
15
1
14
E
28
HE
unit: inches/mm
L
A
A2
C
D
A1
e
D
b
b1
S
Seating Plane
Symbol
e1
y
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.140
-
-
3.56
A1
0.027
-
-
0.69
-
-
A2
0.095
0.100
0.105
2.41
2.54
2.67
b1
0.028 TYP
0.71 TYP
b
0.018 TYP
0.46 TYP
C
0.010 TYP
0.25 TYP
D
-
0.710
0.730
-
18.03
18.54
E
0.295
0.300
0.305
7.49
7.62
7.75
e
0.050 BSC
1.27 BSC
e1
0.255
0.265
0.275
6.48
6.73
6.99
HE
0.329
0.337
0.345
8.36
8.56
8.76
L
0.077
0.087
0.097
1.96
2.21
2.46
S
-
-
0.045
-
-
1.14
y
-
-
0.004
-
-
0.10
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY
(January, 2001, Version 0.0)
10
AMIC Technology, Inc.
A615308 Series
Package Information
TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
D1
Detail "A"
28
A1
E
c
A
A2
1
e
θ
14
L
15
D
D
Detail "A"
y
S
Dimensions in inches
Symbol
Min
Nom
Max
A
-
-
A1
0.002
-
A2
0.037
b
0.007
b
Dimensions in mm
Min
Nom
Max
0.049
-
-
1.25
-
0.05
-
-
0.039
0.041
0.95
1.00
1.05
0.009
0.011
0.17
0.22
0.27
c
0.005
-
0.008
0.12
-
0.21
E
0.311
0.315
0.319
7.90
8.00
8.10
L
0.012
0.020
0.028
0.30
0.50
0.70
D
0.520
0.528
0.536
13.20
13.40
13.60
D1
0.461
0.465
0.469
11.70
11.80
11.90
e
0.022 BSC
S
0.55 BSC
0.017 TYP
0.425 TYP
y
-
-
0.004
-
-
0.10
θ
0°
-
5°
0°
-
5°
Notes:
1. The maximum value of dimension D1 includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(January, 2001, Version 0.0)
11
AMIC Technology, Inc.
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