Gennum GS9090BCNE3 Genlinx iii 270mb/s deserializer for sdi Datasheet

GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Key Features
Description
•
SMPTE 259M-C compliant descrambling and NRZI to
NRZ decoding (with bypass)
•
DVB-ASI 8b/10b decoding
The GS9090B is a 270Mb/s reclocking deserializer with an
internal FIFO. It provides a complete receive solution for
SD-SDI and DVB-ASI applications.
•
Integrated line-based FIFO for data alignment/delay,
clock phase interchange, DVB-ASI data packet
extraction and clock rate interchange, and ancillary
data packet extraction
•
Integrated VCO and reclocker
•
User selectable additional processing features
including:
Š TRS, ANC data checksum, and EDH CRC error
detection and correction
Š programmable ANC data detection
Š illegal code remapping
•
Internal flywheel for noise immune H, V, F extraction
•
Automatic standards detection and indication
•
Enhanced Gennum Serial Peripheral Interface (GSPI)
•
JTAG test interface
•
Polarity insensitive for DVB-ASI and SMPTE signals
•
+1.8V core power supply with optional +1.8V or +3.3V
I/O power supply
•
Small footprint (8mm x 8mm)
•
Low power operation (typically 145mW)
•
Pb-free
Applications
•
SMPTE 259M-C Serial Digital Interfaces
•
DVB-ASI Serial Digital Interfaces
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
In addition to reclocking and deserializing the input data
stream, the GS9090B performs NRZI-to-NRZ decoding, descrambling as per SMPTE 259M-C, and word alignment
when operating in SMPTE mode. When operating in
DVB-ASI mode, the device will word align the data to K28.5
sync characters and 8b/10b decode the received stream.
The internal reclocker features a very wide input jitter tolerance, and is fully compatible with both SMPTE and
DVB-ASI input streams.
The GS9090B includes a range of data processing
functions such as EDH support (error detection and handling), and automatic standards detection. The device can
also detect and extract SMPTE 352M
payload identifier packets and independently identify the
received video standard. This information is read from internal registers via the host interface port.
The GS9090B also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes to carry out tasks such as data alignment / delay, clock phase interchange, MPEG packet extraction and clock rate
interchange, and ancillary data packet extraction.
Parallel data outputs are provided in 10-bit multiplexed
format, with the associated parallel clock output signal operating at 27MHz.
The device may also be used in a low-latency data pass
through mode where only descrambling and word alignment will be performed in SMPTE mode.
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Functional Block Diagram
RD_CLK
RD_RESET
S->P
SMPTE Descramble, Word
Alignment and
Flywheel
SMPTE sync detect
ASI sync detect
TERM
DDI_1
Reclocker
IOPROC_EN
Programmable
I/O
LOCK detect
pll_lock
DDI_1
STAT[3:0]
FW_EN
DVB_ASI
AUTO/MAN
SMPTE_BYPASS
LOCKED
PCLK
LFLF+
LB_CONT
carrier_detect
DVB-ASI
Word Alignment
and
8b/10b Decode
DOUT[9:0]
TRS Check
CSUM Check
ANC Data
Detection
TRS Correct
CSUM Correct
EDH Check &
Correct
Illegal Code Remap
DATA_ERROR
FIFO
HOST Interface
/ JTAG test
JTAG/HOST
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
RESET
GS9090B Functional Block Diagram
Revision History
Version
ECR
PCN
Date
Changes and/or Modifications
5
154185
−
May 2010
Converted document back to Data Sheet.
4
152803
−
October 2009
Changed 6.1 Package Dimensions.
3
150198
50711
July 2008
DVB_ASI operation specification change in Master mode.
2
143668
−
January 2007
Added DVB-ASI payload data rate parameter to Table 2-3: AC Electrical
Characteristics.
1
143101
−
December 2006
Converting to data sheet. Removed ‘Proprietary and Confidential’ footer.
Added section.
0
141913
−
September
2006
New Document.
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Data Sheet
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Contents
Key Features ........................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
Functional Block Diagram ..............................................................................................................................2
Revision History .................................................................................................................................................2
1. Pin Out...............................................................................................................................................................5
1.1 Pin Assignment ..................................................................................................................................5
2. Electrical Characteristics ......................................................................................................................... 12
2.1 Absolute Maximum Ratings ....................................................................................................... 12
2.2 DC Characteristics ......................................................................................................................... 12
2.3 AC Electrical Characteristics ..................................................................................................... 13
2.4 Solder Reflow Profiles .................................................................................................................. 15
2.5 Host Interface Map ........................................................................................................................ 16
2.5.1 Host Interface Map (R/W registers) ............................................................................. 18
2.5.2 Host Interface Map (Read only registers) .................................................................. 20
3. Detailed Description.................................................................................................................................. 22
3.1 Functional Overview .................................................................................................................... 22
3.2 Serial Digital Input ........................................................................................................................ 22
3.3 Clock and Data Recovery ............................................................................................................ 23
3.3.1 Internal VCO and Phase Detector................................................................................ 23
3.4 Serial-To-Parallel Conversion ................................................................................................... 23
3.5 Modes Of Operation ..................................................................................................................... 23
3.5.1 Lock Detect .......................................................................................................................... 24
3.5.2 Auto Mode............................................................................................................................ 26
3.5.3 Manual Mode ...................................................................................................................... 26
3.6 SMPTE Functionality .................................................................................................................... 27
3.6.1 SMPTE Descrambling and Word Alignment ............................................................ 27
3.6.2 Internal Flywheel .............................................................................................................. 27
3.6.3 Switch Line Lock Handling............................................................................................. 28
3.6.4 HVF Timing Signal Generation ..................................................................................... 29
3.7 DVB-ASI Functionality ................................................................................................................ 30
3.7.1 DVB-ASI 8b/10b Decoding............................................................................................. 31
3.7.2 Status Signal Outputs ....................................................................................................... 31
3.8 Data-Through Functionality ...................................................................................................... 31
3.9 Additional Processing Features ................................................................................................ 32
3.9.1 FIFO Load Pulse ................................................................................................................. 32
3.9.2 Ancillary Data Detection and Indication................................................................... 33
3.9.3 EDH Packet Detection...................................................................................................... 34
3.9.4 EDH Flag Detection........................................................................................................... 35
3.9.5 SMPTE 352M Payload Identifier................................................................................... 37
3.9.6 Automatic Video Standard and Data Format Detection ...................................... 38
3.9.7 Error Detection and Indication ..................................................................................... 39
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3.9.8 Additional Processing Functions.................................................................................. 44
3.10 Internal FIFO Operation ........................................................................................................... 47
3.10.1 Video Mode ....................................................................................................................... 47
3.10.2 DVB-ASI Mode ................................................................................................................. 48
3.10.3 Ancillary Data Extraction Mode ................................................................................ 52
3.10.4 Bypass Mode..................................................................................................................... 55
3.11 Parallel Data Outputs ................................................................................................................. 55
3.11.1 Parallel Data Bus Output Buffers............................................................................... 56
3.11.2 Parallel Output in SMPTE Mode................................................................................. 56
3.11.3 Parallel Output in DVB-ASI Mode............................................................................. 56
3.11.4 Parallel Output in Data-Through Mode................................................................... 56
3.12 Programmable Multi-Function Outputs .............................................................................. 56
3.13 GS9090B Low-latency Mode ................................................................................................... 58
3.14 GSPI Host Interface ..................................................................................................................... 59
3.14.1 Command Word Description ...................................................................................... 60
3.14.2 Data Read and Write Timing ....................................................................................... 60
3.14.3 Configuration and Status Registers........................................................................... 63
3.15 JTAG Operation ........................................................................................................................... 63
3.16 Device Power Up ......................................................................................................................... 64
4. References & Relevant Standards ......................................................................................................... 66
5. Application Information .......................................................................................................................... 67
5.1 Typical Application Circuit (Part A) ......................................................................................... 67
5.2 Typical Application Circuit (Part B) ......................................................................................... 68
6. Package & Ordering Information .......................................................................................................... 69
6.1 Package Dimensions ..................................................................................................................... 69
6.2 Recommended PCB Footprint ................................................................................................... 70
6.3 Packaging Data ............................................................................................................................... 70
6.4 Marking Diagram ........................................................................................................................... 71
6.5 Ordering Information ................................................................................................................... 71
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Data Sheet
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1. Pin Out
VCO_VDD
FIFO_EN
FW_EN
AUTO/MAN
SMPTE_BYPASS
CORE_GND
DVB_ASI
LOCKED
CORE_VDD
PCLK
IO_VDD
PLL_GND
LB_CONT
1
VCO_GND
LF-
LF+
1.1 Pin Assignment
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
IO_GND
2
41
DOUT9
PLL_VDD
3
40
DOUT8
BUFF_VDD
4
39
DOUT7
DDI
5
38
DOUT6
DDI
6
37
DOUT5
36
DOUT4
35
DOUT3
34
DOUT2
33
DOUT1
32
DOUT0
BUFF_GND
GS9090B
XXXXE3
YYWW
7
TERM
8
NC
9
GENNUM
CORE_VDD
14
15
16
17
18
19
20
21
22
23
24
25
26
27
29
28
IO_GND
IO_VDD
RESET
STAT3
RD_CLK
STAT2
30
STAT1
13
IO_GND
JTAG/HOST
STAT0
RD_RESET
DATA_ERROR
31
IO_VDD
12
SDIN_TDI
IOPROC_EN
SDOUT_TDO
11
CORE_GND
NC
SCLK_TCK
10
CS_TMS
VBG
Center Pad
(bottom of package)
Figure 1-1: Pin Assignment
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Table 1-1: Pin List and Description
Pin Number
Name
Timing
Type
Description
1
LF-
Analog
Input
Loop filter component connection. Connect to pin 56 (LF+) as
shown in Typical Application Circuit (Part B) on page 68.
2
PLL_GND
Analog
Input
Ground connection for phase-locked loop. Connect to GND.
Power
3
4
PLL_VDD
BUFF_VDD
Analog
Analog
Input
Power
Power supply connection for phase-locked loop. Connect to +1.8V
DC.
Input
Power supply connection for digital input buffers.
Power
When DDI/DDI are AC coupled, this pin should be left unconnected.
When DDI/DDI are DC coupled, this pin should be connected to
+3.3V as shown in Typical Application Circuit (Part B) on page 68.
See Serial Digital Input on page 22 for more details.
5, 6
7
DDI, DDI
Analog
Input
Serial digital differential input pair.
BUFF_GND
Analog
Input
Ground connection for serial digital input buffer. Connect to GND.
Power
8
TERM
Analog
Input
Termination for serial digital input. AC couple to BUFF_GND
NC
–
–
No connect.
10
VBG
Analog
Input
Bandgap filter capacitor. Connect to GND as shown in Typical
Application Circuit (Part B) on page 68.
12
IOPROC_EN
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal Levels are LVCMOS / LVTTL compatible.
9, 11
Used to enable or disable the I/O processing features.
When set HIGH, the following I/O processing features of the device
are enabled:
• Illegal Code Remapping
• EDH CRC Error Correction
• Ancillary Data Checksum Error Correction
• TRS Error Correction
• EDH Flag Detection
To enable a subset of these features, keep the IOPROC_EN pin
HIGH and disable the individual feature(s) in the IOPROC_DISABLE
register accessible via the host interface.
When set LOW, the device will enter low-latency mode.
NOTE: When the internal FIFO is configured for Video mode or
Ancillary Data Extraction mode, the IOPROC_EN pin must be set
HIGH (see Internal FIFO Operation on page 47).
13
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are
configured as GSPI pins for normal host interface operation.
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Table 1-1: Pin List and Description (Continued)
14
RESET
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to reset the internal operating conditions to default setting
or to reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW):
When asserted LOW, all functional blocks will be set to default
conditions and all output signals become high impedance with the
exception of the STAT pins and the DATA_ERROR pin which will
maintain the last state they were in for the duration that RESET is
asserted.
JTAG Test Mode (JTAG/HOST = HIGH):
When asserted LOW, all functional blocks will be set to default and
the JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence
resumes.
NOTE: See Device Power Up on page 64 for power on reset
requirements.
15, 45
16
CORE_VDD
CS_TMS
Non
Synchronous
Input
Power supply for digital logic blocks. Connect to +1.8V DC.
Power
NOTE: For power sequencing requirements please see Device
Power Up on page 64.
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Chip Select / Test Mode Select
Host Mode (JTAG/HOST = LOW):
CS_TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG/HOST = HIGH):
CS_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
17
SCLK_TCK
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Clock / Test Clock. All JTAG / Host Interface address and
data are shifted into/out of the device synchronously with this
clock.
Host Mode (JTAG/HOST = LOW):
SCLK_TCK operates as the host interface serial data clock, SCLK.
JTAG Test Mode (JTAG/HOST = HIGH):
SCLK_TCK operates as the JTAG test clock, TCK.
18, 48
19
CORE_GND
SDOUT_TDO
Non
Synchronous
Input
Synchronous
with
SCLK_TCK
Output
Ground connection for digital logic blocks. Connect to GND.
Power
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Output / Test Data Output
Host Mode (JTAG/HOST = LOW):
SDOUT_TDO operates as the host interface serial output, SDOUT,
used to read status and configuration information from the
internal registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDOUT_TDO operates as the JTAG test data output, TDO.
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Table 1-1: Pin List and Description (Continued)
20
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Input / Test Data Input
Host Mode (JTAG/HOST = LOW):
SDIN_TDI operates as the host interface serial input, SDIN, used to
write address and configuration information to the internal
registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDIN_TDI operates as the JTAG test data input, TDI.
21, 29, 43
IO_VDD
Non
Synchronous
Input
Power supply for digital I/O.
Power
For a 3.3V tolerant I/O, connect pins to either +1.8V DC or +3.3V
DC.
For a 5V tolerant I/O, connect pins to a +3.3V DC.
NOTE: For power sequencing requirements please see Device
Power Up on page 64.
22
DATA_ERROR
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT.
Signal levels are LVCMOS / LVTTL compatible.
The DATA_ERROR signal will be LOW when an error within the
received data stream has been detected by the device. This pin is an
inverted logical ‘OR’ing of all detectable errors listed in the internal
ERROR_STATUS register.
Once an error is detected, DATA_ERROR will remain LOW until the
start of the next video frame / field, or until the ERROR_STATUS
register is read via the host interface.
The DATA_ERROR signal will be HIGH when the received data
stream has been detected without error.
NOTE: It is possible to program which error conditions are
monitored by the device by setting appropriate bits in the
ERROR_MASK register HIGH. All error conditions are detected by
default.
23, 25, 26, 27
STAT[0:3]
Synchronous
with PCLK or
RD_CLK
Output
MULTI FUNCTION I/O PORT
Signal levels are LVCMOS / LVTTL compatible.
Programmable multi-function outputs. By programming the bits is
the IO_CONFIG register, each pin can output one of the following
signals:
• H
• V
• F
• FIFO_LD
• ANC_DETECT
• EDH_DETECT
• FIFO_FULL
• FIFO_EMPTY
These pins are set to certain default values depending on the
configuration of the device and the internal FIFO mode selected.
See Programmable Multi-Function Outputs on page 56 for details.
24, 28, 42
IO_GND
Non
Synchronous
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
Input
Power
Ground connection for digital I/O. Connect to GND.
8 of 72
Table 1-1: Pin List and Description (Continued)
30
RD_CLK
–
Input
FIFO READ CLOCK
Signal levels are LVCMOS / LVTTL compatible.
The parallel data will be clocked out of the FIFO on the rising edge
of RD_CLK.
31
RD_RESET
Synchronous
with RD_CLK
Input
FIFO READ RESET
Signal levels are LVCMOS / LVTTL compatible.
Valid input only when the device is in SMPTE mode (SMPTE_BYPASS
= HIGH and DVB-ASI = LOW), and the internal FIFO is configured
for video mode (See Video Mode on page 47).
A HIGH to LOW transition will reset the FIFO pointer to address
zero of the memory.
32 - 41
DOUT[0:9]
Synchronous
with RD_CLK
or PCLK
Output
PARALLEL VIDEO DATA BUS
Signal levels are LVCMOS / LVTTL compatible.
When the internal FIFO is enabled and configured for either video
mode or DVB-ASI mode, parallel data will be clocked out of the
device on the rising edge of RD_CLK.
When the internal FIFO is in bypass mode, parallel data will be
clocked out of the device on the rising edge of PCLK.
DOUT9 is the MSB and DOUT0 is the LSB.
44
PCLK
–
Output
PIXEL CLOCK OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
27MHz parallel clock output.
46
LOCKED
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode, or when the reclocker
has achieved lock in Data-Through mode.
It will be LOW otherwise. When the signal is LOW, all digital output
signals will be forced to logic LOW levels.
47
DVB_ASI
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
This pin and its function are only supported in Manual mode
(AUTO/MAN = LOW).
When this pin is set HIGH, the device will be configured to operate
in DVB-ASI mode. The SMPTE_BYPASS pin will be ignored.
When set LOW, the device will not support the decoding or word
alignment of received DVB-ASI data.
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Table 1-1: Pin List and Description (Continued)
49
SMPTE_BYPASS
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
This pin is an input in Manual mode, and an output set by the
device in Auto mode.
Auto Mode (AUTO/MAN = HIGH):
The SMPTE_BYPASS signal will be HIGH only when the device has
locked to a SMPTE compliant data stream. It will be LOW
otherwise. When the signal is LOW, no I/O processing features are
available.
Manual Mode (AUTO/MAN = LOW):
When this pin is set HIGH in conjunction with DVB_ASI = LOW, the
device will be configured to operate in SMPTE mode. All I/O
processing features may be enabled in this mode.
When the SMPTE_BYPASS pin is set LOW, the device will not
support the descrambling, decoding, or word alignment of
received SMPTE data. No I/O processing features will be available.
50
AUTO/MAN
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
When set HIGH, the GS9090B will operate in Auto mode. The
SMPTE_BYPASS pin becomes an output status signal set by the
device. In this mode, the GS9090B will automatically detect,
reclock, deserialize, and process SMPTE compliant input data.
When set LOW, the GS9090B will operate in Manual mode. The
DVB_ASI and SMPTE_BYPASS pins become input control signals. In
this mode, these two external pins must be set for the correct
reception of either SMPTE or DVB-ASI data. Manual mode also
supports the reclocking and deserializing of data not conforming
to SMPTE or DVB-ASI streams.
51
FW_EN
Non
Synchronous
Input
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable or disable the noise immune flywheel of the device.
When set HIGH, the internal flywheel is enabled. This flywheel is
used in the extraction of timing signals, the generation of TRS
signals, the automatic detection of video standards, and in manual
switch line lock handling.
When set LOW, the internal flywheel is disabled. Timing based TRS
errors will not be detected.
52
FIFO_EN
Non
Synchronous
Input
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable / disable the internal FIFO.
When FIFO_EN is HIGH, the internal FIFO will be enabled. Data will
be clocked out of the device on the rising edge of the RD_CLK
input pin if the FIFO is in video mode or DVB-ASI mode.
When FIFO_EN is LOW, the internal FIFO is bypassed and parallel
data is clocked out on the rising edge of the PCLK output.
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Table 1-1: Pin List and Description (Continued)
53
VCO_VDD
Analog
Input
Power
Power supply connection for Voltage-Controlled-Oscillator.
Connect to +1.8V DC.
54
LB_CONT
Analog
Input
CONTROL SIGNAL INPUT
Control voltage to fine-tune the loop bandwidth of the PLL.
55
VCO_GND
Analog
Input
Power
Ground connection for Voltage-Controlled-Oscillator. Connect to
GND.
56
LF+
Analog
Input
Loop filter component connection. Connect to pin 1 (LF-) as shown
in Typical Application Circuit (Part B) on page 68.
Center Pad
–
Power
Connect to GND following recommendations in Recommended PCB
Footprint on page 70
–
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Value/Units
Supply Voltage Core
-0.3V to +2.1V
Supply Voltage I/O
-0.3V to +3.47V
Input Voltage Range (any input)
-2.0V to + 5.25V
Ambient Operating Temperature
-20°C < TA < 85°C
Storage Temperature
-40°C < TSTG < 125°C
ESD protection on all pins (see Note 1)
1kV
Solder Reflow Temperature
260°C
NOTES:
1. HBM, per JESD22 - A114B
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions or at any other condition beyond those
indicated in the AC/DC Electrical Characteristic sections is not implied.
2.2 DC Characteristics
Table 2-2: DC Electrical Characteristics
VDD = 1.8V ±5%, 3.3V ±5%; TA = 0°C to 70°C, unless otherwise specified. Typical values: VCC = 1.8V, 3.3V and TA =25°C
Parameter
Symbol
Condition
Min
Typ
Max
Units
Notes
System
Core Power Supply Voltage
CORE_VDD
–
1.71
1.8
1.89
V
–
Digital I/O Buffer Power Supply
Voltage
IO_VDD
1.8V Operation
1.71
1.8
1.89
V
–
IO_VDD
3.3V Operation
3.13
3.3
3.47
V
–
PLL Power Supply Voltage
PLL_VDD
–
1.71
1.8
1.89
V
–
VCO Power Supply Voltage
VCO_VDD
–
1.71
1.8
1.89
V
–
Typical System Power
PD
CORE_VDD = 1.8V
IO_VDD = 1.8V
–
145
–
mW
–
–
–
270
mW
–
T = 25oC
Max. System Power
PD
CORE_VDD = 1.89V
IO_VDD = 3.47V
T = 70oC
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Table 2-2: DC Electrical Characteristics (Continued)
VDD = 1.8V ±5%, 3.3V ±5%; TA = 0°C to 70°C, unless otherwise specified. Typical values: VCC = 1.8V, 3.3V and TA =25°C
Parameter
Symbol
Condition
Min
Typ
Max
Units
Notes
Digital I/O
Input Voltage, Logic LOW
VIL
1.8V Operation or
3.3V Operation
–
–
0.35 x
IO_VDD
V
–
Input Voltage, Logic HIGH
VIH
1.8V Operation or
3.3V Operation
0.65 x
IO_VDD
–
–
V
–
Output Voltage, Logic LOW
VOL
IOL = 8mA @ 3.3V,
4mA @ 1.8V
–
–
0.4
V
–
Output Voltage, Logic HIGH
VOH
IOL = -8mA @ 3.3V,
-4mA @ 1.8V
IO_VDD 0.4
–
–
V
–
Input Common Mode Voltage
VCMIN
BUFF_VDD
connected to 3.3V
supply
BUFF_GND
+ (VDIFF / 2)
–
BUFF_VDD
- (VDIFF / 2)
V
–
Input Termination Resistance
RIN
–
37.5
50
62.5
Ω
–
Serial Digital Inputs
2.3 AC Electrical Characteristics
Table 2-3: AC Electrical Characteristics
VDD = 1.8V ±5%, 3.3V ±5%; TA = 0°C to 70°C, unless otherwise specified. Typical values: VCC = 1.8V, 3.3V and TA =25°C
Parameter
Symbol
Condition
tLOCK
Input jitter of 0.2UI,
Min
Typ
Max
Units
Notes
–
–
235
us
1
–
–
165
us
1
System
Asynchronous Lock Time (LOCKED
signal set HIGH)
No data to SMPTE,
SMPTE_BYPASS = HIGH
DVB_ASI = LOW,
at 25°C
Asynchronous Lock Time (LOCKED
signal set HIGH)
tLOCK
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
Input jitter of 0.2UI,
No data to non-SMPTE,
SMPTE_BYPASS = LOW
DVB_ASI = LOW,
at 25°C
13 of 72
Table 2-3: AC Electrical Characteristics (Continued)
VDD = 1.8V ±5%, 3.3V ±5%; TA = 0°C to 70°C, unless otherwise specified. Typical values: VCC = 1.8V, 3.3V and TA =25°C
Parameter
Symbol
Condition
Min
Typ
Max
Units
Notes
Serial Input Data Rate
DRSDI
–
–
270
–
Mb/s
–
DVB-ASI Payload Data Rate
DRASI
204 byte mode
–
–
213.9
Mb/s
2,4
188 byte mode
–
–
213.7
Mb/s
3,4
–
0.5
–
UI
5
Serial Digital Input
Serial Input Jitter Tolerance
IJT
–
Differential Input Voltage Range
–
BUFF_VDD = 1.8V
200
800
1700
mVp-p
–
–
BUFF_VDD = 3.3V
100
800
2200
mVp-p
–
Parallel Output Clock Frequency
fPCLK
–
–
27
–
MHz
–
Parallel Output Clock Duty Cycle
DCPCLK
–
40
–
60
%
–
Variation of Parallel Output Clock
(from 27MHz)
–
Device Unlocked
-7.5
–
+7.5
%
6
Output Data Hold Time
tOH
With 15pF load
3
–
–
ns
7
Output Delay Time
tOD
With 15pF load
–
–
10
ns
7
GSPI Input Clock Frequency
fGSPI
–
–
–
54
MHz
–
GSPI Clock Duty Cycle
DCGSPI
–
40
–
60
%
–
GSPI Setup Time
tGS
–
1.5
–
–
ns
–
GSPI Hold Time
tGH
–
–
–
1.5
ns
–
Parallel Output
GSPI
NOTES
1. No signal to signal present, or a switch from another data rate to 270Mb/s.
2. Transmission format includes 204 byte data packets preceded by two K28.5 synchronization characters. Payload data rate excludes the two
K28.5 synchronization characters.
3. Transmission format includes 188 byte data packets preceded by two K28.5 synchronization characters. Payload data rate excludes the two
K28.5 synchronization characters.
4. Maximum payload is achieved via data packet mode,however, any combination of burst and packet mode is supported as long as each byte or
packet is preceded by two K28.5 characters.
5. Power supply noise 50mVpp at 15kHz, 100kHz, 1MHz sinusoidal modulation.
6. When the serial input to the GS9090B is removed, the PCLK output signal will continue to operate at 27MHz and the internal VCO will remain
at this frequency within +/-7.5%.
7. Timing includes the following outputs: DOUT[9:0], H, V, F, ANC, EDH_DETECT, FIFO_FULL, FIFO_EMPTY, FIFO_LD, WORDERR, SYNCOUT. When
the FIFO is enabled, the outputs are measured with respect to RD_CLK.
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
14 of 72
2.4 Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both
standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed
using the maximum Pb-free reflow profile shown in Figure 2-1. The recommended
standard eutectic reflow profile is shown in Figure 2-2.
Temperature
60-150 sec.
20-40 sec.
260°C
250°C
3°C/sec max
217°C
6°C/sec max
200°C
150°C
25°C
Time
60-180 sec. max
8 min. max
Figure 2-1: Maximum Pb-free Solder Reflow Profile (Preferred)
60-150 sec.
Temperature
10-20 sec.
230°C
220°C
3°C/sec max
183°C
6°C/sec max
150°C
100°C
25°C
Time
120 sec. max
6 min. max
Figure 2-2: Standard Pb Solder Reflow Profile
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
15 of 72
28h
FIFO_LD_POSITION[12:0]
24h
23h
22h
21h
20h
1Fh
1Eh
1Dh
1Ch
1Bh
1Ah
19h
18h
17h
16h
15h
14h
13h
FF_PIXEL_END_F1[12:0]
FF_PIXEL_START_F1[12:0]
FF_PIXEL_END_F0[12:0]
FF_PIXEL_START_F0[12:0]
AP_PIXEL_END_F1[12:0]
AP_PIXEL_START_F1[12:0]
AP_PIXEL_END_F0[12:0]
AP_PIXEL_START_F0[12:0]
FF_LINE_END_F1[10:0]
FF_LINE_START_F1[10:0]
FF_LINE_END_F0[10:0]
FF_LINE_START_F0[10:0]
AP_LINE_END_F1[10:0]
AP_LINE_START_F1[10:0]
AP_LINE_END_F0[10:0]
AP_LINE_START_F0[10:0]
RASTER_STRUCTURE4[10:0]
RASTER_STRUCTURE3[12:0]
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
14
Not Used
Not Used
15
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
13
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
25h
ERROR_MASK_REGISTER
26h
27h
Address
Register Name
Table 2-4: Host Interface Map
2.5 Host Interface Map
b12
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b12
b12
b12
b12
b12
b12
b12
b12
Not Used
b12
12
b11
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b11
b11
b11
b11
b11
b11
b11
b11
Not Used
b11
11
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
Not Used
b10
10
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
Not Used
b9
9
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
Not Used
b8
8
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
Not Used
b7
7
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
VD_STD_
ERR_
MASK
b6
6
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
FF_CRC_
ERR_
MASK
b5
5
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
AP_CRC_
ERR_
MASK
b4
4
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
LOCK_
ERR_
MASK
b3
3
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
CCS_ERR_
MASK
b2
2
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
SAV_ERR_
MASK
b1
1
16 of 72
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
EAV_ERR
_MASK
b0
0
12h
11h
10h
0Fh
0Eh
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
RASTER_STRUCTURE2[12:0]
RASTER_STRUCTURE1[10:0]
VIDEO_FORMAT_OUT_B(4,3)
VIDEO_FORMAT_OUT_A(2,1)
ANC_TYPE(5)[15:0]
ANC_TYPE(4)[15:0]
ANC_TYPE(3)[15:0]
ANC_TYPE(2)[15:0]
ANC_TYPE(1)[15:0]
ANC_LINE_B[10:0]
ANC_LINE_A[10:0]
FIFO_FULL_OFFSET
FIFO_EMPTY_OFFSET
IO_CONFIG
DATA_FORMAT
EDH_FLAG_OUT
EDH_FLAG_IN
ERROR_STATUS
IOPROC_DISABLE
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b15
b15
b15
b15
b15
VFO2-b7
VFO4-b7
Not Used
Not Used
15
Not Used
Not Used
ANC-UE
_IN
ANC-UES
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b14
b14
b14
b14
b14
VFO2-b6
VFO4-b6
Not Used
Not Used
14
Not Used
Not Used
ANC-IDA
_IN
ANC-IDA
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b13
b13
b13
b13
b13
VFO2-b5
VFO4-b5
Not Used
Not Used
13
Not Used
Not Used
ANC-IDH
_IN
ANC-IDH
Not Used
ANC_
DATA_
SWITCH
Not Used
Not Used
Not Used
Not Used
b12
b12
b12
b12
b12
VFO2-b4
VFO4-b4
Not Used
b12
12
Not Used
Not Used
ANC-EDA
_IN
ANC-EDA
EDH_
FLAG_
UPDATE
STAT3_
CONFIG
b2
ANC_
DATA_
DELETE
Not Used
Not Used
Not Used
b11
b11
b11
b11
b11
VFO2-b3
VFO4-b3
Not Used
b11
11
Not Used
Not Used
ANC-EDH
_IN
ANC-EDH
AP_CRC
_V
STAT3_
CONFIG
b1
Not Used
Not Used
b10
b10
b10
b10
b10
b10
b10
VFO2-b2
VFO4-b2
b10
b10
10
ANC_PKT
_EXT
Not Used
FF-UES_
IN
FF-UES
FF_CRC
_V
STAT3_
CONFIG
b0
b9
b9
b9
b9
b9
b9
b9
b9
b9
VFO2-b1
VFO4-b1
b9
b9
9
FIFO_
MODE
b1
Not Used
FF-IDA_IN
FF-IDA
EDH_
DETECT
STAT2_
CONFIG
b2
b8
b8
b8
b8
b8
b8
b8
b8
b8
VFO2-b0
VFO4-b0
b8
b8
8
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
NOTE: Addresses 02Ch to 42Bh store the contents of the internal FIFO. The contents may be accessed in Ancillary Data Extraction mode (see Section 3.10.3).
Address
Register Name
Table 2-4: Host Interface Map (Continued)
FIFO_
MODE
b0
Not Used
FF-IDH
_IN
FF-IDH
VERSION_
352M
STAT2_
CONFIG
b1
b7
b7
b7
b7
b7
b7
b7
b7
b7
VFO1-b7
VFO3-b7
b7
b7
7
H_
CONFIG
VD_STD_
ERR
FF-EDA
_IN
FF-EDA
Not Used
STAT2_
CONFIG
b0
b6
b6
b6
b6
b6
b6
b6
b6
b6
VFO1-b6
VFO3-b6
b6
b6
6
Not Used
FF_CRC_
ERR
FF-EDH
_IN
FF-EDH
Not Used
STAT1_
CONFIG
b2
b5
b5
b5
b5
b5
b5
b5
b5
b5
VFO1-b5
VFO3-b5
b5
b5
5
Not Used
AP_CRC_
ERR
AP-UES
_IN
AP-UES
STD_
LOCK
STAT1_
CONFIG
b1
b4
b4
b4
b4
b4
b4
b4
b4
b4
VFO1-b4
VFO3-b4
b4
b4
4
ILLEGAL_
REMAP
LOCK_
ERR
AP-IDA_I
N
AP-IDA
DATA_
FORMAT
b3
STAT1_
CONFIG
b0
b3
b3
b3
b3
b3
b3
b3
b3
b3
VFO1-b3
VFO3-b3
b3
b3
3
EDH_CRC
_INS
CCS_ERR
AP-IDH_I
N
AP-IDH
DATA_
FORMAT
b2
STAT0_
CONFIG
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
VFO1-b2
VFO3-b2
b2
b2
2
ANC_
CSUM_
INS
SAV_ERR
AP-EDA_I
N
AP-EDA
DATA_
FORMAT
b1
STAT0_
CONFIG
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
VFO1-b1
VFO3-b1
b1
b1
1
17 of 72
TRS_IN
EAV_ERR
AP-EDH_I
N
AP-EDH
DATA_
FORMAT
b0
STAT0_
CONFIG
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
VFO1-b0
VFO3-b0
b0
b0
0
28h
FIFO_LD_POSITION[12:0]
24h
23h
22h
21h
20h
1Fh
1Eh
1Dh
1Ch
1Bh
1Ah
19h
18h
17h
16h
15h
FF_PIXEL_END_F1[12:0]
FF_PIXEL_START_F1[12:0]
FF_PIXEL_END_F0[12:0]
FF_PIXEL_START_F0[12:0]
AP_PIXEL_END_F1[12:0]
AP_PIXEL_START_F1[12:0]
AP_PIXEL_END_F0[12:0]
AP_PIXEL_START_F0[12:0]
FF_LINE_END_F1[10:0]
FF_LINE_START_F1[10:0]
FF_LINE_END_F0[10:0]
FF_LINE_START_F0[10:0]
AP_LINE_END_F1[10:0]
AP_LINE_START_F1[10:0]
AP_LINE_END_F0[10:0]
AP_LINE_START_F0[10:0]
15
14
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
12h
13h
14h
25h
ERROR_MASK_REGISTER
26h
27h
Address
Register Name
13
Table 2-5: Host Interface Map (R/W registers)
b12
b12
b12
b12
b12
b12
b12
b12
b12
12
2.5.1 Host Interface Map (R/W registers)
b11
b11
b11
b11
b11
b11
b11
b11
b11
11
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
b10
10
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
9
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
8
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
7
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
VD_STD_
ERR_
MASK
b6
6
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
FF_CRC_
ERR_
MASK
b5
5
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
AP_CRC_
ERR_
MASK
b4
4
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
LOCK_
ERR_
MASK
b3
3
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
CCS_ERR_
MASK
b2
2
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
EAV_ERR
_MASK
b0
0
18 of 72
SAV_ERR_
MASK
b1
1
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
ANC_TYPE(3)[15:0]
ANC_TYPE(2)[15:0]
ANC_TYPE(1)[15:0]
ANC_LINE_B[10:0]
ANC_LINE_A[10:0]
FIFO_FULL_OFFSET
FIFO_EMPTY_OFFSET
IO_CONFIG
DATA_FORMAT
00h
01h
02h
b15
b15
b15
b15
b15
15
b14
b14
b14
b14
b14
14
b13
b13
b13
b13
b13
13
ANC_
DATA_
SWITCH
b12
b12
b12
b12
b12
12
EDH_
FLAG_
UPDATE
STAT3_
CONFIG
b2
ANC_
DATA_
DELETE
b11
b11
b11
b11
b11
11
STAT3_
CONFIG
b1
ANC_PKT
_EXT
STAT3_
CONFIG
b0
b9
b9
b9
b9
b10
b10
b9
b9
b9
b9
b9
9
b10
b10
b10
b10
b10
10
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
NOTE: Addresses 02Ch to 42Bh store the contents of the internal FIFO. The contents may be accessed in Ancillary Data Extraction mode (see Section 3.10.3).
IOPROC_DISABLE
0Dh
ANC_TYPE(4)[15:0]
03h
0Eh
0Fh
10h
11h
Address
ANC_TYPE(5)[15:0]
Register Name
Table 2-5: Host Interface Map (R/W registers) (Continued)
FIFO_
MODE
b1
STAT2_
CONFIG
b2
b8
b8
b8
b8
b8
b8
b8
b8
b8
8
FIFO_
MODE
b0
STAT2_
CONFIG
b1
b7
b7
b7
b7
b7
b7
b7
b7
b7
7
H_
CONFIG
STAT2_
CONFIG
b0
b6
b6
b6
b6
b6
b6
b6
b6
b6
6
STAT1_
CONFIG
b2
b5
b5
b5
b5
b5
b5
b5
b5
b5
5
STAT1_
CONFIG
b1
b4
b4
b4
b4
b4
b4
b4
b4
b4
4
ILLEGAL_
REMAP
STAT1_
CONFIG
b0
b3
b3
b3
b3
b3
b3
b3
b3
b3
3
EDH_CRC
_INS
STAT0_
CONFIG
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
2
TRS_IN
STAT0_
CONFIG
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
0
19 of 72
ANC_
CSUM_
INS
STAT0_
CONFIG
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
1
13h
12h
11h
RASTER_STRUCTURE3[12:0]
RASTER_STRUCTURE2[12:0]
RASTER_STRUCTURE1[10:0]
15
14
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
Address
RASTER_STRUCTURE4[10:0]
Register Name
13
b12
b12
12
Table 2-6: Host Interface Map (Read only registers)
b11
b11
11
2.5.2 Host Interface Map (Read only registers)
b9
b9
b10
b9
b9
9
b10
b10
b10
10
b8
b8
b8
b8
8
b7
b7
b7
b7
7
b6
b6
b6
b6
6
b5
b5
b5
b5
5
b4
b4
b4
b4
4
b3
b3
b3
b3
3
b2
b2
b2
b2
2
b1
b1
b1
b1
1
20 of 72
b0
b0
b0
b0
0
10h
0Fh
VIDEO_FORMAT_OUT_B(4,3)
VIDEO_FORMAT_OUT_A(2,1)
03h
02h
01h
EDH_FLAG_OUT
EDH_FLAG_IN
ERROR_STATUS
Not Used
Not Used
VFO2-b7
VFO4-b7
15
ANC-UES
_IN
ANC-UES
VFO2-b6
VFO4-b6
14
ANC-IDA
_IN
ANC-IDA
VFO2-b5
VFO4-b5
13
ANC-IDH
_IN
ANC-IDH
VFO2-b4
VFO4-b4
12
ANC-EDA
_IN
ANC-EDA
VFO2-b3
VFO4-b3
11
ANC-EDH
_IN
ANC-EDH
AP_CRC_
V
VFO2-b2
VFO4-b2
10
FF-UES
_IN
FF-UES
FF_CRC_V
VFO2-b1
VFO4-b1
9
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
NOTE: Addresses 02Ch to 42Bh store the contents of the internal FIFO. The contents may be accessed in Ancillary Data Extraction mode (see Section 3.10.3).
00h
04h
DATA_FORMAT
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Address
Register Name
Table 2-6: Host Interface Map (Read only registers) (Continued)
FF-IDA_IN
FF-IDA
EDH_
DETECT
VFO2-b0
VFO4-b0
8
FF-IDH
_IN
FF-IDH
VERSION_
352M
VFO1-b7
VFO3-b7
7
VD_STD_
ERR
FF-EDA
_IN
FF-EDA
VFO1-b6
VFO3-b6
6
FF_CRC_
ERR
FF-EDH
_IN
FF-EDH
VFO1-b5
VFO3-b5
5
AP_CRC_
ERR
AP-UES
_IN
AP-UES
STD_
LOCK
VFO1-b4
VFO3-b4
4
LOCK_
ERR
AP-IDA
_IN
AP-IDA
DATA_
FORMAT
b3
VFO1-b3
VFO3-b3
3
CCS_ERR
AP-IDH
_IN
AP-IDH
DATA_
FORMAT
b2
VFO1-b2
VFO3-b2
2
EAV_ERR
AP-EDH
_IN
AP-EDH
DATA_
FORMAT
b0
VFO1-b0
VFO3-b0
0
21 of 72
SAV_ERR
AP-EDA
_IN
AP-EDA
DATA_
FORMAT
b1
VFO1-b1
VFO3-b1
1
3. Detailed Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Functional Overview
Serial Digital Input
Clock and Data Recovery
Serial-To-Parallel Conversion
Modes Of Operation
SMPTE Functionality
DVB-ASI Functionality
Data-Through Functionality
Additional Processing Features
Internal FIFO Operation
Parallel Data Outputs
Programmable Multi-Function Outputs
GS9090B Low-latency Mode
GSPI Host Interface
JTAG Operation
Device Power Up
3.1 Functional Overview
The GS9090B is a 270Mb/s reclocking deserializer with an internal FIFO and
programmable multi-function output port. The device has two basic modes of operation.
In Auto mode, the GS9090B can automatically detect SMPTE data streams at its input. In
Manual mode, the device can be set to process SMPTE or DVB/ASI data streams.
The digital signal processing core handles ancillary data detection/indication, error
detection and handling (EDH), SMPTE352M extraction, and automatic video standards
detection. These features are all enabled by default, but may be individually disabled via
internal registers accessible through the GSPI host interface.
The provided programmable multi-function output pins may be configured to output
various status signals including H, V, and F timing, ancillary data detection, EDH
detection, and a FIFO load pulse. The internal FIFO supports 4 modes of operation,
which may be used for data alignment, data delay, MPEG packet extraction, or ancillary
data extraction.
The GS9090B contains a JTAG interface for boundary scan test implementations.
3.2 Serial Digital Input
The GS9090B contains a current mode differential serial digital input buffer. The input
buffer has internal 50Ω termination resistors, which are connected to ground via the
TERM pin.
If the input signal is AC coupled to the device, the signal source common mode level will
be set internally to typically 1.45V. If the input signal is DC coupled to the device, the
internal biasing will be ignored. Please see AC Electrical Characteristics for Common
Mode range and swing characteristics.
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3.3 Clock and Data Recovery
The GS9090B contains an integrated clock and data recovery block. The function of this
block is to lock to the input data stream, extract a clean clock, and retime the serial
digital data to remove high frequency jitter.
3.3.1 Internal VCO and Phase Detector
The GS9090B uses an internal VCO and PFD as part of the reclocker's phase-locked loop.
Each block requires a +1.8V DC power supply, which is supplied via the VCO_VDD /
VCO_GND and PLL_VDD / PLL_GND pins.
3.4 Serial-To-Parallel Conversion
The retimed data and phase-locked clock signals from the reclocker are fed to the
serial-to-parallel converter. The function of this block is to extract 10-bit parallel data
words from the reclocked serial data stream and simultaneously present them to the
SMPTE and DVB-ASI word alignment blocks.
3.5 Modes Of Operation
The GS9090B has two basic modes of operation: Auto mode and Manual mode. Auto
mode is enabled when AUTO/MAN is set HIGH, and Manual mode is enabled when
AUTO/MAN is set LOW. As indicated in Figure 3-1. DVB_ASI and data-through are only
supported in Manual mode.
In Auto mode (AUTO/MAN = HIGH), the GS9090B will automatically detect, reclock,
deserialize, and process SMPTE 259M-C input data.
In Manual mode (AUTO/MAN = LOW), the SMPTE_BYPASS and DVB_ASI pins must be
set as per Table 3-2 for the correct reception of either SMPTE or DVB-ASI data. Manual
mode also supports the reclocking and deserializing of 270Mb/s data not conforming to
SMPTE or DVB-ASI streams.
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Auto Mode
(Section 3.5.2)
GS9090
SMPTE Functionality
(section 3.6)
SMPTE Functionality
(section 3.6)
Manual Mode
(Section 3.5.3)
DVB-ASI Functionality
(section 3.7)
Data-Through
Functionality
(Section 3.8)
Figure 3-1: GS9090B’s Modes of Operation
3.5.1 Lock Detect
Once the reclocker has locked to the received serial digital data stream, the lock detect
block of the GS9090B searches for the appropriate sync words, and indicates via the
LOCKED output pin when the device has successfully achieved lock. The LOCKED pin
is designed to be stable. It will not toggle during the locking process, nor will it glitch
during a SMPTE synchronous switch.
The lock detection process is summarized in Figure 3-2.
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Power Up
or RESET
Valid Serial
Digital Input?
Device
sets LOCKED
pin LOW
NO (Input data invalid)
YES
Device in Auto Mode? YES
(Section 3.6.2)
Internal reclocker NO
locked?
NO
YES
(Device in
Manual Mode)
SMPTE TRS
words
detected?
Device
sets SMPTE_BYPASS
pin LOW
Device
outputs 27MHz +/- 7%
clock on PCLK pin
NO
Device
sets all other
output pins LOW
YES
SMPTE_BYPASS and DVB_ASI pins must
be set to support different
functionalities (Section 3.6.3).
Device sets
LOCKED pin HIGH
Device sets SMPTE_BYPASS
status pin
(Section 3.6.2)
Device outputs accurate
27MHz clock on PCLK pin
Figure 3-2: Lock Detection Process
The lock detection algorithm (Figure 3-2) first determines if the input is a 270Mb/s serial
digital data stream.
When the serial data input signal is considered invalid, the LOCKED pin will be set LOW,
and all device outputs will be forced LOW, except PCLK.
If a valid serial digital input signal has been detected, and the device is in Auto mode, the
lock algorithm will attempt to detect the presence of SMPTE TRS words. Assuming that
a valid 270Mb/s SMPTE signal has been applied to the device, the LOCKED pin will be
set HIGH.
The PCLK output frequency will be 27MHz +/- 7.5% when the device is not locked, as
well as during the lock detection process.
For serial inputs that do not conform to SMPTE or DVB-ASI formats, the device can only
achieve the locked state in manual mode. In Auto mode, the LOCKED signal will be
asserted LOW, the parallel outputs will be latched to logic LOW, and the
SMPTE_BYPASS and DVB_ASI output signals will also be set LOW.
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In Manual mode, the SMPTE_BYPASS and DVB_ASI input pins must be set LOW. If the
GS9090B achieves lock to the input data signal, data will be passed directly to the
parallel outputs without any further processing (see Section 3.8).
3.5.2 Auto Mode
The GS9090B is in Auto mode when the AUTO/MAN input pin is set HIGH. In this mode,
SMPTE_BYPASS becomes an output status pin, as shown in Table 3-1.
Table 3-1: Auto Mode Output Status Signals
Pin Settings
Format
SMPTE_BYPASS
SD SMPTE
HIGH
NOT SMPTE
LOW
3.5.3 Manual Mode
The GS9090B is in Manual mode when the AUTO/MAN input pin is set LOW. In this
mode, the SMPTE_BYPASS and DVB_ASI pins become input signals, and the operating
mode of the device is set by these pins as shown in Table 3-2
.
Table 3-2: Manual Mode Input Status Signals
Pin Settings
Format
SMPTE_BYPASS
DVB_ASI
SD SMPTE
HIGH
LOW
DVB-ASI
X
HIGH
NOT SMPTE OR DVB-ASI
(Data-Through mode)*
LOW
LOW
*NOTE: See Section 3.8 for more detail on Data-Through mode
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3.6 SMPTE Functionality
The GS9090B is in SMPTE mode once the device has detected two SMPTE TRS sync
words. The GS9090B will remain in SMPTE mode until six SMPTE TRS sync words fail to
be detected.
TRS word detection is a continuous process, and the device will identify both 8-bit and
10-bit TRS words.
In Auto mode, the GS9090B sets the SMPTE_BYPASS pin HIGH to indicate that it has
locked to a SMPTE input data stream. When operating in Manual mode, the DVB_ASI pin
must be set LOW and the SMPTE_BYPASS pin must be set HIGH in order to enable
SMPTE operation.
3.6.1 SMPTE Descrambling and Word Alignment
The GS9090B performs NRZI-to-NRZ decoding, descrambling according to SMPTE
259M-C, and word alignment of the data to the TRS sync words when in SMPTE mode.
NOTE: When 8-bit data is embedded into the SMPTE signal, the source must have the
two LSBs of the 10-bit stream set to logic LOW in order for word alignment to function
correctly.
3.6.2 Internal Flywheel
The GS9090B has an internal flywheel for the generation of internal / external timing
signals, the detection and correction of certain error conditions, and the automatic
detection of video standards. The flywheel is only operational in SMPTE mode.
The flywheel 'learns' the video standard by timing the horizontal and vertical reference
information contained in the TRS ID words of the received video stream. The flywheel
maintains information about the total line length, active line length, total number of
lines per field / frame, and total active lines per field / frame for the received video
stream. Full synchronization of the flywheel to the received video standard therefore
requires one complete video frame.
Once synchronization has been achieved, the flywheel will continue to monitor the
received TRS timing information to maintain synchronization.
The FW_EN input pin controls the synchronization mechanism of the flywheel. When
this input signal is LOW, the flywheel will re-synchronize all pixel and line based
counters on every received TRS ID word.
When FW_EN is set to logic HIGH, re-synchronization occurs when the flywheel detects
three to four consecutive video lines containing mistimed TRS information. This
provides a measure of noise immunity to internal and external timing signal generation.
The flywheel will be disabled if the device loses lock, or a LOW-to-HIGH transition
occurs on the RESET pin.
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3.6.3 Switch Line Lock Handling
The principle of switch line lock handling is that the switching of synchronous video
sources will only disturb the horizontal timing and alignment of the stream, whereas the
vertical timing remains in synchronization.
3.6.3.1 Automatic Switch Line Lock Handling
The GS9090B also implements automatic switch line lock handling. By utilizing both the
synchronous switch point defined in SMPTE RP168, and the automatic video standards
detect function, the device automatically re-synchronizes the flywheel at the switch
point. This will occur whether or not the device has detected TRS word errors. Word
alignment re-synchronization will also take place at this time.
Automatic switch line lock handling will occur regardless of the setting of the FW_EN
pin.
The switch line is defined as follows:
•
for 525 line interlaced systems: re-sync takes place at the end of lines 10 & 273
•
for 625 line interlaced systems: re-sync takes place at the end of lines 6 & 319
A full list of 270Mb/s video standards and switching lines is shown in Table 3-3.
At every PCLK cycle the device samples the FW_EN pin. When the FW_EN pin is set
LOW anywhere within the active line, the flywheel will re-synchronize immediately to
the next TRS word.
3.6.3.2 Manual Switch Line Lock Handling
The ability to manually re-synchronize the flywheel is also important when switching
asynchronous sources or to implement other non-standardized video switching
functions.
To account for the horizontal disturbance caused by a synchronous switch, it is
necessary to re-synchronize the flywheel immediately after the switch has taken place.
Rapid re-synchronization of the GS9090B to the new video standard can be achieved by
disabling the flywheel (setting the FW_EN pin to logic LOW) after the switch, and
re-enabling the flywheel after the next TRS word.
Table 3-3: Switch Line Position for 270MB/s Digital Systems
System
Video Format
Sampling
Signal
Standard
Parallel
Interface
Serial Interface
Switch Line
Number
SDTI
720x576/50 (2:1)
4:2:2
BT.656
BT.656 + 305M
259M-C
6, 319
720x483/59.94 (2:1)
4:2:2
125M
125M + 305M
259M-C
10, 273
525
720x483/59.94 (2:1)
4:2:2
125M
125M
259M-C
10, 273
625
720x576/50 (2:1)
4:2:2
BT.656
125M
259M-C
6, 319
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3.6.4 HVF Timing Signal Generation
The GS9090B extracts timing parameters, and outputs them to the F, V and H pins, from
either the received TRS signals (FW_EN = LOW) or from the internal flywheel-timing
generator (FW_EN = HIGH).
Horizontal blanking period (H), vertical blanking period (V), and field odd / even timing
(F) are extracted and are available for output on any of the multi-function output port
pins, if so programmed (see Section 3.12).
The H signal timing is configurable via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line-based blanking, or TRS-based blanking
(see Table 3-14 in Section 3.9.8).
Active line-based blanking is enabled when the H_CONFIG bit is set LOW. In this mode,
the H output is HIGH for the entire horizontal blanking period, including the EAV and
SAV TRS words. This is the default H timing used by the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H output
will be HIGH for the entire horizontal blanking period as indicated by the H bit in the
received TRS ID words.
The timing of these signals is shown in Figure 3-3.
NOTE 1: When the internal FIFO is configured for video mode, the H, V, and F signals
will be timed to the data output from the FIFO (see Section 3.10.1).
NOTE 2: When the GS9090B is configured for Low-latency mode, the H, V, and F output
timing will be TRS-based as shown in Section 3.13. Active line-based timing is not
available in this mode, and the setting of the H_CONFIG host interface bit will be
ignored.
PCLK
Y/Cr/Cb DATA OUT
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(sav)
H
V
F
H SIGNAL TIMING:
H_CONFIG = LOW
H_CONFIG = HIGH
Figure 3-3: H,V,F Timing
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3.7 DVB-ASI Functionality
DVB_ASI functionality is only supported in Manual mode.
In Manual mode, the DVB_ASI pin must be set to logic HIGH in order to enable DVB-ASI
operation. The input SMPTE_BYPASS pin will be ignored but should not be left floating.
When using DVB-ASI mode, the use of the application circuit in Figure 3-4 is required.
The use of this application circuit will prevent the internal PLL from false locking to a
DVB-ASI signal harmonic rather than the 270MHz fundamental. This application circuit
will detect the false lock state and restart the on-chip PLL. The application circuit does
this by detecting if the LOCKED pin has been de-asserted for longer than ~700μs, and if
so resets the PLL by discharging the loop filter capacitor through a CMOS switch.
The applications circuit below show how this can be implemented by using a STG719
switch as a reference. Other low leakage CMOS switches may also be substituted within
the circuit.
STG719
1
In
1
6
S2
2
5
D
4
S1
LF+
6
5
LF-
GS9090B
GS9091B
RESTART_PLL
3
STG719
LOCKED
OUT
IN
FPGA or
Microcontroller
GPIO
Figure 3-4: GS9090B False Lock Restart Circuit
The circuit above can be implemented using either a small state machine in an FPGA or
general purpose I/O on a microcontroller in combination with some firmware.
Typically, a system using the GS9090B will have an existing FPGA and/or
microcontroller that may have some spare I/O that can be used to implement the false
lock restart circuit. The choice of method will depend on what spare system resources
are available. In either case, the waveform shown in Figure 3-5 on page 30 represents
how the PLL restart must be driven. The delay values of 700μs and 20μs are nominal but
the values can be longer. In the case where the SDI inputs are not driven with a valid
DVB-ASI signal, the RESTART_PLL signal should be repeated indefinitely as long as
LOCKED remains de-asserted.
DDI
VALID DVB-ASI INPU T SIGNA L
VALID DVB-ASI INPU T SIGNA L
POWER_OK
LOCKED
RESTART_PLL
~700μs
~20μs
~700μs
~20μs
Figure 3-5: GS9090B False Lock Restart Circuit Waveforms of False Lock After
Power-up and False Lock After a Signal Switch.
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3.7.1 DVB-ASI 8b/10b Decoding
The GS9090B will word align the data to the K28.5 sync characters, and 8b/10b decode
and bit-swap the data to achieve bit alignment with the data outputs.
NOTE: DVB-ASI sync words must be immediately followed by an MPEG packet header
for word alignment to correctly function.
The extracted 8-bit data will be presented to DOUT [7:0], bypassing all internal SMPTE
mode data processing.
3.7.2 Status Signal Outputs
In DVB-ASI mode, the DOUT9 and DOUT8 pins will be configured as DVB-ASI status
signals WORDERR and SYNCOUT respectively.
SYNCOUT will be HIGH whenever a K28.5 sync character is present on the output.
WORDERR will be HIGH whenever the device has detected an illegal 8b/10b code word
or there is a running disparity error.
3.8 Data-Through Functionality
The GS9090B may be configured to operate as a simple serial-to-parallel converter. In
this mode, the data is output to the parallel output without performing any decoding,
descrambling, or word-alignment.
Data-Through functionality is enabled when the AUTO/MAN, SMPTE_BYPASS, and
DVB_ASI input pins are set to logic LOW. Under these conditions, the GS9090B allows
270Mb/s input data not conforming to SMPTE or DVB-ASI streams to be reclocked and
deserialized. If the device is in Data-Through mode, and the reclocker locks to the data
stream, the LOCKED pin will be representative of the serial digital input data frequency.
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3.9 Additional Processing Features
The GS9090B contains additional processing features that are available in SMPTE mode
only (see Section 3.6).
3.9.1 FIFO Load Pulse
To aid in the implementation of auto-phasing and line synchronization functions, the
GS9090B will generate a FIFO load pulse to reset line-based FIFO storage. This FIFO_LD
signal is available for output on one of the multi-function output port pins, if so
programmed (see Section 3.12).
The FIFO_LD pulse is an active LOW signal which will assert LOW for one PCLK period,
generating a FIFO write reset signal. This signal is co-timed to the SAV XYZ code word
present on the output data bus. This ensures that the next PCLK cycle will correspond
with the first active sample of the video line.
NOTE: When the internal FIFO of the GS9090B is set to operate in video mode, the
FIFO_LD pulse can be used to drive the RD_RESET input to the device (see
Section 3.10.1).
Figure 3-6 shows the default timing relationship between the FIFO_LD signal and the
output video data.
PCLK
Y'CbCr DATA
3FF
000
000
XYZ
FIFO_LD
Figure 3-6: FIFO_LD Pulse Timing
3.9.1.1 Programmable FIFO Load Position
The position of the FIFO_LD pulse can be moved in PCLK increments from its default
position at the SAV XYZ code word to a maximum of one full line from the default
position. The offset number of PCLK's must be programmed in the
FIFO_LD_POSITION[12:0] internal register (address 28h), via the host interface.
The FIFO_LD_POSITION[12:0] register is designed to accommodate the longest SD line
length. If a value greater than the maximum line length at the operating SD standard is
programmed in this register, the FIFO_LD pulse will not be generated.
After a device reset, the FIFO_LD_POSITION[12:0] register is set to zero and the FIFO_LD
pulse will assume the default timing.
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3.9.2 Ancillary Data Detection and Indication
The GS9090B will detect all types of ancillary data in either the vertical or horizontal
data spaces. The ANC status signal is provided to indicate the position of ancillary data
in the output data stream. This signal is available for output on the multi-function output
port pins (see Section 3.12).
The ANC status signal is synchronous with PCLK and can be used as a clock enable to
external logic, or as a write enable to an external FIFO or other memory device. The ANC
signal will be asserted HIGH whenever ancillary data is detected in the video data
stream (see Figure 3-7). Both 8-bit and 10-bit ancillary data preambles will be detected
by the GS9090B.
NOTE: When the internal FIFO is configured for video mode, the ANC signal will be
timed to the data output from the FIFO (see Section 3.10.1).
PCLK
Y'CbCr DATA
000
3FF
3FF
DID
DBN
DC
ANC DATA
ANC DATA
CSUM
BLANK
ANC
Figure 3-7: ANC Status Signal
3.9.2.1 Programmable Ancillary Data Detection
The GS9090B will detect all types of ancillary data by default. In addition, up to five
different ancillary data types can be programmed for detection. This is accomplished by
programming the ANC_TYPE registers with the DID and/or SDID values, via the host
interface, for each data type to be detected (see Table 3-4).
The GS9090B will compare the received DID and/or SDID with the programmed values
and assert ANC only if an exact match is found.
If the DID or SDID values are set to zero in the ANC_TYPE register, a comparison or
match for that codeword will not be made. For example, if the DID is programmed but
the SDID is set to zero, the device will detect all ancillary data types matching the DID
value, regardless of the SDID. If both DID and SDID values are non-zero, then the
received ancillary data type must match both the DID and SDID cases before the device
will assert ANC HIGH.
In the case where all five DID and SDID values are set to zero, the GS9090B will detect
all ancillary data types. This is the default setting after a device reset.
If greater than one, but less than five, DID and/or SDID values have been programmed,
then only those matching ancillary data types will be detected and indicated.
NOTE: See SMPTE 291M for a definition of ancillary data terms.
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Table 3-4: Host Interface Description for Programmable Ancillary Data Type registers
Register Name
Bit
Name
Description
R/W
Default
ANC_TYPE 1
Address: 0Ah
15-8
ANC_TYPE1[15:8]
Used to program the DID for ancillary data
detection at ANC output
R/W
0
7-0
ANC_TYPE1[7:0]
Used to program the SDID for ancillary data
detection at ANC output. Should be set to
zero if no SDID is present in the ancillary data
packet to be detected.
R/W
0
15-8
ANC_TYPE2[15:8]
Used to program the DID for ancillary data
detection at ANC output
R/W
0
7-0
ANC_TYPE2[7:0]
Used to program the SDID for ancillary data
detection at ANC output. Should be set to
zero if no SDID is present in the ancillary data
packet to be detected.
R/W
0
15-8
ANC_TYPE3[15:8]
Used to program the DID for ancillary data
detection at ANC output
R/W
0
7-0
ANC_TYPE3[7:0]
Used to program the SDID for ancillary data
detection at ANC output. Should be set to
zero if no SDID is present in the ancillary data
packet to be detected.
R/W
0
15-8
ANC_TYPE4[15:8]
Used to program the DID for ancillary data
detection at ANC output
R/W
0
7-0
ANC_TYPE4[7:0]
Used to program the SDID for ancillary data
detection at ANC output. Should be set to
zero if no SDID is present in the ancillary data
packet to be detected.
R/W
0
15-8
ANC_TYPE5[15:8]
Used to program the DID for ancillary data
detection at ANC output
R/W
0
7-0
ANC_TYPE5[7:0]
Used to program the SDID for ancillary data
detection at ANC output. Should be set to
zero if no SDID is present in the ancillary data
packet to be detected.
R/W
0
ANC_TYPE 2
Address: 0Bh
ANC_TYPE 3
Address: 0Ch
ANC_TYPE 4
Address: 0Dh
ANC_TYPE 5
Address: 0Eh
3.9.3 EDH Packet Detection
The GS9090B will determine if EDH packets are present in the incoming video data and
assert the EDH_DETECT output status signal appropriately.
EDH_DETECT will be set HIGH when EDH packets have been detected and will remain
HIGH until EDH packets are no longer present. The signal will be set LOW at the end of
the vertical blanking (falling edge of V) if an EDH packet has not been received and
detected during vertical blanking.
EDH_DETECT can be programmed to be available for output on the multi-function
output port pins (see Section 3.12). The EDH_DETECT bit is also available in the
DATA_FORMAT register at address 04h (see Table 3-7).
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3.9.4 EDH Flag Detection
As described in Section 3.9.3, the GS9090B can detect EDH packets in the received data
stream. The EDH flags for ancillary data, active picture, and full field areas are extracted
from the detected EDH packets and placed in the EDH_FLAG_IN register at address 02h
(Table 3-5).
When the EDH_FLAG_UPDATE bit in the DATA_FORMAT register 04h (Table 3-7) is set
HIGH, the GS9090B will update the ancillary data, full field, and active picture EDH flags
according to SMPTE RP165. The updated EDH flags are available in the EDH_FLAG_OUT
register at address 03h (Table 3-6). The EDH packet output from the device will contain
the updated flags.
One set of flags is provided for both fields 1 and 2. Field 1 flag data will be overwritten
by field 2 flag data.
When EDH packets are not detected, the UES flags in the EDH_FLAG_OUT register will
be set HIGH to signify that the received signal does not support Error Detection and
Handling. In addition, the EDH_DETECT bit will be set LOW. These flags are set
regardless of the setting of the EDH_FLAG_UPDATE bit.
EDH_FLAG_OUT and EDH_FLAG_UPDATE may be read by the host interface at any
time during the received frame except on the lines defined in SMPTE RP165, where
these flags are updated.
The GS9090B will indicate the CRC validity for both active picture and full field CRCs.
The AP_CRC_V bit in the DATA_FORMAT register indicates the active picture CRC
validity, and the FF_CRC_V bit indicates the full field CRC validity (see Table 3-7). When
EDH_DETECT = LOW, these bits will be cleared.
The EDH_FLAG_OUT and EDH_FLAG_UPDATE register values remain set until
overwritten by the decoded flags in the next received EDH packet in the following field.
When an EDH packet is not detected during vertical blanking, the flag registers will be
cleared at the end of the vertical blanking period.
Table 3-5: Host Interface Description for EDH Flag Registers
Register Name
Bit
Name
Description
R/W
Default
EDH_FLAG_IN
15
–
Not Used
–
–
14
ANC-UES_IN
Ancillary Unknown Error Status Flag
R
0
13
ANC-IDA_IN
Ancillary Internal device error Detected Already Flag.
R
0
12
ANC-IDH_IN
Ancillary Internal device error Detected Here Flag.
R
0
11
ANC-EDA_IN
Ancillary Error Detected Already Flag.
R
0
10
ANC-EDH_IN
Ancillary Error Detected Here Flag.
R
0
9
FF-UES_IN
Full Field Unknown Error Status Flag.
R
0
8
FF-IDA_IN
Full Field Internal device error Detected Already Flag.
R
0
7
FF-IDH_IN
Full Field Internal device error Detected Here Flag.
R
0
Address: 02h
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Table 3-5: Host Interface Description for EDH Flag Registers (Continued)
Register Name
Bit
Name
Description
R/W
Default
6
FF-EDA_IN
Full Field Error Detected Already Flag.
R
0
5
FF-EDH_IN
Full Field Error Detected Here Flag.
R
0
4
AP-UES_IN
Active Picture Unknown Error Status Flag.
R
0
3
AP-IDA_IN
Active Picture Internal device error Detected Already
Flag.
R
0
2
AP-IDH_IN
Active Picture Internal device error Detected Here
Flag
R
0
1
AP-EDA_IN
Active Picture Error Detected Already Flag.
R
0
0
AP-EDH_IN
Active Picture Error Detected Here Flag.
R
0
R/W
Default
Table 3-6: Host Interface Description for EDH Flag Registers
Register Name
Bit
Name
Description
EDH_FLAG_OUT
15
–
Not Used
–
–
14
ANC-UES
Ancillary Unknown Error Status Flag
R
0
13
ANC-IDA
Ancillary Internal device error Detected Already Flag.
R
0
12
ANC-IDH
Ancillary Internal device error Detected Here Flag.
R
0
11
ANC-EDA
Ancillary Error Detected Already Flag.
R
0
10
ANC-EDH
Ancillary Error Detected Here Flag.
R
0
9
FF-UES
Full Field Unknown Error Status Flag.
R
0
8
FF-IDA
Full Field Internal device error Detected Already Flag.
R
0
7
FF-IDH
Full Field Internal device error Detected Here Flag.
R
0
6
FF-EDA
Full Field Error Detected Already Flag.
R
0
5
FF-EDH
Full Field Error Detected Here Flag.
R
0
4
AP-UES
Active Picture Unknown Error Status Flag.
R
0
3
AP-IDA
Active Picture Internal device error Detected Already
Flag.
R
0
2
AP-IDH
Active Picture Internal device error Detected Here
Flag
R
0
1
AP-EDA
Active Picture Error Detected Already Flag.
R
0
0
AP-EDH
Active Picture Error Detected Here Flag.
R
0
Address: 03h
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Table 3-7: Host Interface Description for Data Format Register
Register
Name
DATA_FORMAT
Address: 04h
Bit
Name
Description
R/W
Default
15-12
–
Not Used
–
–
11
EDH_FLAG_UPDATE
When set HIGH, the device will update the ancillary
data, full field, and active picture EDH flags
according to SMPTE RP165.
R/W
0
10
AP_CRC_V
Active Picture CRC Valid bit.
R
0
9
FF_CRC_V
Full Field CRC Valid bit.
R
0
8
EDH_DETECT
Set HIGH by the device when EDH packets are
detected in the incoming video data.
R
0
7
VERSION_352M
Indicates whether decoded SMPTE 352M packet is
version 0 or version 1. See Section 3.9.5.
R
0
6-5
–
Not Used
–
–
4
STD_LOCK
Standard Lock bit. This bit will be set HIGH when the
flywheel has achieved full synchronization to the
received video standard. See Section 3.9.6.
R
0
3-0
DATA_FORMAT[3:0]
Displays the data format being carried on the serial
digital interface. See Section 3.9.6.1.
R
0
3.9.5 SMPTE 352M Payload Identifier
The GS9090B can receive and detect the presence of the SMPTE 352M payload
identifier.
Upon detection of this packet, the device will extract the four words contained in the
packet to the VIDEO_FORMAT_OUT_A and VIDEO_FORMAT_OUT_B registers at
addresses 10h and 0fh (Table 3-8). The device will also indicate the version of the
payload packet in bit 7 of the DATA_FORMAT register (Table 3-7). When bit 7 is set
HIGH the received SMPTE 352M packet is version 1, otherwise it is version 0.
The VIDEO_FORMAT registers will only be updated if the received checksum is the
same as the locally calculated checksum.
If the device loses lock to the input data stream (LOCKED = LOW), or if the
SMPTE_BYPASS pin is asserted LOW, the VIDEO_FORMAT_OUT_A and
VIDEO_FORMAT_OUT_B registers will be cleared to zero, indicating an undefined
format. This is also the default setting after a device reset.
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Table 3-8: Host Interface Description for SMPTE 352M Payload Identifier Registers
Register Name
Bit
Name
Description
VIDEO_FORMAT_OUT_B
Address: 10h
15-8
SMPTE 352M Byte 4
7-0
VIDEO_FORMAT_OUT_A
Address: 0Fh
R/W
Default
Data will be available in this register when
Video Payload Identification Packets are
detected in the data stream.
R
0
SMPTE 352M Byte 3
Data will be available in this register when
Video Payload Identification Packets are
detected in the data stream.
R
0
15-8
SMPTE 352M Byte 2
Data will be available in this register when
Video Payload Identification Packets are
detected in the data stream.
R
0
7-0
SMPTE 352M Byte 1
Data will be available in this register when
Video Payload Identification Packets are
detected in the data stream.
R
0
3.9.6 Automatic Video Standard and Data Format Detection
The GS9090B can detect the input video standard and data format by using the timing
parameters extracted from the received TRS ID. Total samples per line, active samples
per line, total lines per frame, and active lines per field are all calculated and presented
to the host interface via the RASTER_STRUCTURE registers (Table 3-9).
Also associated with the RASTER_STRUCTURE registers is the STD_LOCK status bit. The
GS9090B will set STD_LOCK HIGH when the flywheel has achieved full
synchronization to the received video standard. STD_LOCK is stored in the
DATA_FORMAT register (Table 3-7).
The four RASTER_STRUCTURE registers, as well as the STD_LOCK status bit will default
to zero after a device reset, or if the device loses lock to the input data stream (LOCKED
= LOW).
Table 3-9: Host Interface Description for Raster Structure Registers
Register Name
Bit
Name
Description
RASTER_STRUCTURE1
Address: 11h
15-11
–
10-0
RASTER_STRUCTURE2
Address: 12h
RASTER_STRUCTURE3
Address: 13h
RASTER_STRUCTURE4
Address: 14h
R/W
Default
Not Used
–
–
RASTER_STRUCTURE1[10:0]
Total Lines Per Frame
R
0
15-13
–
Not Used
–
–
12-0
RASTER_STRUCTURE2[12:0]
Total Words Per Line
R
0
15-13
–
Not Used
–
–
12-0
RASTER_STRUCTURE3[12:0]
Words Per Active Line
R
0
15-11
–
Not Used
–
–
10-0
RASTER_STRUCTURE4[10:0]
Active Lines Per Field
R
0
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3.9.6.1 Data Format Indication
The GS9090B can extract the data format being carried on the serial digital interface (i.e.
SDTI, SDI, or DVB-ASI). This information is represented by bits 0 to 3 of the
DATA_FORMAT register (Table 3-7).
DATA_FORMAT[3:0] register codes are shown in Table 3-10.
The DATA_FORMAT[3:0] register defaults to Fh (undefined) after a system reset. The
register will also be set to its default value if the device is not locked (LOCKED = LOW),
or if both SMPTE_BYPASS and DVB_ASI pins are LOW.
Table 3-10: Data Format Register Codes
Data Format[3:0]
Data Format
Applicable Standards
0h
SDTI DVCPRO - No ECC
SMPTE 321M
1h
SDTI DVCPRO - ECC
SMPTE 321M
2h
SDTI DVCAM
SMPTE 322M
3h
SDTI CP
SMPTE 326M
4h
Other SDTI fixed block size
–
5h
Other SDTI variable block size
–
6h
SDI
–
7h
DVB-ASI
–
8h ~ Eh
Reserved
–
Unknown data format
–
Fh
3.9.7 Error Detection and Indication
The GS9090B contains a number of error detection functions to enhance operation of
the device when operating in SMPTE mode. These functions, except lock error detection,
will not be available in DVB-ASI mode (Section 3.7) or Data-Through mode (Section 3.8).
The ERROR_STATUS register is at address 01h (Table 3-11). All bits, except the
LOCK_ERR bit, will be cleared at the start of each video field or when read by the host
interface, whichever condition occurs first.
All bits, with the exception of the LOCK_ERR, will also be cleared if a change in the video
standard is detected, if the device loses lock to the input data stream (LOCKED = LOW),
or if the SMPTE_BYPASS pin is asserted LOW.
The ERROR_STATUS register, including the LOCK_ERR bit, will be set LOW during a
system reset (RESET = LOW).
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The ERROR_MASK register (Table 3-12) is available to indivudally mask each error type
in the ERROR_STATUS register. Each error type may be individually masked by setting
its corresponding bit HIGH. The bits of the ERROR_MASK register will default to '0' after
a device reset, thus allowing all error types to be detected.
The DATA_ERROR signal pin indicates the status of the ERROR_STATUS register. This
output pin is an inverted logical OR of each error status flag stored in the
ERROR_STATUS register. DATA_ERROR will be set LOW by the device when an error
condition that has not been masked is detected.
Table 3-11: Host Interface Description for Error Status Register
Register Name
Bit
Name
Description
ERROR_STATUS
15-7
–
6
Address: 01h
R/W
Default
Not Used
–
–
VD_STD_ERR
Video Standard Error Flag. Set HIGH when a
mismatch between the received SMPTE 352M
packets (version 1 or version 0) and the
calculated video standard occurs.
R
0
5
FF_CRC_ERR
Full Field CRC Error Flag. Set HIGH when a Full
Field (FF) CRC mismatch has been detected in
Field 1 or 2
R
0
4
AP_CRC_ERR
Active Picture CRC Error Flag. Set HIGH when
an Active Picture (AP) CRC mismatch has been
detected in Field 1 or 2.
R
0
3
LOCK_ERR
Lock Error Flag. Set HIGH whenever the
LOCKED pin is LOW (indicating the device is not
correctly locked).
R
0
2
CS_ERR
Checksum Error Flag. Set HIGH when ancillary
data packet checksum error has been detected.
R
0
1
SAV_ERR
Start of Active Video Error Flag. Set HIGH when
TRS errors are detected in either 8-bit or 10-bit
TRS words.
R
0
0
EAV_ERR
End of Active Video Error Flag. Set HIGH when
TRS errors are detected in either 8-bit or 10-bit
TRS words.
R
0
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Table 3-12: Host Interface Description for Error Mask Register
Register Name
Bit
Name
Description
ERROR_MASK
15-7
–
Not Used
6
VD_STD_ERR_MASK
Address: 25h
R/W
Default
–
–
Video Standard Error Flag Mask bit.
R/W
0
FF_CRC_ERR_MASK
Full Field CRC Error Flag Mask bit.
R/W
0
4
AP_CRC_ERR_MASK
Active Picture CRC Error Flag Mask bit
R/W
0
3
LOCK_ERR_MASK
Lock Error Flag Mask bit.
R/W
0
2
CS_ERR_MASK
Checksum Error Flag Mask bit.
R/W
0
1
SAV_ERR_MASK
Start of Active Video Error Flag Mask bit.
R/W
0
0
EAV_ERR_MASK
End of Active Video Error Flag Mask bit.
R/W
0
5
3.9.7.1 Video Standard Error Detection
If a mismatch between the decoded SMPTE 352M packets and the calculated video
standard occurs, the GS9090B will indicate a video standard error by setting the
VD_STD_ERR bit of the ERROR_STATUS register HIGH. The device will detect errors in
both version 1 and version 0 352M packets.
3.9.7.2 EDH CRC Error Detection
The GS9090B calculates the Full Field (FF) and Active Picture (AP) CRC words according
to SMPTE RP165 in support of Error Detection and Handling packets in SD signals.
These calculated CRC values are compared with the received CRC values. If a mismatch
is detected, the error is flagged in the AP_CRC_ERR and/or FF_CRC_ERR bits of the
ERROR_STATUS register. These two flags are shared between fields 1 and 2.
The AP_CRC_ERR bit will be set HIGH when an active picture CRC value mismatch has
been detected in field 1 or 2. The FF_CRC_ERR bit will be set HIGH when a full field CRC
value mismatch has been detected in field 1 or 2.
EDH CRC errors will only be indicated when the device has correctly received EDH
packets.
SMPTE RP165 specifies the calculation ranges and scope of EDH data for standard 525
and 625 component digital interfaces. The GS9090B will utilize these standard ranges by
default.
If the received video format does not correspond to 525 or 625 digital component video
standards as determined by the flywheel pixel and line counters, the ranges will be
based on the line and pixel ranges programmed by the host interface. In the absence of
user-programmed calculation ranges, the ranges will be determined from the received
TRS timing information.
The registers available to the host interface for programming EDH calculation ranges
include active picture and full field line/pixel start and end positions for both fields
(Table 3-13). These registers default to '0' after a device reset.
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If any or all of these register values are zero, then the EDH CRC calculation ranges will
be determined from the flywheel generated timing. The first active and full field pixel
will always be the first pixel after the SAV TRS code word. The last active and full field
pixel will always be the last pixel before the start of the EAV TRS code words.
Table 3-13: Host Interface Description for EDH Calculation Range Registers
Register Name
Bit
Name
Description
AP_LINE_START_F0
Address: 15h
15-11
–
Not Used
10-0
AP_LINE_START_F0[10:0]
Field 0 Active Picture start line data
used to set EDH calculation range
outside of SMPTE RP 165 values.
15-11
–
Not Used
10-0
AP_LINE_END_F0[10:0]
Field 0 Active Picture end line data
used to set EDH calculation range
outside of SMPTE RP 165 values.
15-11
–
Not Used
10-0
AP_LINE_START_F1[10:0]
Field 1 Active Picture start line data
used to set EDH calculation range
outside of SMPTE RP 165 values.
15-11
–
Not Used
10-0
AP_LINE_END_F1[10:0]
Field 1 Active Picture end line data
used to set EDH calculation range
outside of SMPTE RP 165 values.
15-11
–
Not Used
10-0
FF_LINE_START_F0[10:0]
Field 0 Full Field start line data used to
set EDH calculation range outside of
SMPTE RP 165 values.
15-11
–
Not Used
10-0
FF_LINE_END_F0[10:0]
Field 0 Full Field end line data used to
set EDH calculation range outside of
SMPTE RP 165 values.
15-11
–
Not Used
10-0
FF_LINE_START_F1[10:0]
Field 1 Full Field start line data used to
set EDH calculation range outside of
SMPTE RP 165 values.
15-11
–
Not Used
10-0
FF_LINE_END_F1[10:0]
Field 1 Full Field end line data used to
set EDH calculation range outside of
SMPTE RP 165 values.
15-13
–
Not Used
12-0
AP_PIXEL_START_F0[12:0]
Field 0 Active Picture start pixel data
used to set EDH calculation range
outside of SMPTE RP 165 values.
AP_LINE_END_F0
Address: 16h
AP_LINE_START_F1
Address: 17h
AP_LINE_END_F1
Address: 18h
FF_LINE_START_F0
Address: 19h
FF_LINE_END_F0
Address: 1Ah
FF_LINE_START_F1
Address: 1Bh
FF_LINE_END_F1
Address: 1Ch
AP_PIXEL_START_F0
Address: 1Dh
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R/W
Default
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
42 of 72
Table 3-13: Host Interface Description for EDH Calculation Range Registers (Continued)
Register Name
Bit
Name
Description
AP_PIXEL_END_F0
Address: 1Eh
15-13
–
Not Used
12-0
AP_PIXEL_END_F0[12:0]
Field 0 Active Picture end pixel data
used to set EDH calculation range
outside of SMPTE RP 165 values.
15-13
–
Not Used
12-0
AP_PIXEL_START_F1[12:0]
Field 1 Active Picture start pixel data
used to set EDH calculation range
outside of SMPTE RP 165 values.
15-13
–
Not Used
12-0
AP_PIXEL_END_F1[12:0]
Field 1 Active Picture end pixel data
used to set EDH calculation range
outside of SMPTE RP 165 values.
15-13
–
Not Used
12-0
FF_PIXEL_START_F0[12:0]
Field 0 Full Field start pixel data used
to set EDH calculation range outside
of SMPTE RP 165 values.
15-13
–
Not Used
12-0
FF_PIXEL_END_F0[12:0]
Field 0 Full Field end pixel data used to
set EDH calculation range outside of
SMPTE RP 165 values.
15-13
–
Not Used
12-0
FF_PIXEL_START_F1[12:0]
Field 1 Full Field start pixel data used
to set EDH calculation range outside
of SMPTE RP 165 values.
15-13
–
Not Used
12-0
FF_PIXEL_END_F1[12:0]
Field 1 Full Field end pixel data used to
set EDH calculation range outside of
SMPTE RP 165 values.
AP_PIXEL_START_F1
Address: 1Fh
AP_PIXEL_END_F1
Address: 20h
FF_PIXEL_START_F0
Address: 21h
FF_PIXEL_END_F0
Address: 22h
FF_PIXEL_START_F1
Address: 23h
FF_PIXEL_END_F1
Address: 24h
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R/W
Default
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
–
–
R/W
0
43 of 72
3.9.7.3 Lock Error Detection
The LOCKED pin of the GS9090B asserts HIGH when the device has correctly locked to
the received data stream (see Section 3.5.1).
The GS9090B will also indicate lock error to the host interface when LOCKED = LOW by
setting the LOCK_ERR bit in the ERROR_STATUS register HIGH (Table 3-11).
3.9.7.4 Ancillary Data Checksum Error Detection
The GS9090B will calculate checksums for all received ancillary data types and compare
the calculated values to the received checksum words. If a mismatch is detected, the
CS_ERR bit of the ERROR_STATUS register will be set HIGH (Table 3-11).
Although the GS9090B will calculate and compare checksum values for all ancillary
data types by default, the host interface may be programmed to check only certain types
of ancillary data checksums, as described in Section 3.9.2.1.
3.9.7.5 TRS Error Detection
TRS error flags are generated by the GS9090B when the received TRS H timing does not
correspond to the internal flywheel timing, or when the received TRS Hamming codes
are incorrect.
These errors are flagged via the SAV_ERR and/or EAV_ERR bits of the ERROR_STATUS
register (Table 3-11). Both 8-bit and 10-bit SAV and EAV errors are handled by the
GS9090B.
NOTE: H timing based TRS errors will only be detected if the FW_EN pin is set HIGH. F &
V timing errors are not detected or corrected.
3.9.8 Additional Processing Functions
The GS9090B contains an additional processing block which is available in SMPTE mode
only. The IOPROC_EN pin must be set HIGH to enable these functions. These functions,
which are all enabled by default, may be enabled or disabled individually by setting bits
0 to 3 in the IOPROC_DISABLE register (Table 3-14).
NOTE: After a device reset, these functions will revert to their default values.
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Table 3-14: Host Interface Description for Internal Processing Disable Register
Register Name
Bit
Name
Description
IOPROC_DISABLE
15-10
–
Not Used
9
ANC_PKT_EXT
Ancillary Packet Extraction. When the FIFO is
configured for Ancillary Data Extraction mode, this
bit must be set HIGH to begin extraction.
Address: 00h
R/W
Default
–
–
R/W
0
NOTE: Setting ANC_PKT_EXT LOW will not
automatically disable ancillary data extraction (see
Section 3.10.3.1).
8-7
FIFO_MODE[1:0]
FIFO Mode: These bits control which mode the
internal FIFO is operating in (see Table 3-15)
R/W
0
6
H_CONFIG
Horizontal sync timing output configuration. Set
LOW for active line blanking timing. Set HIGH for H
blanking based on the H bit setting of the TRS word.
See Figure 3-3 in Section 3.6.4.
R/W
0
Not Used.
5-4
3
ILLEGAL_REMAP
Illegal Code re-mapping. Correction of illegal code
words within the active picture. Set HIGH to disable.
The IOPROC_EN pin must be set HIGH.
R/W
0
2
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical
Redundancy Check (CRC) error correction insertion.
Set HIGH to disable. The IOPROC_EN pin must be set
HIGH.
R/W
0
1
ANC_CSUM_INS
Ancillary Data Checksum insertion. Set HIGH to
disable. The IOPROC_EN pin must be set HIGH.
R/W
0
0
TRS_INS
Timing Reference Signal Insertion. The device will
correct TRS based errors when set LOW (see
Section 3.9.8.4). The IOPROC_EN pin must also be
HIGH.
R/W
0
Set this bit HIGH to disable.
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3.9.8.1 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the GS9090B
will remap all codes within the active picture between the values 3FCh and 3FFh to
3FBh. All codes within the active picture area between the values 00h and 03h will be
re-mapped to 04h. In addition, 8-bit TRS and ancillary data preambles will be remapped
to 10-bit values.
3.9.8.2 EDH CRC Error Correction
If the EDH_CRC_INS bit of the IOPROC_DISABLE register is set LOW, the GS9090B will
calculate and overwrite the active picture and full field CRC words into the EDH data
packets received by the device.
Additionally, when EDH_CRC_INS is LOW, the device will set the active picture and full
field CRC ‘V’ bits HIGH in the EDH packet (see Section 3.9.4). The AP_CRC_V and
FF_CRC_V register bits will only report the received EDH validity flags.
EDH CRC calculation ranges are described in Section 3.9.7.2.
NOTE: Although the GS9090B will modify and insert EDH CRC words and EDH packet
checksums, the device will only update EDH error flags when the EDH_FLAG_UPDATE
bit is set HIGH (see Section 3.9.4).
3.9.8.3 Ancillary Data Checksum Error Correction
If the ANC_CSUM_INS bit of the IOPROC_DISABLE register is set LOW, ancillary
checksum error correction and insertion is enabled, and the GS9090B will calculate and
overwrite ancillary data checksums for all ancillary data words by default. If the
Ancillary Data type has been specified in the ANC_TYPE registers of the host interface
(see Section 3.9.2.1), only the checksums for the ancillary data programmed will be
updated.
3.9.8.4 TRS Error Correction
If the TRS_INS bit of the IOPROC_DISABLE register is set LOW, TRS error correction and
insertion is enabled. In this mode, the GS9090B will calculate and overwrite 10-bit TRS
code words as required.
TRS code word generation will be performed using the timing parameters generated by
the flywheel to provide an element of noise immunity, and will only take place if the
flywheel in enabled (FW_EN = HIGH).
NOTE: Only H timing based errors will be corrected (see Section 3.9.7.5).
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3.10 Internal FIFO Operation
The GS9090B contains an internal video line-based FIFO, which can be programmed to
work in any of the following modes:
1. Video Mode,
2. DVB-ASI Mode,
3. Ancillary Data Extraction Mode, or
4. Bypass Mode
The FIFO can be configured to one of the four modes by using the host interface to set
the FIFO_MODE[1:0] bits of the IOPROC_DISABLE register (see Table 3-14 in
Section 3.9.8). The setting of these bits is shown in Table 3-15. To enable the FIFO, the
FIFO_EN pin must be set HIGH. Additionally, if the FIFO is configured for video mode or
ancillary data extraction mode, the IOPROC_EN pin must be set HIGH.
The FIFO is fully asynchronous, allowing simultaneous read and write access. It has a
depth of 2048 words, which will accommodate 1 full line of SD video for both 525 and
625 standards. The FIFO is 15 bits wide: 10 bits for video data and 5 bits for other signals,
such as H, V, F, EDH_DETECT, and ANC.
Table 3-15: FIFO Configuration Bit Settings
FIFO Mode
FIFO_MODE[1:0]
Register Setting
FIFO_EN
Pin Setting
IOPROC_EN
Pin Setting
Video Mode
00b
HIGH
HIGH
DVB-ASI Mode
01b
HIGH
X
Ancillary Data Extraction Mode
10b
HIGH
HIGH
Bypass Mode
11b
X
X
NOTE: ‘X’ signifies ‘don’t care’. The pin is ignored and may be set HIGH or LOW.
3.10.1 Video Mode
The internal FIFO is in video mode when the FIFO_EN and IOPROC_EN pins are set
HIGH, and the FIFO_MODE[1:0] bits in the IOPROC_DISABLE register are configured to
00b. By default, the FIFO_MODE[1:0] bits are set to 00b by the device whenever the
SMPTE_BYPASS pin is set HIGH and the DVB_ASI pin is set LOW (i.e. the device is in
SMPTE mode); however, the FIFO_MODE[1:0] bits may be programed as required.
Figure 3-8 shows the input and output signals of the FIFO when it is configured for video
mode.
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Application Interface
Internal
10-bit Video Data
10-bit Video Data
H
H
FIFO
(Video Mode)
V
V
F
F
ANC
ANC
EDH_DETECT
EDH_DETECT
RD_RESET
WR_RESET
WR_CLK (PCLK)
RD_CLK
Figure 3-8: FIFO in Video Mode
When operating in video mode, the GS9090B will write data sequentially into the FIFO,
starting with the first active pixel in location zero of the memory. In this mode, it is
possible to use the FIFO for clock phase interchange and data alignment / delay. The
extracted H, V, and F information will also be written into the FIFO. The H, V, and F
outputs will be timed to the video data read from the FIFO. (see Section 3.6.4).
The device will ensure write-side synchronization is maintained, according to the
extracted PCLK and flywheel timing information.
Full read-control of the FIFO is made available such that data will be clocked out of the
FIFO on the rising edge of the externally provided RD_CLK signal. When there is a
HIGH-to-LOW transition at the RD_RESET pin, the first pixel presented to the video data
bus will be the first 000 of the SAV (see Figure 3-9). The FIFO_LD pulse may be used to
control the RD_RESET pin.
NOTE: The RD_RESET pulse should not be held LOW for more than one RD_CLK cycle.
RD_CLK
Y'CbCr DATA
3FF
000
000
XYZ
RD_RESET
Figure 3-9: RD_RESET Pulse Timing
In video mode, the ANC output signal will be timed to the data output from the FIFO (see
Section 3.9.2 for more detail).
3.10.2 DVB-ASI Mode
The internal FIFO is in DVB-ASI mode when the FIFO_EN pin is set HIGH, and the
FIFO_MODE[1:0] bits in the IOPROC_DISABLE register are configured to 01b. By
default, the FIFO_MODE[1:0] bits are set to 01b by the device whenever the DVB_ASI
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pin is set HIGH (i.e. the device is in DVB-ASI mode); however, the FIFO_MODE[1:0] bits
may be programed as required.
Figure 3-10 shows the input and output signals of the FIFO when it is configured for
DVB-ASI Mode.
Application Interface
Internal
8-bit MPEG Data
8-bit MPEG Data
WORDERR
SYNCOUT
WORDERR
FIFO
(DVB-ASI Mode)
SYNCOUT
FIFO_EMPTY
FIFO_FULL
WR_CLK
(PCLK gated with SYNCOUT)
RD_CLK
Figure 3-10: FIFO in DVB-ASI Mode
When operating in DVB-ASI mode, the GS9090B's FIFO can be used for clock rate
interchange operation. The extracted 8-bit MPEG packets will be written into the FIFO
at 27MHz based on the SYNCOUT signal from the internal DVB-ASI decoder block. The
SYNCOUT and WORDERR bits are also stored in the FIFO (see Section 3.7.2).
When SYNCOUT goes HIGH, K28.5 stuffing characters have been detected and no data
will be written into the FIFO.
Data is read out of the FIFO using the RD_CLK pin. In DVB-ASI mode, the RD_RESET pin
is not used.
NOTE: With the internal FIFO enabled in DVB-ASI mode, SYNCOUT will always be LOW
since the K28.5 sync characters are not stored in the FIFO.
3.10.2.1 Reading From the FIFO
The FIFO contains internal read and write pointers used to designate which spot in the
FIFO the MPEG packet will be read from or written to. These internal pointers control the
status flags FIFO_EMPTY and FIFO_FULL, which are available for output on the
multi-function output port pins, if so programmed (see Section 3.12).
In the case where the write pointer is originally ahead of the read pointer, the
FIFO_EMPTY flag will be set HIGH when both pointers arrive at the same address (see
block A in Figure 3-12). This flag can be used to determine when to stop reading from the
device.
A write and read pointer offset may be programmed in the FIFO_EMPTY_OFFSET[9:0]
register of the host interface. If an offset value is programmed in this register, the
FIFO_EMPTY flag will be set HIGH when the read and write pointers of the FIFO are at
the same address, and will remain HIGH until the write pointer reaches the programmed
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offset. Once the pointer offset has been exceeded, the FIFO_EMPTY flag will go LOW
(see block B in Figure 3-12).
In the case where the read pointer is originally ahead of the write pointer, the
FIFO_FULL flag will be set HIGH when both pointers arrive at the same address (see
block C in Figure 3-12). This flag can be used to determine when to begin reading from
the device.
A read and write pointer offset may also be programmed in the FIFO_FULL_OFFSET[9:0]
register of the host interface. If an offset value is programmed in this register, the
FIFO_FULL flag will be set HIGH when the read and write pointers of the FIFO are at the
same address, and will remain set HIGH until the read pointer reaches the programmed
offset. Once the pointer offset has been exceeded, the FIFO_FULL flag will be cleared
(see block D in Figure 3-12).
Gating the RD_CLK Using the FIFO_EMPTY Flag
Using the asynchronous FIFO_EMPTY flag to gate RD_CLK requires external clock
gating circuity. The recommended circuit for this application is shown in Figure 3-11.
FIFO_EMPTY
D
RD_CLK
SET
CLR
Q
Q
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
GATED
RD_CLK
RD_CLK
FIFO_EMPTY
GATED
RD_CLK
Figure 3-11: Recommended Circuit to Gate RD_CLK Using the FIFO_EMPTY
Flag
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B
A
Read
Pointer
Read
Pointer
Exmple 1: FIFO Empty Flag Operation when
FIFO_EMPTY[9:0] = 0h
Address
Address
0
Exmple 2: FIFO Empty Flag Operation when
FIFO_EMPTY[9:0] = 3FFh
1023
2047
2047
0
FIFO
FIFO
Write
Pointer
Write
Pointer
FIFO_EMPTY
FIFO_EMPTY
C
D
Read
Pointer
Exmple 4: FIFO Full Flag Operation when FIFO_FULL[9:0] = 3FFh
Read
Pointer
Exmple 3: FIFO Full Flag Operation when
FIFO_FULL[9:0] = 0h
Address
Address
5
0
1023
2047
2047
FIFO
Write
Pointer
Write
Pointer
FIFO_FULL
FIFO_FULL
Figure 3-12: Reading From the FIFO in DVB-ASI Mode
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3.10.3 Ancillary Data Extraction Mode
The internal FIFO is in ancillary data extraction mode when the FIFO_EN and
IOPROC_EN pins are set HIGH, and the FIFO_MODE[1:0] bits in the IOPROC_DISABLE
register are configured to 10b.
Once the FIFO enters ancillary data extraction mode, it takes 2200 PCLKs (82us) to
initialize the FIFO before ancillary data extraction can begin.
In this mode, the FIFO is divided into two separate blocks of 1024 words each. This
allows ancillary data to be written to one side of the FIFO and from the other. Thus, in
each half of the FIFO, the GS9090B will write the contents of the packets up to a
maximum of 1024 8-bit words.
As described in Section 3.9.2.1, up to five specific types of ancillary data to be extracted
can be programmed in the ANC_TYPE registers. If the ANC_TYPE registers are all set to
zero, the device will extract all types of ancillary data.
The entire packet, including the ancillary data flag (ADF), data identification (DID),
secondary data identification (SDID), data count (DC), and checksum word will be
written into the memory. The device will detect ancillary data packet DID's placed
anywhere in the video data stream, including the active picture area.
Additionally, the lines from which the packets are to be extracted from can be
programmed into the ANC_LINE_A[10:0] and ANC_LINE_B[10:0] registers, allowing
ancillary data from a maximum of two lines per frame to be extracted. If only one line
number register is programmed (with the other set to zero), ancillary data packets will
be extracted from one line per frame only. When both registers are set to zero, the device
will extract packets from all lines.
The extracted ancillary data is read through the host interface starting at address 02Ch
up to 42Bh inclusive (1024 words). This must be done while there is a valid video signal
present at the serial input and the device is locked (LOCKED = HIGH).
3.10.3.1 Ancillary Data Extraction and Reading
To start ancillary data extraction, the ANC_PKT_EXT bit of the IOPROC_DISABLE
register must be set HIGH (see Table 3-14 in Section 3.9.8). Packet extraction will begin
in the following frame after this bit has been set HIGH.
NOTE: Ancillary data extraction will not begin until 2200 PCLKs (82us) after the device
has entered into ancillary data extraction mode (FIFO_MODE[1:0] = 10b), regardless of
the setting of the ANC_PKT_EXT bit.
When the FIFO is configured for ancillary data extraction mode, setting the IOPROC_EN
pin LOW will disable packet extraction. If IOPROC_EN is LOW, the setting of the
ANC_PKT_EXT host interface bit will be ignored.
Clearing the ANC_PKT_EXT bit will not automatically disable ancillary data extraction.
To disable ancillary data extraction, switch the FIFO into bypass mode by setting
FIFO_MODE[1:0] = 11b. 2200 PCLK cycles after the device re-enters ancillary data
extraction mode, data extraction will commence immediately if ANC_PKT_EXT is still
HIGH.
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The ANC output flag available on the I/O output pin (see Section 3.12) can be used to
determine the length of the ancillary data extracted and when to begin reading the
extracted data from memory. Recall that ANC is HIGH whenever ancillary data has been
detected.
In addition, the data count (DC) word, which is located three words after the ancillary
data flag (ADF) in the memory, can be read to determine how many valid user data
words (UDW) are present in the extracted packet (see SMPTE 291M for more details).
The DC value can then be used to preset how many address reads must be performed to
obtain only the user data words.
Ancillary data will be written into the first half of the FIFO until it is full or until the
ANC_DATA_SWITCH bit is toggled (i.e. a HIGH-to-LOW or LOW-to-HIGH transition). If
the ANC_DATA_SWITCH bit is not toggled, extracted data will not be written into
memory after the first half of the FIFO is full (see block A in Figure 3-13).
When the ANC_DATA_SWITCH bit is toggled, new extracted data will be written to the
second half starting at address zero (see block B in Figure 3-13). The data in the first half
of the FIFO may still be read.
Once the data in the first half of the FIFO has been read, the ANC_DATA_SWITCH may
be toggled again to enable the second half of the FIFO to be read. The first half of the
FIFO will be cleared, and the device will continue to write ancillary data to the second
half of the FIFO (see block C in Figure 3-13).
If the ANC_DATA_SWITCH bit is toggled again, new extracted data will be written to the
first half starting at address zero (see block D in Figure 3-13). The data in the second half
of the FIFO may still be read.
Toggling ANC_DATA_SWITCH again will clear the second half of the FIFO and restore
the read and write pointers to the situation shown in block A. The switching process
(shown in blocks A to D in Figure 3-13) will continue with each toggle of the
ANC_DATA_SWITCH bit.
NOTE: At least 1100 PCLK cycles (41us) must pass between toggles of the
ANC_DATA_SWITCH bit. Also, the ANC_DATA_SWITCH bit must be toggled at a point
in the video where no extraction is occurring (i.e. the ANC signal is LOW).
By default, the ancillary data is not removed from the video stream. If desired, the
ancillary data may be deleted from the video stream after extraction by setting the
ANC_DATA_DELETE bit of the host interface HIGH. In this case, all existing ancillary
data will be removed and replaced with blanking values. If any of the ANC_TYPE
registers are programmed with a DID and/or a DID and SDID, only the ancillary data
packets with the matching ID's will be deleted from the video stream.
NOTE: After the ancillary data determined by the ANC_TYPE registers has been deleted,
other existing ancillary data may not be contiguous. The device will not concatenate the
remaining ancillary data.
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A
0
Application layer
read pointer
B
0
ANC_DATA
ANC_DATA
Internal write
pointer
0
ANC_DATA
Application layer
read pointer
ANC_DATA
ANC_DATA
Internal write
pointer
0
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
1023
1023
1023
1023
ANC_DATA_SWITCH = HIGH
ANC_DATA_SWITCH = LOW
ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written
to second half of FIFO starting at adress zero. Application layer continues to
read from the first half of the FIFO.
D
C
0
Application layer 0
read pointer
ANC_DATA
Internal write
pointer
0
0
%%
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
Application layer
read pointer
ANC_DATA
Internal write
pointer
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
%%
1023
1023
1023
ANC_DATA_SWITCH = LOW
ANC_DATA_SWITCH toggled LOW. First half of FIFO cleared and ancillary
data read from second half of FIFO. Device continues to write ancillary data
to second half of FIFO.
1023
ANC_DATA_SWITCH = HIGH
ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written to first half of
FIFO starting at address zero. Application layer continues to read from second half
of FIFO. Toggling ANC_DATA_SWITCH back LOW will clear the second half of the
FIFO and go back the situation depicted in box A.
NOTE: At least 1100 PCLK cycles must pass between toggles of the ANC_DATA_SWITCH bit.
The bit must be toggled at a point where no extraction is occuring (i.e. the ANC signal is LOW).
Figure 3-13: Ancillary Data Extraction and Reading
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3.10.4 Bypass Mode
The internal FIFO is in bypass mode when the FIFO_EN or IOPROC_EN pin is set LOW,
or the FIFO_MODE[1:0] bits in the IOPROC_DISABLE register are configured to 11b. By
default, the FIFO_MODE[1:0] bits are set to 11b by the device whenever both the
SMPTE_BYPASS and DVB_ASI pins are LOW; however, the FIFO_MODE[1:0] bits may
be programed as required.
In bypass mode, the FIFO is not inserted into the video path and data is presented to the
output of the device synchronously with the PCLK output. The FIFO will be disabled and
placed in static mode to save power.
3.11 Parallel Data Outputs
The parallel data outputs are clocked out of the device on the rising edge of PCLK as
shown in Figure 3-14.
tOH
tOD
PCLK
50%
VOH
VOH
VOL
VOL
VOH
VOH
VOL
VOL
DOUT[9:0]
CONTROL
SIGNAL OUTPUT
Figure 3-14: PCLK to Data & Control Signal Output Timing
The output data format is defined by the settings of the external SMPTE_BYPASS and
DVB_ASI pins (see Table 3-16). In Manual mode, these pins are set as inputs to the
device. In Auto mode, the GS9090B sets the SMPTE_BYPASS pin as an output status
signal.
Table 3-16: Parallel Data Output Format
Pin Settings
Output Data Format
DOUT[9:0]
SMPTE_BYPASS
DVB_ASI
10-bit Data
DATA
LOW
LOW
10-bit Multiplexed SD
Luma / Chroma
HIGH
LOW
10-bit DVB-ASI
DVB-ASI data
LOW
HIGH
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3.11.1 Parallel Data Bus Output Buffers
The parallel data outputs of the GS9090B are driven by high-impedance buffers that
support both LVTTL and LVCMOS levels. These buffers use either +1.8V or +3.3V,
supplied at the IO_VDD and IO_GND pins. When interfacing with +5V logic levels, the
IO_VDD pins should be supplied with +3.3V. For a low power connection, the IO_VDD
pins may be connected to +1.8V.
All output buffers, including the PCLK output, will be in a high-impedance state when
the RESET signal is asserted LOW.
3.11.2 Parallel Output in SMPTE Mode
When the device is operating in SMPTE mode (see Section 3.6), SMPTE data is output on
the DOUT[9:0] pins.
3.11.3 Parallel Output in DVB-ASI Mode
When operating in DVB-ASI mode (see Section 3.7), the decoded 8-bit data words will be
presented on DOUT[7:0]. DOUT7 = HOUT is the most significant bit of the decoded
transport stream data and DOUT0 = AOUT is the least significant bit. DOUT9 will be
configured as the DVB-ASI status signal WORDERR and DOUT8 as SYNCOUT. See
Section 3.7.2 for a description of these DVB-ASI specific output signals.
3.11.4 Parallel Output in Data-Through Mode
When operating in Data-Through mode (see Section 3.8), the GS9090B presents data to
the output data bus without performing any decoding, descrambling, or
word-alignment.
3.12 Programmable Multi-Function Outputs
The GS9090B has a 4-pin multi-function output port, STAT[3:0]. Each pin can be
programmed to output one of the following signals: H, V, F, FIFO_LD, ANC,
EDH_DETECT, FIFO_FULL, and FIFO_EMPTY.
Table 3-17: Output Signals Available on Multi-Function Output Ports
Output Status Signal
Reference
H
Section 3.6.4
V
Section 3.6.4
F
Section 3.6.4
FIFO_LD
Section 3.9.1
ANC
Section 3.9.2
EDH_DETECT
Section 3.9.3
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Table 3-17: Output Signals Available on Multi-Function Output Ports
FIFO_FULL
Section 3.10.2.1
FIFO_EMPTY
Section 3.10.2.1
Each of the STAT[3:0] pins can be configured individually using the
STAT0_CONFIG[2:0], STAT1_CONFIG[2:0], STAT2_CONFIG[2:0], and
STAT3_CONFIG[2:0] registers. Table 3-18 shows the setting of the IO_CONFIG registers
for each of the available output signals.
Table 3-18: IO_CONFIG Settings
Function
I/O
IO_CONFIG Setting
H
Output
000b
V
Output
001b
F
Output
010b
FIFO_LD
Output
011b
ANC
Output
100b
EDH_DETECT
Output
101b
FIFO_FULL
Output
110b
FIFO_EMPTY
Output
111b
The default setting for each IO_CONFIG register depends on the configuration of the
device and the internal FIFO mode selected. This is shown in Table 3-19.
If the programmed signal is not relevant to the current mode of operation, the output
will be set to a high-impedance state.
Table 3-19: IO_CONFIG Default Configuration
Device Configuration
IO_CONFIG
Register
I/O
Function
Default IO_CONFIG
Setting
SMPTE Functionality
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
FIFO: Video Mode or Ancillary Data
Extraction Mode
STAT0_CONFIG
Output
H
000b
STAT1_CONFIG
Output
V
001b
STAT2_CONFIG
Output
F
010b
STAT3_CONFIG
Output
FIFO_LD
011b
STAT0_CONFIG
Output
FIFO_FULL
110b
STAT1_CONFIG
Output
FIFO_EMPTY
111b
STAT2_CONFIG
Output
High Z
000b
STAT3_CONFIG
Output
High Z
000b
DVB-ASI
DVB_ASI = HIGH
FIFO: DVB-ASI Mode
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Table 3-19: IO_CONFIG Default Configuration
Device Configuration
IO_CONFIG
Register
I/O
Function
Default IO_CONFIG
Setting
Data-Through
SMPTE_BYPASS = LOW
DVB_ASI = LOW
STAT0_CONFIG
Output
High Z
000b
STAT1_CONFIG
Output
High Z
000b
STAT2_CONFIG
Output
High Z
000b
STAT3_CONFIG
Output
High Z
000b
3.13 GS9090B Low-latency Mode
When the IOPROC_EN pin is set LOW, the GS9090B will be set into low-latency mode.
The parallel data will be output with the minimum PCLK latency possible. The FIFO and
all processing blocks except the descrambling and word alignment blocks will be
bypassed when SMPTE_BYPASS is HIGH.
Low-latency mode will also be selected when SMPTE_BYPASS is set LOW, regardless of
the setting of the IOPROC_EN signal (see Table 3-20).
In DVB-ASI mode, the device latency is less than in SMPTE mode.
Table 3-20: Pin Settings in Low-latency Mode
IOPROC_EN Setting
SMPTE_BYPASS Setting
Latency (PCLK Cycles)
LOW
LOW
9
HIGH
LOW
10
LOW
HIGH
10
HIGH
HIGH
25
NOTE: Latency applies to parallel processing core only.
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When the GS9090B is configured for low-latency mode, the H,V, and F output timing
will be based on the incoming TRS codes as shown in Figure 3-15. Active line-based
timing is not available and the setting of the H_CONFIG host interface bit will be ignored.
PCLK
Y/Cr/Cb DATA OUT
3FF
000
XYZ
(eav)
000
3FF
000
000
XYZ
(sav)
H
V
F
Figure 3-15: H,V,F Timing In Low-latency Mode
3.14 GSPI Host Interface
The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to allow
access to the host interface of the GS9090B and/or to provide additional status
information through configuration registers in the device.
The GSPI comprises a serial data input signal SDIN, serial data output signal SDOUT, an
active low chip select CS, and a burst clock SCLK. The burst clock must have a duty cycle
between 40% and 60%.
Because these pins are shared with the JTAG interface port, an additional control signal
pin JTAG/HOST is provided. When JTAG/HOST is LOW, the GSPI interface is enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS signals are provided by the
application interface. The SDOUT pin is a non-clocked loop-through of SDIN and may
be connected to the SDIN of another device, allowing multiple devices to be connected
to the GSPI chain. The interface is illustrated in Figure 3-16.
Application Host
GS9090B
SCLK
CS1
SDOUT
SCLK
CS
SDIN
SDOUT
GS9090B
SCLK
CS2
CS
SDIN
SDIN
SDOUT
Figure 3-16: GSPI Application Interface Connection
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All read or write access to the GS9090B is initiated and terminated by the host processor.
Each access always begins with a 16-bit command word on SDIN indicating the address
of the register of interest. This is followed by a 16-bit data word on SDIN in write mode,
or a 16-bit data word on SDOUT in read mode.
3.14.1 Command Word Description
The command word consists of a 16-bit word transmitted MSB first and contains a
read/write bit, an Auto-Increment bit and a 12-bit address. Figure 3-17 shows the
command word format and bit configurations.
Command words are clocked into the GS9090B on the rising edge of the serial clock
SCLK, which operates in a burst fashion.
When the Auto-Increment bit is set LOW, each command word must be followed by
only one data word to ensure proper operation. If the Auto-Increment bit is set HIGH,
the following data word will be written into the address specified in the command word,
and subsequent data words will be written into incremental addresses from the
previous data word. This facilitates multiple address writes without sending a command
word for each data word.
Auto-Increment may be used for both read and write access.
3.14.2 Data Read and Write Timing
Read and write mode timing for the GSPI interface is shown in Figure 3-19 and
Figure 3-20 respectively. The timing parameters are defined in Table 3-21.
When several devices are connected to the GSPI chain, only one CS must be asserted
during a read sequence.
During the write sequence, all command and following data words input at the SDIN pin
are output at the SDOUT pin as is. Where several devices are connected to the GSPI
chain, data can be written simultaneously to all the devices that have CS set LOW.
Table 3-21: GSPI Timing Parameters
Parameter
Definition
Specification
t0
The minimum duration of time chip select, CS, must be
LOW before the first SCLK rising edge.
1.5 ns
t1
The minimum SCLK period.
12.5 ns
t2
Duty cycle tolerated by SCLK.
t3
Minimum input setup time.
1.5 ns
t4
Write Cycle: the minimum duration of time between
the last SCLK command (or data word if the
Auto-Increment bit is HIGH) and the first SCLK of the
data word.
37.1 ns
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Table 3-21: GSPI Timing Parameters (Continued)
Parameter
Definition
Specification
t5
Read Cycle: the minimum duration of time between
the last SCLK command (or data word if the
Auto-Increment bit is HIGH) and the first SCLK of the
data word.
148.4 ns
t5
Read Cycle - FIFO in ANC Extraction Mode: the
minimum duration of time between the last SCLK
command (or data word if the Auto-Increment bit is
HIGH) and the first SCLK of the data word.
222.6 ns
t6
Minimum output hold time.
1.5 ns
t7
The minimum duration of time between the last SCLK
of the GSPI transaction and when CS can be set HIGH.
37.1 ns
t8
Minimum input hold time.
1.5 ns
MSB
R/W RSV
LSB
RSV
A10
A11
AutoInc
A8
A9
RSV = Reserved. Must be set to zero.
A7
A5
A6
A4
A3
A2
A1
A0
R/W: Read command when R/W = 1
Write command when R/W = 0
Figure 3-17: Command Word Format
MSB
D15
LSB
D14
D12
D13
D11
D10
D8
D9
D7
D5
D6
D4
D2
D3
D1
D0
Figure 3-18: Data Word Format
t5
SCLK
t6
CS
SDIN
R/W
RSV
RSV
AutoInc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDOUT
R/W
RSV
RSV
AutoInc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3-19: GSPI Read Mode Timing
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t0
t7
t4
t1
SCLK
t3
CS
t2
t8
SDIN
R/W
RSV
RSV
AutoInc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDOUT
R/W
RSV
RSV
AutoInc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3-20: GSPI Write Mode Timing
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3.14.3 Configuration and Status Registers
Table 3-22 summarizes the GS9090B's internal status and configuration registers.
All of these registers are available to the host via the GSPI and are all individually
addressable.
Where status registers contain less than the full 16 bits of information, two or more
registers may be combined at a single logical address.
Table 3-22: GS9090B Internal Registers
Address
Register Name
Reference
00h
IOPROC_DISABLE
Section 3.9.8
01h
ERROR_STATUS
Section 3.9.7
02h
EDH_FLAG_IN
Section 3.9.4
03h
EDH_FLAG_OUT
Section 3.9.4
04h
DATA_FORMAT
Section 3.9.6.1
05h
IO_CONFIG
Section 3.12
06h
FIFO_EMPTY_OFFSET
Section 3.10.2.1
07h
FIFO_FULL_OFFSET
Section 3.10.2.1
08h - 0Eh
ANC_TYPE
Section 3.9.2
11h - 14h
RASTER_STRUCTURE
Section 3.9.6
15h - 24h
EDH_CALC_RANGES
Section 3.9.7.2
25h
ERROR_MASK
Section 3.9.7
28h
FIFO_LD_POSITION
Section 3.9.1.1
02Ch - 42Bh
INTERNAL FIFO
Section 3.10.3
3.15 JTAG Operation
When the JTAG/HOST pin is set HIGH, the host interface port (as described in
Section 3.14) will be configured for JTAG test operation. In this mode, pins 16, 17, 19, and
20 become TMS, TCK, TDO, and TDI respectively. In addition, the RESET pin will operate
as the test reset pin, as well as resetting the internal registers.
Boundary scan testing using the JTAG interface will be possible in this mode.
There are two methods in which JTAG can be used on the GS9090B:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly; or
2. Under control of the host for applications such as system power self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other devices
driving the digital I/O pins. If the tests are to be applied only at ATE, this can be
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accomplished with tri-state buffers used in conjunction with the JTAG/HOST input
signal. This is shown in Figure 3-21.
Alternatively, if the test capabilities are to be used in the system, the host may still
control the JTAG/HOST input signal, but some means for tri-stating the host must exist
in order to use the interface at ATE. This is represented in Figure 3-22.
Application HOST
GS9090B
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_EN
In-circuit ATE probe
Figure 3-21: In-Circuit JTAG
Application HOST
GS9090B
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_EN
Tri-State
In-circuit ATE probe
Figure 3-22: System JTAG
3.16 Device Power Up
The GS9090B has a recommended power supply sequence. To ensure correct power up,
power the CORE_VDD pins before the IO_VDD pins. In order to initialize all internal
operating conditions to their default state the RESET pin must be held LOW for a
minimum of treset = 1ms. (See Figure 3-23)
Device pins can be driven prior to power up without causing damage.
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CORE_VDD
+1.71V
+1.8V
treset
treset
Reset
Reset
RESET
Figure 3-23: Reset pulse
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4. References & Relevant Standards
SMPTE 125M
Component video signal 4:2:2 – bit parallel interface
SMPTE 259M
10-Bit 4:2:2 Component and 4fSC Composite Digital Signals - Serial Digital
Interface
SMPTE 291M
Ancillary Data Packet and Space Formatting
SMPTE 293M
720 x 483 active line at 59.94 Hz progressive scan production – digital
representation
SMPTE 305.2M
Serial Data Transport Interface
SMPTE 352M
Video Payload Identification for Digital Television Interfaces
SMPTE RP165
Error Detection Checkwords and Status Flags for Use in Bit-Serial Digital
Interfaces for Television
SMPTE RP168
Definition of Vertical Interval Switching Point for Synchronous Video
Switching
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5. Application Information
5.1 Typical Application Circuit (Part A)
CD
MUTE
EQ_VCC
EQ_VCC
1
13
VCC_D
6.2n
MUTE
VCC_A
SDI
14
15
CD
16
10n
10n
VEE_D
VEE_A
12
EQ_GND
EQ_GND
1u
2
SDO
SDI
11
SDO
GS9074A
75
3
EQ_GND
6
5
7
MCLADJ
VEE_A
BYPASS
37R4
AGC
4
75
SDO
SDI
AGC
1u
EQ_GND
VEE_D
SDO
9
EQ_GND
8
MCLADJ
470n
470n
EQ_GND
10
BYPASS
EQ_GND
NOTE: All resistors in Ohms, capacitors in Farads,
and inductors in Henrys, unless otherwise noted.
NOTE: For up-to-date component values and detailed operation of the equalizer, please
see the GS9074A data sheet.
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5.2 Typical Application Circuit (Part B)
+1.8V
10n
DATA_ERRORb
GND_D
LOCKED
1u
+1.8V _A
DVB_ASI
0
0
SMPTE_BYPASSb
(NP)
JTAG_HOSTb
+1.8V_A
1u
100k
RESETb
100n
+1.8V
GND_D
IOPROC_EN
10n
GND_A
AUTO_MANb
GND_A
GND_A
FW_EN
10n
FIFO_EN
GND_A
+3.3V
NP (0)
GND_D
PCLK
DVB_ASI
LOCKED
FIFO_EN
FW_EN
AUTO_MANb
SMPTE_BYPASSb
(NP)
IO_VDD
0
4n7
LF+
VCO_GND
LB_CONT
VCO_VDD
FIFO_EN
FW_EN
AUTO/MAN
SMPTE_BYPASS
CORE_GND
DVB_ASI
LOCKED
CORE_VDD
PCLK
IO_VDD
56
55
54
53
52
51
50
49
48
47
46
45
44
43
10n
NP
GND_A
(NP)
10n
1u
+1.8V_A
1u
DATA[9..0]
GND_D
GND_A
GND_A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1u
DDI
DDIb
1u
10n
EQ_GND
1u
EQ_GND
GND_A
IOPROC_EN
JTAG_HOSTb
RESETb
LFPLL_GND
PLL_VDD
BUFF_VDD
DDI
DDI
BUFF_GND
TERM
NC
VBG
NC
IOPROC_EN
JTAG/HOST
RESET
IO_GND
DOUT9
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
RD_RESET
RD_CLK
IO_VDD
GS9090B
42
41
40
39
38
37
36
35
34
33
32
31
30
29
DOUT9
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
RD_RESETb
RD_CLK
CORE_VDD
CS_TMS
SCLK_TCK
CORE_GND
SDOUT_TDO
SDIN_TDI
IO_VDD
DATA_ERROR
STAT0
IO_GND
STAT1
STAT2
STAT3
IO_GND
IO_VDD
10n
1u
15
16
17
18
19
20
21
22
23
24
25
26
27
28
+1.8V
GND_D
10n
GND_D
(NP)
(NP)
(NP)
(NP)
(NP)
(NP)
DATA_ERRORb
GND_D
STAT2
STAT1
STAT0
IO_VDD
1u
GND_D
STAT3
10n
IO_VDD
GND_D
100K
100K
100K
SCLK_TCK
SDIN_TDI
SDOUT_TDO
CSb_TMS
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6. Package & Ordering Information
6.1 Package Dimensions
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6.2 Recommended PCB Footprint
0.25
0.50
0.55
7.70
6.76
CENTER PAD
NOTE: All dimensions
are in millimeters.
6.76
7.70
The Center Pad of the PCB footprint should be connected to the CORE_GND plane by a
minimum of 25 vias.
NOTE: Suggested dimensions only. Final dimensions should conform to customer
design rules and process optimizations.
6.3 Packaging Data
Parameter
Value
Package Type
8mm x 8mm 56-pin QFN
Package Drawing Reference
JEDEC M0220
Moisture Sensitivity Level
3
Junction to Case Thermal Resistance, θj-c
12.2°C/W
Junction to Air Thermal Resistance, θj-a (at zero airflow)
25.8°C/W
Psi, Ψ
9.1°C/W
Pb-free and RoHS compliant
Yes
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Pin 1 ID
GS9090B
XXXXE3
YYWW
Instructions :
GS9090B
Package Mark
XXXX
Last 4 digits (excluding decimal) of SAP
Batch Assembly (FIN) as listed on Packing
Slip
YYWW
Date Code
E3
Pb free and Green indicator
Figure 6-1: Package marking
6.4 Ordering Information
Part Number
Package
Temperature Range
GS9090BCNE3
56-pin QFN
0oC to 70oC
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DOCUMENT IDENTIFICATION
CAUTION
DATA SHEET
ELECTROSTATIC SENSITIVE DEVICES
The product is in production. Gennum reserves the right to make changes at
any time to improve reliability, function or design, in order to provide the best
product possible.
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
STATIC-FREE WORKSTATION
GENNUM CORPORATION
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Street Addresses: 4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada
Phone: +1 (905) 632-2996
Fax: +1 (905) 632-2055
Email: [email protected]
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Fax: +1 (613) 270-0429
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Fax: +1 (408) 392-9404
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Phone: +44 (1279) 714170
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Seoul, Korea 138-828
Phone: +82-2-414-2991
Fax: +82-2-414-2998
Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of
the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent
infringement.
All other trademarks mentioned are the properties of their respective owners.
GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.
© Copyright 2006 Gennum Corporation. All rights reserved. Printed in Canada.
www.gennum.com
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