ISSI IS41LV32256 256K x 32 (8-Mbit) EDO DYNAMIC RAM 3.3V, 100/83/66 MHz ® SEPTEMBER 2000 DESCRIPTION The ISSI IS41LV32256 is organized in a 262,122 x 32-bit FEATURES • 262,144-word by 32-bit organization • Single +3.3V ± 0.3V power supply • Four CAS inputs for Byte Write and Byte Read control • Refresh modes: RAS-Only, CAS-Before-RAS (CBR), and Hidden • 512-cycle refresh in 8 ms • Fast Page Mode with Extended Data Out • 100-pin PQFP, TQFP package CMOS Dynamic Random Access Memory. Four CAS signals facilitate execution of Byte Read and Byte Write operations. A very fast EDO cycle time of 10 ns allows an operating frequency of 100 MHz and makes the IS41LV32256 an ideal frame buffer memory for graphics applications. The IS41LV32256 is compatible with JEDEC standard SGRAMs. This 8-Mbit EDO memory offers a significantly lower latency and a faster memory cycle than the SGRAM. ISSI's IS41LV32256 3.3V 256K x 32 device is pin/voltage compatible with all standard SGRAM parts. The IS41LV32256 is available in a 100-pin PQFP and TQFP package. KEY TIMING PARAMETERS Parameter -28 -30 -35 Unit Max. RAS Access Time (tRAC) 28 30 35 ns Max. CAS Access Time (tCAC) 9 9 10 ns Max. Column Address Access Time (tAA) 15 16 18 ns Max. OE Access Time (tOE) 9 9 10 ns Min. Read/Write Cycle Time (tRC) 48 53 60 ns Min. EDO Cycle Time (tPC) 12 12 15 ns ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. Rev. A 09/29/00 1 ISSI IS41LV32256 ® FUNCTIONAL BLOCK DIAGRAM OE OE CLOCK GENERATOR WE WE CLOCK GENERATOR Data I/O Buffers CAS0 CAS1 CAS2 CAS3 I/O0-31 CAS CLOCK GENERATOR AY0-AY8 COLUMN DECODERS A0-A8 SENSE AMPLIFIERS CONTROLS AX0-AX8 RAS 2 ROW DECODERS 512 x 32 512 MEMORY ARRAY 256K x 32 RAS CLOCK GENERATOR Integrated Silicon Solution, Inc. Rev. A 09/29/00 ISSI IS41LV32256 ® PIN CONFIGURATIONS I/O2 GND I/O1 I/O0 Vcc NC NC NC NC NC NC NC NC NC NC GND I/O31 I/O30 GND I/O29 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100-Pin PQFP, TQFP Vcc Vcc 15 66 GND GND 16 65 Vcc I/O20 17 64 I/O11 I/O21 18 63 I/O10 GND 19 62 GND I/O22 20 61 I/O9 I/O23 21 60 I/O8 Vcc 22 59 Vcc CAS0 23 58 NC CAS2 24 57 CAS3 WE 25 56 CAS1 NC 26 55 NC NC 27 54 NC RAS 28 53 OE NC 29 52 NC NC 30 51 A8 50 67 A7 14 49 I/O12 Vcc A6 68 48 13 A5 I/O13 I/O19 47 69 A4 12 46 GND I/O18 GND 70 45 11 NC I/O14 GND 44 71 NC 10 43 I/O15 I/O17 NC 72 42 9 NC Vcc I/O16 41 73 NC 8 40 I/O24 Vcc NC 74 39 7 NC I/O25 I/O7 38 75 NC 6 37 GND I/O6 NC 76 36 5 NC I/O26 GND 35 77 Vcc 4 34 I/O27 I/O5 A3 78 33 3 A2 Vcc I/O4 32 I/O28 79 31 80 2 A1 1 Vcc A0 I/O3 PIN DESCRIPTIONS A0-A8 RAS Address Inputs Row Address Strobe CAS0 Column Address Strobe for First Byte (I/O0-I/O7) CAS1 Column Address Strobe for Second Byte (I/O8-I/O15) CAS2 Column Address Strobe for Third Byte (I/O16-I/O23) CAS3 Column Address Strobe for Fourth Byte (I/O24-I/O31) WE Write Enable OE Output Enable I/O0-I/O31 Data Inputs/Outputs Vcc +3.3V Supply GND Ground NC No Connection: This pin should be left unconnected or tied to ground. Integrated Silicon Solution, Inc. Rev. A 09/29/00 3 ISSI IS41LV32256 ® TRUTH TABLE Function RAS CAS0 CAS1 CAS2 CAS3 WE OE Address I/O High-Z DOUT I/O0-7=DOUT; I/O8-31=High-Z I/O0-7=High-Z; I/O8-15=DOUT; I/O16-31=High-Z I/O0-15=High-Z; I/O16-23=DOUT; I/O24-31=High-Z I/O0-23=High-Z; I/O24-31=DOUT Standby Read: Double Word Read: 1st Byte H L L H L L H L H H L H H L H X H H X L L X ROW/COL ROW/COL Read: 2nd Byte L H L H H H L ROW/COL Read: 3rd Byte L H H L H H L ROW/COL Read: 4th Byte L H H H L H L ROW/COL Write: Double Word (Early) Write: 1st Byte (Early) L L L L L H L H L H L L X X ROW/COL ROW/COL Write: 2nd Byte (Early) L H L H H L X ROW/COL Write: 3rd Byte (Early) L H H L H L X ROW/COL Write: 4th Byte (Early) L H H H L L X ROW/COL L H∅L H∅L H∅L H∅L H∅L H∅L H∅L H∅L L L H L L H∅L H∅L H∅L H∅L H∅L H∅L H∅L H∅L L L H L Read-Write(1,2) L L (2) Fast-Page-Mode Read: EDO 1st Cycle: L H∅L Subsequent Cycles: L H∅L Fast-Page-Mode Read: High-Z(2) 1st Cycle: L H∅L Subsequent Cycles: L H∅L Fast-Page-Mode Write: (Early)(1) 1st Cycle: L H∅L Subsequent Cycles: L H∅L Fast-Page-Mode Read-Write(1,2) 1st Cycle: L H∅L Subsequent Cycles: L H∅L Hidden Refresh Read(2) L∅H∅L L (1) Hidden Refresh Write L∅H∅L L RAS-Only Refresh L H (3) CBR Refresh H∅L L L H∅L L∅H H∅L H L H∅L H L H∅L H H∅L H∅L H H∅L H∅L L X H∅L L X H∅L H∅L L∅H H∅L H∅L L∅H L H L L L X H X X L X X ROW/COL ROW/COL COL ROW/COL COL ROW/COL COL ROW/COL COL ROW/COL ROW/COL ROW X DIN I/O0-7=DIN; I/O8-31=X I/O0-8=X; I/O8-15=DIN; I/O16-31=X I/O0-15=X; I/O16-23=DIN; I/O24-31=X I/O0-23=X; I/O24-31=DIN DOUT∅DIN DOUT DOUT DOUT DOUT DIN DIN DOUT∅DIN DOUT∅DIN DOUT DIN∅High-Z High-Z High-Z Notes: 1. BYTE WRITE may be executed with CAS0, CAS1, CAS2 or CAS3 active. 2. BYTE READ may be executed with CAS0, CAS1, CAS2 or CAS3 active. 3. Only one CAS signal (CAS0, CAS1, CAS2 or CAS3) must be active. 4 Integrated Silicon Solution, Inc. Rev. A 09/29/00 ISSI IS41LV32256 ® POWER-ON The initial application of the VCC supply requires a 200-µs wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges. ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters tA tSTG VT IOUT PD Ambient Temperature Under Bias Storage Temperature Voltage Relative to GND Data Output Current Power Dissipation Rating Unit –1.0 to +80 –50 to +125 –1.0 to +5.5 50 1.0 °C °C V mA W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS(1) (TA = 0°C to 70°C) Symbol VCC VIH VIL Parameter Min. Typ. Max. Unit Power Supply Input High Voltage Input Low Voltage 3.0 2.4 –0.5 3.3 — — 3.6 VCC + 0.5 0.4 V V V Note: 1. Voltages are referenced to GND. CAPACITANCE(1,2) Symbol Parameter CIN CIO Input Capacitance Data Input/Output Capacitance Max. Unit 5 7 pF pF Notes: 1. Capacitance is sampled and 100% tested. 2. Test conditions: TA = 25°C, f = 1 MHz, VCC = 3.3V. Integrated Silicon Solution, Inc. Rev. A 09/29/00 5 ISSI IS41LV32256 ® DC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ± 0.3V) -28 Min. Max. Symbol Parameter Condition VIH VIL VOH VOL ILI ILO Input HIGH (Logic 1) Voltage, All Inputs Input LOW (Logic 1) Voltage, All Inputs Output HIGH Voltage Output LOW Voltage Input Leakage Current Output Leakage Current ICC1 Average Power Supply Current (Operating)(2,3,15,16) Power Supply Current (Standby) Average Power Supply Current (RAS-Only Refresh)(2,3,15,16) Average Power Supply Current (Fast Page Mode)(2,3,15,18) Average Power Supply Current (CAS-before-RAS Refresh)(2,3,15.16) — 2.0 Vcc + 0.5 — –0.5 0.8 IOH = –2 mA 2.4 Vcc IOL = 2 mA 0 0.4 0V < VIN < VCC –10 10 0V < VOUT < 3.6V; –10 10 Output Disable RAS, CAS Cycling; — 250 tRC = Min. RAS, CAS = VIH — 2.5 RAS = Cycling; — 250 CAS = VIH; tRC = Min. RAS = VIL; — 230 CAS = Cycling; tPC = Min. RAS = Cycling; — 250 CAS-before-RAS CMOS Standby Current RAS, CAS = VCC –0.2V ICC2 Icc3 ICC4 ICC5 ICC6 — 600 -30 Min. Max. -35 Min. Max. 2.0 Vcc + 0.5 –0.5 0.8 2.4 Vcc 0 0.4 –10 10 –10 10 2.0 Vcc + 0.5 –0.5 0.8 2.4 Vcc 0 0.4 –10 10 –10 10 Units V V V V µA µA — 250 — 240 mA — — 2.5 250 — — 2.5 240 mA mA — 230 — 220 mA — 250 — 240 mA — 600 — 600 µA AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -28 Symbol tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR tRAD tRAL tRPC tRSH 6 Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(26) CAS Precharge Time(9, 25) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time(27) -30 -35 Min. 48 — — — 28 17 5 5 28 10 0 6 0 5 21 Max. — 28 9 15 10K — 10K — — 19 — — — — — Min. 53 — — — 30 18 5 5 30 10 0 6 0 5 22 Max. — 30 9 16 10K — 10K — — 21 — — — — — Min. 60 — — — 35 20 6 5 35 11 0 7 0 6 25 Max. — 35 10 18 10K — 10K — — 28 — — — — — 8 15 0 7 13 — — — 8 16 0 7 15 — — — 9 18 0 8 16 — — — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Continued) Integrated Silicon Solution, Inc. Rev. A 09/29/00 ISSI IS41LV32256 ® AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -28 Symbol tCLZ tCRP tOD tOE tOEHC tOEP tOES tRCS tRRH tRCH tWCH tWCR tWP tWPZ tRWL tCWL tWCS tDHR tACH tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tCHO tOFF tWHZ Parameter CAS to Output in Low-Z(15, 29) CAS to RAS Precharge Time(21) Output Disable Time(19, 28, 29) Output Enable Time(15, 16) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) EDO Page Mode READ or WRITE Cycle Time(24) RAS Pulse Width in EDO Page Mode Access Time from CAS Precharge(15) EDO Page Mode READ-WRITE Cycle Time(24) Data Output Hold after CAS LOW Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) Output Disable Delay from WE -30 -35 Min. 3 5 3 — 10 10 5 0 0 Max. — — 15 9 — — — — — Min. 3 5 3 — 10 10 5 0 0 Max. — — 15 9 — — — — — Min. 3 5 3 — 10 10 5 0 0 Max. — — 15 10 — — — — — Units ns ns ns ns ns ns ns ns ns 0 — 0 — 0 — ns 5 21 — — 5 22 — — 5 24 — — ns ns 5 10 7 5 0 21 15 — — — — — — — 5 10 7 5 0 22 15 — — — — — — — 6 10 8 8 0 24 15 — — — — — — — ns ns ns ns ns ns ns 5 — 5 — 6 — ns 0 5 73 40 — — — — 0 5 73 40 — — — — 0 6 80 45 — — — — ns ns ns ns 18 24 12 — — — 18 25 12 — — — 20 30 15 — — — ns ns ns 28 — 34 100K 17 — 30 — 35 100K 18 — 35 — 40 100K 21 — ns ns ns 3 3 — 7 3 3 — 7 3 3 — 15 ns ns 3 10 3 10 3 15 ns (Continued) Integrated Silicon Solution, Inc. Rev. A 09/29/00 7 ISSI IS41LV32256 ® AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -28 Symbol tCLCH tCSR tCHR tORD tREF tT Parameter Last CAS going LOW to First CAS returning HIGH(23) CAS Setup Time (CBR REFRESH)(30, 20) CAS Hold Time (CBR REFRESH)(30, 21) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Refresh Period (512 Cycles) Transition Time (Rise or Fall)(2, 3) -30 -35 Min. 10 Max. — Min. 10 Max. — Min. 10 Max. — Units ns 5 7 0 — — — 5 7 0 — — — 8 8 0 — — — ns ns ns — 1 8 50 — 1 8 50 — 1 8 50 ms ns Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD • tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD • tRWD (MIN), tAWD • tAWD (MIN) and tCWD • tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first χCAS edge to transition LOW. 21. The last χCAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling χCAS edge to first rising χCAS edge. 24. Last rising χCAS edge to next cycle’s last rising χCAS edge. 25. Last rising χCAS edge to first falling χCAS edge. 26. Each χCAS must meet minimum pulse width. 27. Last χCAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. 8 Integrated Silicon Solution, Inc. Rev. A 09/29/00 ISSI IS41LV32256 ® READ CYCLE (Outputs Controlled by RAS) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH CAS0-CAS3 tAR tRAD tASR ADDRESS tRAH tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Don't Care Integrated Silicon Solution, Inc. Rev. A 09/29/00 9 ISSI IS41LV32256 ® READ CYCLE (Outputs Controlled by CAS) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH CAS0-CAS3 tAR tRAD tRAH tASR ADDRESS tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES 10 Don't Care Integrated Silicon Solution, Inc. Rev. A 09/29/00 ISSI IS41LV32256 ® EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS0-CAS3 tAR tRAD tRAH tASR ADDRESS tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don't Care Integrated Silicon Solution, Inc. Rev. A 09/29/00 11 ISSI IS41LV32256 ® READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS0-CAS3 tAR tRAD tRAH tASR tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tRCS tAWD tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tDH Valid DIN Open tOD tOEH OE Undefined Don't Care 12 Integrated Silicon Solution, Inc. Rev. A 09/29/00 ISSI IS41LV32256 ® EDO-PAGE-MODE READ CYCLE tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tCP tPC(1) tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP CAS0-CAS3 tAR tRAD tASR ADDRESS tASC tCAH tASC Row Column tRAL tCAH tCAH tASC Column Column Row tRAH tRRH tRCS tRCH WE tAA tRAC tCAC tCLZ I/O Open tAA tCPA tCAC tCOH Valid Data tOE tOES tAA tCPA tCAC tCLZ tOFF Valid Data tOEHC Valid Data Open tOE tOD tOES tOD OE tOEP Undefined Don't Care Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. Integrated Silicon Solution, Inc. Rev. A 09/29/00 13 ISSI IS41LV32256 ® EDO-PAGE-MODE EARLY-WRITE CYCLE tRASP tRP RAS tCSH tCRP tPC tCAS, tCLCH tRCD tCP tCAS, tCLCH tRSH tCAS, tCLCH tCP tCP CAS0-CAS3 tAR tACH tCAH tASC tRAD tASR ADDRESS tASC Row Column tRAH tACH tRAL tCAH tACH tCAH tASC Column tCWL tWCS Column tCWL tWCS tWCH tCWL tWCS tWCH tWCH tWP tWP Row tWP WE tWCR tDHR tRWL tDS tDS tDH I/O Valid Data tDS tDH Valid Data tDH Valid Data OE Don't Care 14 Integrated Silicon Solution, Inc. Rev. A 09/29/00 ISSI IS41LV32256 ® EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tCP tPC / tPRWC(1) tCAS, tCLCH tRSH tCAS, tCLCH tCP tCP CAS0-CAS3 tASR tRAH ADDRESS tAR tRAD tASC tCAH Row tASC tCAH Column tRWD tRCS tRAL tCAH tASC Column tCWL tWP Column tRWL tCWL tWP tCWL tWP tAWD tCWD Row tAWD tCWD tAWD tCWD WE tAA tAA tCPA tDH tDS tRAC tCAC tCLZ I/O Open tCAC tCLZ DOUT DIN DIN DOUT tOD tOE tDH tDS tCAC tCLZ DOUT tOD tOE tAA tCPA tDH tDS Open DIN tOD tOE tOEH OE Undefined Don't Care Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. Integrated Silicon Solution, Inc. Rev. A 09/29/00 15 ISSI IS41LV32256 ® EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE) tRASP tRP RAS tCSH tPC tPC tCRP tCAS tRCD tCAS tCP tRSH tCAS tCP tCP CAS0-CAS3 tASR tRAH ADDRESS tAR tRAD tASC Row tCAH tASC tCAH Column (A) tASC Column (B) tRCS tACH tRAL tCAH Column (N) Row tRCH tWCS tWCH WE tAA tRAC tCAC tCPA tCAC tAA tWHZ tCOH I/O Open Valid Data (A) tDS Valid Data (B) tDH DIN Open tOE OE Don't Care 16 Integrated Silicon Solution, Inc. Rev. A 09/29/00 ISSI IS41LV32256 ® AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCP tCAS CAS0-CAS3 tAR tRAD tASR ADDRESS tRAH tCAH tASC Row tASC Column tRCS Column tRCH tRCS WE tAA tRAC tCAC tCLZ Open I/O tWHZ tCLZ Valid Data Open tOE tOD OE Undefined Don't Care RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC CAS0-CAS3 tASR ADDRESS I/O tRAH Row Row Open Don't Care Integrated Silicon Solution, Inc. Rev. A 09/29/00 17 ISSI IS41LV32256 ® CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tCHR tRPC tCP tCHR tRPC tCSR tCSR CAS0-CAS3 Open I/O HIDDEN REFRESH CYCLE (WE = HIGH; OE = LOW)(1) tRAS tRP tRAS RAS tCRP tRCD tASR tRAD tRAH tASC tRSH tCHR CAS0-CAS3 tAR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Open Valid Data tOE tOD tORD OE Undefined Don't Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 18 Integrated Silicon Solution, Inc. Rev. A 09/29/00 ISSI IS41LV32256 ® ORDERING INFORMATION Commercial Range: 0⋅⋅ C to 70⋅⋅ C Speed (ns) 28 30 35 Order Part No. Package IS41LV32256-28PQ IS41LV32256-28TQ IS41LV32256-30PQ IS41LV32256-30TQ IS41LV32256-35PQ IS41LV32256-35TQ PQFP TQFP PQFP TQFP PQFP TQFP ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com Integrated Silicon Solution, Inc. Rev. A 09/29/00 19