LINER LTC2207IUK 16-bit, 105msps/80msps adc Datasheet

LTC2207/LTC2206
16-Bit, 105Msps/80Msps
ADCs
DESCRIPTIO
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FEATURES
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Sample Rate: 105Msps/80Msps
78.2dBFS Noise Floor
100dB SFDR
SFDR >82dB at 250MHz (1.5VP-P Input Range)
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
Single 3.3V Supply
Power Dissipation: 900mW/725mW
Optional Clock Duty Cycle Stabilizer
Out-of-Range Indicator
Pin Compatible Family
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit)
40Msps: LTC2204 (16-Bit)
25Msps: LTC2203 (16-Bit) Single-Ended Clock
10Msps: LTC2202 (16-Bit) Single-Ended Clock
48-Pin 7mm × 7mm QFN Package
U
APPLICATIO S
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The LTC®2207/LTC2206 are 105Msps/80Msps, sampling
16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals up to input frequencies
of 700MHz. The input range of the ADC can be optimized
with the PGA front end.
The LTC2207/LTC2206 are perfect for demanding communications applications, with AC performance that includes
78.2dB Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultralow jitter of 80fsRMS allows undersampling of
high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes) over temperature.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of
clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patents Pending.
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
U
TYPICAL APPLICATIO
LTC2207: 64K Point FFT,
fIN = 14.8MHz, –1dBFS,
PGA = 0, 105Msps
3.3V
SENSE
OVDD
2.2µF
AIN+
1.25V
COMMON MODE
BIAS VOLTAGE
+
ANALOG
INPUT
AIN–
INTERNAL ADC
REFERENCE
GENERATOR
16-BIT
PIPELINED
ADC CORE
S/H
AMP
–
0.5V TO 3.6V
0.1µF
OF
CLKOUT+
CLKOUT–
D15
•
•
•
D0
OUTPUT
DRIVERS
CORRECTION
LOGIC AND
SHIFT REGISTER
AMPLITUDE (dBFS)
VCM
OGND
CLOCK/DUTY
CYCLE
CONTROL
3.3V
VDD
GND
0.1µF
0.1µF
0.1µF
22054 TA01
ENC+
ENC–
PGA
SHDN
DITH
MODE
OE
ADC CONTROL INPUTS
RAND
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
30
40
20
FREQUENCY (MHz)
50
22076 G05
22076fa
1
LTC2207/LTC2206
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
OVDD = VDD (Notes 1, 2)
TOP VIEW
48 GND
47 PGA
46 RAND
45 MODE
44 OE
43 OF
42 D15
41 D14
40 D13
39 D12
38 OGND
37 OVDD
Supply Voltage (VDD) ................................... –0.3V to 4V
Digital Output Ground Voltage (OGND)........ –0.3V to 1V
Analog Input Voltage (Note 3) ......–0.3V to (VDD + 0.3V)
Digital Input Voltage .....................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation............................................ 2000mW
Operating Temperature Range
LTC2207C/LTC2206C ............................... 0°C to 70°C
LTC2207I/LTC2206I ............................. –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V
SENSE 1
VCM 2
VDD 3
VDD 4
GND 5
AIN+ 6
AIN– 7
GND 8
ENC+ 9
ENC– 10
GND 11
VDD 12
36 OVDD
35 D11
34 D10
33 D9
32 D8
31 OGND
30 CLKOUT+
29 CLKOUT–
28 D7
27 D6
26 D5
25 OVDD
VDD 13
VDD 14
GND 15
SHDN 16
DITH 17
D0 18
D1 19
D2 20
D3 21
D4 22
OGND 23
OVDD 24
49
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
EXPOSED PAD IS GND (PIN 49)
MUST BE SOLDERED TO PCB BOARD
TJMAX = 150°C, θJA = 29°C/W
ORDER PART NUMBER
UK PART MARKING*
LTC2207CUK
LTC2206CUK
LTC2207IUK
LTC2206IUK
LTC2207UK
LTC2206UK
LTC2207UK
LTC2206UK
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult factory for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
CONVERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
Integral Linearity Error
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Drift
Differential Analog Input (Note 5) TA = 25°C
Differential Analog Input (Note 5)
Differential Analog Input
(Note 6)
Gain Error
Full-Scale Drift
External Reference
Internal Reference
External Reference
Transition Noise
MIN
●
●
●
●
TYP
MAX
UNITS
±1.2
1.5
±0.3
±1
±10
±4
±4.5
±1
±8.5
LSB
LSB
LSB
mV
µV/°C
±0.2
±30
±15
2.8
±1.5
%FS
ppm/°C
ppm/°C
LSBRMS
22076fa
2
LTC2207/LTC2206
ANALOG INPUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
VIN
VIN, CM
IIN
ISENSE
IMODE
CIN
PARAMETER
Analog Input Range (AIN+ – AIN–)
Analog Input Common Mode
Analog Input Leakage Current
SENSE Input Leakage Current
MODE Pin Pull-Down Current to GND
Analog Input Capacitance
tAP
Sample-and-Hold
Acquisition Delay Time
Sample-and-Hold
Acquisition Delay Time Jitter
Analog Input
Common Mode Rejection Ratio
Full Power Bandwidth
tJITTER
CMRR
BW-3dB
CONDITIONS
3.135V ≤ VDD ≤ 3.465V
Differential Input (Note 7)
0V ≤ AIN+, AIN– ≤ VDD (Note 10)
0V ≤ SENSE ≤ VDD (Note 11)
MIN
10
6.7
1.8
1
UNITS
VP-P
V
µA
µA
µA
pF
pF
ns
80
fs RMS
1V < (AIN+ = AIN–) <1.5V
80
dB
RS ≤ 25Ω
700
MHz
●
●
●
●
1
–1
–3
Sample Mode ENC+ < ENC–
Hold Mode ENC+ > ENC–
TYP
1.5 to 2.25
1.25
MAX
1.5
1
3
DYNAMIC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER
CONDITIONS
SNR
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
Signal-to-Noise Ratio
15MHz Input (2.25V Range, PGA = 0),
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
MIN
SFDR
Spurious Free
Dynamic Range
2nd or 3rd
Harmonic
MAX
MIN
77.9
75.5
●
76.5
76.2
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1),
140MHz Input (1.5V Range, PGA = 1)
LTC2206
TYP
77.8
77.5
75.4
76.5
76.2
77.5
75.3
●
73.8
73.4
76.7
74.8
74.5
73.8
73.4
LTC2207
TYP
MAX
UNITS
77.9
75.5
dBFS
dBFS
77.8
77.5
75.4
dBFS
dBFS
dBFS
77.5
75.3
dBFS
dBFS
76.7
74.8
74.5
dBFS
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
76.2
75.4
76.2
75.4
dBFS
dBFS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
100
100
100
100
dBc
dBc
95
95
100
dBc
dBc
dBc
90
95
dBc
dBc
85
90
89
dBc
dBc
dBc
82
86
dBc
dBc
15MHz Input (2.25V Range, PGA = 0),
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
●
87
86
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1),
140MHz Input (1.5V Range, PGA = 1)
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
95
95
100
88
87
90
95
●
84
83
85
90
89
82
86
84
83
22076fa
3
LTC2207/LTC2206
DYNAMIC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)
SYMBOL PARAMETER
CONDITIONS
SFDR
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
Spurious Free
Dynamic Range
4th Harmonic
or Higher
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
MIN
●
90
Signal-to-Noise
Plus Distortion Ratio
●
88
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (2.25V Range, PGA = 0
15MHz Input (1.5V Range, PGA = 1)
●
76.3
75.9
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
140MHz Input (1.5V Range, PGA = 1)
SFDR
SFDR
Spurious Free
Dynamic Range
at –25dBFS
Dither “OFF”
Spurious Free
Dynamic Range
at –25dBFS
Dither “ON”
MIN
●
MAX
UNITS
dBc
dBc
100
100
dBc
dBc
100
100
dBc
dBc
95
100
dBc
dBc
90
95
90
95
dBc
dBc
77.9
75.5
77.9
75.5
dBFS
dBFS
77.8
77.4
75.4
dBFS
dBFS
dBFS
77.1
75.2
dBFS
dBFS
75.6
74.6
74.3
dBFS
dBFS
dBFS
100
100
90
95
100
77.8
77.4
75.4
88
76.3
75.9
77.1
75.2
73.6
73.2
LTC2207
TYP
100
100
100
100
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
S/(N+D)
MAX
100
100
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
LTC2206
TYP
75.6
74.6
74.3
73.6
73.2
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
74.4
73.9
74.4
73.9
dBFS
dBFS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
105
105
105
105
dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
105
105
105
105
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
105
105
105
105
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
100
100
100
100
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
100
100
100
100
dBFS
dBFS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
115
115
115
115
dBFS
dBFS
115
115
dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
●
100
115
115
100
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
115
115
115
115
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
110
110
110
110
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
105
105
105
105
dBFS
dBFS
22076fa
4
LTC2207/LTC2206
COMMON MODE BIAS CHARACTERISTICS
The ● denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
VCM Output Voltage
VCM Output Tempco
VCM Line Regulation
CONDITIONS
IOUT = 0
IOUT = 0
3.135V ≤ VDD ≤ 3.465V
VCM Output Resistance
–1mA ≤ | IOUT | ≤ 1mA
MIN
1.15
TYP
1.25
40
1
MAX
1.35
UNITS
V
ppm/°C
mV/ V
Ω
2
DIGITAL INPUTS AND DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
ENCODE INPUTS (ENC+, ENC–)
VID
Differential Input Voltage
VICM
Common Mode Input Voltage
RIN
Input Resistance
CIN
Input Capacitance
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Input Current
CIN
Input Capacitance
LOGIC OUTPUTS
OVDD = 3.3V
VOH
High Level Output Voltage
CONDITIONS
MIN
●
(Note 7)
Internally Set
Externally Set (Note 7)
TYP
MAX
0.2
V
V
1.6
1.4
(See Figure 2)
(Note 7)
3.0
kΩ
pF
6
3
●
VDD = 3.3V
VDD = 3.3V
VIN = 0V to VDD
(Note 7)
2
0.8
±10
1.5
V
V
µA
pF
3.299
3.29
0.01
0.10
–50
50
0.4
V
V
V
V
mA
mA
●
●
VDD = 3.3V
IO = –10µA
IO = –200µA
●
IO = 160µA
IO = 1.6mA
●
3.1
UNITS
VOL
Low Level Output Voltage
VDD = 3.3V
ISOURCE
ISINK
OVDD = 2.5V
VOH
VOL
OVDD = 1.8V
VOH
VOL
Output Source Current
Output Sink Current
VOUT = 0V
VOUT = 3.3V
High Level Output Voltage
Low Level Output Voltage
VDD = 3.3V
VDD = 3.3V
IO = –200µA
IO = 1.60mA
2.49
0.1
V
V
High Level Output Voltage
Low Level Output Voltage
VDD = 3.3V
VDD = 3.3V
IO = –200µA
IO = 1.60mA
1.79
0.1
V
V
POWER REQUIREMENTS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER
VDD
Analog Supply Voltage
PSHDN
Shutdown Power
CONDITIONS
●
MIN
LTC2206
TYP
MAX
MIN
LTC2207
TYP
MAX
UNITS
3.135
3.3
3.465
3.135
3.3
3.465
V
SHDN = VDD
0.2
●
0.5
0.2
3.6
0.5
mW
OVDD
Output Supply Voltage
3.6
V
IVDD
Analog Supply Current
DC Input
●
220
265
273
325
mA
PDIS
Power Dissipation
DC Input
●
725
875
900
1,073
mW
22076fa
5
LTC2207/LTC2206
TIMING CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
LTC2206
TYP
MAX
MIN
80
1
LTC2207
TYP
MAX
UNITS
105
MHz
fS
Sampling Frequency
(Note 9)
●
1
tL
ENC Low Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
●
●
5.94
4.06
6.25
6.25
500
500
4.52
3.10
4.762
4.762
500
500
ns
ns
tH
ENC High Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
●
●
5.94
4.06
6.25
6.25
500
500
4.52
3.10
4.762
4.762
500
500
ns
ns
tAP
Sample-and-Hold
Aperture Delay
tD
ENC to DATA Delay
(Note 7)
●
1.3
2.7
4
1.3
2.7
4
ns
tC
ENC to CLKOUT Delay
(Note 7)
●
1.3
2.7
4
1.3
2.7
4
ns
tSKEW
DATA to CLKOUT Skew
(tC-tD) (Note 7)
●
–0.6
0
0.6
–0.6
0
0.6
ns
tOE
DATA Access time
Bus Relinquish time
CL = 5pF (Note 7)
(Note 7)
●
●
5
5
15
15
5
5
15
15
ns
ns
–0.7
Pipeline
Latency
–0.7
7
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 105MHz (LTC2207), 80MHz (LTC2206)
differential ENC+/ENC– = 2VP-P sine wave with 1.6V common mode,
input range = 2.25VP-P with differential drive (PGA = 0), unless otherwise
specified.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
7
ns
Cycles
“best fit straight line” to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3.3V, fSAMPLE = 105MHz (LTC2207) or 80MHz (LTC2206),
input range = 2.25VP-P with differential drive.
Note 9: Recommended operating conditions.
Note 10: The dynamic current of the switched capacitors analog inputs
can be large compared to the leakage current and will vary with the sample
rate.
Note 11: Leakage current will have higher transient current at power up.
Keep drive resistance at or below 1Kohm.
TIMING DIAGRAM
tAP
ANALOG
INPUT
N+1
N+4
N
N+3
N+2
tH
tL
ENC–
ENC+
tD
N–7
D0-D15, OF
CLKOUT+
CLKOUT –
N–6
N–5
N–4
N–3
tC
22076 TD01
22076fa
6
LTC2207/LTC2206
TYPICAL PERFORMANCE CHARACTERISTICS
1000
–2.0
–1.0
8192 16384 24576 32768 40960 49152 57344 65536
OUTPUT CODE
0
22076 G01
10
30
40
20
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
50
0
10
30
40
20
FREQUENCY (MHz)
50
120
120
SFDR (dBc AND dBFS)
140
100
80
60
40
100
80
60
40
20
20
0
22076 G07
0
10
30
40
20
FREQUENCY (MHz)
0
–80 –70 –60 –50 –40 –30 -20 –10
INPUT LEVEL (dBFS)
50
22076 G06
LTC2207: 64K Point 2-Tone FFT,
fIN = 14.8MHz and 18.6MHz,
–7dBFS, PGA = 0, 105Msps
LTC2207: SFDR vs Input Level,
fIN = 15MHz, PGA = 0,
Dither “On”, 105Msps
140
0
–80 –70 –60 –50 –40 –30 -20 –10
INPUT LEVEL (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
22076 G05
22076 G04
LTC2207: SFDR vs Input Level,
fIN = 15MHz, PGA = 0,
Dither “Off”, 105Msps
22076 G03
LTC2207: 64K Point FFT,
fIN = 14.8MHz, –10dBFS,
PGA = 0, 105Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2207: 64K Point FFT,
fIN = 14.8MHz, –1dBFS,
PGA = 0, 105Msps
AMPLITUDE (dBFS)
0
OUTPUT CODE
22076 G02
LTC2207: 128K Point FFT,
fIN = 4.93MHz, –1dBFS,
PGA = 0, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
8192 16384 2457632768 40960 49152 57344 65536
OUTPUT CODE
AMPLITUDE (dBFS)
0
32821
2000
–0.8
32823
–0.6
–1.5
32819
3000
32815
4000
–0.4
32817
–0.2
32811
–1.0
6000
5000
32813
0
32807
–0.5
7000
0.2
32809
0
8000
0.4
COUNT
0.5
9000
0.6
32805
INL ERROR (LSB)
INL ERROR (LSB)
1.0
10000
32803
1.5
1.0
0.8
32801
2.0
SFDR (dBc AND dBFS)
LTC2207: AC Grounded Input
Histogram, 105Msps
LTC2207: DNL, 105Msps
LTC2207: INL, 105Msps
0
22076 G08
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
30
40
20
FREQUENCY (MHz)
50
22076 G09
22076fa
7
LTC2207/LTC2206
TYPICAL PERFORMANCE CHARACTERISTICS
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
30
40
20
FREQUENCY (MHz)
50
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
30
40
20
FREQUENCY (MHz)
22076 G10
10
30
40
20
FREQUENCY (MHz)
50
–50 –40 –30 –20
INPUT LEVEL (dBFS)
–10
0
0
10
30
40
20
FREQUENCY (MHz)
8
50
30
40
20
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
30
40
20
FREQUENCY (MHz)
22076 G14
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
–70
–60
–50 –40 –30 –20
INPUT LEVEL (dBFS)
–10
50
50
22076 G15
LTC2207: 64K Point FFT,
fIN = 170.2MHz, –1dBFS,
PGA = 0, 105Msps
AMPLITUDE (dBFS)
SFDR (dBc AND dBFS)
22076 G16
10
22076 G12
LTC2207: SFDR vs Input Level,
fIN = 140MHz, PGA = 1,
Dither “On”, 105Msps
SFDR (dBc AND dBFS)
–60
0
LTC2207: 64K Point FFT,
fIN = 140.2MHz, –1dBFS,
PGA = 1, 105Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
22076 G13
LTC2207: SFDR vs Input Level,
fIN = 140MHz, PGA = 1,
Dither “Off”, 105Msps
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
–70
50
LTC2207: 128K Point FFT,
fIN = 70.1MHz, –20dBFS,
PGA = 0, Dither “On”, 105Msps
AMPLITUDE (dBFS)
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
22076 G11
LTC2207: 128K Point FFT,
fIN = 70.1MHz, –20dBFS,
PGA = 0, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
LTC2207: 64K Point FFT,
fIN = 70.1MHz, –1dBFS,
PGA = 1, 105Msps
AMPLITUDE (dBFS)
LTC2207: 64K FFT,
fIN = 70.1MHz, –1dBFS,
PGA = 0, 105Msps
LTC2207: 64K Point 2-Tone FFT,
fIN = 14.8MHz and 18.6MHz,
–15dBFS, PGA = 0, 105Msps
0
22076 G17
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
30
40
20
FREQUENCY (MHz)
50
22076 G18
22076fa
LTC2207/LTC2206
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2207: SFDR (HD2 and HD3) vs
Input Frequency, 105Msps
100
77
95
76
90
75
30
40
20
FREQUENCY (MHz)
SNR (dBFS)
78
85
PGA = 0
80
70
71
100
400
300
INPUT FREQUENCY (MHz)
0
200
500
22076 G19
PGA = 1
73
72
65
50
PGA = 1
PGA = 0
74
75
70
0
100
200
400
300
INPUT FREQUENCY (MHz)
22076 G20
500
22076 G21
LTC2207: SNR and SFDR vs
Supply Voltage (VDD),
fIN = 5MHz, 105Msps
LTC2207: 5MHz SNR and SFDR vs
Sample Rate, 105Msps
105
110
100
105
UPPER LIMIT
SNR AND SFDR (dBFS)
SFDR
95
90
LIMIT
85
80
SNR
75
100
SFDR
95
90
LOWER LIMIT
85
80
SNR
75
70
2.8
70
0
25
75 100 125
50
SAMPLE RATE (Msps)
150
175
3.2
3
SUPPLY VOLTAGE (V)
3.4
22076 G23
22076 G22
LTC2207: IVDD vs Sample Rate,
5MHz Sine Wave, –1dBFS,
105Msps
LTC2207: SNR and SFDR vs Duty
Cycle, 105Msps
110
300
100
280
290
270
90
IVDD (mA)
10
LTC2207: SNR vs Input
Frequency, 105Msps
105
SFDR (dBc)
0
SNR AND SFDR (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
SFDR AND SNR (dBFS)
AMPLITUDE (dBFS)
LTC2207: 64K Point FFT,
fIN = 250.2MHz, –1dBFS,
PGA = 0, 105Msps
80
260
250
240
230
SNR DCS OFF
SNR DCS ON
SFDR DCS OFF
SFDR DCS ON
70
60
30
40
50
60
70
DUTY CYCLE (%)
22076 G24
220
210
200
0
100
50
SAMPLE RATE (Msps)
150
22076 G25
22076fa
9
LTC2207/LTC2206
TYPICAL PERFORMANCE CHARACTERISTICS
1000
–2.0
–1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
OUTPUT CODE
0
22076 G26
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
0
5
10
15 20 25 30
FREQUENCY (MHz)
10
15 20 25 30
FREQUENCY (MHz)
35
40
22076 G32
0
5
10
15 20 25 30
FREQUENCY (MHz)
40
LTC2206: SFDR vs Input Level,
fIN = 15MHz, PGA = 0, 80Msps
120
100
SFDR (dBc AND DBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
35
22076 G31
LTC2206: 64K Point FFT,
fIN = 15.1MHz, –1dBFS, PGA = 0,
80Msps
AMPLITUDE (dBFS)
5
40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
22076 G30
LTC2206: 128K Point FFT,
fIN = 10.1MHz, –20dBFS,
PGA = 0, Dither “On”, 80Msps
0
35
22076 G28
LTC2206: 128K Point FFT,
fIN = 10.1MHz, –20dBFS,
PGA = 0, Dither “Off”, 80Msps
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
22076 G29
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
OUTPUT CODE
22076 G27
LTC2206: 64K Point FFT,
fIN = 10.1MHz, –1dBFS, PGA = 0,
80Msps
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
8192 16384 2457632768 40960 49152 57344 65536
OUTPUT CODE
32833
2000
–0.8
32831
–0.6
–1.5
32829
3000
32825
4000
–0.4
LTC2206: 128K Point FFT,
fIN = 4.93MHz, –1dBFS, PGA = 0,
80Msps
AMPLITUDE (dBFS)
5000
32827
0
–0.2
32821
–1.0
6000
32823
–0.5
7000
0.2
32817
0
8000
0.4
32819
0.5
9000
0.6
32815
INL ERROR (LSB)
INL ERROR (LSB)
1.0
10000
32813
1.5
1.0
0.8
COUNT
2.0
AMPLITUDE (dBFS)
LTC2206: 64K Point AC Grounded
Histogram, 80Msps
LTC2206: DNL, 80Msps
32811
LTC2206: INL, 80Msps
80
60
40
20
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
22076 G33
0
–70 –60
–50 –40 –30 –20
INPUT LEVEL (dBFS)
–10
0
22076 G34
22076fa
10
LTC2207/LTC2206
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2206: SFDR vs Input Level
fIN = 15MHz, PGA = 0,
Dither “On”, 80Msps
140
100
AMPLITUDE (dBFS)
SFDR (dBc AND DBFS)
120
80
60
40
20
0
–70 –60
–50 –40 –30 –20
INPUT LEVEL (dBFS)
–10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5
10
15 20 25 30
FREQUENCY (MHz)
22076 G35
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
0
5
10
15 20 25 30
FREQUENCY (MHz)
10
15 20 25 30
FREQUENCY (MHz)
35
40
22076 G41
35
40
15 20 25 30
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
35
40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
22076 G40
LTC2206: 64K Point FFT,
fIN = 140.2MHz, –1dBFS,
PGA = 0, 80Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
10
22076 G37
LTC2206: 64K Point 2-Tone FFT,
fIN = 69.2MHz and 76.5MHz,
–15dBFS, PGA = 0, 80Msps
AMPLITUDE (dBFS)
5
5
22076 G39
22076 G38
0
0
LTC2206: 64K Point FFT,
fIN = 70.2MHz, –1dBFS, PGA = 1,
80Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
LTC2206: 64K Point 2-Tone FFT,
fIN = 69.2MHz and 76.5MHz,
–7dBFS, PGA = 0, 80Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
40
LTC2206: 64K Point FFT,
fIN = 70.2MHz, –1dBFS, PGA = 0,
80Msps
AMPLITUDE (dBFS)
0
35
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
22076 G36
LTC2206: 64K Point FFT,
fIN = 25.1MHz, –1dBFS, PGA = 0,
80Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
LTC2206: 64K Point 2-Tone FFT,
fIN = 14.8MHz and 18.6MHz,
–15dBFS, PGA = 0, 80Msps
AMPLITUDE (dBFS)
LTC2206: 64K Point 2-Tone FFT,
fIN = 14.8MHz and 18.6MHz,
–7dBFS, PGA = 0, 80Msps
40
22076 G42
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
22076 G43
22076fa
11
LTC2207/LTC2206
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2206: SFDR vs Input Level,
fIN = 140.2MHz, PGA = 0,
Dither “On”, 80Msps
130
130
120
120
110
110
100
90
80
70
60
50
100
90
80
70
60
50
40
40
30
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
30
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
22076 G44
105
79
100
78
10
15 20 25 30
FREQUENCY (MHz)
35
10
15 20 25 30
FREQUENCY (MHz)
SNR (dBFS)
85
PGA = 1
80
PGA = 0
75
72
71
65
70
69
500
400
100
300
200
INPUT FREQUENCY (MHz)
22076 G47
PGA = 1
73
70
0
PGA = 0
74
75
0
100
300
400
200
INPUT FREQUENCY (MHz)
105
LTC2206: IVDD vs Sample Rate,
5MHz Sine Wave, –1dBFS,
80Msps
250
110
LOWER LIMIT
SFDR
240
105
100
500
22076 G49
22076 G48
LTC2206: SNR and SFDR vs
Supply Voltage (VDD),
fIN = 5MHz, 80Msps
LTC2206: 5MHz SFDR and SNR vs
Sample Rate, 80Msps
40
76
60
40
35
77
90
5
5
LTC2206: SNR vs Input
Frequency, 80Msps
95
0
0
22076 G46
LTC2206: SFDR (HD2 and HD3) vs
Input Frequency, 80Msps
SFDR (dBc)
AMPLITUDE (dBFS)
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
22076 G45
LTC2206: 64K Point FFT,
fIN = 250.2MHz, –1dBFS,
PGA = 1, 80Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
LTC2206: 64K Point FFT,
fIN = 170.2MHz, –1dBFS,
PGA = 1, 80Msps
AMPLITUDE (dBFS)
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
LTC2206: SFDR vs Input Level,
fIN = 140.2MHz, PGA = 0,
Dither “Off”, 80Msps
90
LIMIT
85
80
100
95
90
85
75
0
20
40
60
80
100 120 140 160
SAMPLE RATE (MHz)
22076 G50
200
190
170
SNR
UPPER LIMIT
70
210
180
80
SNR
75
220
SFDR
IVDD (mA)
SNR AND SFDR (dBFS)
SFDR AND SNR (dBRS)
230
95
70
2.8
160
150
3.2
3
SUPPLY VOLTAGE (V)
3.4
22076 G51
0
20
60
80
40
SAMPLE RATE (Msps)
100
22076 G52
22076fa
12
LTC2207/LTC2206
TYPICAL PERFORMANCE CHARACTERISTICS
Normalized Full-Scale Error vs
Temperature, Internal Reference,
5 Units
Offset Voltage vs Temperature,
Internal Reference, 5 Units
105
6
1.000
4
2
0
–2
–4
95
0.999
0.998
0.997
90
70MHz
85
80
75
70
0.996
–6
10MHz
100
SFDR (dBFS)
NORMALIZED FULL-SCALE
OFFSET VOLTAGE (mV)
110
1.001
8
–8
–40
SFDR vs Analog Input Common
Mode Voltage, 10MHz and
70MHz, –1dBFS, PGA = 0
65
–15
10
35
TEMPERATURE (°C)
60
85
22076 G53
0.995
–40
60
–15
10
35
TEMPERATURE (°C)
60
85
22076 G54
1.75
0.75
1.25
1.5
0.5
2
1
ANALOG INPUT COMMON MODE VOLTAGE (V)
22076 G55
22076fa
13
LTC2207/LTC2206
PIN FUNCTIONS
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
OVDD (Pins 24, 25, 36, 37): Positive Supply for the Output
Drivers. Bypass to ground with 0.1µF capacitor.
VCM (Pin 2): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum
of 2.2µF. Ceramic chip capacitors are recommended.
CLKOUT+ (Pin 30): Inverted Data Valid Output. CLKOUT+
will toggle at the sample rate. Latch the data on the rising
edge of CLKOUT+.
VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin.
Bypass to GND with 0.1µF ceramic chip capacitors.
GND (Pins 5, 8, 11, 15, 48, 49): ADC Power Ground.
AIN+ (Pin 6): Positive Differential Analog Input.
AIN– (Pin 7): Negative Differential Analog Input.
ENC+ (Pin 9): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2kΩ resistor. Output
data can be latched on the rising edge of ENC+.
ENC– (Pin 10): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC–.
Internally biased to 1.6V through a 6.2kΩ resistor. Bypass to ground with a 0.1µF capacitor for a single-ended
Encode signal.
SHDN (Pin 16): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
DITH (Pin 17): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal
dither. Refer to Internal Dither section of this data sheet
for details on dither operation.
D0-D15 (Pins 18-22, 26-28, 32-35 and 39-42): Digital
Outputs. D15 is the MSB.
OGND (Pins 23, 31 and 38): Output Driver Ground.
CLKOUT– (Pin 29): Data Valid Output. CLKOUT– will toggle
at the sample rate. Latch the data on the falling edge of
CLKOUT–.
OF (Pin 43): Over/Under Flow Digital Output. OF is high
when an over or under flow has occurred.
⎯O⎯E (Pin 44): Output Enable Pin. Low enables the digital
output drivers. High puts digital outputs in Hi-Z state.
MODE (Pin 45): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 46): Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D15 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interferance.
PGA (Pin 47): Programmable Gain Amplifier Control Pin. Low
selects a front-end gain of 1, input range of 2.25VP-P. High
selects a front-end gain of 1.5, input range of 1.5VP-P.
GND (Exposed Pad, Pin 49): ADC Power Ground. The exposed pad on the bottom of the package must be soldered
to ground.
22076fa
14
LTC2207/LTC2206
BLOCK DIAGRAM
AIN+
AIN–
VDD
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
GND
DITHER
SIGNAL
GENERATOR
CORRECTION LOGIC
AND
SHIFT REGISTER
ADC CLOCKS
RANGE
SELECT
OVDD
SENSE
PGA
VCM
BUFFER
ADC
REFERENCE
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
CLKOUT+
CLKOUT–
OF
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
VOLTAGE
REFERENCE
OGND
ENC+
ENC–
SHDN PGA RAND MODE DITH
D15
D14
D1
D0
22076 F01
OE
Figure 1. Functional Block Diagram
22076fa
15
LTC2207/LTC2206
OPERATION
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
first five harmonics.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = –20Log (√(V22 + V32 + V42 + ... VN2)/V1)
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through nth harmonics.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3nd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is
defined as the ration of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
Spurious Free Dynamic Range (SFDR)
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
Full Power Bandwidth
The Full Power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC+ equals the ENC– voltage
to the instant that the input signal is held by the sampleand-hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from convertion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
22076fa
16
LTC2207/LTC2206
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2207/LTC2206 are CMOS pipelined multistep converters with a front-end PGA. As shown in Figure 1, the converter has five pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles clock later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2207/LTC2206 have two phases of operation,
determined by the state of the differential ENC+/ENC–
input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as
ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifier. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplifier which
drives the first pipelined ADC stage. The first stage acquires
the output of the S/H amplifier during the high phase of
ENC. When ENC goes back low, the first stage produces
its residue which is acquired by the second stage. At the
same time, the input S/H goes back to acquiring the analog
input. When ENC goes high, the second stage produces
its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fifth
stage for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
22076fa
17
LTC2207/LTC2206
APPLICATIONS INFORMATION
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Input Drive Impedence
Sample/Hold Operation
As with all high performance, high speed ADCs the
dynamic performance of the LTC2207/LTC2206 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of
ENC the sample-and-hold circuit will connect the 4.9pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally,
the input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
Figure 2 shows an equivalent circuit for the LTC2207/
LTC2206 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling
capacitors (CSAMPLE) through NMOS transitors. The
capacitors shown attached to each input (CPARASITIC) are
the summation of all other capacitance associated with
each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions for high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specified performance. Each input should
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The VCM output pin (Pin 2) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2µF or greater.
For the best performance it is recomended to have a source
impedence of 100Ω or less for each input. The source
impedence should be matched for the differential inputs.
Poor matching will result in higher even order harmonics,
especially the second.
LTC2207/LTC2206
VDD
CSAMPLE
4.9pF
AIN+
CPARASITIC
1.8pF
VDD
CSAMPLE
4.9pF
AIN–
CPARASITIC
1.8pF
VDD
1.6V
6k
ENC+
ENC–
6k
1.6V
22076 F02
Figure 2. Equivalent Input Circuit
22076fa
18
LTC2207/LTC2206
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
Input Filtering
A first order RC lowpass filter at the input of the ADC
can serve two functions: limit the noise from input circuitry and provide isolation from ADC S/H switching. The
LTC2207/LTC2206 have a very broadband S/H circuit, DC
to 700MHz; it can be used in a wide range of applications;
therefore, it is not possible to provide a single recommended RC filter.
Figures 3, 4a and 4b show three examples of input RC
filtering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well
as noise coupled from the digital circuitry. The LTC2207/
LTC2206 do not require any input filter to achieve data sheet
specifications; however, no filtering will put more stringent
noise requirements on the input drive circuitry.
high frequency distortion. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequencies below 1MHz.
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has
much better high frequency response and balance than
flux coupled center tap transformers. Coupling capacitors
are added at the ground and input primary terminals to
allow the secondary terminals to be biased at 1.25V. Figure
4b shows the same circuit with components suitable for
higher input frequencies.
VCM
2.2µF
0.1µF
Transformer Coupled Circuits
Figure 3 shows the LTC2207/LTC2206 being driven by
an RF transformer with a center-tapped secondary. The
secondary center tap is DC biased with VCM, setting the
ADC input signal at its optimum DC level. Figure 3 shows
a 1:1 turns ratio transformer. Other turns ratios can be
used; however, as the turns ratio increases so does the
impedance seen by the ADC. Source impedance greater
than 50Ω can reduce the input bandwidth and increase
0.1µF
5Ω AIN+
10Ω
ANALOG
INPUT
25Ω
0.1µF
25Ω
10Ω
T1
1:1
4.7pF
4.7pF
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF
LTC2207/
LTC2206
5Ω AIN–
4.7pF
22076 F04a
Figure 4a. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 100MHz to 250MHz
VCM
VCM
2.2µF
5Ω
5Ω AIN+
10Ω
T1
8.2pF
2.2µF
LTC2207/
LTC2206
35Ω
0.1µF
5Ω
ANALOG
INPUT
25Ω
8.2pF
0.1µF
10Ω
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF
35Ω
0.1µF
5Ω AIN–
8.2pF
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 5MHz to 150MHz
22076 F03
T1
1:1
0.1µF
25Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF
AIN+
2.2pF
5Ω
2.2pF
LTC2207/
LTC2206
AIN–
22076 F04b
Figure 4b. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 250MHz to 500MHz
22076fa
19
LTC2207/LTC2206
APPLICATIONS INFORMATION
Direct Coupled Circuits
Figure 5 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential amplifiers tend to have
high noise. As a result, the SNR will be degraded unless
the noise bandwidth is limited prior to the ADC input.
Reference Operation
Figure 6 shows the LTC2207/LTC2206 reference circuitry
consisting of a 2.5V bandgap reference, a programmable
gain amplifier and control circuit. The LTC2207/LTC2206
have three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference.
To use the internal reference, tie the SENSE pin to VDD. To
use an external reference, simply apply either a 1.25V or
2.5V reference voltage to the SENSE input pin. Both 1.25V
and 2.5V applied to SENSE will result in a full scale range
of 2.25VP-P (PGA = 0). A 1.25V output VCM is provided
for a common mode bias for input drive circuitry. An
external bypass capacitor is required for the VCM output.
This provides a high frequency low impedance path to
ground for internal and external circuitry. This is also the
compensation capacitor for the reference; it will not be
stable without this capacitor. The minimum value required
for stability is 2.2µF.
The internal programmable gain amplifier provides the
internal reference voltage for the ADC. This amplifier has
very stringent settling requirements and is not accessible
for external use.
The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to VDD as close to the converter
as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1µF (or larger) ceramic capacitor.
PGA Pin
The PGA pin selects between two gain settings for the
ADC front-end. PGA = 0 selects an input range of 2.25VPP; PGA = 1 selects an input range of 1.5VP-P. The 2.25V
input range has the best SNR; however, the distortion will
be higher for input frequencies above 100MHz. For applications with high input frequencies, the low input range
will have improved distortion; however, the SNR will be
2.4dB worse. See the Typical Performance Characteristics
section of this datasheet.
LTC2207/
LTC2206
TIE TO VDD TO USE
INTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 1.25V
REFERENCE
VCM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
ANALOG
INPUT
+
2.2µF
AIN+
25Ω
12pF
+
–
PGA
2.5V
BANDGAP
REFERENCE
VCM
AMPLIFIER = LTC6600-20,
LTC1993, ETC.
12pF
BUFFER
1.25V
2.2µF
AIN–
25Ω
INTERNAL
ADC
REFERENCE
SENSE
LTC2207/
LTC2206
CM
–
RANGE
SELECT
AND GAIN
CONTROL
22076 F05
22076 F06
Figure 5. DC Coupled Input with Differential Amplifier
Figure 6. Reference Circuit
22076fa
20
LTC2207/LTC2206
APPLICATIONS INFORMATION
VDD
LTC2207/
LTC2206
VDD
6k
+
ENC
2.2µF
2
LTC1461-2.5
1µF
1.6V
VCM
1.25V
3.3V
TO INTERNAL
ADC CLOCK
DRIVERS
6
SENSE
LTC2207/
LTC2206
VDD 1.6V
6k
2.2µF
4
ENC–
22076 F07
22076 F08a
Figure 7. A 2.25V Range ADC with
an External 2.5V Reference
0.1µF
Figure 8a. Equivalent Encode Input Circuit
ENC+
T1
50Ω
LTC2207/
LTC2206
100Ω
8.2pF
0.1µF
ENC+
VTHRESHOLD = 1.6V
50Ω
1.6V ENC–
0.1µF
ENC–
LTC2207/
LTC2206
0.1µF
22076 F09
22076 F08b
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 8b. Transformer Driven Encode
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
3.3V
MC100LVELT22
3.3V
Q0
ENC+
D0
Q0
ENC–
LTC2207/
LTC2206
22076 F10
Figure 10. ENC Drive Using a CMOS to PECL Translator
22076fa
21
LTC2207/LTC2206
APPLICATIONS INFORMATION
Driving the Encode Inputs
Maximum and Minimum Encode Rates
The noise performance of the LTC2207/LTC2206 can
depend on the encode signal quality as much as for the
analog input. The encode inputs are intended to be driven
differentially, primarily for noise immunity from common
mode noise sources. Each input is biased through a 6k
resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can
set the logic threshold for single-ended drive circuits.
The maximum encode rate for the LTC2207 is 105Msps.
The maximum encode rate for the LTC2206 is 80Msps. For
the ADC to operate properly the encode signal should have
a 50% (±5%) duty cycle. Each half cycle must be at least
4.52ns for the LTC2207 internal circuitry to have enough
settling time for proper operation. For the LTC2206, each
half cycle must be at least 5.94ns. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.
Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequencies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a fixed frequency sinusoidal
signal, filter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to VDD. Each input may be driven from ground to VDD for
single-ended drive.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2207/LTC2206 sample rate is
determined by droop of the sample and hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operating
frequency for the LTC2207/LTC2206 is 1Msps.
22076fa
22
LTC2207/LTC2206
APPLICATIONS INFORMATION
Table 1. MODE Pin Function
DIGITAL OUTPUTS
Digital Output Buffers
Figure 11 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
eliminates the need for external damping resistors.
As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital
outputs of the LTC2207/LTC2206 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as a ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
output may be used but is not required since the output
buffer has a series resistor of 33Ω on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
MODE
Output Format
Clock Duty
Cycle Stabilizer
0(GND)
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
An overflow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overflow or underflow.
Output Clock
The ADC has a delayed version of the encode input available
as a digital output. Both a noninverted version, CLKOUT+
and an inverted version CLKOUT– are provided. The
CLKOUT+/CLKOUT– can be used to synchronize the converter data to the digital system. This is necessary when
using a sinusoidal encode. Data can be latched on the
rising edge of CLKOUT+ or the falling edge of CLKOUT–.
CLKOUT+ falls and CLKOUT– rises as the data outputs
are updated.
The LTC2207/LTC2206 parallel digital output can be
selected for offset binary or 2’s complement format. The
format is selected with the MODE pin. This pin has a four
level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD.
An external resistor divider can be user to set the 1/3VDD
and 2/3VDD logic levels. Table 1 shows the logic states
for the MODE pin.
LTC2207/LTC2206
CLKOUT+
CLKOUT
OF
OF
D15
D15/D0
D14
LTC2207/LTC2206
OVDD
VDD
0.5V
TO 3.6V
VDD
D2
D14/D0
•
•
•
D2/D0
0.1µF
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
D1
33Ω
TYPICAL
DATA
OUTPUT
RAND = HIGH,
SCRAMBLE
ENABLED
D1/D0
RAND
OGND
D0
D0
22076 F11
22076 F12
Figure 11. Equivalent Circuit for a Digital Output Buffer
Figure 12. Functional Equivalent of Digital Output Randomizer
22076fa
23
LTC2207/LTC2206
APPLICATIONS INFORMATION
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise floor for a large reduction in
unwanted tone amplitude.
The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output Randomizer function is active
when the RAND pin is high.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OVDD should be tied to that same
1.8V supply. In CMOS mode OVDD can be powered with
any logic voltage up to the VDD of the ADC. OGND can be
powered with any voltage from ground up to 1V and must
be less than OVDD. The logic outputs will swing between
OGND and OVDD.
Internal Dither
The LTC2207/LTC2206 are 16-bit ADCs with a very linear transfer function; however, at low input levels even
slight imperfections in the transfer function will result in
unwanted tones. Small errors in the transfer function are
usually a result of ADC element mismatches. An optional
internal dither mode can be enabled to randomize the input
location on the ADC transfer curve, resulting in improved
SFDR for low signal levels.
As shown in Figure 15, the output of the sample-and-hold
amplifier is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
DAC is calibrated to result in less than 0.5dB elevation in
the noise floor of the ADC, as compared to the noise floor
with dither off.
LTC2207/LTC2206
AIN+
ANALOG
INPUT
AIN–
16-BIT
PIPELINED
ADC CORE
S/H
AMP
CLOCK/DUTY
CYCLE
CONTROL
PRECISION
DAC
DIGITAL
SUMMATION
CLKOUT
OF
D15
•
•
•
D0
OUTPUT
DRIVERS
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
22076 F13
ENC
+
ENC
–
DITH
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
Figure 13. Functional Equivalent Block Diagram of Internal Dither Circuit
22076fa
24
LTC2207/LTC2206
APPLICATIONS INFORMATION
PC BOARD
FPGA
CLKOUT
OF
D15/D0
D15
LTC2207/
LTC2206
D14/D0
D14
D2/D0
•
•
•
D2
D1/D0
D1
D0
D0
22076 F14
Figure 14. Descrambling a Scrambled Digital Output
22076fa
25
LTC2207/LTC2206
APPLICATIONS INFORMATION
Grounding and Bypassing
The LTC2207/LTC2206 require a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2207/LTC2206 has been optimized for a flowthrough
layout so that the interaction between inputs and digital
outputs is minimized. Layout for the printed circuit board
should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, VCM, and OVDD pins. Bypass capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2207/LTC2206 differential inputs should run
parallel and close to each other. The input traces should
be as short as possible to minimize capacitance and to
minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTC2207/LTC2206 is
transferred from the die through the bottom-side exposed
pad. For good electrical and thermal performance, the
exposed pad must be soldered to a large grounded pad
on the PC board. It is critical that the exposed pad and all
ground pins are connected to a ground plane of sufficient
area with as many vias as possible.
22076fa
26
LTC2207/LTC2206
APPLICATIONS INFORMATION
Silkscreen Top
Top Side
22076fa
27
LTC2207/LTC2206
APPLICATIONS INFORMATION
Inner Layer 2
Inner Layer 3
Inner Layer 4
Inner Layer 5
22076fa
28
LTC2207/LTC2206
APPLICATIONS INFORMATION
Bottom Side
Silkscreen Bottom
22076fa
29
LTC2207/LTC2206
APPLICATIONS INFORMATION
Ordering Guide:
DEMO BOARD NUMBER
PART NUMBER
RESOLUTION
SPEED
INPUT FREQUENCY
USB I/F BOARD
DC918C-A
LTC2207CUK
16-Bit
105Msps
1MHz to 70MHz
DC718
DC918C-B
LTC2207CUK
16-Bit
105Msps
70MHz to 140MHz
DC718
DC918C-C
LTC2206CUK
16-Bit
80Msps
1MHz to 70MHz
DC718
DC918C-D
LTC2206CUK
16-Bit
80Msps
70MHz to 140MHz
DC718
DC918C-E
LTC2205CUK
16-Bit
65Msps
1MHz to 70MHz
DC718
DC918C-F
LTC2205CUK
16-Bit
65Msps
70MHz to 140MHz
DC718
DC918C-G
LTC2204CUK
16-Bit
40Msps
1MHz to 70MHz
DC718
DC918C-H
LTC2207CUK-14
14-Bit
105Msps
1MHz to 70MHz
DC718
DC918C-I
LTC2207CUK-14
14-Bit
105Msps
70MHz to 140MHz
DC718
DC918C-J
LTC2206CUK-14
14-Bit
80Msps
1MHz to 70MHz
DC718
DC918C-K
LTC2206CUK-14
14-Bit
80Msps
70MHz to 140MHz
DC718
DC918C-L
LTC2205CUK-14
14-Bit
65Msps
1MHz to 70MHz
DC718
See Web site for ordering details or contact local sales.
22076fa
30
LTC2207/LTC2206
PACKAGE DESCRIPTION
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704)
0.70 ±0.05
5.15 ±0.05
6.10 ±0.05 7.50 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
7.00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.115
TYP
47 48
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
PIN 1
CHAMFER
2
5.15 ± 0.10
(4-SIDES)
0.25 ± 0.05
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
(UK48) QFN 1103
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
22076fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2207/LTC2206
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1747
12-Bit, 80Msps ADC
72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
LTC1748
14-Bit, 80Msps, 5V ADC
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LTC1749
12-Bit, 80Msps Wideband ADC
Up to 500MHz IF Undersampling, 87dB SFDR
LTC1750
14-Bit, 80Msps, 5V Wideband ADC
Up to 500MHz IF Undersampling, 90dB SFDR
LTC1993-2
High Speed Differential Op Amp
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LTC1994
Low Noise, Low Distortion Fully Differential
Input/Output Amplifier/Driver
Low Distortion: –94dBc at 1MHz
LTC2202
16-Bit, 10Msps, 3.3V ADC, Lowest Noise
140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2203
16-Bit, 25Msps, 3.3V ADC, Lowest Noise
220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2204
16-Bit, 40Msps, 3.3V ADC
480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2205
16-Bit, 65Msps, 3.3V ADC
590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2206
16-Bit, 80Msps, 3.3V ADC
725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2207
16-Bit, 105Msps, 3.3V ADC
900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2208
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN
LTC2220
12-Bit, 170Msps ADC
890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2220-1
12-Bit, 185Msps, 3.3V ADC, LVDS Outputs
910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
LTC2224
12-Bit, 135Msps, 3.3V ADC, High IF Sampling
630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
LTC2249
14-Bit, 80Msps ADC
230mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2250
10-Bit, 105Msps ADC
320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251
10-Bit, 125Msps ADC
395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252
12-Bit, 105Msps ADC
320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253
12-Bit, 125Msps ADC
395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254
14-Bit, 105Msps ADC
320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255
14-Bit, 125Msps, 3V ADC, Lowest Power
395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2284
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LTC2299
Dual 14-Bit, 80Msps ADC
230mW, 71.6dB SNR, 5mm x 5mm QFN Package
LTC5512
DC-3GHz High Signal Level
Downconverting Mixer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LTC5514
Ultralow Distortion IF Amplifier/ADC Driver with
Digitally Controlled Gain
450 MHz to 1dB BW, 47dB OIP3,
Digital Gain Control 10.5dB to 33dB in 1.5dB/Step
LTC5515
1.5 GHz to 2.5GHz Direct Conversion Quadrature High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator
Demodulator
LTC5516
800MHz to 1.5GHz Direct Conversion
Quadrature Demodulator
High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator
LTC5517
40MHz to 900MHz Direct Conversion
Quadrature Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5522
600MHz to 2.7GHz High Linearity
Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50Ω Single-Ended RF and LO Ports
22076fa
32 Linear Technology Corporation
LT 0606 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006