Cypress CY62158EV30LL-45BVXI 8-mbit (1024k x 8) static ram Datasheet

CY62158EV30 MoBL®
8-Mbit (1024K x 8) Static RAM
Functional Description [2]
Features
• Very high speed: 45 ns
The CY62158EV30 is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Placing the device into standby
mode reduces power consumption significantly when
deselected (CE1 HIGH or CE2 LOW). The eight input and
output pins (IO0 through IO7) are placed in a high impedance
state when the device is deselected (CE1 HIGH or CE2 LOW),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE1 LOW and CE2 HIGH and WE LOW).
— Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62158DV30
• Ultra low standby power
— Typical standby current: 2 µA
— Maximum standby current: 8 µA
• Ultra low active power
•
•
•
•
— Typical active current: 1.8 mA @ f = 1 MHz
Easy memory expansion with CE1, CE2, and OE features
Automatic power down when deselected
CMOS for optimum speed/power
Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and
48-pin TSOP I packages[1]
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight
IO pins (IO0 through IO7) is then written into the location
specified on the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and
CE2 HIGH) and OE LOW while forcing the WE HIGH. Under
these conditions, the contents of the memory location
specified by the address pins appear on the IO pins. See the
“Truth Table” on page 8 for a complete description of read and
write modes.
Logic Block Diagram
IO0
DATA IN DRIVERS
SENSE AMPS
ROW DECODER
IO1
1024K x 8
ARRAY
IO2
IO3
IO4
IO5
IO6
A15
A16
A17
A13
A14
OE
POWER
DOWN
IO7
A19
COLUMN DECODER
WE
A18
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Notes
1. For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet.
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05578 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 19, 2007
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CY62158EV30 MoBL®
Pin Configurations [3]
48-Ball VFBGA
44-Pin TSOPII
Top View
Top View
1
2
3
4
5
6
NC
OE
A0
A1
A2
CE2
A
NC
NC
A3
A4
CE1
NC
B
IO 0
NC
A5
A6
NC
IO 4
C
VSS
IO1
A17
A7
IO5
VCC
D
VCC
IO 2
NC
A16
IO 6
VSS
E
IO 3
NC
A14
A15
NC
IO 7
F
NC
NC
A12
A13
WE
NC
G
A11
A19
A18
A8
A9
A10
A4
A3
A2
A1
A0
CE1
NC
NC
IO 0
IO 1
VCC
VSS
IO 2
IO 3
NC
NC
WE
A19
A18
A17
A16
A15
H
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
37
36
35
34
33
32
31
30
29
28
27
13
14
15
16
17
18
19
20
21
22
26
25
24
23
A5
A6
A7
OE
CE2
A8
NC
NC
IO 7
IO 6
VSS
VCC
IO 5
IO 4
NC
NC
A9
A10
A11
A12
A13
A14
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62158EV30LL
Speed
(ns)
Min
Typ[4]
Max
2.2
3.0
3.6
45
Operating ICC (mA)
f = 1 MHz
Standby, ISB2 (µA)
f = fmax
Typ[4]
Max
Typ[4]
Max
Typ[4]
Max
1.8
3
18
25
2
8
Notes
3. NC pins are not connected on the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 38-05578 Rev. *D
Page 2 of 11
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CY62158EV30 MoBL®
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Latch up Current...................................................... >200 mA
Storage Temperature .................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential –0.3V to VCC(max) + 0.3V
Product
DC Voltage Applied to Outputs
in High-Z State[5, 6] ......................... –0.3V to VCC(max) + 0.3V
Range
CY62158EV30LL Industrial
Ambient
Temperature
(TA)
VCC[7]
–40°C to +85°C 2.2V – 3.6V
DC Input Voltage[5, 6] ..................... –0.3V to VCC(max) + 0.3V
Electrical Characteristics (Over the Operating Range)
Parameter
Description
Test Conditions
45 ns
Min
Typ[4]
Unit
Max
VOH
Output HIGH Voltage
IOH = –0.1 mA
2.0
V
IOH = –1.0 mA, VCC > 2.70V
2.4
VOL
Output LOW Voltage
IOL = 0.1 mA
0.4
V
IOL = 2.1 mA, VCC > 2.70V
0.4
V
1.8
VCC + 0.3V
V
V
VIH
Input HIGH Voltage
VCC = 2.2V to 2.7V
VCC = 2.7V to 3.6V
2.2
VCC + 0.3V
V
VIIL
Input LOW Voltage
VCC = 2.2V to 2.7V
–0.3
0.6
V
VCC = 2.7V to 3.6V
–0.3
0.8
V
–1
+1
µA
IIX
Input Leakage Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply Current f = fmax = 1/tRC
f = 1 MHz
+1
µA
18
25
mA
1.8
3
mA
–1
VCC = VCCmax
IOUT = 0 mA
CMOS levels
ISB1
Automatic CE
Power down Current —
CMOS Inputs
CE1 > VCC – 0.2V, CE2 < 0.2V
VIN > VCC – 0.2V, VIN < 0.2V)
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60V
2
8
µA
ISB2[8]
Automatic CE
Power down Current —
CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
2
8
µA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes
5. VIL(min) = –2.0V for pulse durations less than 20 ns.
6. VIH(max)= VCC + 0.75V for pulse duration less than 20 ns.
7. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
8. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05578 Rev. *D
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CY62158EV30 MoBL®
Thermal Resistance[9]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
BGA
TSOP II
Unit
72
76.88
°C/W
8.86
13.52
°C/W
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
GND
R2
30 pF
10%
90%
10%
90%
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
Parameters
2.5V
R1
R2
RTH
VTH
VTH
3.0V
Unit
16667
1103
Ω
15385
1554
Ω
8000
645
Ω
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR[8]
Data Retention Current
tCDR[9]
Chip Deselect to Data
Retention Time
tR[10]
Operation Recovery
Time
Min
Typ[4]
Max
1.5
VCC = 1.5V, CE1 > VCC − 0.2V
or CE2 < 0.2V, VIN > VCC − 0.2V
or VIN < 0.2V
Unit
V
2
5
µA
0
ns
tRC
ns
Data Retention Waveform
VCC
VCC, min
tCDR
DATA RETENTION MODE
VDR > 1.5V
VCC, min
tR
CE1
or
CE2
Note
10. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
Document #: 38-05578 Rev. *D
Page 4 of 11
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CY62158EV30 MoBL®
Switching Characteristics (Over the Operating Range) [11]
Parameter
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z[12]
tHZOE
OE HIGH to High Z[12, 13]
45
10
CE1 HIGH or CE2 LOW to High
tPU
CE1 LOW and CE2 HIGH to Power Up
Write
10
Z[12, 13]
ns
ns
ns
18
0
CE1 HIGH or CE2 LOW to Power Down
ns
ns
18
tHZCE
tPD
45
22
Z[12]
ns
ns
5
CE1 LOW and CE2 HIGH to Low
tLZCE
ns
45
ns
ns
45
ns
Cycle[14]
tWC
Write Cycle Time
45
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tSD
Data Setup to Write End
25
ns
tHD
Data Hold from Write End
0
ns
Z[12, 13]
tHZWE
WE LOW to High
tLZWE
WE HIGH to Low Z[12]
18
10
ns
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.
12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
13. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05578 Rev. *D
Page 5 of 11
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CY62158EV30 MoBL®
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[15, 16]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[16, 17]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
50%
ICC
ISB
Notes
15. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
Document #: 38-05578 Rev. *D
Page 6 of 11
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CY62158EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[14, 18, 19]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA IO
tHD
VALID DATA
NOTE 20
tHZOE
Write Cycle No. 2 (CE1 or CE2 Controlled)[14, 18, 19]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tHA
tAW
tPWE
WE
OE
tSD
DATA IO
tHD
VALID DATA
Notes
18. Data IO is high impedance if OE = VIH.
19. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
20. During this period, the IOs are in output state. Do not apply input signals.
Document #: 38-05578 Rev. *D
Page 7 of 11
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CY62158EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[19]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tSA
tHA
tPWE
WE
tSD
DATA IO
NOTE 20
tHD
VALID DATA
tLZWE
tHZWE
Truth Table
CE1
CE2
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
X
High Z
Deselect/Power Down
Standby (ISB)
X
L
X
X
High Z
Deselect/Power Down
Standby (ISB)
L
H
H
L
Data Out
Read
Active (ICC)
L
H
H
H
High Z
Output Disabled
Active (ICC)
L
H
L
X
Data in
Write
Active (ICC)
Ordering Information
Speed
(ns)
Ordering Code
45
CY62158EV30LL-45BVXI
51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62158EV30LL-45ZSXI
51-85087 44-pin TSOP II (Pb-free)
Document #: 38-05578 Rev. *D
Package
Diagram
Package Type
Operating
Range
Industrial
Page 8 of 11
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CY62158EV30 MoBL®
Package Diagrams
Figure 1. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
0.55 MAX.
6.00±0.10
0.10 C
0.21±0.05
0.25 C
B
0.15(4X)
Document #: 38-05578 Rev. *D
1.00 MAX
0.26 MAX.
SEATING PLANE
C
51-85150-*D
Page 9 of 11
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CY62158EV30 MoBL®
Package Diagrams (continued)
Figure 2. 44-Pin TSOP II, 51-85087
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05578 Rev. *D
Page 10 of 11
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62158EV30 MoBL®
Document History Page
Document Title: CY62158EV30 MoBL®, 8-Mbit (1024K x 8) Static RAM
Document Number: 38-05578
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
270329
See ECN
PCI
New Data Sheet
*A
291271
See ECN
SYT
Converted from Advance Information to Preliminary
Changed ICCDR from 4 to 4.5 µA
*B
444306
See ECN
NXR
Converted from Preliminary to Final.
Removed 35 ns speed bin
Removed “L” bin.
Removed 44 pin TSOP II package
Included 48 pin TSOP I package
Changed the ICC Typ value from 16 mA to 18 mA and ICC max value from 28
mA to 25 mA for test condition f = fax = 1/tRC.
Changed the ICC max value from 2.3 mA to 3 mA for test condition f = 1MHz.
Changed the ISB1 and ISB2 max value from 4.5 µA to 8 µA and Typ value from
0.9 µA to 2 µA respectively.
Updated Thermal Resistance table
Changed Test Load Capacitance from 50 pF to 30 pF.
Added Typ value for ICCDR .
Changed the ICCDR max value from 4.5 µA to 5 µA
Corrected tR in Data Retention Characteristics from 100 µs to tRC ns
Changed tLZOE from 3 to 5
Changed tLZCE from 6 to 10
Changed tHZCE from 22 to 18
Changed tPWE from 30 to 35
Changed tSD from 22 to 25
Changed tLZWE from 6 to 10
Updated the ordering Information and replaced the Package Name column with
Package Diagram.
*C
467052
See ECN
NXR
Included 44 pin TSOP II package in Product Offering.
Removed TSOP I package; Added reference to CY62157EV30 TSOP I
Updated the ordering Information table
*D
1015643
See ECN
VKN
Added footnote #8 related to ISB2 and ICCDR
Document #: 38-05578 Rev. *D
Page 11 of 11
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