[ /Title (CD74 HC377 , CD74 HCT37 7) /Subject (High Speed CMOS Logic Octal DType Flip- CD54HC377, CD74HC377, CD54HCT377, CD74HCT377 Data sheet acquired from Harris Semiconductor SCHS184C High-Speed CMOS Logic Octal D-Type Flip-Flop With Data Enable September 1997 - Revised February 2004 Features Description • Buffered Common Clock The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flipflops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E) is Low. • Buffered Inputs • Typical Propagation Delay at CL = 15pF, VCC = 5V, TA = 25oC Ordering Information - 14 ns (HC Types - 16 ns (HCT Types) TEMP. RANGE (oC) PACKAGE CD54HC377F3A -55 to 125 20 Ld CERDIP PART NUMBER • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD54HCT377F3A -55 to 125 20 Ld CERDIP • Wide Operating Temperature Range . . . -55oC to 125oC CD74HC377E -55 to 125 20 Ld PDIP • Balanced Propagation Delay and Transition Times CD74HC377M -55 to 125 20 Ld SOIC • Significant Power Reduction Compared to LSTTL Logic ICs CD74HC377M96 -55 to 125 20 Ld SOIC CD74HC377PW -55 to 125 20 Ld TSSOP CD74HC377PWR -55 to 125 20 Ld TSSOP CD74HCT377E -55 to 125 20 Ld PDIP CD74HCT377M -55 to 125 20 Ld SOIC CD74HCT377M96 -55 to 125 20 Ld SOIC • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. Pinout CD54HC377, CD54HCT377 (CERDIP) CD74HC377 (PDIP, SOIC, TSSOP) CD74HCT377 (PDIP, SOIC) TOP VIEW E 1 Q0 2 19 Q7 D0 3 18 D7 20 VCC D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, Texas Instruments Incorporated 1 CD54HC377, CD74HC377, CD54HCT377, CD74HCT377 Functional Diagram D0 D1 D2 D3 D4 D5 D6 D7 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 11 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 CP GND = 10 VCC = 20 E TRUTH TABLE INPUTS OPERATING MODE CP OUPUTS E Dn Qn Load “1” ↑ l h H Load “0” ↑ l l L Hold (Do Nothing) ↑ h X No Change X H X No Change H = High Voltage Level Steady State. h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition. L = Low Voltage Level Steady State. l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition. X = Don’t Care. ↑ = Low to High Clock Transition. Logic Diagram D0 D1 D2 D3 D4 D5 D6 D7 E D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP CP Q0 Q1 Q2 Q3 2 Q4 Q5 Q6 Q7 CD54HC377, CD74HC377, CD54HCT377, CD74HCT377 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 69 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 58 PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . 83 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD54HC377, CD74HC377, CD54HCT377, CD74HCT377 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS E 1.5 CP 0.5 All Dn Inputs 0.25 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Prerequisite for Switching Specifications PARAMETER SYMBOL TEST CONDITIONS fMAX - VCC (V) 25oC MIN TYP -40oC TO 85oC -55oC TO 125oC MAX MIN MAX MIN MAX UNITS HC TYPES Maximum Clock Frequency Clock Pulse Width tW - 2 6 - - 5 - 4 - MHz 4.5 30 - - 25 - 20 - MHz 6 35 - - 29 - 23 - MHz 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 4 CD54HC377, CD74HC377, CD54HCT377, CD74HCT377 Prerequisite for Switching Specifications PARAMETER (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tSU - 2 60 - - 75 - 90 - ns 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns 2 3 - - 3 - 3 - ns 4.5 3 - - 3 - 3 - ns 6 3 - - 3 - 3 - ns 2 5 - - 5 - 5 - ns 4.5 5 - - 5 - 5 - ns 6 5 - - 5 - 5 - ns Set-up Time, E, Data to CP Hold Time, Data to CP tH Hold Time, E to CP tH - - HCT TYPES Maximum Clock Frequency fMAX - 4.5 25 - - 20 - 16 - MHz Clock Pulse Width tW - 4.5 20 - - 25 - 30 - ns Set-up, Time E, Data to CP tSU - 4.5 12 - - 15 - 18 - ns Hold Time, Data to CP tH - 4.5 3 - - 3 - 3 - ns Hold Time, E to CP tH - 4.5 5 - - 5 - 5 - ns Switching Specifications Input tr, tf = 6ns PARAMETER TEST SYMBOL CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns HC TYPES Propagation Delay (Figure 1) CP to Q Output Transition Time (Figure 1) Input Capacitance tPLH, tPHL CL = 50pF CIN CL = 50pF - - - 10 - 10 - 10 pF Maximum Clock Frequency fMAX CL =15pF 5 - 60 - - - - - MHz Power Dissipation Capacitance (Notes 3, 4) CPD CL =15pF 5 - 31 - - - - - pF tPLH, tPHL CL = 50pF 4.5 - - 38 - 48 - 57 ns CL =15pF 5 - 16 - - - - - ns 4.5 - - 15 - 19 - 22 ns - - - 10 - 10 - 10 pF HCT TYPES Propagation Delay (Figure 1) CP to Q Output Transition Time (Figure 1) Input Capacitance tTLH, tTHL CL = 50pF CIN CL = 50pF 5 CD54HC377, CD74HC377, CD54HCT377, CD74HCT377 Switching Specifications Input tr, tf = 6ns (Continued) TEST SYMBOL CONDITIONS PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Maximum Clock Frequency fMAX CL =15pF 5 - 50 - - - - - MHz Power Dissipation Capacitance (Notes 3, 4) CPD CL =15pF 5 - 35 - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per flip-flop. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms CLOCK INPUT trCL tfCL trCL VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET 1.3V 0.3V tH(L) DATA INPUT 3V 2.7V CLOCK INPUT 50% 10% tfCL CL 50pF FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8976901RA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC CD54HC377F3A ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC CD54HCT377F3A ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC CD74HC377E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC377EE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC377M ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC377M96 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC377M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC377ME4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC377PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC377PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC377PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC377PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT377E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT377EE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT377M ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT377M96 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT377M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT377ME4 ACTIVE SOIC DW 20 CU NIPDAU Level-1-260C-UNLIM 25 Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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