IDT54/74FCT543 IDT54/74FCT543A IDT54/74FCT543C FAST CMOS OCTAL LATCHED TRANSCEIVER Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • The IDT54/74FCT543/A/C is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. These devices contain two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0–A7 or to take data from B0–B7, as indicated in the Function Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses the CEBA, LEBA and OEBA inputs. • • • • • • • • • IDT54/74FCT543 equivalent to FAST speed IDT54/74FCT543A 25% faster than FAST IDT54/74FCT543C 40% faster than FAST Equivalent to FAST output drive over full temperature and voltage supply extremes IOL = 64mA (commercial), 48mA (military) Separate controls for data flow in each direction Back-to-back latches for storage CMOS power levels (1mW typ. static) Substantially lower input current levels than FAST (5µA max.) TTL input and output level compatible CMOS output level compatible Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B FUNCTIONAL BLOCK DIAGRAMS DETAIL A D Q B0 LE Q A0 D LE A1 A2 A3 A4 A5 A6 A7 DETAIL A x 7 B1 B2 B3 B4 B5 B6 B7 OEBA OEAB CEBA LEBA CEAB LEAB 2614 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a registered trademark of National Semiconductor Co. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1992 Integrated Device Technology, Inc. 7.17 MAY 1992 DSC-4602/3 1 IDT54/74FCT543/A/C FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT54/74FCT861 10-BIT TRANSCEIVERS 1 24 2 23 3 22 4 5 6 7 P24-1, D24-1, SO24-2 & E24-1 21 20 19 18 8 17 9 16 10 15 11 14 12 13 INDEX Vcc CEBA B0 B1 B2 B3 B4 B5 B6 B7 LEAB OEAB 4 A1 A2 A3 NC A4 A5 A6 3 25 6 24 7 23 L28-1 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 B1 B2 B3 NC B4 B5 B6 2614 drw 02 LCC TOP VIEW FUNCTION TABLE (1,2) PIN DESCRIPTION OEAB OEBA CEAB CEBA LEAB LEBA 28 27 26 1 DIP/SOIC/CERPACK TOP VIEW Pin Names 2 5 A7 CEAB GND NC OEAB LEAB B7 LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND A0 OEBA LEBA NC Vcc CEBA B0 PIN CONFIGURATIONS For A-to-B (Symmetric with B-to-A) Description Latch Status A-to-B Output Enable Input (Active LOW) Inputs B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A0–A7 A-to-B Data Inputs or B-to-A 3-State Outputs B0–B7 B-to-A Data Inputs or A-to-B 3-State Outputs 2614 tbl 02 LOGIC SYMBOL Output Buffers CEAB LEAB OEAB H — — Storing — H — Storing — — H — L L L Transparent Current A Inputs L H L Storing Previous* A Inputs A-to-B B0–B7 High Z — High Z NOTES: 2614 tbl 01 1. * Before LEAB LOW-to-HIGH Transition H = HIGH Voltage Level L = LOW Voltage Level — = Don’t Care or Irrelevant 2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA. LEAB CEAB CEBA LEBA A0 B0 A1 A2 B1 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 OEBA B7 OEAB 2614 drw 03 7.17 2 IDT54/74FCT543/A/C FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Rating VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature PT Power Dissipation IOUT DC Output Current Symbol Commercial Military Unit –0.5 to +7.0 –0.5 to +7.0 V –0.5 to VCC –0.5 to VCC V 0 to +70 –55 to +125 °C –55 to +125 –65 to +135 °C –55 to +125 –65 to +150 °C 0.5 120 0.5 120 W mA Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 6 10 pF CI/O I/O Capacitance VOUT = 0V 8 12 pF NOTE: 2614 tbl 04 1. This parameter is guaranteed by characterization data and not tested. NOTES: 2614 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Inputs and VCC terminals only. 3. Outputs and I/O terminals only. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V, VHC = VCC – 0.2V Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10% Symbol Test Conditions(1) Min. Typ.(2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V Input HIGH Current VCC = Max. µA IIH IIL IIH IIL Parameter VI = VCC — — 5 (Except I/O pins) VI = 2.7V — — 5(4) Input LOW Current VI = 0.5V — — –5(4) (Except I/O pins) VI = GND — — –5 VI = VCC — — 15 (I/O pins Only) VI = 2.7V — — 15(4) Input LOW Current VI = 0.5V — — –15(4) (I/O pins Only) VI = GND — — –15 Input HIGH Current VCC = Max. VIK Clamp Diode Voltage VCC = Min., IN = –18mA IOS Short Circuit Current VCC = Max.(3), VO = GND VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µA VOL Output LOW Voltage –0.7 –1.2 V –120 — mA V VCC — VCC — IOH = –12mA MIL. 2.4 4.3 — IOH = –15mA COM’L. VIN = VIH or VIL µA — VHC IOH = –300µA µA –60 VHC(4) VCC = Min. µA 2.4 4.3 — VCC = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC VCC = Min. IOL = 300µA — GND VLC(4) VIN = VIH or VIL IOL = 48mA MIL.(5) — 0.3 0.55 IOL = 64mA COM’L.(5) — 0.3 0.55 V NOTES: 2614 tbl 05 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. These are maximum IOL values per output, for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is 512mA for commercial and 384mA for military. Derate IOL for number of outputs exceeding 8 turned on simultaneously. 7.17 3 IDT54/74FCT543/A/C FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = VCC – 0.2V Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit ICC Quiescent Power Supply Current VCC = Max. VIN ≥ VHC; VIN ≤ VLC — 0.2 1.5 mA ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max., VIN = 3.4V(3) — 0.5 2.0 mA ICCD Dynamic Power Supply Current(4) VIN ≥ VHC VIN ≤ VLC — 0.15 0.25 mA/ MHz VCC = Max., Outputs Open fCP = 10MHz (LEAB) 50% Duty Cycle CEAB and OEAB = GND CEBA = VCC One Bit Toggling at fi = 5MHz 50% Duty Cycle VIN ≥ VHC VIN ≤ VLC (FCT) — 1.7 4.0 mA VIN = 3.4V VIN = GND — 2.2 6.0 VCC = Max., Outputs Open fCP = 10MHz (LEAB) 50% Duty Cycle CEAB and OEAB = GND CEBA = VCC Eight Bits Toggling at fi = 5MHz 50% Duty Cycle VIN ≥ VHC VIN ≤ VLC (FCT) — 7.0 12.8(5) VIN = 3.4V VIN = GND — 9.2 21.8(5) VCC = Max., Outputs Open CEAB and OEAB = GND CEBA = VCC One Input Toggling 50% Duty Cycle IC Total Power Supply Current(6) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT +IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD(fCP/2 + fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 7.17 2614 tbl 06 4 IDT54/74FCT543/A/C FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE IDT54/74FCT543 Com’l. Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay Transparent Mode An to Bn or Bn to An Propagation Delay LEBA to An, LEAB to Bn (1) Condition CL = 50pF RL = 500Ω (2) Min. Mil. (2) Max. Min. IDT54/74FCT543A Com’l. (2) Max. Min. Mil. (2) Max. Min. IDT54/74FCT543C Com’l. (2) Max. Min. Mil. (2) Max. Min. Max. Unit 2.5 8.5 2.5 10.0 2.5 6.5 2.5 7.5 2.5 5.3 2.5 6.1 ns 2.5 12.5 2.5 14.0 2.5 8.0 2.5 9.0 2.5 7.0 2.5 8.0 ns tPZH tPZL Output Enable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn 2.0 12.0 2.0 14.0 2.0 9.0 2.0 10.0 2.0 8.0 2.0 9.0 ns tPHZ tPLZ Output Disable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn 2.0 9.0 2.0 13.0 2.0 7.5 2.0 8.5 2.0 6.5 2.0 7.5 ns tSU Set-up Time, HIGH or LOW An or Bn to LEBA or LEAB 3.0 — 3.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns tH Hold Time, HIGH or LOW An or Bn to LEBA or LEAB 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns 5.0 — 5.0 — 5.0 — 5.0 — 5.0 — 5.0 — ns tW LEBA or LEAB Pulse Width LOW NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 2513 tbl 07 7.17 5 IDT54/74FCT543/A/C FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS VCC 7.0V 500Ω V OUT VIN Pulse Generator D.U.T. 50pF RT 500Ω SET-UP, HOLD AND RELEASE TIMES Closed All Other Tests Open 3V 1.5V 0V tH TIMING INPUT 3V 1.5V 0V LOW-HIGH-LOW PULSE 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V tW t REM PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. Open Drain Disable Low Enable Low PULSE WIDTH DATA INPUT ASYNCHRONOUS CONTROL Switch DEFINITIONS: 2614 tbl 08 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. CL t SU Test t SU 1.5V 3V 1.5V 0V tH PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE DISABLE 3V 3V 1.5V SAME PHASE INPUT TRANSITION t PLH t PHL CONTROL INPUT t PZL 0V OUTPUT NORMALLY SWITCH LOW CLOSED t PZH VOH 1.5V OUTPUT VOL t PLH t PHL OUTPUT SWITCH NORMALLY OPEN HIGH 3V OPPOSITE PHASE INPUT TRANSITION 1.5V 1.5V 0V t PLZ 3.5V 3.5V 1.5V 0.3V V OL t PHZ 0.3V 1.5V 0V V OH 0V 0V NOTES 2614 drw 05 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns; tR ≤ 2.5ns. 7.17 6 IDT54/74FCT543/A/C FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX FCT XXXX Temperature Range Device Type X X Package Process Blank B Commercial MIL-STD-883, Class B P D L SO E Plastic DIP CERDIP Leadless Chip Carrier Small Outline IC CERPACK 543 543A 543C Octal Registered Transceiver Fast Octal Registered Transceiver Super Fast Octal Registered Transceiver 54 74 7.17 -55°C to +125°C 0° to +70°C 2614 drw 04 7