IDT IDT70V35TSGGI High-speed 3.3v 8/4k x 18 dual-port 8/4k x 16 dual-port static ram Datasheet

HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70V35/34
– Commercial: 15/20/25ns (max.)
– Industrial: 20ns
IDT70V25/24
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns
Low-power operation
– IDT70V35/34S
– IDT70V35/34L
Active: 430mW (typ.)
Active: 415mW (typ.)
Standby: 3.3mW (typ.)
Standby: 660µW (typ.)
– IDT70V25/24S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
◆
◆
◆
◆
◆
◆
◆
◆
– IDT70V25/24L
Active: 380mW (typ.)
Standby: 660µW (typ.)
◆
◆
IDT70V35/34S/L
IDT70V25/24S/L
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
,
I/O9R-I/O17R(5)
I/O9L-I/O17L(5)
I/O
Control
I/O
Control
I/O0R-I/O8R(4)
I/O0L-I/O8L(4)
(2,3)
BUSYR (2,3)
BUSYL
A12L(1)
A0L
Address
Decoder
MEMORY
ARRAY
13
CEL
OEL
R/WL
SEML
INTL(3)
Address
Decoder
A12R(1)
A0R
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
CER
OER
R/WR
SEMR
INTR(3)
5624 drw 01
NOTES:
1. A 12 is a NC for IDT70V34 and for IDT70V24.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
4. I/O0x - I/O 7x for IDT70V25/24.
5. I/O8x - I/O15 x for IDT70V25/24.
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC-5624/7
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V35/34 (IDT70V25/24) is a high-speed 8/4K x 18 (8/4K
x16) Dual-Port Static RAM. The IDT70V35/34 (IDT70V25/24) is designed to be used as a stand-alone Dual-Port RAM or as a combination
MASTER/SLAVE Dual-Port RAM for 36-bit (32-bit) or wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 430mW (IDT70V35/34) and 400mW
(IDT70V25/24) of power.
The IDT70V35/34 (IDT70V25/24) is packaged in a plastic 100-pin
Thin Quad Flatpack. The IDT70V25/24 is packaged in a ceramic 84-pin
PGA and 84-Pin PLCC.
Pin Configurations(1,2,3,4)
I/O10L
I/O9L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
Vss
I/O1L
I/O0L
OEL
VDD
R/WL
SEML
CEL
UBL
LBL
A12L(1)
A11L
A10L
A9L
A8L
A7L
A6L
06/24/04
Index
N/C
N/C
I/O8L
I/O17L
I/O11L
I/O12L
I/O13L
I/O14L
Vss
I/O15L
I/O16L
VDD
Vss
I/O0R
I/O1R
I/O2R
VDD
I/O3R
I/O4R
I/O5R
I/O6R
I/O8R
I/O17R
N/C
N/C
100 99 98 9796 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
3
74
73
4
72
5
6
71
70
69
7
8
68
67
9
66
10
11
12
13
14
15
IDT70V35/34PF
PN100-1(5)
100-Pin TQFP
Top View(6)
65
64
63
62
61
16
60
17
59
18
19
58
57
20
56
21
55
22
54
53
23
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
24
N/C
N/C
N/C
N/C
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
Vss
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
N/C
N/C
N/C
N/C
,
I/O7R
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
I/O15R
Vss
I/O16R
OER
R/WR
Vss
SEMR
CER
UBR
LBR
A12R(1)
A11R
A10R
A9R
A8R
A7R
A6R
A5R
5624 drw 02
NOTES:
1. A12 is a NC for IDT70V34.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
2
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3,4)(con't)
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
VSS
I/O1L
I/O0L
OEL
VDD
R/WL
SEML
CEL
UBL
LBL
A12L(1)
A11L
A10L
A9L
A8L
A7L
A6L
06/24/04
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
1
4
72
71
5
6
7
70
69
8
68
9
67
10
11
12
13
14
IDT70V25/24PF
PN100-1(4)
100-Pin TQFP
Top View(5)
66
65
64
63
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
23
54
53
24
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O7R
I/O8R
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
VSS
I/O15R
OER
R/WR
VSS
SEMR
CER
UBR
LBR
A12R(1)
A11R
A10R
A9R
A8R
A7R
A6R
A5R
N/C
N/C
N/C
N/C
I/O10L
I/O11L
I/O12L
I/O13L
VSS
I/O14L
I/O15L
VDD
VSS
I/O0R
I/O1R
I/O2R
VDD
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
N/C
NOTES:
1. A12 is a NC for IDT70V24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
3
N/C
N/C
N/C
N/C
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
VSS
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
N/C
N/C
N/C
N/C
5624 drw 03
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3,4)(con't)
06/11/04
63
11
61
64
I/O10L
67
09
OEL
49
I/O1L
SEML
50
UBL
53
VSS
48
46
LBL
47
CEL
45
A11L
A9L
33
73
VDD
IDT70V25/24
G
G84-3(4)
74
VSS
VSS
28
VDD
83
I/O5R
7
1
I/O6R
2
I/O9R
3
I/O8R
A
5
I/O10R
4
I/O11R
B
11
VSS
I/O7R
8
I/O13R
6
I/O12R
C
10
I/O15R
9
I/O14R
D
12
VSS
14
R/WR
15
OER
E
23
SEMR
13
20
A11R
16
LBR
CER
F
G
22
A8R
18
A12R(1)
H
J
A3R
24
A6R
19
A10R
A1R
25
A5R
17
UBR
BUSYR
27
A2R
I/O4R
A1L
30
INTR
26
80
INTL
36
M/S
29
A0R
A2L
34
A0L
31
VSS
84-Pin PGA
Top View(5)
78
I/O2R
32
A4L
37
35
BUSYL
A5L
39
A3L
I/O14L
I/O3R
A8L
A6L
R/WL
A7L
40
41
52
VDD
A10L
43
44
A12L(1)
42
38
77
84
01
I/O3L
51
I/O12L
I/O1R
82
02
56
57
70
81
03
I/O6L
54
I/O0L
I/O9L
I/O0R
79
04
I/O2L
59
62
71
I/O15L
76
05
55
68
I/O13L
75
06
I/O4L
I/O8L
I/O11L
72
07
58
65
69
08
I/O5L
I/O7L
66
10
60
A4R
21
A9R
A7R
K
L
5624 drw 04
Index
NOTES:
1. A12 is a NC for IDT70V24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. G84-3 package body is approximately 1.12 in x 1.12 in x .16 in.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
4
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
I/O8L
I/O9L
14
I/O12L
16
17
IDT70V25/24J
J84-1(4)
VDD
21
22
84-Pin PLCC
Top View(5)
I/O5R
I/O6R
I/O7R
I/O8R
A8L
A9L
A10L
69
68
20
I/O4R
A12L(1)
A11L
70
I/O15L
VDD
I/O3R
CEL
15
I/O14L
I/O2R
UBL
LBL
72
71
18
19
VSS
I/O0R
I/O1R
SEML
VDD
R/WL
OEL
I/O0L
I/O1L
VSS
I/O2L
I/O3L
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
12
73
13
I/O10L
I/O11L
I/O13L
VSS
I/O4L
INDEX
I/O5L
I/O7L
06/08/04
I/O6L
Pin Configurations(1,2,3,4)(con't)
67
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
66
65
INTL
64
VSS
23
24
63
62
M/S
25
26
61
60
27
28
59
58
57
29
BUSYL
BUSYR
INTR
A0R
A1R
A2R
A3R
56
A4R
55
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
A5R
30
31
A6R
NOTES:
1. A12 is a NC for IDT70V24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
5
A7R
A8R
A10R
A9R
A12R(1)
A11R
LBR
CER
UBR
SEMR
R/WR
VSS
OER
I/O15R
VSS
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O9R
,
5624 drw 05
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
(1)
A 0L - A12L
I/O0L - I/O17L
Output Enable
(1)
A0R - A 12R
(2)
Address
(2)
I/O0R - I/O17R
Data Input/Output
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select(3)
LBL
LBR
Lower Byte Select(4)
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VDD
Power (3.3V)
VSS
Ground (0V)
NOTES:
1. A12 is a NC for IDT70V34 and for IDT70V24.
2. I/O0x - I/O15 x for IDT70V25/24.
3. Upper Byte Select controls pins 9-17 for IDT70V35/34 and controls pins 8-15
for IDT70V25/24.
4. Lower Byte Select controls pins 0-8 for IDT70V35/34 and controls pins 0-7
for IDT70V25/24.
5624 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
(3)
I/O9-17
I/O0-8(2)
CE
R/W
OE
UB
LB
SEM
H
X
X
X
X
H
High-Z
High-Z
Deselected: Power Down
X
X
X
H
H
H
High-Z
High-Z
Both Bytes Deselected
L
L
X
L
H
H
DATAIN
High-Z
Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATAIN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
H
L
L
H
H
DATAOUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
DATA OUT
Read Lower Byte Only
Mode
L
H
L
L
L
H
DATAOUT
DATA OUT
Read Both Bytes
X
X
H
X
X
X
High-Z
High-Z
Outputs Disabled
5624 tbl 02
NOTES:
1. A0L-A12L ≠ A0R-A12R for IDT70V35/34 and A0L -A11L ≠ A0R-A11R for IDT70V25/24.
2. Outputs for IDT70V25/24 are I/O0x-I/O7x.
3. Outputs for IDT70V25/24 are I/O8x-I/O15 x.
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
CE
R/W
OE
UB
LB
SEM
I/O9-17(1)
I/O0-8(1)
H
H
L
X
X
L
DATAOUT
DATAOUT
Read Data in Semaphore Flag
X
H
L
H
H
L
DATAOUT
DATAOUT
Read Data in Semaphore Flag
H
↑
X
X
X
L
DATAIN
DATAIN
Write I/O0 into Semaphore Flag
Mode
X
↑
X
H
H
L
DATAIN
DATAIN
L
X
X
L
X
L
____
____
Not Allowed
L
X
X
X
L
L
____
____
Not Allowed
Write I/O0 into Semaphore Flag
5624 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24). These eight semaphores
are addressed by A0-A2.
6.42
6
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
Maximum Operating Temperature
and Supply Voltage(1)
(1)
Symbol
Rating
Commercial
& Industrial
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-65 to +150
o
C
TJN
Junction Temperature
+150
o
C
IOUT
DC Output
Current
V TERM(2)
Grade
50
Industrial
Parameter
Input Capacitance
COUT
0OC to +70OC
0V
3.3V + 0.3V
-40OC to +85OC
0V
3.3V + 0.3V
Output Capacitance
5624 tbl 05
mA
Recommended DC Operating
Conditions
Symbol
Capacitance(1) (TA = +25°C, f = 1.0MHz)
(2)
VDD
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
5624 tbl 04
CIN
GND
Commercial
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
Symbol
Ambient
Temperature
Parameter
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
V
V
V DD
Supply Voltage
V SS
Ground
V IH
Input High Voltage
2.0
____
V DD+0.3(2)
VIL
Input Low Voltage
-0.3(1)
____
0.8
V
5624 tbl 06
Conditions
Max.
Unit
VIN = 0V
9
pF
VOUT = 0V
10
pF
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
5624 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
Symbol
|ILI|
|ILO|
VOL
VOH
Parameter
(1)
Input Leakage Current
(1)
Output Leakage Currentt
Output Low Voltage
Output High Voltage
Test Conditions
70V35/34/25/24S
70V35/34/25/24L
Min.
Max.
Min.
Max.
Unit
10
___
5
µA
VDD = 3.6V, VIN = 0V to VDD
___
CE = VIH, VOUT = 0V to VDD
___
10
___
5
µA
IOL = +4mA
___
0.4
___
0.4
V
2.4
___
2.4
___
V
IOH = -4mA
5624 tbl 08
NOTE:
1. At VDD < 2.0V leakages are undefined.
6.42
7
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34(1) (VDD = 3.3V ± 0.3V)
70V35/34X15
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CE = V IL, Outputs Disabled
SEM = V IH
f = fMAX(3)
70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
Typ. (2)
Max.
Typ. (2)
Max.
Typ. (2)
Max.
Unit
mA
COM'L
S
L
150
140
215
185
140
130
200
175
130
125
190
165
IND
S
L
____
____
225
195
____
____
140
130
____
____
____
____
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
MIL &
IND
S
L
____
____
45
40
____
____
20
15
____
____
____
____
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
MIL &
IND
S
L
____
____
130
115
____
____
80
75
____
____
____
____
Both Ports CEL and
CER > V DD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VDD - 0.2V
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
MIL &
IND
S
L
____
____
15
5
____
____
1.0
0.2
____
____
____
____
CE"A" < 0.2V and
CE"B" > V DD - 0.2V (5)
SEMR = SEML > VDD - 0.2V
VIN > VDD - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
MIL &
IND
S
L
____
____
____
____
80
75
130
115
____
____
____
____
CER and CEL = V IH
SEMR = SEML = VIH
f = fMAX(3)
CE"A" = V IL and CE"B" = VIH
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
(5)
mA
mA
mA
mA
5624 tbl 09
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. I DD DC = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
AC Test Conditions
Input Pulse Levels
3.3V
3.3V
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
590Ω
590Ω
3ns Max.
DATAOUT
BUSY
INT
DATAOUT
435Ω
30pF
435Ω
5pF*
Figures 1 and 2
,
5624 tbl 10
5624 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test
Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
Timing of Power-Up Power-Down
CE
ICC
tPU
tPD
50%
50%
ISB
5624 drw 07
6.42
8
,
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range for 70V25/24(1) (VDD = 3.3V ± 0.3V)
70V25/24X15
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
CE = VIL, Outputs Open
SEM = VIH
f = fMAX(3)
Version
70V25/24X20
Com'l
& Ind
70V25/24X25
Com'l
& Ind
Typ. (2)
Max.
Typ. (2)
Max.
Typ. (2)
Max.
Unit
190
165
mA
COM'L
S
L
150
140
215
185
140
130
200
175
130
125
IND
S
L
____
____
225
195
____
____
140
130
____
____
125
180
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
MIL &
IND
S
L
____
____
45
40
____
____
20
15
____
____
13
40
CE"A" = V IL and CE"B" = V IH
Active Port Outputs Open,
f=fMAX(3)
SEMR = SEML = V IH
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
MIL &
IND
S
L
____
____
130
115
____
____
80
75
____
____
72
110
Both Ports CEL and
CER > VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > V DD - 0.2V
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
MIL &
IND
S
L
____
____
15
5
____
____
1.0
0.2
____
____
0.2
5
CE"A" < 0.2V and
CE"B" > V DD - 0.2V(5)
SEMR = SEML > V DD - 0.2V
VIN > VDD - 0.2V or VIN < 0.2V
Active Port Outputs Open,
f = fMAX(3)
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
MIL &
IND
S
L
____
____
130
115
____
____
80
75
____
____
70
105
CER and CEL = VIH
SEMR = SEML = V IH
f = fMAX(3)
(5)
mA
mA
mA
mA
5624 tbl 09a
70V25/24X35
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CE = V IL, Outputs Open
SEM = V IH
f = fMAX(3)
70V25/24X55
Com'l Only
Typ. (2)
Max.
Typ. (2)
Max.
Unit
mA
COM'L
S
L
120
115
180
155
120
115
180
155
IND
S
L
____
____
____
____
____
____
____
____
COM'L
S
L
13
11
25
20
13
11
25
20
MIL &
IND
S
L
____
____
____
____
____
____
____
____
COM'L
S
L
70
65
100
90
70
65
100
90
MIL &
IND
S
L
____
____
____
____
____
____
____
____
Both Ports CEL and
CER > V DD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VDD - 0.2V
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
MIL &
IND
S
L
____
____
____
____
____
____
____
____
CE"A" < 0.2V and
CE"B" > V DD- 0.2V(5)
SEMR = SEML > VDD - 0.2V
VIN > VDD - 0.2V or VIN < 0.2V
Active Port Outputs Open,
f = fMAX(3)
COM'L
S
L
65
60
100
85
65
60
100
85
MIL &
IND
S
L
____
____
____
____
____
____
____
____
CER and CEL = V IH
SEMR = SEML = VIH
f = fMAX(3)
CE"A" = V IL and CE"B" = VIH
Active Port Outputs Open,
f=fMAX(3)
SEMR = SEML = VIH
(5)
mA
mA
mA
mA
5624 tbl 09b
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. I DD DC = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.42
9
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34(4)
70V35/34X15
Com'l Only
Symbol
Parameter
70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
ns
tAA
Address Access Time
____
15
____
20
____
25
ns
20
____
25
ns
20
____
25
ns
13
ns
tACE
Chip Enable Access Time
(3)
____
15
____
tABE
Byte Enable Access Time (3)
____
15
____
tAOE
Output Enable Access Time (3)
____
10
____
12
____
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
3
____
3
____
3
____
ns
____
10
____
12
____
15
ns
0
____
0
____
0
____
ns
____
15
____
20
____
25
ns
10
____
10
____
ns
____
20
____
25
ns
(1,2)
tLZ
Output Low-Z Time
tHZ
Output High-Z Time (1,2)
(1,2)
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time(1,2)
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
tSAA
Semaphore Address Access (3)
____
15
5624 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
Waveform of Read Cycles(5)
tRC
ADDR
(4)
CE
tAA
(4)
tACE
tAOE
(4)
OE
tABE
(4)
UB, LB
R/W
tLZ
DATAOUT
tOH
(1)
(4)
VALID DATA
tHZ
(2)
BUSYOUT
tBDD
(3,4)
5624 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE , tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
10
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V25/24(4)
70V25/24X15
Com'l Only
Symbol
Parameter
70V25/24X20
Com'l
& Ind
70V25/24X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
ns
tAA
Address Access Time
____
15
____
20
____
25
ns
tACE
Chip Enable Access Time (3)
____
15
____
20
____
25
ns
tABE
Byte Enable Access Time (3)
____
15
____
20
____
25
ns
tAOE
Output Enable Access Time (3)
____
10
____
12
____
13
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time(1,2)
3
____
3
____
3
____
ns
tHZ
Output High-Z Time (1,2)
____
10
____
12
____
15
ns
tPU
Chip Enable to Power Up Time (1,2)
0
____
0
____
0
____
ns
tPD
Chip Disable to Power Down Time (1,2)
____
15
____
20
____
25
ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
10
____
ns
tSAA
Semaphore Address Access (3)
____
15
____
20
____
25
ns
5624 tbl 11a
70V25/24X35
Com'l Only
Symbol
Parameter
70V25/24X55
Com'l Only
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
____
55
____
ns
tAA
Address Access Time
____
35
____
55
ns
tACE
Chip Enable Access Time (3)
____
35
____
55
ns
tABE
Byte Enable Access Time (3)
____
35
____
55
ns
tAOE
Output Enable Access Time (3)
____
20
____
30
ns
3
____
3
____
ns
3
____
3
____
ns
____
15
____
25
ns
0
____
0
____
ns
____
35
____
50
ns
15
____
15
____
ns
35
____
55
ns
tOH
tLZ
tHZ
tPU
Output Hold from Address Change
Output Low-Z Time
(1,2)
Output High-Z Time
(1,2)
Chip Enable to Power Up Time
(1,2)
(1,2)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
tSAA
Semaphore Address Access
(3)
____
5624 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = V IH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
6.42
11
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage for 70V35/34 (5)
70V35/34X15
Com'l Only
Symbol
Parameter
70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15
____
20
____
25
____
ns
12
____
15
____
20
____
ns
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
ns
WRITE CYCLE
tWC
tEW
tAW
tAS
tWP
tWR
Write Cycle Time
Chip Enable to End-of-Write
(3)
Address Valid to End-of-Write
Address Set-up Time
(3)
Write Pulse Width
Write Recovery Time
tDW
Data Valid to End-of-Write
10
____
15
____
15
____
tHZ
Output High-Z Time (1,2)
____
10
____
12
____
15
ns
tDH
Data Hold Time (4)
0
____
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z(1,2)
____
10
____
12
____
15
ns
tOW
Output Active from End-of-Write (1,2,4)
0
____
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
5624 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and t OW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
6.42
12
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage for 70V25/24 (5)
70V25/24X15
Com'l Only
Symbol
Parameter
70V25/24X20
Com'l
& Ind
70V25/24X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15
____
20
____
25
____
ns
12
____
15
____
20
____
ns
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
10
____
15
____
15
____
ns
____
10
____
12
____
15
ns
ns
WRITE CYCLE
Write Cycle Time
tWC
Chip Enable to End-of-Write
tEW
(3)
Address Valid to End-of-Write
tAW
Address Set-up Time
tAS
tWP
(3)
Write Pulse Width
Write Recovery Time
tWR
tDW
Data Valid to End-of-Write
Output High-Z Time
tHZ
(1,2)
(4)
tDH
Data Hold Time
0
____
0
____
0
____
tWZ
Write Enable to Output in High-Z(1,2)
____
10
____
12
____
15
ns
tOW
Output Active from End-of-Write (1,2,4)
0
____
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
5624 tbl 12a
70V25/24X35
Com'l Only
Symbol
Parameter
70V25/24X55
Com'l Only
Min.
Max.
Min.
Max.
Unit
35
____
55
____
ns
30
____
45
____
ns
30
____
45
____
ns
0
____
0
____
ns
25
____
40
____
ns
ns
WRITE CYCLE
tWC
tEW
tAW
tAS
tWP
Write Cycle Time
Chip Enable to End-of-Write
(3)
Address Valid to End-of-Write
Address Set-up Time
(3)
Write Pulse Width
tWR
Write Recovery Time
0
____
0
____
tDW
Data Valid to End-of-Write
15
____
30
____
ns
tHZ
Output High-Z Time (1,2)
____
15
____
25
ns
tDH
Data Hold Time (4)
0
tWZ
(1,2)
Write Enable to Output in High-Z
tOW
Output Active from End-of-Write
tSWRD
SEM Flag Write to Read Time
tSPS
SEM Flag Contention Window
(1,2,4)
____
0
____
ns
____
15
____
25
ns
0
____
0
____
ns
5
____
5
____
ns
5
____
5
____
ns
5624 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and t OW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
6.42
13
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE or SEM
CE or SEM
(9)
(9)
tAS
(6)
tWP
(3)
(2)
tWR
R/W
tWZ
(7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
5624 drw 09
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
tAW
(9)
CE or SEM
tAS (6)
UB or LB
tWR (3)
tEW (2)
(9)
R/W
tDW
tDH
DATAIN
5624 drw 10
NOTES:
1. R/W or CE or UB & LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or UB or LB.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP .
9. To access SRAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB and LB = VIH, and SEM = V IL. tEW must be met for either condition.
6.42
14
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
tSAA
A0-A2
VALID ADDRESS
tAW
VALID ADDRESS
tWR
tACE
tEW
SEM
tSOP
tDW
DATAIN
VALID
I/O0
tAS
tWP
DATAOUT
VALID(2)
tDH
R/W
tAOE
tSWRD
OE
Write Cycle
Read Cycle
5624 drw 11
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O 0-I/O15 for IDT70V25/24) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
5624 drw 12
NOTES:
1. DOR = DOL = V IL, CE R = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
6.42
15
,
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34(6)
70V35/34X15
Com'l Ony
Symbol
Parameter
70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15
____
20
____
20
ns
15
____
20
____
20
ns
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
tBDA
BUSY Disable Time from Address Not Matched
____
tBAC
BUSY Access Time from Chip Enable LOW
____
15
____
20
____
20
ns
tBDC
BUSY Dis able Time from Chip Enable HIGH
____
15
____
17
____
17
ns
5
____
5
____
5
____
ns
____
18
____
30
____
30
ns
12
____
15
____
17
____
ns
tAPS
Arbitration Priority Set-up Time
tBDD
BUSY Disable to Valid Data
tWH
Write Hold After BUSY
(2)
(3)
(5)
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write (4)
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
17
____
ns
____
30
____
45
____
50
ns
25
____
35
____
35
ns
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay
(1)
____
5624 tbl 13
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY (M/S = V IH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part number indicates power rating (S or L).
Timing Waveform of Write Port-to-Port Read and BUSY(2,4,5) (M/S = VIH)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDH
tDW
DATAIN "A"
VALID
tAPS
(1)
ADDR"B"
MATCH
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = V IL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”.
6.42
16
5624 drw 13
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V25/24(6)
70V25/24X15
Com'l Ony
Symbol
Parameter
70V25/24X20
Com'l
& Ind
70V25/24X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
15
____
20
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20
ns
tBAC
BUSY Access Time from Chip Enable LOW
____
15
____
20
____
20
ns
tBDC
BUSY Disable Time from Chip Enable HIGH
____
15
____
17
____
17
ns
5
tAPS
Arbitration Priority Set-up Time
tBDD
BUSY Disable to Valid Data
tWH
Write Hold After BUSY
(2)
(3)
(5)
____
5
____
5
____
ns
____
18
____
30
____
30
ns
12
____
15
____
17
____
ns
0
____
0
____
0
____
ns
12
____
15
____
17
____
ns
____
30
____
45
____
50
ns
25
____
35
____
35
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write (4)
tWH
Write Hold After BUSY
(5)
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay (1)
Write Data Valid to Read Data Delay
(1)
____
ns
5624 tbl 13a
70V25/24X35
Com'l Only
Symbol
Parameter
70V25/24X55
Com'l Only
Min.
Max.
Min.
Max.
Unit
20
____
45
ns
20
____
40
ns
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
tBDA
BUSY Disable Time from Address Not Matched
____
tBAC
BUSY Access Time from Chip Enable LOW
____
20
____
40
ns
tBDC
BUSY Disable Time from Chip Enable HIGH
____
20
____
35
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
35
____
40
ns
25
____
25
____
ns
0
____
0
____
ns
25
____
25
____
ns
____
60
____
80
ns
45
____
65
tWH
Write Hold After BUSY
(5)
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write (4)
tWH
Write Hold After BUSY
(5)
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay (1)
Write Data Valid to Read Data Delay
(1)
____
ns
5624 tbl 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY (M/S = V IH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part number indicates power rating (S or L).
6.42
17
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/W"A"
tWB
(3)
BUSY"B"
tWH
R/W"B"
(1)
(2)
5624 drw 14
,
NOTES:
1. tWH must be met for both master BUSY input (slave) and output (master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS (2)
CE"B"
tBAC
tBDC
BUSY"B"
5624 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDRESS "N"
tAPS
(2)
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
5624 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.42
18
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34(1)
70V35/34X15
Com'l Only
Symbol
Parameter
70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
0
____
0
____
0
____
ns
0
____
0
____
0
____
ns
ns
INTERRUPT TIMING
Address Set-up Time
tAS
tWR
Write Recovery Time
tINS
Interrupt Set Time
____
15
____
20
____
20
tINR
Interrupt Reset Time
____
15
____
20
____
20
ns
5624 tbl 14
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V25/24(1)
70V25/24X15
Com'l Only
Symbol
Parameter
70V25/24X20
Com'l
& Ind
70V25/24X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
0
____
0
____
0
____
ns
0
____
0
____
0
____
ns
INTERRUPT TIMING
Address Set-up Time
tAS
tWR
Write Recovery Time
tINS
Interrupt Set Time
____
15
____
20
____
20
ns
tINR
Interrupt Reset Time
____
15
____
20
____
20
ns
5624 tbl 14a
70V25/24X35
Com'l Only
Symbol
Parameter
70V25/24X55
Com'l Only
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
25
____
40
ns
25
____
40
ns
tINS
tINR
Interrupt Set Time
____
Interrupt Reset Time
____
5624 tbl 14b
NOTES:
1. 'X' in part number indicates power rating (S or L).
6.42
19
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
ADDR"A"
INTERRUPT SET ADDRESS
(2)
(3)
tAS
tWR
(4)
CE"A"
R/W"A"
tINS (3)
INT"B"
5624 drw 17
tRC
INTERRUPT CLEAR ADDRESS
ADDR"B"
(2)
tAS (3)
CE"B"
OE"B"
tINR
(3)
INT"B"
5624 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
20
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III — Interrupt Flag
(1)
Left Port
R/WL
CEL
OEL
L
L
X
X
X
X
X
X
X
Right Port
R/WR
CER
OER
1FFF(4)
X
X
X
X
X
X
X
X
L
L
1FFF(4)
(4)
X
L
(4)
INTL
A12L-A0L
X
L
(4)
1FFE
(3)
L
L
X
(2)
X
X
X
L
(4)
H
A12R-A0R
1FFE
INTR
Function
L(2)
Set Right INTR Flag
H(3)
Reset Right INTR Flag
X
Set Left INTL Flag
X
Reset Left INTL Flag
X
5624 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = V IL, then no change.
3. If BUSYR = VIL, then no change.
4. A12 is a NC for IDT70V34 and for IDT70V24, therefore Interrupt Addresses are FFF and FFE.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
(4)
CEL
CER
A12L-A0L
A12R-A0R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
Note (2)
Note (2)
Write Inhibit(3)
5624 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70V35/34 (IDT70V25/24) are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A12 is a NC for IDT70V34 and for IDT70V24. Address comparison will be for A0 - A11.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
D0 - D17 Left(2)
D0 - D17 Right(2)
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Functions
Status
5624 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V35/34 (IDT70V25/24).
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24). These eight semaphores
are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables.
6.42
21
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
BUSYL
CE
SLAVE
CE
Dual Port
SRAM
BUSYR
BUSYL
BUSYR
MASTER
CE
Dual Port
SRAM
BUSYR
BUSYL
SLAVE
CE
Dual Port
SRAM
BUSYR
BUSYL
DECODER
MASTER
Dual Port
SRAM
BUSYL
Industrial and Commercial Temperature Ranges
BUSYR
,
5624 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V35/34 (IDT70V25/24) SRAMs.
Functional Description
The IDT70V35/34 (IDT70V25/24) provides two ports with separate
control, address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT70V35/34 (IDT70V25/24) has
an automatic power down feature controlled by CE. The CE controls onchip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE HIGH). When a port is enabled,
access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 1FFE
(HEX) (FFE for IDT70V34 and IDT70V24), where a write is defined as
the CER = R/WR = VIL per Truth Table III. The left port clears the interrupt
on the IDT70V35 and IDT70V25 by an address location 1FFE (FFE for
IDT70V34 and IDT70V24) access when CEL = OEL = VIL, R/WL is a "don't
care". Likewise, the right port interrupt flag (INTR) is set when the left port
writes to memory location 1FFF for IDT70V35 and IDT70V25 (HEX) (FFF
for IDT70V34 and IDT70V24) and to clear the interrupt flag (INTR), the
right port must read the memory location 1FFF for IDT70V35 and
IDT70V25 (FFF for IDT70V34 and IDT70V24). The message (16 bits)
at 1FFE or 1FFF for IDT70V35 and IDT70V25 (FFE or FFF for
IDT70V34 and IDT70V24) is user-defined, since it is an addressable
SRAM location. If the interrupt function is not used, address locations 1FFE
and 1FFF for IDT70V35 and IDT70V25 (FFE and FFF for IDT70V34 and
IDT70V24) are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table III for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the SRAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the SRAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70V35/34 (IDT70V25/24) SRAM in
master mode, are push-pull type outputs and do not require pull up
resistors to operate. If these SRAMs are being expanded in depth, then
the BUSY indication for the resulting array requires the use of an external
AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V35/34 (IDT70V25/24) SRAM array in
width while using BUSY logic, one master part is used to decide which side
of the SRAM array will receive a BUSY indication, and to output that
indication. Any number of slaves to be addressed in the same address
range as the master, use the BUSY signal as a write inhibit signal. Thus
on the IDT70V35/34 (IDT70V25/24) SRAM the BUSY pin is an output if
the part is used as a master (M/S pin = VIH), and the BUSY pin is an input
if the part used as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT70V35/34 (IDT70V25/24) is an extremely fast Dual-Port 8/
4K x 18 (8/4K x 16) CMOS Static RAM with an additional 8 address
locations dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port SRAM to claim a privilege
over the other processor for functions defined by the system designer’s
6.42
22
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
software. As an example, the semaphore can be used by one processor
to inhibit the other from accessing a portion of the Dual-Port SRAM or any
other shared resource.
The Dual-Port SRAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be accessed
at the same time with the only possible conflict arising from the simultaneous
writing of, or a simultaneous READ/WRITE of, a non-semaphore location.
Semaphores are protected against such ambiguous situations and may
be used by the system program to avoid any conflicts in the nonsemaphore portion of the Dual-Port SRAM. These devices have an
automatic power-down feature controlled by CE, the Dual-Port SRAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM are both HIGH.
Systems which can best use the IDT70V35/34 (IDT70V25/24) contain
multiple processors or controllers and are typically very high-speed
systems which are software controlled or software intensive. These
systems can benefit from a performance increase offered by the IDT70V35/
34 (IDT70V25/24)'s hardware semaphores, which provide a lockout
mechanism without requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT70V35/34 (IDT70V25/24) does not use its semaphore flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very highspeed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port SRAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT70V35/34 (IDT70V25/
24) in a separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts as
a chip select for the semaphore flags) and using the other control pins
(Address, OE, and R/W) as they would be used in accessing a standard
static RAM. Each of the flags has a unique address which can be accessed
by either side through address pins A0 – A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
6.42
23
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
semaphore request latch. The critical case of semaphore timing is when
both sides request a single token by attempting to write a zero into it at the
same time. The semaphore logic is specially designed to resolve this
problem. If simultaneous requests are made, the logic guarantees that only
one side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be arbitrarily made
to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT70V35/34 (IDT70V25/24)’s Dual-Port
SRAM. Say the 8K x 18 SRAM was to be divided into two 4K x 18 blocks
which were to be dedicated at any one time to servicing either the left or
right port. Semaphore 0 could be used to indicate the side which would
control the lower section of memory, and Semaphore 1 could be defined
as the indicator for the upper section of memory.
To take a resource, in this example the lower 4K of Dual-Port SRAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 4K. Meanwhile the right processor was attempting to gain control of
the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 4K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
4K blocks of Dual-Port SRAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the DualPort SRAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
SEMAPHORE
REQUEST FLIP FLOP
Q
Q
D
WRITE
D0
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
5624 drw 20
Figure 4. IDT70V35/34 (IDT70V25/24) Semaphore Logic
6.42
24
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
A
Device Step Power
Type
999
A
Speed
Package
A
A
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
PF
G
J
100-pin TQFP (PN100-1) 70V35/34/25/24
84-Pin PGA (G84-3)
70V25/24
84-Pin PLCC (J84-1)
70V25/24
15
20
25
25
35
55
Commercial Only - 70V35/34/25/24
Commercial & Industrial - 70V35/34/25/24
Commercial Only - 70V35/34
Commercial & Industrial - 70V25/24
Commercial Only - 70V25/24
Commercial Only - 70V25/24
S
L
Standard Power
Low Power
Blank
T
No stepping designation
Current Stepping
,
Speed in Nanoseconds
70V35 144K (8K x 18-Bit) 3.3V Dual-Port RAM
70V34 72K (4K x 18-Bit) 3.3V Dual-Port RAM
70V25 128K (8K x 16-Bit) 3.3V Dual-Port RAM
70V24 64K (4K x 16-Bit) 3.3V Dual-Port RAM
5624 drw 21a
NOTES:
1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
Datasheet Document History
06/08/00:
08/09/01:
07/02/02:
06/22/04:
10/28/04:
04/05/05:
10/23/08:
Initial Public Offering
Page 1 Corrected I/O numbering
Page 5-7, 10 & 12 Removed Industrial temperature range offering for 25ns from DC & AC Electrical Characteristics
Page 17 Removed Industrial temperature range offering for 25ns speed from the ordering information
Added Industrial temperature offering footnote
Page 2 Added date revision for pin configuration
Added 70V34 to datasheet (4K x 18)
Consolidated 70V25/24 datasheets (8/4K x 16) into 70V35/34 (8/4K x 18) datasheet
Removed Preliminary status from datasheet
Page 2 & 3 Changed naming convention from VCC to VDD and from GND to VSS for PN100 packages
Page 7 Updated Conditions in Capacitance table
Page 7 Added Junction Temperature to Absolute Maximum Ratings table
Page 9, 11, 13, 17 &, 19 Added DC and AC Electrical Characteristics tables for 70V25/24 data
Page 21 & 22 Changed Interrupt flag table, footnotes and Interrupts text to reflect 70V25/24 data
Page 1 & 15 Replaced old ® logo with new TM logo
Page 25 Added stepping indicator to ordering information
Page 1 Added green availability to features
Page 25 Added green indicator to ordering information
Page 25 Removed "IDT" from orderable part number
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Technology,
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25
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