AD AD9148BBCZ Quad 16-bit,1 gsps, txdac digital-to-analog converter Datasheet

Quad 16-Bit,1 GSPS,
TxDAC+ Digital-to-Analog Converter
AD9148
Preliminary Technical Data
FEATURES
GENERAL DESCRIPTION
Single-carrier W-CDMA ACLR = 80 dBc @ 150 MHz IF
Channel-to-channel isolation > 90 dB
Analog output
Adjustable 8.7 mA to 31.7 mA
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator eases data interface
On-chip fine complex NCO allows carrier placement
anywhere in DAC bandwidth
High performance, low noise PLL clock multiplier
Multiple chip synchronization interface
Programmable digital inverse sinc filter
Auxiliary DACs allow for offset control
Gain DACs allow for I and Q gain matching
Programmable I and Q phase compensation
Digital gain control
Flexible LVDS digital I/F supports 32- or 16-bit bus widths
196-ball CSP_BGA, 12 mm × 12 mm
The AD9148 is a quad, 16-bit, high dynamic range, digital-toanalog converter (DAC) that provides a sample rate of 1000 MSPS.
These devices include features optimized for direct conversion
transmit applications, including gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with
analog quadrature modulators such as the ADL5371/ ADL5372/
ADL5373/ADL5374/ADL5375. A serial peripheral interface (SPI)
is provided for programming of the internal device parameters.
Full-scale output current can be programmed over a range of 10 mA
to 30 mA. The devices operate from 1.8 V and 3.3 V supplies for
a total power consumption of 3 W at the maximum sample rate.
They are enclosed in 196-ball chip scale package ball grid array
with the option of an attached heat spreader.
PRODUCT HIGHLIGHTS
1.
APPLICATIONS
2.
Wireless infrastructure
LTE, TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM
MIMO/transmit diversity
Digital high or low IF synthesis
3.
4.
Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals from baseband
to high intermediate frequencies.
A proprietary DAC output switching technique enhances
dynamic performance.
The current outputs are easily configured for various
single-ended or differential circuit topologies.
LVDS data input interface includes FIFO to ease input timing.
TYPICAL SIGNAL CHAIN
COMPLEX BASEBAND
COMPLEX IF
RF
fIF
LO ± fIF
DC
DIGITAL INTERPOLATION FILTERS
↑2
↑2
↑2
DAC1
POST DAC
ANALOG FILTER
AQM
↑2
↑2
↑2
DAC2
LO
↑2
↑2
↑2
DAC3
LO
PA
FPGA/ASIC/DSP
↑2
↑2
↑2
DAC4
AQM
PA
08910-001
POST DAC
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
Figure 1.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD9148
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Synchronizing Multiple Devices .............................................. 44
Applications ....................................................................................... 1
Synchronization with Clock Multiplication ............................... 44
General Description ......................................................................... 1
Synchronization with Direct Clocking .................................... 46
Product Highlights ........................................................................... 1
Additional Synchronization Features ...................................... 47
Typical Signal Chain......................................................................... 1
Interface Timing ............................................................................. 49
Revision History ............................................................................... 2
Digital Data Path ............................................................................ 50
Functional Block Diagram .............................................................. 3
Premodulation ............................................................................ 50
Specifications..................................................................................... 4
Programmable Inverse Sinc Filter ............................................ 50
DC Specifications ......................................................................... 4
Interpolation Filters ................................................................... 51
Input/Output Signal Specifications ............................................ 5
Fine Modulation ......................................................................... 54
Digital Input Data Timing Specifications ................................. 6
Clock Generation ........................................................................... 56
AC Specifications.......................................................................... 7
DAC Input Clock Configurations ............................................ 56
Absolute Maximum Ratings............................................................ 8
Driving the CLK_x and REFCLK_x Inputs ............................ 56
Thermal Resistance ...................................................................... 8
Direct Clocking .......................................................................... 56
Maximum Safe Power Dissipation ............................................. 8
Clock Multiplication .................................................................. 57
ESD Caution .................................................................................. 8
Analog Outputs............................................................................... 59
Pin Configurations and Function Descriptions ......................... 10
Transmit DAC Operation.......................................................... 59
Typical Performance Characteristics ........................................... 14
Auxiliary DAC Operation ......................................................... 60
Terminology .................................................................................... 20
Interfacing to Modulators ......................................................... 61
Serial Peripheral Interface ............................................................. 21
Device Power Dissipation.............................................................. 63
General Operation of the Serial Interface ............................... 21
Temperature Sensor ....................................................................... 65
Data Format ................................................................................ 21
Interrupt Request Operation ........................................................ 66
SPI Pin Descriptions .................................................................. 21
Interrupt Service Routine .......................................................... 66
SPI Options ................................................................................. 22
Interface Timing Validation .......................................................... 67
SPI Register Map............................................................................. 23
SED Operation............................................................................ 67
SPI Register Descriptions .......................................................... 25
SED Example .............................................................................. 67
Input Data Ports .............................................................................. 39
Test Access Port .............................................................................. 68
Dual-Port Mode .......................................................................... 39
Example Start-Up Routine ............................................................ 71
Single-Port Mode ........................................................................ 39
Derived PLL Settings ................................................................. 71
Byte Mode .................................................................................... 40
Derived NCO Settings ............................................................... 71
Data Interface Options .............................................................. 40
Start-Up Sequence ...................................................................... 71
FIFO Operation .............................................................................. 41
Device Verification Sequence ................................................... 71
Synchronizing and Resetting the FIFO ................................... 42
Outline Dimensions ....................................................................... 72
Monitoring the FIFO Status ...................................................... 43
Ordering Guide .......................................................................... 73
Device Synchronization ................................................................. 44
REVISION HISTORY
4/10—Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 73
Preliminary Technical Data
AD9148
FUNCTIONAL BLOCK DIAGRAM
310MHz
310MHz
fS/2
SINC–1
MOD
310MHz/620MHz
2×
2×
I OFFSET I GAIN
2×
32-BIT
NCO SIN
AUX2
16-BIT
DAC3
2×
2×
FIFO
I OFFSET I GAIN
AUX3
2×
fS/2
2×
2×
16-BIT
DAC4
SINC–1
MOD
AUX1_N
IOUT2_P
IOUT2_N
AUX2_P
AUX2_N
IOUT3_P
IOUT3_N
GAIN
Q OFFSET Q GAIN
DCIB_P/
DCIB_N
AUX1_P
GAIN
SINC–1
MOD
2×
FRAMEB_P/
FRAMEB_N
AUX1
16-BIT
DAC2
COS
fS/2
IOUT1_N
GAIN
2×
SINC–1
MOD
DATA RECEIVER
AUX3_P
AUX3_N
IOUT4_P
IOUT4_N
HB3_EN
HB3_CLK
HB2_EN
HB2_CLK
AUX4
HB1_CLK
INVSINE_EN
FILTER
COEFFICIENT
PREMOD_EN
PREMOD_CLK
INTERNAL CLOCK TIMING AND CONTROL LOGIC
AUX4_P
AUX4_N
GAIN/
OFFSET_CTRL
PLL_CTRL
REFERENCE
BIAS
VREF
I120
CLK_P
CLK_N
DAC_CLK
SERIAL
IN/OUT PORT
POWER-ON
RESET
MULTI-CHIP
SYNC
CLOCK
MULTIPLIER
(2× – 16×)
REFCLK_P/
SYNC_P
REFCLK_N/
SYNC_N
RESET
08910-002
SYNC
IRQ
PROGRAMMING
REGISTERS
SDO
SDIO
SCLK
CSB
MODE
GAIN
HB1_EN
16
fS/2
PHASE
CORRECTION
16
IOUT1_P
2×
Q OFFSET Q GAIN
2×
B[15:0]_P/
B[15:0]_N
1GHz
FIFO
FRAMEA_P/
FRAMEA_N
A[15:0]_P/
A[15:0]_N
500MHz/1GHz
16-BIT
DAC1
1.2GHz
DCIA_P/
DCIA_N
500MHz/1GHz
Figure 2.
Rev. PrA | Page 3 of 73
AD9148
Preliminary Technical Data
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current1
Output Compliance Range
Output Resistance
Gain DAC Monotonicity
Settling Time to Within ±0.5 LSB
TEMPERATURE DRIFT
Main DAC Offset
Main DAC Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
IOVDD
DVDD18
POWER CONSUMPTION (NCO OFF, PLL DISABLED, AND SINC−1 FILTER BYPASSED,
UNLESS OTHERWISE NOTED)
1 × Mode, fDAC = 300 MSPS, fINTERFACE = 600 MSPS
2 × Mode, fDAC = 500 MSPS, fINTERFACE = 500 MSPS
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, NCO On
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, PLL Enabled
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, Sinc−1 Filter Enabled
8 × Mode, fDAC = 1000 MSPS, fINTERFACE = 250 MSPS
Power-Down Mode
OPERATING RANGE
1
Based on a 10 kΩ external resistor.
Rev. PrA | Page 4 of 73
Min
8.66
−1.0
Typ
16
Max
Unit
Bits
±2.1
±3.7
LSB
LSB
±0.001
±2
20.2
% FSR
% FSR
mA
V
MΩ
31.66
+1.0
10
Guaranteed
20
ns
0.04
100
30
ppm/°C
ppm/°C
ppm/°C
1.2
5
V
kΩ
3.13
1.71
3.3
1.8
3.47
1.89
V
V
1.71
1.71
1.8/3.3
1.8
3.47
1.89
V
V
−40
0.79
1.49
2.18
2.47
2.23
2.44
2.48
0.03
+25
TBD
+85
W
W
W
W
W
W
W
W
°C
Preliminary Technical Data
AD9148
INPUT/OUTPUT SIGNAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL (SCLK, SDIO, CSB, RESET, TMS, TDI, TCK)
Input VIN Logic High (IOVDD = 1.8 V)
Input VIN Logic High (IOVDD = 3.3 V)
Input VIN Logic Low (IOVDD = 1.8 V)
Input VIN Logic Low (IOVDD = 3.3 V)
CMOS OUTPUT LOGIC LEVEL (SDIO, SDO, IRQ, PLL_LOCK, TDO)
Output VOUT Logic High (IOVDD = 1.8 V)
Output VOUT Logic High (IOVDD = 3.3 V)
Output VOUT Logic Low (IOVDD = 1.8 V)
Output VOUT Logic Low (IOVDD = 3.3 V)
LVDS RECEIVER INPUTS (A[15:0]_x, B[15:0]_x, DCIA_x, DCIB_x, FRAMEA_x, FRAMEB_x)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH to VIDTHL
Receiver Differential Input Impedance, RIN
LVDS Input Rate, fINTERFACE (See Table 4)
DAC CLOCK INPUT (CLK_P, CLK_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage (Self-Biasing, AC-Coupled)
Maximum Clock Rate
REFERENCE CLOCK INPUT (REFCLK_P/SYNC_P AND REFCLK_N/SYNC_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage (Self-Biasing, AC-Coupled)
Maximum Clock Rate
Minimum Clock Rate (PLL Enabled)
Loop Divider = /2
Loop Divider = /4
Loop Divider = /8
Loop Divider = /16
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High (tPWH)
Minimum Pulse Width Low (tPWL)
Set-Up Time, SDI to SCLK (tDS)
Hold Time, SDI to SCLK (tDH)
Data Valid, SDO to SCLK (tDV)
Setup time, CSB to SCLK (tDCSB)
Min
Typ
Max
Unit
0.6
0.8
V
V
V
V
0.4
0.4
V
V
V
V
E
1.2
2.0
E
Rev. PrA | Page 5 of 73
1.4
2.4
825
−100
1575
+100
20
80
100
120
1200
500
1.25
2000
mV
V
MSPS
500
1.25
2000
mV
V
MSPS
125
62.5
31.25
15.625
MSPS
MSPS
MSPS
MSPS
1000
100
mV
mV
mV
Ω
MSPS
500
40
12.5
12.5
1.9
0.2
23
1.4
MHz
ns
ns
ns
ns
ns
ns
AD9148
Preliminary Technical Data
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter
LATENCY (DACCLK CYCLES)
1× Interpolation (With or Without Coarse Modulation)
2× Interpolation (With or Without Coarse Modulation)
4× Interpolation (With or Without Coarse Modulation)
8× Interpolation (With or Without Coarse Modulation)
Inverse Sinc (1× Interpolation)
Inverse Sinc (2× Interpolation)
Inverse Sinc (4× Interpolation)
Inverse Sinc (8× Interpolation)
Fine Modulation
Power–Up Time
Min
Typ
Max
Unit
64
125
254
508
10
20
40
80
12
TBD
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
ms
Table 4. Maximum Rate
Interface Mode
Dual Port Mode
Single Port Mode or Byte Mode
fINTERFACE
620
1200
fDATA
310
300
32
DATA
PORT A
INPUT
LATCH
32
FIFO A
DATA
ASSEMBLER
Maximum Rate (MSPS)
fHB1
fHB2
620
1000
600
1000
32
2×
2×
2×
fHB3
1000
1000
fDAC
1000
1000
DAC1
AND
DAC2
WRITE PTR A
DCIA
READ PTR A
DATAPATH
CLK GENERATOR
AND DISTRIBUTOR
DACCLK
WRITE PTR B
DCIB
READ PTR B
DATAPATH
ONE DCI
INPUT
LATCH
DATA
ASSEMBLER
32
32
32
2×
2×
2×
FIFO B
DAC3
AND
DAC4
INTERFACE
MODE
fINTERFACE
fDATA
Figure 3. Defining Maximum Rates
Rev. PrA | Page 6 of 73
fHB1
fHB2
fHB3
fDAC
08910-003
DATA
PORT B
Preliminary Technical Data
AD9148
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 5.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 400 MSPS, fOUT = 80 MHz
fDAC = 600 MSPS, fOUT = 100 MHz
fDAC = 1000 MSPS, fOUT = 100 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 400 MSPS, fOUT = 100 MHz
fDAC = 600 MSPS, fOUT = 120 MHz
fDAC = 1000 MSPS, fOUT = 150 MHz
NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING
fDAC = 200 MSPS, fOUT = 80 MHz
fDAC = 400 MSPS, fOUT = 100 MHz
fDAC = 800 MSPS, fOUT = 100 MHz
W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER
fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL Off
fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL On
fDAC = 737.28 MSPS, fOUT = 200 MHz, PLL Off
fDAC = 737.28 MSPS, fOUT = 200 MHz, PLL On
W-CDMA ALTERNATE CHANNEL LEAKAGE RATIO, SINGLE CARRIER
fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL Off
fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL On
fDAC = 737.28 MSPS, fOUT = 200 MHz, PLL Off
fDAC = 737.28 MSPS, fOUT = 200 MHz, PLL On
Rev. PrA | Page 7 of 73
Min
Typ
Max
Unit
72
67
65
dBc
dBc
dBc
85
82
76
dBc
dBc
dBc
−160
−161
−162.5
dBm/Hz
dBm/Hz
dBm/Hz
−81
−78
−79
−72.5
dBc
dBc
dBc
dBc
−87
−83
−84
−80.5
dBc
dBc
dBc
dBc
AD9148
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 7. Thermal Resistance
Table 6.
Parameter
AVDD33, IOVDD
DVDD18, CVDD18
AGND
DGND
CGND
I120, VREF
OUT1_P, OUT1_N,
OUT2_P, OUT2_N,
OUT3_P, OUT3_N,
OUT4_P, OUT4_N
A15_P to A0_P,
A15_N to A0_N,
B15_P to B0_P,
B15_N, B0_N
DCIA_P, DCIA_N,
FRAMEA_P, FRAMEA_N,
DCIB_P, DCIB_N,
FRAMEB_P, FRAMEB_N
CLK_P, CLK_N,
REFCLK_P, REFCLK_N
CSB, SCLK, SDIO, SDO,
TDO, TDI, TCK, TMS,
RESET, IRQ, PLL_LOCK
Junction Temperature
Storage Temperature
Range
E
With
Respect To
AGND,
DGND,
CGND
AGND,
DGND,
CGND
DGND,
CGND
AGND,
CGND
AGND,
DGND
AGND
AGND
−0.3 V to AVDD33 + 0.3 V
−1.0 V to AVDD33 + 0.3 V
DGND
−0.3 V to DVDD18 + 0.3 V
DGND
−0.3 V to DVDD18+ 0.3 V
Package Type
196-Ball CSP_BGA
Rating
−0.3 V to +3.6 V
−0.3 V to +2.10 V
θJA
24.7
θJB
12.6
θJC
5.7
Unit
°C/W
19.2
10.9
5.3
°C/W
18.1
10.5
5.3
°C/W
18.0
10.5
5.3
°C/W
20.9
8.6
3.1
°C/W
16.2
7.7
3.1
°C/W
15.2
7.4
3.1
°C/W
15.0
7.4
3.1
°C/W
−0.3 V to +0.3 V
196-Ball BGA_EP
−0.3 V to +0.3 V
−0.3 V to +0.3 V
Notes
4-layer board,
25 PCB vias
8-layer board,
25 PCB vias
10-layer board,
25 PCB vias
12-layer board,
25 PCB vias
4-layer board,
25 PCB vias
8-layer board,
25 PCB vias
10-layer board,
25 PCB vias
12-layer board,
25 PCB vias
MAXIMUM SAFE POWER DISSIPATION
The maximum junction temperature for the AD9148 is 125°C.
With the thermal resistance of the molded package (CSP_BGA)
given for a 12 layer board, the maximum power that can be
dissipated in this package can be calculated as
PowerMAX =
CGND
DGND
−0.3 V to CVDD18 + 0.3
V
−0.3 V to IOVDD + 0.3 V
E
125°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Typical θJA, θJB, and θJC are specified vs. the number of PCB layers in
still air for each package offering Airflow increases heat dissipation
effectively reducing θJA and θJB.
(TJ − TA ) = (125 − 85) = 2.22W
θ JA
18.0
To increase the maximum power, the AD9148 is available in a
second package option (BGA_EP) which includes a heat spreader
on top of the package. Also, an external heat sink can be
attached to the top of the AD9148 CSP_BGA package. The
adjusted maximum power for each of these conditions is shown in
Table 8.
With the thermal resistance of the heat spreader package
(BGA_EP) given for a 12 layer board, the maximum power that
can be dissipated in this package can be calculated as
PowerMAX =
(TJ − TA ) = (125 − 85) = 2.67W
θ JA
15.0
To increase the maximum power, an external heat sink can be
attached to the top of the AD9148 BGA_EP package. The
adjusted maximum power for an external heat sink is shown in
Table 8.
To aid in the selection of package, the maximum fDAC rate for a given
power dissipation over several operating conditions is shown in
Table 9. The maximum fDAC rate applies to all interpolation rates.
Note that if the programmable inverse sinc filter is enabled the
maximum fDAC rate specified in Table 9 decreases.
ESD CAUTION
Rev. PrA | Page 8 of 73
Preliminary Technical Data
AD9148
Table 8. Thermal Resistance and Maximum Power
Package Type
196-ball CSP_BGA
196-ball CSP_BGA
196-ball BGA_EP
196-ball BGA_EP
1
TA (°C)
85
85
85
85
PCB
PCB Vias
25
25
25
25
PCB Layers
12
12
12
12
External Heatsink1
No
Yes
No
Yes
Case
CSP_BGA
CSP_BGA
BGA_EP
BGA_EP
TJ (°C)
125
125
125
125
θJA (°C/W)
18.0
16.0
15.0
14.0
Maximum
Power (W)
2.22
2.50
2.67
2.86
Heat sink is used in the thermal model: 13 mm × 13 mm, 15 mm tall.
Table 9. Power vs. fDAC Rate and Functionality
Maximum Power (W)
2.22
2.50
2.67
2.86
1
2
Package
CSP_BGA
CSP_BGA
BGA_EP
BGA_EP
Heat-Sink Combination2
No
Yes
No
Yes
Typical maximum fDAC rate with inverse sinc filter off.
Heat sink is used in the thermal model: 13 mm × 13 mm, 15 mm tall.
Rev. PrA | Page 9 of 73
Maximum fDAC (MSPS)1
Coarse Modulation
Fine Modulation (NCO)
PLL Off
PLL On
PLL Off
PLL On
820
740
695
630
950
875
810
740
1000
945
870
810
1000
1000
940
870
AD9148
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
3
4
6
7
8
9
11
12
A
2
OUT2
OUT2
CLK
VREF
I120
REF
OUT3
OUT3
A
B
AUX2
AUX2
CLK
NC
NC
REF
AUX3
AUX3
B
1
5
10
14
13
C
OUT1
AUX1
AUX4
OUT4 C
D
OUT1
AUX1
AUX4
OUT4 D
E
F
X
+
+
+
+
X
X
X
X
E
X
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
+
3
CVDD18
4
X
5
AVDD33
6
7
AVSS
8
10
9
CLK
11
12
13
POSITIVE
NEGATIVE
TERMINAL CLK TERMINAL
Figure 4. Pin Configuration (Top View), Analog and Clock Domain Pins
Rev. PrA | Page 10 of 73
14
08910-004
2
1
Preliminary Technical Data
3
4
5
6
7
8
10
9
11
12
13
14
A
A
B
B
C
C
D
D
E
E
F
F
G
SDO
CS
+
+
Trch
Trch
TMS
TDI
G
H
SDIO
SCLK
RST
IRQ
NC
PLL
TCK
TDO
H
J
FrB
DCIB
B0
B2
X
X
X
X
X
X
B11
B13
DCIA
FrA
J
K
FrB
DCIB
B0
B2
X
X
X
X
X
X
B11
B13
DCIA
FrA
K
L
A0
A2
B1
B3
B4
B5
B6
B7
B8
B9
B10
B12
B14
B15
L
M
A0
A2
B1
B3
B4
B5
B6
B7
B8
B9
B10
B12
B14
B15
M
N
A1
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
N
P
A1
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A15
+LVDS
+
IOVDD
X
DVDD18
DVSS
A15
TAP
INTERFACE
–LVDS
08910-005
2
1
SPI
INTERFACE
AD9148
Figure 5. Pin Configuration (Top View), Digital Domain Pins
Table 10. Pin Function Description
Pin No.
E6, E7, E8, E9
F5, F6, F7, F8, F9, F10
A1, A2, A5, A10, A13, A14, B1,
B2, B5, B10, B13, B14, C3, C4, C5,
C6, C7, C8, C9, C10, C11, C12, D3,
D4, D5, D6, D7, D8, D9, D10, D11,
D12E1, E2, E3, E4, E5, E10, E11,
E12, E13, E14, F1, F2, F3, F4, F11,
F12, F13, F14
G5, G6, G7, G8, G9, G10, H5, H6,
H7, H8, H9, H10
G3, G4
Mnemonic
CVDD18
AVDD33
AVSS
Description
1.8 V Clock Supply.
3.3 V Analog Supply.
Analog Supply Ground.
DVSS
Digital Supply Ground.
IOVDD
J5, J6, J7, J8, J9, J10, K5, K6, K7,
K8, K9, K10
B7, B8, H11
C1
D1
A3
A4
A11
A12
C14
D14
C2
D2
DVDD18
Supply for Serial Ports (SPI and TAP), RESET and IRQ. 1.8 V to 3.3 V can be
supplied to these pins.
1.8 V Digital Supply.
NC
IOUT1_N
IOUT1_P
IOUT2_N
IOUT2_P
IOUT3_P
IOUT3_N
IOUT4_N
IOUT4_P
AUX1_N
AUX1_P
Not Connect. Leave this pin unconnected.
DAC 1 Complementary Output Current.
DAC 1 Positive Output Current.
DAC 2 Complementary Output Current.
DAC 2 Positive Output Current.
DAC 3 Positive Output Current.
DAC 3 Complementary Output Current.
DAC 4 Complementary Output Current.
DAC 4 Positive Output Current.
Auxiliary DAC 1 Complementary Output Current.
Auxiliary DAC 1 Positive Output Current.
Rev. PrA | Page 11 of 73
AD9148
Preliminary Technical Data
Pin No.
B3
B4
B11
B12
C13
D13
A8
A7
Mnemonic
AUX2_N
AUX2_P
AUX3_P
AUX3_N
AUX4_N
AUX4_P
I120
VREF
B6, A6
B9, A9
H4
CLK_P/CLK_N
REFCLK_P/REFCLK_N or
SYNC_P/SYNC_N
IRQ
H3
G1
G2
H1
H2
G11, G12
H12
G13
G14
H13
H14
M1, L1
P1, N1
M2, L2
P2, N2
P3, N3
P4, N4
P5, N5
P6, N6
P7, N7
P8, N8
P9, N9
P10, N10
P11, N11
P12, N12
P13, N13
P14, N14
K13, J13
K14, J14
K3, J3
M3, L3
K4, J4
M4, L4
M5, L5
M6, L6
M7, L7
M8, L8
M9, L9
M10, L10
M11, L11
RESET
SDO
CSB
SDIO
SCLK
TRENCH
PLL_LOCK
TMS
TDI
TCK
TDO
A0_P/A0_N
A1_P/A1_N
A2_P/A2_N
A3_P/A3_N
A4_P/A4_N
A5_P/A5_N
A6_P/A6_N
A7_P/A7_N
A8_P/A8_N
A9_P/A9_N
A10_P/A10_N
A11_P/A11_N
A12_P/A12_N
A13_P/A13_N
A14_P/A14_N
A15_P/A15_N
DCIA_P/DCIA_N
FRAMEA_P/FRAMEA_N
B0_P/B0_N
B1_P/B1_N
B2_P/B2_N
B3_P/B3_N
B4_P/B4_N
B5_P/B5_N
B6_P/B6_N
B7_P/B7_N
B8_P/B8_N
B9_P/B9_N
B10_P/B10_N
Description
Auxiliary DAC 2 Complementary Output Current.
Auxiliary DAC 2 Positive Output Current.
Auxiliary DAC 3 Positive Output Current.
Auxiliary DAC 3 Complementary Output Current.
Auxiliary DAC 4 Complementary Output Current.
Auxiliary DAC 4 Positive Output Current.
Tie to analog ground via 10 kΩ resistor to generate a 120 μA reference current.
Band Gap Voltage Reference I/O. Decouple to analog ground via 0.1 μF
capacitor. Output impedance is approximately 5 kΩ.
Positive/Negative DAC Clock Input (CLK).
PLL Reference Clock Input (REFCLK_x). This pin has a secondary function as
a synchronization input (SYNC_x).
Active Low Open-Drain Interrupt Request Output. Pull up to IOVDD with
a 10 kΩ resistor.
An active low LVCMOS input resets the device. Pull up to IOVDD.
Serial Data Output for SPI.
Active Low Chip Select for SPI.
Serial Data Input/Output for SPI.
Qualifying Clock Input for SPI.
Connect this pin to VSS.
Active High LVCMOS Output. It indicates the lock status of the PLL circuitry.
TAP Test Mode Select
TAP Test Data Input.
TAP Test Clock Input.
TAP Test Data Output.
LVDS Data Input Pair, Port A (LSB).
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A (MSB).
LVDS Data Clock Input Pair for Port A.
LVDS Frame Input for Port A.
LVDS Data Input Pair, Port B (LSB).
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
Rev. PrA | Page 12 of 73
Preliminary Technical Data
Pin No.
K11, J11
M12, L12
K12, J12
M13, L13
M14, L14
K2, J2
K1, J1
Mnemonic
B11_P/B11_N
B12_P/B12_N
B13_P/B13_N
B14_P/B14_N
B15_P/B15_N
DCIB_P/DCIB_N
FRAMEB_P/FRAMEB_N
AD9148
Description
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B (MSB).
LVDS Data Clock Input Pair for Port B.
LVDS Frame Input for Port B.
Rev. PrA | Page 13 of 73
AD9148
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
–30
–30
fDATA = 200MSPS, SECOND HARMONIC
fDATA = 200MSPS, THIRD HARMONIC
fDATA = 310MSPS, SECOND HARMONIC
fDATA = 310MSPS, THIRD HARMONIC
–45
–35
–45
SPUR LEVEL (dBc)
–50
–55
–60
–65
–70
–60
–65
–70
–75
–80
–85
–85
0
50
100
150
200
250
300
–90
50
100
150
200
250
300
Figure 9. Highest Digital Spur vs. fOUT over fDATA, 2× Interpolation,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
–30
–30
fDATA = 150MSPS, SECOND HARMONIC
fDATA = 150MSPS, THIRD HARMONIC
fDATA = 250MSPS, SECOND HARMONIC
fDATA = 250MSPS, THIRD HARMONIC
–40
–45
–35
–45
SPUR LEVEL (dBc)
–50
–55
–60
–65
–70
–50
–55
–60
–65
–70
–75
–75
–80
–80
–85
–85
50
100
150
200
250
300
350
400
450
500
fOUT (MHz)
–90
0
08910-007
0
fDATA = 150MSPS, fDATA + fOUT
fDATA = 250MSPS, 2fDATA – fOUT
–40
50
100
150
200
250
300
350
400
450
500
fOUT (MHz)
Figure 7. Harmonic Level vs. fOUT over fDATA, 4× Interpolation,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
08910-010
–35
Figure 10. Highest Digital Spur vs. fOUT over fDATA, 4× Interpolation,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
–30
–30
–35
–35
fDATA = 125MSPS, SECOND HARMONIC
fDATA = 125MSPS, THIRD HARMONIC
–40
–40
–45
–50
–50
SPUR LEVEL (dBc)
–45
–55
–60
–65
–70
–55
–60
–70
–75
–75
–80
–80
–85
–85
–90
fDATA = 125MSPS, fDATA + FOUT
–65
–90
50
100
150
200
250
300
fOUT (MHz)
350
400
450
500
0
08910-008
0
Figure 8. Harmonic Level vs. fOUT, 8× Interpolation over fDATA = 125 MSPS,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
50
100
150
200
250
300
fOUT (MHz)
350
400
450
500
08910-011
–90
0
fOUT (MHz)
Figure 6. Harmonic Level vs. fOUT over fDATA, 2× Interpolation,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
HARMONIC LEVEL (dBc)
–55
–80
fOUT (MHz)
HARMONIC LEVEL (dBc)
–50
–75
–90
fDATA = 200MSPS, fDATA + fOUT
fDATA = 310MSPS, fDATA + fOUT
–40
08910-006
HARMONIC LEVEL (dBc)
–40
08910-009
–35
Figure 11. Highest Digital Spur vs. fOUT, 8× Interpolation, fDATA = 125 MSPS,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
Rev. PrA | Page 14 of 73
Preliminary Technical Data
AD9148
–30
–35
HARMONIC LEVEL (dBc)
–45
–50
–55
–60
–65
–70
–75
–50
–55
–60
–65
–70
–75
–80
–85
–85
0
50
100
150
200
250
300
fOUT (MHz)
–90
0
50
100
150
200
250
300
fOUT (MHz)
Figure 12. Second Harmonic vs. fOUT over Digital Scale,
Full-Scale Current = 20 mA, 4× Interpolation, fDATA = 150 MSPS
Figure 15. Third Harmonic vs. fOUT over Digital Scale,
Full-Scale Current = 20 mA, 4× Interpolation, fDATA = 150 MSPS
–30
0
10mA, SECOND HARMONIC
10mA, THIRD HARMONIC
20mA, SECOND HARMONIC
20mA, THIRD HARMONIC
30mA, SECOND HARMONIC
30mA, THIRD HARMONIC
–40
–45
–50
–10
–20
POWER LEVEL (dBm)
–35
HARMONIC LEVEL (dBc)
–45
–80
–90
0dBFS, THIRD HARMONIC
–6dBFS, THIRD HARMONIC
–12dBFS, THIRD HARMONIC
–18dBFS, THIRD HARMONIC
–40
08910-012
HARMONIC LEVEL (dBc)
–35
0dBFS, SECOND HARMONIC
–6dBFS, SECOND HARMONIC
–12dBFS, SECOND HARMONIC
–18dBFS, SECOND HARMONIC
–40
08910-015
–30
–55
–60
–65
–70
–75
–30
–40
–50
–60
–70
–80
50
100
150
200
250
300
fOUT (MHz)
–90
–10
–20
–20
POWER LEVEL (dBm)
–10
–30
–40
–50
–60
–90
500
600
FREQUENCY (MHz)
600
–60
–80
400
500
–50
–80
300
400
–40
–70
200
300
–30
–70
08910-014
POWER LEVEL (dBm)
0
100
200
Figure 16. 2× Interpolation, fDATA = 310 MSPS, fOUT = 131 MHz
0
0
100
FREQUENCY (MHz)
Figure 13. Second Harmonic vs. fOUT over Full-Scale Current,
Digital Scale = 0 dBFS, 4× Interpolation, fDATA = 150 MSPS
–90
0
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (MHz)
Figure 17. 8× Interpolation, fDATA = 125 MSPS, fOUT = 131 MHz
Figure 14. 4× Interpolation, fDATA = 150 MSPS, fOUT = 131 MHz
Rev. PrA | Page 15 of 73
08910-017
0
08910-013
–90
08910-016
–80
–85
AD9148
Preliminary Technical Data
–30
–30
–35
–35
–40
–40
–45
–45
fDATA = 200MSPS
fDATA = 310MSPS
–50
–50
fDATA = 150MSPS
fDATA = 250MSPS
–55
–60
IMD (dBc)
–65
–70
–60
–65
–70
–75
–75
–80
–80
–85
–85
–90
–90
–95
50
100
150
200
250
300
350
fOUT (MHz)
08910-018
0
–100
0
–30
–35
–40
–40
–45
–45
–50
–50
–55
–55
–60
IMD (dBc)
fDATA = 125MSPS
250
300
350
400
450
500
10mA
20mA
30mA
–60
–65
–70
–75
–75
–80
–80
–85
–85
–90
–90
–95
–95
50
100
150
200
250 300
fOUT (MHz)
350
400
450
500
–100
08910-019
0
–30
–30
–35
0dBFS
–6dBFS
–12dBFS
–18dBFS
–45
–50
50
100
150
200
250
300
300
Figure 22. IMD vs. fOUT over Full-Scale Current,
4× Interpolation, fDATA = 150 MSPS, Digital Scale = 0 dBFS
–35
–40
0
fOUT (MHz)
Figure 19. IMD vs. fOUT, 8× Interpolation, fDATA = 125 MSPS,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
–40
–45
PLL OFF
PLL ON
–50
–55
–55
IMD (dBc)
–60
–65
–70
–60
–65
–70
–75
–75
–80
–80
–85
–85
–90
–90
–95
–95
–100
–100
0
50
100
150
200
250
fOUT (MHz)
300
08910-020
IMD (dBc)
200
08910-022
IMD (dBc)
–30
–100
150
Figure 21. IMD vs. fOUT over fDATA, 4× Interpolation,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
–35
–70
100
fOUT (MHz)
Figure 18. IMD vs. fOUT over fDATA, 2× Interpolation,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
–65
50
08910-021
–95
–100
08910-023
IMD (dBc)
–55
Figure 20. IMD vs. fOUT over Digital Scale, 4× Interpolation,
fDATA = 150 MSPS, Full-Scale Current = 20 mA
0
50
100
150
200
250
fOUT (MHz)
Figure 23. IMD vs. fOUT ,PLL On and Off,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
Rev. PrA | Page 16 of 73
Preliminary Technical Data
AD9148
–144
–144
1×,
2×,
4×,
8×,
–146
200MSPS
200MSPS
200MSPS
100MSPS
–150
–150
–152
–152
–154
–156
–158
–162
–164
–164
100
150
200
250
fOUT (MHz)
300
350
–166
08910-024
50
400
0
50
100
150
200
250
300
350
400
fOUT (MHz)
Figure 27. 8-Tone NSD Performance vs. fOUT, Digital Scale = 0 dBFS,
Full-Scale Current = 20 mA
–144
–144
–146
–146
–150
–150
NSD (dBm/Hz)
–152
–154
–156
–158
–152
–154
–156
–158
–160
–160
–162
–162
–164
–164
50
100
150
200
250
fOUT (MHz)
300
350
–166
08910-025
–166
0
2×, 200MSPS
4×, 200MSPS
8×, 100MSPS
–148
400
Figure 25. Single-Tone NSD Performance vs. fOUT , Digital Scale = 0 dBFS,
4× fDATA = 200 MSPS, Full-Scale Current = 20 mA, PLL On
0
50
100
150
200
250
300
350
400
fOUT (MHz)
08910-028
2×, 200MSPS
4×, 200MSPS
8×, 100MSPS
–148
Figure 28. Single-Tone NSD Performance vs. fOUT, Digital Scale = 0 dBFS,
Full-Scale Current = 20 mA, PLL On
–144
–144
–146
–148
–148
–150
–152
–152
NSD (dBm/Hz)
–150
–154
–156
–158
–154
–156
–158
–160
–160
–162
–162
–164
–164
50
100
150
200
250
300
350
08910-026
–166
0
0dB
–6dB
–12dB
–18dB
–146
0dB
–6dB
–12dB
–18dB
400
fOUT (MHz)
Figure 26. Single-Tone NSD Performance vs. fOUT over Digital Scale,
4× fDATA = 200 MSPS, Full-Scale Current = 20 mA
Rev. PrA | Page 17 of 73
–166
0
50
100
150
200
250
300
350
400
fOUT (MHz)
Figure 29. 8-Tone NSD Performance vs. fOUT over Digital Scale,
4× fDATA = 200 MSPS, Full-Scale Current = 20 mA
08910-029
NSD (dBm/Hz)
–158
–162
Figure 24. Single-Tone NSD Performance vs. fOUT,, Digital Scale = 0 dBFS,
4× fDATA = 200 MSPS, Full-Scale Current = 20 mA
NSD (dBm/Hz)
–156
–160
–166
200MSPS
200MSPS
200MSPS
100MSPS
–154
–160
0
1×,
2×,
4×,
8×,
–148
NSD (dBm/Hz)
NSD (dBm/Hz)
–148
08910-027
–146
AD9148
Preliminary Technical Data
–50
–55
0dB, PLL ON
0dB, PLL OFF
–3dB, PLL OFF
–6dB, PLL OFF
–60
ACLR (dBc)
–65
–70
–75
–80
CENTER 150.00MHz
#RES BW 30kHz
VBW 300kHz
–90
0
50
100
150
200
250
300
350
fOUT (MHz)
08910-030
RMS RESULTS
–95
Figure 30. 1-Carrier W-CDMA ACLR vs. fOUT, Adjacent Channel,
4× Interpolation, fDATA = 184.32 MHz
CARRIER POWER
–13.47dBm/
3.84000MHz
FREQ
OFFSET
5.000MHz
10.00MHz
15.00MHz
REF BW
3.840MHz
3.840MHz
3.840MHz
SPAN 34.68MHz
SWEEP 112.5ms (601 PTS)
LOWER
dBc
dBm
UPPER
dBc
dBm
–78.88 –92.35
–82.12 –95.59
–82.18 –95.65
–77.98 –91.45
–82.65 –96.12
–82.28 –95.75
08910-033
–85
Figure 33. 1-Carrier W-CDMA ACLR, fOUT = 150 MHz,
4× Interpolation, fDATA = 184.32 MHz, PLL Off
–50
–55
0dB, PLL ON
0dB, PLL OFF
–3dB, PLL OFF
–6dB, PLL OFF
–60
ACLR (dBc)
–65
–70
–75
–80
CENTER 150.00MHz
#RES BW 30kHz
VBW 300kHz
–90
0
50
100
150
200
250
300
350
fOUT (MHz)
08910-031
RMS RESULTS
–95
Figure 31. 1-Carrier W-CDMA ACLR vs. fOUT, Alternate Channel,
4× Interpolation, fDATA = 184.32 MHz
CARRIER POWER
–12.77dBm/
3.84000MHz
FREQ
OFFSET
5.000MHz
10.00MHz
15.00MHz
REF BW
3.840MHz
3.840MHz
3.840MHz
SPAN 34.68MHz
SWEEP 112.5ms (601 PTS)
LOWER
dBc
dBm
UPPER
dBc
dBm
–74.50 –87.27
–82.72 –95.49
–82.97 –95.74
–73.79 –86.56
–82.99 –95.76
–83.54 –96.31
08910-034
–85
Figure 34. 1-Carrier W-CDMA ACLR, fOUT = 150 MHz,
4× Interpolation, fDATA = 184.32 MHz, PLL On
–50
–55
0dB, PLL ON
0dB, PLL OFF
–3dB, PLL OFF
–6dB, PLL OFF
–60
ACLR (dBc)
–65
–70
–75
–80
–85
0
50
100
150
200
fOUT (MHz)
250
300
350
Figure 32. 1-Carrier W-CDMA ACLR vs. fOUT, Second Alternate Channel,
4× Interpolation, fDATA = 184.32 MHz
Rev. PrA | Page 18 of 73
START 1.0MHz
#RES BW 30kHz
VBW 30kHz
STOP 368.6MHz
SWEEP 1.685s (601 PTS)
08910-035
–95
08910-032
–90
Figure 35. 1-Carrier W-CDMA, fOUT = 150 MHz, fDAC = 737.28 MSPS,
4× Interpolation, −3 dBFS
Preliminary Technical Data
CENTER 150.00MHz
#RES BW 30kHz
VBW 300kHz
AD9148
SPAN 59.58MHz
SWEEP 193.2ms (601 PTS)
2 –19.29dBm
3 –19.24dBm
4 –19.61dBm
FREQ
OFFSET
5.000MHz
10.00MHz
15.00MHz
INTEG BW
3.840MHz
3.840MHz
3.840MHz
LOWER
dBc
dBm
UPPER
dBc
dBm
–72.59 –91.81
–73.58 –92.81
–75.18 –94.40
–72.99 –92.22
–74.45 –93.67
–75.28 –94.51
START 1.0MHz
#RES BW 30kHz
STOP 368.6MHz
SWEEP 1.685s (601 PTS)
VBW 30kHz
08910-038
1 –19.14dBm
08910-036
TOTAL CARRIER POWER –13.30dBm/15.3600MHz
REF CARRIER POWER –19.14dBm/3.84000MHz
RCC FILTER: ON FILTER ALPHA 0.22
Figure 38. 4-Carrier W-CDMA, fOUT = 150 MHz, fDAC = 737.28 MSPS,
4× Interpolation, −3 dBFS
Figure 36. 4-Carrier W-CDMA, fOUT = 150 MHz, fDAC = 737.28 MSPS,
4× Interpolation, −3 dBFS, PLL Off
–80
–82
–84
–86
SPAN 59.58MHz
SWEEP 193.2ms (601 PTS)
TOTAL CARRIER POWER –13.28dBm/15.3600MHz
REF CARRIER POWER –19.07dBm/3.84000MHz
RCC FILTER: ON FILTER ALPHA 0.22
2 –19.42dBm
3 –19.28dBm
4 –19.45dBm
INTEG BW
3.840MHz
3.840MHz
3.840MHz
–92
–94
–96
–98
–100
–102
–104
LOWER
dBc
dBm
UPPER
dBc
dBm
–64.50 –83.67
–65.12 –84.29
–65.40 –84.57
–64.39 –83.56
–65.20 –84.37
–65.35 –84.52
–106
–108
–110
08910-037
1 –19.07dBm
FREQ
OFFSET
5.000MHz
10.00MHz
15.00MHz
–90
Figure 37. 4-Carrier W-CDMA, fOUT = 150 MHz, fDAC = 737.28 MSPS,
4× Interpolation, −3 dBFS, PLL On
0
50
100
150
fOUT (MHz)
200
250
300
08910-039
CENTER 150.00MHz
#RES BW 30kHz
VBW 300kHz
CROSSTALK (dB)
–88
Figure 39. Crosstalk (DAC Set 1 to DAC Set 2), 4× Interpolation,
fDATA = 150 MSPS, Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
Rev. PrA | Page 19 of 73
AD9148
Preliminary Technical Data
TERMINOLOGY
Integral Nonlinearity (INL)
INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero scale to full scale.
In-Band Spurious Free Dynamic Range (SFDR)
The difference, in decibels, between the peak amplitude of the
output signal and the peak spurious signal between dc and the
frequency equal to half the input data rate.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Out-of-Band Spurious Free Dynamic Range (SFDR)
The difference, in decibels, between the peak amplitude of the
output signal and the peak spurious signal within the band that
starts at the frequency of the input data rate and ends at the
Nyquist frequency of the DAC output sample rate. Normally,
energy in this band is rejected by the interpolation filters. This
specification, therefore, defines how well the interpolation
filters work and the effect of other parasitic coupling paths to
the DAC output.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTx_P, 0 mA output is expected when
the inputs are all 0s. For IOUTx_N, 0 mA output is expected
when all inputs are set to 1.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the difference between the output
when all inputs are set to 1 and the output when all inputs are
set to 0.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degrees Celsius. For reference drift, the drift is
reported in ppm per degrees Celsius.
Power Supply Rejection (PSR)
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band around its final value, measured from the
start of the output transition.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Interpolation Filter
An interpolation filter up-samples the input digital data by a
multiple of fDATA (interpolation rate) and then filters out the
undesired spectral images created by the up-sampling process.
Adjacent Channel Leakage Ratio (ACLR)
The ratio in dBc between the measured power within a channel
relative to its adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect of
wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
Rev. PrA | Page 20 of 73
Preliminary Technical Data
AD9148
SERIAL PERIPHERAL INTERFACE
DATA FORMAT
SDO G1
SCLK G2
The instruction byte contains the information shown in Table 11.
SPI
PORT
CSB H2
Table 11. SPI Instruction Byte
I7 (MSB)
R/W
08910-040
SDIO H1
Figure 40. SPI Port
The serial port is a flexible, synchronous serial communications
port allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola SPI and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9148.
Single- or multiple-byte transfers are supported, as well as MSBfirst or LSB-first transfer formats. The serial interface ports can
be configured as a single pin I/O (SDIO) or two unidirectional
pins for input/output (SDIO/SDO).
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the AD9148.
Phase 1 is the instruction cycle (the writing of an instruction
byte into the device), coincident with the first eight SCLK rising
edges. The instruction byte provides the serial port controller
with information regarding the data transfer cycle, Phase 2 of
the communication cycle. The Phase 1 instruction byte defines
whether the upcoming data transfer is a read or write and the
starting register address for the first byte of the data transfer.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the device.
A logic high on the CSB pin followed by a logic low resets the
SPI port timing to the initial state of the instruction cycle. From
this state, the next eight rising SCLK edges represent the instruction
bits of the current I/O operation, regardless of the state of the
internal registers or the other signal levels at the inputs to the
SPI port. If the SPI port is in an instruction cycle or a data
transfer cycle, none of the present data is written.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the device and
the system controller. Phase 2 of the communication cycle is a
transfer of one or more data bytes. Registers change immediately
upon writing to the last bit of each transfer byte.
I6
A6
I5
A5
I4
A4
I3
A3
I2
A2
I1
A1
I0 (LSB)
A0
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic high indicates a read operation, and Logic 0 indicates a
write operation.
A6 through A0—Bit 6 through Bit 0 of the instruction byte
determine the register that is accessed during the data transfer
portion of the communication cycle. For multibyte transfers, this
address is the starting byte address. The remaining register
addresses are generated by the device based on the LSB-first bit
(Register 0x00, Bit 6).
SPI PIN DESCRIPTIONS
Serial Clock (SCLK)
The serial clock pin synchronizes data to and from the device
and runs the internal state machines. The maximum frequency
of SCLK is 40 MHz. All data input is registered on the rising
edge of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CSB)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should stay
low during the entire communication cycle.
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However, this
pin can be used as a bidirectional data line. The configuration
of this pin is controlled by Register 0x00, Bit 7. The default is
Logic 0, configuring the SDIO pin as unidirectional.
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the device
operates in a single bidirectional I/O mode, this pin does not
output data and is set to a high impedance state.
Rev. PrA | Page 21 of 73
AD9148
Preliminary Technical Data
INSTRUCTION CYCLE
SPI OPTIONS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by the LSB first bit
(Register 0x00, Bit 6). The default is MSB first (LSB first = 0).
The serial port controller data address decrements from the data
address written toward 0x00 for multibyte I/O operations if the
MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x1F for
multibyte I/O operations if the LSB-first mode is active.
A4 A3
A2 A1
D7 D6N D5N
D30 D20 D10 D00
D7 D6 N D5N
D30 D20 D10 D0 0
N0 N1 R/W D0 0 D10 D20
D4N D5 N D6 N D7N
D00 D10 D20
D4N D5N D6 N D7N
tSCLK
CSB
tPWH
tPWL
tDCSB
SDIO
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
08910-043
SCLK
Figure 43. Timing Diagram for SPI Register Write
CSB
SCLK
tDV
SDIO
SDO
DATA TRANSFER CYCLE
A0
A3 A4
tDS
DATA BIT n
DATA BIT n – 1
Figure 44. Timing Diagram for SPI Register Read
08910-041
SDO
N0
A2
Figure 42. Serial Register Interface Timing LSB First
SCLK
R/W N1
A1
SDO
CSB
SDIO
A0
Figure 41. Serial Register Interface Timing MSB First
Rev. PrA | Page 22 of 73
08910-044
When LSB first = 1 (LSB first), the instruction and data bit must
be written from LSB to MSB. Multibyte data transfers in LSBfirst format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple data
bytes. The serial port internal byte address generator increments
for each byte of the multibyte communication cycle.
SDIO
08910-042
SCLK
When LSB first = 0 (MSB first), the instruction and data bit must
be written from MSB to LSB. Multibyte data transfers in MSBfirst format start with an instruction byte that includes the register
address of the most significant data byte. Subsequent data bytes
should follow from the high address to the low address. In MSBfirst mode, the serial port internal byte address generator decrements
for each data byte of the multibyte communication cycle.
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
Preliminary Technical Data
AD9148
SPI REGISTER MAP
Table 12. Register Map
Addr
0x00
Register
Name
Comm
Bit 7
SDIO
direction
PowerDown DAC
Set 1
Bit 6
LSB/
MSB first
PowerDown
DAC Set 2
Binary
format
Enable PLL
lock lost
Q first
enable
Enable
PLL lock
Bit 5
Software
reset
PowerDown
Data
Receiver
Dual-port
mode
Enable
sync
lock lost
Bit 4
DAC SPI
select
Power
control
0x03
Data format
0x04
Interrupt
Enable 0
0x05
Interrupt
Enable 1
0x06
Event Flag 0
0x07
Event Flag 1
0x08
0x0A
Clock
receiver
control
PLL Control 0
0x0C
0x0D
PLL Control 1
PLL Control 2
0x0E
0x0F
0x10
PLL Status 0
PLL Status 1
Sync Control 0
0x11
0x12
Sync Control 1
Sync Status 0
0x14
Data receiver
control
Data receiver
status
LVDS rcvr
frame high
LVDS rcvr
frame low
LVDS rcvr
DCI high
LVDS rcvr
DCI low
0x17
FIFO Status/
Control Port A
FIFO
Warning 1
FIFO
Warning 2
FIFO reset
aligned
FIFO SPI
align ack
0x18
FIFO Status
Port A
FIFO Status/
Control Port B
FIFO
Warning 1
FIFO
Warning 2
FIFO reset
aligned
FIFO SPI
align ack
Enable
pre mod
Bypass
sinc−1
0x15
0x19
0x1A
0x1C
FIFO Status
Port B
HB1 control
0x1D
HB2 control
0x1E
HB3 control
0x1F
CHIP ID
Bus swap
Sync lock
lost
REFCLK
CLK cross
duty
correction
correction
PLL enable
PLL
manual
enable
PLL Loop Bandwidth[2:0]
N2[1:0]
Sync
enable
FIFO rate/
data rate
toggle
Sync lost
Sync
locked
One DCI
Bit 1
Byte
swap
Enable
FIFO SPI
aligned
Enable
SED
compare
fail
FIFO SPI
aligned
SED
compare
fail
1
Enable AED
compare
fail
Sync lock
AED compare
pass
CLK duty
correction
Byte mode
Enable
sync lock
Enable AED
compare pass
PLL lock
Bit 2
Bit 0
Default
0x00
0x00
0x01
PLL lock
lost
Bit 3
REFCLK cross
correction
AED
compare
fail
0
0x20
Enable
FIFO
Warning 1
Enable
FIFO
Warning 2
0x00
FIFO
Warning 1
FIFO
Warning 2
1
1
Manual VCO Band[5:0]
0
PLL cross
control enable
1
0x00
0x37
0x40
0
0
N0[1:0]
1
N1[1:0]
PLL Control Voltage[3:0]
VCO Band Readback[5:0]
Rising
Sync Averaging[2:0]
edge sync
Sync Phase Request[5:0]
0xF1
0xD9
0x08
0x00
0x00
LVDS rcvr
Port B high
FIFO SPI
align
requesting
FIFO Level[7:0]
LVDS rcvr
LVDS rcvr
LVDS rcvr
Port B
Port A
Port A low
low
high
FIFO Phase Offset[2:0]
FIFO SPI
align
requesting
FIFO Level[7:0]
FIFO Phase Offset[2:0]
HB1[1:0]
HB2[2:0]
Bypass
phase adj
HB3[2:0]
Chip ID[7:0]
Rev. PrA | Page 23 of 73
Bypass
HB1
Bypass
HB2
Bypass
HB3
0x00
0x00
0x40
0x00
0x81
0x20
AD9148
Preliminary Technical Data
0x211
Register
Name
Coeff I Byte0
Coeff I Byte1
1
0x22
Coeff I Byte 2
0x231
Coeff I Byte 3
0
0x241
Coeff Q Byte 0
0
0x251
Coeff Q Byte 1
Coeff_3q[2:0]
1
0x26
Coeff Q Byte 2
Coeff_4q[2:0]
0x271
Coeff Q Byte3
1
0x28
I phase adj LSB
0x291
I phase adj
MSB
Q phase adj
LSB
Q phase adj
MSB
I DC offset LSB
Addr
0x201
0x2A1
0x2B1
0x2C1
1
0x2D
0x2E1
0x2F1
IDAC FSC adj
1
0x31
IDAC control
0x321
AUX IDAC data
0x33
AUX IDAC
control
0x341
QDAC FSC adj
0x351
QDAC control
0x361
AUX QDAC
data
AUX QDAC
control
0x371
Bit 6
Bit 5
Bit 4
Coeff_1i[3:0]
Bit 3
Coeff_3i[2:0]
Bit 2
Bit 1
Bit 0
Coeff_0i[2:0]
Coeff_2i[4:0]
Coeff_4i[2:0]
0
Coeff_3i[6:3]
0x7F
Coeff_1q[3:0]
Coeff_0q[2:0]
Coeff_2q[4:0]
0
0
0x0D
Coeff_4q[9:3]
0x00
0x00
Phase Word I[9:8]
Phase Word Q[7:0]
0x00
0x00
Phase Word Q[9:8]
0x00
DC Offset I[7:0]
0x00
DC Offset I[15:8]
0x00
DC Offset Q[7:0]
0x00
DC Offset Q[15:8]
0x00
IDAC FSC Adj[7:0]
0xF9
IDAC sleep
IDAC FSC Adj[9:8]
AUX IDAC Data[7:0]
AUX IDAC
current
direction
0x69
0xE6
Coeff_3q[6:3]
Phase Word I[7:0]
AUX IDAC
sign
Default
0x00
0xC0
0xEF
Coeff_4i[9:3]
I DC offset
MSB
Q DC offset
LSB
Q DC offset
MSB
0x301
1
Bit 7
0
0x01
0x00
AUX IDAC
power
down
AUX IDAC Data[9:8]
0x00
QDAC FSC Adj[9:8]
0x01
QDAC FSC Adj[7:0]
0xF9
QDAC sleep
AUX QDAC Data[7:0]
0x00
AUX QDAC Data[9:8]
0x00
0x381
SED_S0_L
AUX QDAC
power
down
SED Compare Pattern Sample0[7:0]
0x391
SED_S0_H
SED Compare Pattern Sample0[15:8]
0x3A1
SED_S1_L
SED Compare Pattern Sample1[7:0]
0x45
1
SED_S1_H
SED Compare Pattern Sample1[15:8]
0xEA
0x3B
AUX QDAC
sign
AUX QDAC
current
direction
0xB6
0x7A
0x3C1
SED3_S2_L
SED Compare Pattern Sample2[7:0]
0x16
0x3D1
SED3_S2_H
SED Compare Pattern Sample2[15:8]
0x1A
0x3E1
SED4_S3_L
SED Compare Pattern Sample3[7:0]
0xC6
0x3F1
0x40
SED4_S3_H
SED Compare Pattern Sample3[15:8]
0xAA
0x411
SED_R_L
Autoclear
enable
SED Status Rising Edge Samples[7:0]
0x421
SED_R_H
SED Status Rising Edge Samples[15:8]
0x431
SED_F_L
SED Status Falling Edge Samples[7:0]
0x441
SED_F_H
SED Status Falling Edge Samples[15:8]
0x501
I gain control
I Gain[7:0]
0x40
1
Q gain control
Q Gain[7:0]
0x40
0x51
SED control/
status
SED
compare
enable
Port B
error
detected
Port A
error
detected
Rev. PrA | Page 24 of 73
Port B
compare
failed
Port A
compare
failed
Compare
passed
0x00
Preliminary Technical Data
Addr
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
Register
Name
FTW (LSB)
FTW
FTW
FTW (MSB)
Phase offset
(MSB)
Phase offset
(LSB)
DDS/mod
control
0x5C
Die Temp
Control 0
0x5D
Die Temp
Control 1
Die temp LSB
Die temp MSB
DCI delay
PLL Ctrl (Test)
0x5E
0x5F
0x72
0x79
1
Bit 7
Bit 6
AD9148
Bit 5
Bit 4
Bit 3
FTW[7:0]
FTW [15:8]
FTW[23:16]
FTW[31:24]
NCO Phase Offset[15:8]
Bit 2
Bit 1
Bit 0
Default
0x00
0x00
0x00
0x00
0x00
NCO Phase Offset[7:0]
Bypass
DDS/MOD
Frame NCO
reset ack
Frame NCO
reset request
0x00
FTW
update ack
Sideband
select
0x80
0x01
1
Temp
Sensor
power
down
0
1
DCI Delay[1:0]
1
0x00
0x40
FTW
update
request
Latch
temp
data
0
0
0
0
1
0
0x20
Die Temp[7:0]
Die Temp[15:8]
1
1
1
1
1
1
Register 0x20 to Register 0x3F and Register 0x41 to Register 0x51 configure DAC 1 (I) and DAC 2 (Q) data paths with DAC SPI select = 0 (Register 0x00[4]). Register 0x20
to Register 0x3F and Register 0x41 to Register 0x51 configure DAC 3 (I) and DAC 4 (Q) data paths with DAC SPI select = 1 (Register 0x00[4]).
SPI REGISTER DESCRIPTIONS
Table 13. Register Descriptions
Register Name
Addr
(Hex)
Bit
Name
Function
Default
Comm
00
7
SDIO
SDIO operation.
0
0 = SDIO operates as an input only.
1 = SDIO operates as bidirectional input/output.
6
LSB/MSB first
SPI communication LSB first (default is MSB first).
0
0 = MSB first.
1 = LSB first.
5
Software Reset
Software reset.
0
Reset is asserted when this bit transitions from 0 to 1.
4
DAC SPI select
Selects which DAC data path Register 0x20 to Register 0x3F and
Register 0x41 to Register 0x51 configure.
0
0 = DAC 1 (I path) and DAC 2 (Q path) are configured.
0
1 = DAC 3 (I path) and DAC 4 (Q path) are configured.
Power Control
01
7
Power-Down
DAC Set 1
Power down DAC 1 and power down DAC 2.
0
6
Power-Down
DAC Set 2
Power-down DAC 3 and power down DAC 4.
0
5
Power-down
data receiver
Power down the input data receiver.
0
Rev. PrA | Page 25 of 73
AD9148
Preliminary Technical Data
Register Name
Addr
(Hex)
Bit
Name
Function
Default
Data Format
03
7
Binary format
Input data is in twos complement format (0) or unsigned
binary format (1).
0
6
Q first enable
Indicates I/Q data pairing on data input; I first (0), Q first (1).
0
5
Dual port mode
Number of input data ports used.
1
Single port (0), dual port (1).
4
Bus swap
0 = normal data input bus pin out (MSB to LSB).
0
1 = inverted data input bus pin out (LSB to MSB).
3
Byte mode
0 = data input bus is 16-bit wide on each port.
0
1 = data input bus is two 8-bit wide buses on Port A.
2
Byte swap
0 = normal data input bus pin out (MSB to LSB).
0
1 = inverted data input bus pin out (LSB to MSB).
Interrupt Enable 0
Interrupt Enable 1
04
05
7
Enable PLL lock lost
Enables interrupt for PLL lock lost.
0
6
Enable PLL lock
Enables interrupt for PLL lock.
0
5
Enable sync
lock lost
Enables interrupt for sync lock lost.
0
4
Enable sync lock
Enables interrupt for sync lock.
0
2
Enable FIFO
SPI aligned
Enables interrupt for FIFO SPI aligned.
0
1
Enable FIFO
Warning 1
Enables interrupt for FIFO Warning 1.
0
0
Enable FIFO
Warning 2
Enables interrupt for FIFO Warning 2.
0
4
Enable AED
compare pass
Enable interrupt for AED compare pass.
0
3
Enable AED
compare fail
Enables interrupt for AED compare fail.
0
2
Enable SED
compare fail
Enables interrupt for SED compare fail.
0
Rev. PrA | Page 26 of 73
Preliminary Technical Data
Register Name
Addr
(Hex)
06
Event Flag 0 (All bits
are high when interrupt
is active. Clear interrupt
by writing respective
bit high.)
Event Flag 1(All bits are 07
high when interrupt is
active. Clear interrupt
by writing respective
bit high).
Clock receiver control
PLL Control 0
PLL Control 1
08
0A
0C
AD9148
Bit
Name
Function
Default
7
PLL lock lost
1 = indicates that the PLL that was previously locked, has
unlocked from the reference signal.
0
6
PLL lock
1 = indicates that the PLL has locked to the reference clock
input.
0
5
Sync lock lost
1 = indicates that the sync logic that was previously locked,
has lost alignment.
0
4
Sync lock
1 = indicates that the sync logic achieved sync alignment. This 0
is indicated when no phase changes are requested for at least
a few full averaging cycles.
2
FIFO SPI aligned
1 = indicates that a FIFO reset originating from a serial portbased request has successfully completed.
0
1
FIFO Warning 1
1 = indicates that the difference between the FIFO read and
write pointers is 1.
0
0
FIFO Warning 2
1 = indicates that the difference between the FIFO read and
write pointers is 2.
0
4
AED compare pass
1 = indicates that the SED logic detected a valid input data
pattern comparison against the preprogrammed expected
values.
0
3
AED compare fail
1 = indicates that the SED logic detected an invalid input data 0
pattern comparison against the preprogrammed expected
values. This automatically clears when eight valid I/Q data
pairs are received.
2
SED compare fail
1 = indicates that the SED logic detected an invalid input data 0
pattern comparison against the preprogrammed expected
values.
7
CLK duty
correction
Enables duty-cycle correction on CLK input.
0
6
REFCLK duty
correction
Enables duty-cycle correction on REFCLK input.
0
5
CLK cross
correction
Enables differential crossing correction on CLK input.
1
4
REFCLK cross
correction
Enables differential crossing correction on REFCLK input.
1
3:0
0111
Always set these bits to 0111
0111
7
PLL enable
Enables PLL clock multiplier.
0
6
PLL manual
enable
Enables PLL band selection mode (0 = auto, and 1 = manual).
1
5:0
Manual VCO band
VCO band used in manual mode.
0
7:5
PLL loop bandwidth Selects PLL loop filter bandwidth.
110
000 = narrowest bandwidth.
…
111 = widest bandwidth.
4:0
01001
Set these bits to 01001 for optimal PLL operation.
Rev. PrA | Page 27 of 73
10001
AD9148
Preliminary Technical Data
Register Name
Addr
(Hex)
Bit
Name
Function
Default
PLL Control 2
0D
7:6
N2
DAC CLK to PLL controller clock rate (fPC_CLK).
11
00 = 2.
01 = 4.
10 = 8.
11 = 16.
fPC_CLK must always be less than 50 MHz.
4
PLL cross
control enable
Enables PLL cross point control.
3:2
N0
VCO to DACCLK divider.
001
00 = 1.
01 = 2.
10 = 4.
11 = 4.
1:0
N1
DACCLK-to-REFCLK divider.
01
00 = 2.
01 = 4.
10 = 8.
11 = 16.
PLL Status 0
0E
3:0
PLL control voltage
PLL VCO control voltage readback value.
Readonly
PLL Status 1
0F
5:0
VCO band readback
VCO band value.
Readonly
Sync Control 0
10
7
Sync enable
Enables synchronization logic.
0
6
FIFO rate/data
rate toggle
Operates synchronization at the FIFO reset rate (0)/data rate (1).
0
3
Rising edge sync
Rising edge of CLK samples sync input (1), falling edge of
CLK samples sync input (0).
1
2:0
Sync averaging
Average sync input of number of samples.
000
000 = 1.
001 = 2.
010 = 4.
011 = 8.
100 = 16.
101 = 32.
110 = 64.
111 = 128.
Rev. PrA | Page 28 of 73
Preliminary Technical Data
AD9148
Register Name
Addr
(Hex)
Bit
Name
Function
Default
Sync Control 1
11
5:0
Sync phase request
Offset of internal divided by 64 clock phase after sync.
000000
000000 = 0 DAC clocks.
…
111111 = 63 DAC clocks.
Sync Status 0
Data Receiver Control
12
14
7
Sync Lost
Synchronization lost.
Readonly
6
Sync locked
Synchronization found.
Readonly
6
One DCI
0 = two DCIs used, DCIA_x and DCIB_x.
0
1 = one DCI used, DCIA_x.
Data Receiver Status
FIFO status/
Control Port A
15
17
7
LVDS receiver
frame high
Frame input LVDS level > 1.7 V.
Readonly
6
LVDS receiver
frame low
Frame input LVDS level < 0.7 V.
Readonly
5
LVDS receiver
DCI high
DCI input LVDS level > 1.7 V.
Readonly
4
LVDS receiver
DCI low
DCI input LVDS level < 0.7 V.
Readonly
3
LVDS receiver
Port B high
Port B input LVDS level > 1.7 V.
Readonly
2
LVDS receiver
Port B low
Port B input LVDS level < 0.7 V.
Readonly
1
LVDS receiver
Port A high
Port A input LVDS level > 1.7 V.
Readonly
0
LVDS receiver
Port A low
Port A input LVDS level < 0.7 V.
Readonly
7
FIFO Warning 1
FIFO read and write pointers within ±1.
Readonly
6
FIFO Warning 2
FIFO read and write pointers within ±2
Readonly
5
FIFO reset aligned
FIFO read and write pointers aligned after chip reset.
Readonly
4
FIFO SPI align
acknowledge
FIFO read and write pointers aligned after SPI driven
FIFO reset.
Readonly
3
FIFO SPI align
requesting
Request FIFO read and write pointers alignment via SPI.
0
2:0
FIFO phase offset
FIFO read and write pointer phase offset from optimal
phase following FIFO reset.
000
000 = 0 offset from optimal phase.
…
111 = 7 offset from optimal phase.
The optimal value is 0.
Rev. PrA | Page 29 of 73
AD9148
Preliminary Technical Data
Register Name
Addr
(Hex)
Bit
Name
Function
Default
FIFO Status Port A
18
7:0
FIFO Level
Thermometer encoded measure of the FIFO level.
Readonly
7
FIFO Warning 1
FIFO read and write pointers within ±1.
Readonly
6
FIFO Warning 2
FIFO read and write pointers within ±2.
Readonly
5
FIFO reset aligned
FIFO read and write pointers aligned after chip reset.
Readonly
4
FIFO SPI align
acknowledge
FIFO read and write pointers aligned after SPI driven FIFO
reset.
Readonly
3
FIFO SPI align
requesting
Request FIFO read and write pointers alignment via SPI.
0
2:0
FIFO phase offset
FIFO read and write pointer phase offset from optimal
phase following FIFO reset.
000
FIFO status/
Control Port B
000 = 0 offset from optimal phase.
…
111 = 7 offset from optimal phase.
The optimal value is 0.
FIFO Status Port B
1A
7:0
FIFO level
Thermometer encoded measure of the FIFO Level
Readonly
HB1 Control
1C
7
Enable pre mod
Enable fS/2 modulation stage that precedes Stage 1
interpolation filter.
0
6
Bypass sinc-1
Sinc-1 filter bypass.
1
2:1
HB1[1:0]
Modulation mode for first stage interpolation filter
(fHB1 = 2 × fIN1).
00
00 = input signal modulated by dc. Filter pass band is
from −0.2 to +0.2 of fHB1.
01 = input signal modulated by dc. Filter pass band is
from 0.05 to 0.45 of fHB1.
10 = input signal modulated by fHB1/2. Filter pass band is
from 0.3 to 0.7 of fHB1.
11 = input signal modulated by fHB1/2. Filter pass band is
from 0.55 to 0.95 of fHB1.
0
Bypass HB1
First stage interpolation filter bypass.
Rev. PrA | Page 30 of 73
0
Preliminary Technical Data
Register Name
Addr
(Hex)
Bit
HB2 Control
AD9148
Name
Function
Default
HB2[2:0]
Modulation mode for second stage interpolation filter
(fHB2 = 2 × fIN2).
000
000 = input signal modulated by dc. Filter pass band is
from −0.1 to +0.1 of fHB2.
001 = input signal modulated by dc. Filter pass band is
from 0.025 to 0.225 of fHB2.
010 = input signal modulated by fHB2/4. Filter pass band is
from 0.15 to 0.35 of fHB2.
011 = input signal modulated by fHB2/4. Filter pass band is
from 0.275 to 0.475 of fHB2.
100 = input signal modulated by fHB2/2. Filter pass band is
from 0.4 to 0.6 of fHB2.
101 = input signal modulated by fHB2/2. Filter pass band is
from 0.525 to 0.725 of fHB2.
110 = input signal modulated by 3fHB2/4. Filter pass band is
from 0.65 to 0.85 of fHB2.
111 = input signal modulated by 3fHB2/4. Filter pass band is
from 0.775 to 0.975 of fHB2.
HB3 Control
1E
0
Bypass HB2
Second stage interpolation filter bypass.
0
7
Bypass Phase Adj
1 = bypass phase compensation.
1
3:1
HB3[2:0]
Modulation mode for third stage interpolation filter
(fHB3 = 2 × fIN3).
000
000 = input signal modulated by dc. Filter pass band is
from −0.1 to +0.1 of fHB3.
001 = input signal modulated by dc. Filter pass band is
from 0.025 to 0.225 of fHB3.
010 = input signal modulated by fHB3/4. Filter pass band is
from 0.15 to 0.35 of fHB3.
011 = input signal modulated by fHB3/4. Filter pass band is
from 0.275 to 0.475 of fHB3.
100 = input signal modulated by fHB3/2. Filter pass band is
from 0.4 to 0.6 of fHB3.
101: Input signal modulated by fHB3/2. Filter pass band is
from 0.525 to 0.725 of fHB3.
110 = input signal modulated by 3fHB3/4. Filter pass band is
from 0.65 to 0.85 of fHB3.
111 = input signal modulated by 3F HB3/4. Filter pass band is
from 0.775 to 0.975 of fHB3.
Chip ID
1F
0
Bypass HB3
Third stage interpolation filter bypass.
1
7:0
Chip ID
Chip ID Readback
20
Rev. PrA | Page 31 of 73
AD9148
Preliminary Technical Data
Register Name
Addr
(Hex)
Bit
Name
Function
Default
Coeff I Byte 0
20
7
0
Set this bit to 0.
0
6:3
Coeff_1i
I-Path DAC Sinc-1 Filter Coefficient 2 in twos complement
format.
0
2:0
Coeff_0i
I-Path DAC Sinc-1 Filter Coefficient 1 in twos complement
format.
0
Set DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select = 1 to configure DAC 3 path.
Coeff I Byte 1
21
7:5
Coeff_3i[2:0]
I-Path DAC Sinc-1 Filter Coefficient 4 (LSB) in twos
complement format.
6
4:0
Coeff_2i
I-Path DAC Sinc-1 Filter Coefficient 3 in twos complement
format.
0
Set DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select = 1 to configure DAC 3 path.
Coeff I Byte 2
22
7:5
Coeff_4i[2:0]
I-Path DAC Sinc-1 Filter Coefficient 5 (LSB) in twos
complement format.
7
4
0
Set this bit to 0.
0
3:0
Coeff_3i[6:3]
Set I-Path DAC Sinc-1 Filter Coefficient 4 (MSB) in twos
complement format.
F
DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select = 1 to configure DAC 3 path.
Coeff I Byte 3
23
7
6:0
0
Coeff_4i[9:3]
Set this bit to 0.
-1
I-Path DAC Sinc Filter Coefficient 5 (MSB) in twos
complement format.
0
7F
Set DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select = 1 to configure DAC 3 path.
Coeff Q Byte 0
24
7
0
Set this bit to 0.
0
6:3
Coeff_1q
Q-Path DAC Sinc-1 Filter Coefficient 2 in twos complement
format
D
2:0
Coeff_0q
Q-Path DAC Sinc-1 Filter Coefficient 1 in twos complement
format.
1
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
Coeff Q Byte 1
25
7:5
Coeff_3q[2:0]
Q-Path DAC Sinc-1 Filter Coefficient 4 (LSB) in twos
complement format.
7
4:0
Coeff_2q
Q-Path DAC Sinc-1 Filter Coefficient 3 in twos complement
format.
6
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
Rev. PrA | Page 32 of 73
Preliminary Technical Data
AD9148
Register Name
Addr
(Hex)
Bit
Name
Function
Default
Coeff Q Byte 2
26
7:5
Coeff_4q[2:0]
Q-Path DAC Sinc-1 Filter Coefficient 5 (LSB) in twos
complement format.
0
4
0
Set this bit to 0.
0
3:0
-1
Coeff_3q[6:3]
Q-Path DAC Sinc Filter Coefficient 4 (MSB) in twos
complement format.
D
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
Coeff Q Byte 3
27
7
0
Set this bit to 0.
0
6:0
Coeff_4q[9:3]
Q-Path DAC Sinc-1 Filter Coefficient 5 (MSB) in twos
complement format.
0
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
I Phase Adj LSB
28
7:0
Phase Word I[7:0]
See Register 0x29.
0
I Phase Adj MSB
29
1:0
Phase Word I[9:8]
Phase Word I[9:0] is used to insert a phase offset between the 0
I and Q data paths.
Set DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select = 1 to configure DAC 3 path.
Q Phase Adj LSB
2A
7:0
Phase Word Q[7:0]
See Register 0x2B.
0
Q Phase Adj MSB
2B
1:0
Phase Word Q[9:8]
Phase Word Q[9:0] is used to insert a phase offset between
the I and Q data paths.
0
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
I DC Offset LSB
2C
7:0
DC Offset I[7:0]
See Register 0x2D.
I DC Offset MSB
2D
7:0
DC Offset I[15:8]
DC Offset I[15:0] is a value added directly to the samples
written to the IDAC. The LSB bit weight is 20.
Set DAC SPI select = 0 to configure DAC 1 path.
0
0
Set DAC SPI select = 1 to configure DAC 3 path.
Q DC Offset LSB
2E
7:0
DC Offset Q[7:0]
See Register 0x2F.
Q DC Offset MSB
2F
7:0
DC Offset Q[15:8]
DC Offset Q[15:0] is a value added directly to the samples
written to the QDAC. The LSB bit weight is 20.
0
Set DAC SPI select = 0 to configure DAC 2 path.
0
Set DAC SPI select = 1 to configure DAC 4 path.
0
Rev. PrA | Page 33 of 73
AD9148
Preliminary Technical Data
Register Name
Addr
(Hex)
Bit
Name
Function
IDAC FSC Adj
30
7:0
IDAC FSC Adj[7:0]
IDAC full-scale current adjustment (LSB part). IDAC FS Adj[9:0] F9
sets the full-scale current of the IDAC. The full-scale current
can be adjusted from 8.64 mA to 31.6 mA in step sizes of
approximately 22.5 μA.
Default
0x000 = 8.64 mA.
...
0x200 = 20.14 mA.
…
0x3FF = 31.66 mA.
Set DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select = 1 to configure DAC 3 path.
IDAC Control
31
7
IDAC sleep
I DAC sleep mode (fast wake-up mode).
0
1:0
IDAC FSC Adj[9:8]
IDAC full-scale current adjustment (MSB part)
01
Set DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select = 1 to configure DAC 3 path.
Aux IDAC Data
32
7:0
AUX IDAC Data[7:0]
Auxiliary IDAC data (LSB part). AUX IDAC Data[9:0] sets the
magnitude of the aux DAC current. The range is 0 mA to
2 mA, and the step size is 2 μA.
00
0x000 = 0.000 mA.
0x001 = 0x002 mA.
…
0x3FF = 2.046 mA.
Set DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select = 1 to configure DAC 3 path.
Aux IDAC Control
33
7
AUX IDAC sign
Auxiliary IDAC output sign.
0
0 = positive, current is directed to the AUXx_P pin.
1 = negative, current is directed to the AUXx_N pin.
6
Auxiliary IDAC current direction.
AUX IDAC
current direction
0
0 = source.
1 = sink.
5
AUX IDAC
power down
Auxiliary IDAC power down.
0
1:0
AUX IDAC Data[9:8]
Auxiliary IDAC data (MSB part).
00
Set DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select =1 to configure DAC 3 path.
Rev. PrA | Page 34 of 73
Preliminary Technical Data
AD9148
Register Name
Addr
(Hex)
Bit
Name
Function
QDAC FSC Adj
34
7:0
QDAC FSC Adj[7:0]
F9
Q DAC full-scale current adjustment (LSB part). QDAC FS
Adj[9:0] sets the full-scale current of the QDAC. The full-scale
current can be adjusted from 8.64 mA to 31.6 mA in step sizes
of approximately 22.5 μA.
Default
0x000 = 8.64 mA
...
0x200 = 20.14mA
…
0x3FF = 31.66 mA
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
QDAC Control
35
7
QDAC sleep
Q DAC sleep mode (fast wake-up mode).
0
1:0
QDAC FSC Adj[9:8]
QDAC full-scale current adjustment (MSB part).
01
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
Aux QDAC Data
36
7:0
AUX QDAC
Data[7:0]
Auxiliary QDAC data (LSB part). AUX QDAC Data[9:0] sets
the magnitude of the AUX DAC current. The range is 0 mA
to 2 mA and the step size is 2 μA.
00
0x000 = 0.000 mA.
0x001 = 0x002 mA.
…
0x3FF = 2.046 mA.
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
Aux QDAC Control
37
7
AUX QDAC sign
Auxiliary QDAC output sign.
0
0 = positive, current is directed to the AUXx_P pin.
1 = negative, current is directed to the AUXx_N pin.
6
AUX QDAC
current direction
Auxiliary QDAC current direction.
0
0 = source.
1 = sink.
5
AUX QDAC
power down
Auxiliary QDAC power down.
0
1:0
AUX QDAC
Data[9:8]
Auxiliary QDAC data (MSB part).
00
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
Rev. PrA | Page 35 of 73
AD9148
Preliminary Technical Data
Register Name
Addr
(Hex)
Bit
Name
SED_S0_L
38
7:0
SED Compare
Compare Pattern Sample0[15:0] is the word that is compared
Pattern Sample0[7:0] with Data Sample 0 captured at the input interface by the
rising edge of DCI.
Function
Set DAC SPI select = 0 to configure Port A.
Set DAC SPI select = 1 to configure Port B.
SED_S0_H
39
7:0
SED Compare
Pattern
Sample0[15:8]
Compare Pattern Sample0[15:0] is the word that is compared
with Data Sample 0 captured at the input interface by the
rising edge of DCI.
Set DAC SPI select = 0 to configure Port A.
Set DAC SPI select = 1 to configure Port B.
SED_S1_L
3A
7:0
SED Compare
Compare Pattern Sample1[15:0] is the word that is compared
Pattern Sample1[7:0] with Data Sample 1 captured at the input interface by the
falling edge of DCI.
Set DAC SPI select = 0 to configure Port A.
Set DAC SPI select = 1 to configure Port B.
SED_S1_H
3B
7:0
SED Compare
Pattern
Sample1[15:8]
Compare Pattern Sample1[15:0] is the word that is compared
with Data Sample 1 captured at the input interface by the
falling edge of DCI.
Set DAC SPI select = 0 to configure Port A.
Set DAC SPI select = 1 to configure Port B.
SED_S2_L
3C
7:0
SED Compare
Compare Pattern Sample2[15:0] is the word that is compared
Pattern Sample2[7:0] with Data Sample 2 captured at the input interface by the
rising edge of DCI.
Set DAC SPI select = 0 to configure Port A.
Set DAC SPI select = 1 to configure Port B.
SED_S2_H
3D
7:0
SED Compare
Pattern
Sample2[15:8]
Compare Pattern Sample2[15:0] is the word that is compared
with Data Sample 2 captured at the input interface by the
rising edge of DCI.
Set DAC SPI select = 0 to configure Port A.
Set DAC SPI select = 1 to configure Port B.
SED_S3_L
3E
7:0
SED Compare
Pattern Sample3
[7:0]
Compare Pattern Sample3[15:0] is the word that is compared
with Data Sample 3 captured at the input interface by the
falling edge of DCI.
Set DAC SPI select = 0 to configure Port A.
Set DAC SPI select = 1 to configure Port B.
SED_S3_H
3F
7:0
SED Compare
Pattern
Sample3[15:8]
Compare Pattern Sample3[15:0] is the word that is compared
with Data Sample 3 captured at the input interface by the
falling edge of DCI.
Set DAC SPI select = 0 to configure Port A.
Set DAC SPI select = 1 to configure Port B.
Rev. PrA | Page 36 of 73
Default
Preliminary Technical Data
AD9148
Register Name
Addr
(Hex)
Bit
Name
SED Control/Status
40
7
SED compare enable Enables the SED circuitry.
6
Port B error
detected
Status of last compare on Port B.
0
5
Port A error
detected
Status of last compare on Port A.
0
3
Auto-clear enable
Enables the auto reset after eight valid sample sets.
0
2
Port B compare
failed
Fail status determined for last sample set on Port B.
0
1
Port A compare
failed
Fail status determined for last sample set on Port A.
0
0
Compare passed
Pass status determined for last sample set.
0
7:0
SED Status Rising
Edge Samples[7:0]
SED Status Rising Edge Samples[15:0] indicate which bits
were received in error.
Readonly
SED_R_L
41
Function
Default
0
Set DAC SPI select = 0 to read back errors on Port A.
Set DAC SPI select = 1 to read back errors on Port B.
SED_R_H
42
7:0
SED Status Rising
Edge Samples[15:8]
SED Status Rising Edge Samples[15:0] indicate which bits
were received in error.
Readonly
Set DAC SPI select = 0 to read back errors on Port A.
Set DAC SPI select = 1 to read back errors on Port B.
SED_F_L
43
7:0
SED Status Falling
Edge Samples[7:0]
SED Status Falling Edge Samples[15:0] indicate which bits
were received in error.
Readonly
Set DAC SPI select = 0 to read back errors on Port A.
Set DAC SPI select = 1 to read back errors on Port B.
SED_F_H
44
7:0
SED Status Falling
Edge Samples[15:8]
SED Status Falling Edge Samples[15:0] indicate which bits
were received in error.
Readonly
Set DAC SPI select = 0 to read back errors on Port A.
Set DAC SPI select = 1 to read back errors on Port B.
I Gain Control
50
7:0
IGain[7:0]
IGain[7:0] is a value that directly scales the samples written to 40
the IDAC. The bit weighting is MSB = 21 and LSB = 2−6, which
yields a multiplier range of 0 to 3.984375.
Set DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select = 1 to configure DAC 3 path.
Q Gain Control
51
7:0
QGain[7:0]
QGain[7:0] is a value that directly scales the samples written
to the QDAC. The bit weighting is MSB = 21 and LSB = 2−6,
which yields a multiplier range of 0 to 3.984375.
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
Rev. PrA | Page 37 of 73
40
AD9148
Preliminary Technical Data
Register Name
Addr
(Hex)
Bit
Name
Function
Default
FTW (LSB)
54
7:0
FTW[7:0]
See Register 0x57.
0
FTW
55
7:0
FTW[15:8]
See Register 0x57.
0
FTW
56
7:0
FTW [23:16]
See Register 0x57.
0
FTW (MSB)
57
7:0
FTW [31:24]
FTW[31:0] is the 32-bit frequency tuning word that
determines frequency of the complex carrier generated by
the on-chip NCO. The frequency is not updated when the
FTW registers are written. The values are only updated when
Register 0x5A[2] transitions from 0 to 1.
0
Phase Offset MSB
58
7:0
NCO Phase
Offset[15:8]
See Register 0x59.
0
Phase Offset LSB
59
7:0
NCO Phase
Offset[7:0]
NCO Phase Offset[15:0] sets the phase of the complex carrier 0
signal when the NCO is reset. The phase offset spans between
0º and 360º. Each bit represents an offset of 0.0055º. Value is
in twos complement format.
DDS/Mod Control
5A
7
Bypass DDS/MOD
1 = bypass NCO.
5
Frame NCO reset ack 1 = indicates that the NCO has been reset due to an
extended FRAME pulse signal.
0
4
Frame NCO
reset request
0→1 = The NCO is reset on the first extended FRAME
pulse after this bit transitions from 0 to 1.
0
3
FTW update ack
1 = indicates that the FTW has been updated with the
SPI value.
0
2
FTW update request 0→1 = FTW is updated with the SPI value on 0 to 1
transition of this bit.
0
0
Sideband select
0
0 = The modulator outputs high-side image.
1
1 = The modulator outputs low-side image. The image is
spectrally inverted compared to the input data.
Die Temp Control 0
5C
1
Latch temp data
0 → 1 = latches temp sensor data. This should be completed
before the Die Temp[15:0] is readback.
0
0
Temp Sensor
power down
1 = powers down aux ADC that converts die temperature.
1
Die Temp Control 1
5D
7:0
00001010
Set these bits to 00001010 for optimal temperature sensor
operation.
100000
Die Temp (LSBs)
5E
7:0
Die Temp[7:0]
Die Temp[15:0] indicates the approximate die temperature.
Readonly
Die Temp (MSBs)
5F
7:0
Die Temp[15:8]
Die Temp[15:0] indicates the approximate die temperature.
Readonly
DCI Delay
72
1:0
DCI Delay[1:0]
Programmable delay added DCI.
00
00 = no added delay.
01 = 200 ps delay.
10 = 400 ps delay.
11 = 600 ps delay.
PLL Ctrl (Test)
79
7:0
11111111
Set these bits to 11111111 for optimal PLL operation.
Rev. PrA | Page 38 of 73
40
Preliminary Technical Data
AD9148
INPUT DATA PORTS
DUAL-PORT MODE
In dual-port mode, the DCI signal indicates to which DAC the
data is intended. On the rising edge of DCI, data is latched into
DAC 1 and DAC 3. On the falling edge of DCI, data is latched
into DAC 2 and DAC 4. This pattern continuously repeats.
There is a SPI programmable option (Register 0x14[6]) to provide
one DCI for both input ports or two DCIs where each DCI is
associated with one input port. Two DCIs are useful when the
data for each port is coming from a different data source. These
cases are illustrated in Figure 45 and Figure 46.
Each data sample, by default, is expected to be formatted as
MSB sent to Bit 15 and LSB sent to Bit 0 for each port. The
AD9148 contains an option to swap the bus (Register 0x03[4]).
When this bus swap bit is set, the MSB should be sent to Bit 0
and the LSB should be sent to Bit 15 for each port.
SINGLE-PORT MODE
In single-port mode, a FRAME signal must be provided along
with the DCI signal and the data. The FRAME signal indicates
to which DAC the data is intended. When FRAME goes high,
the first data-word goes to DAC 1, and the second data-word
goes to DAC 2. When FRAME goes low, the first data-word
goes to DAC 3, and the second data-word goes to DAC 4. This
pattern continuously repeats as illustrated in Figure 47.
DCIA
FRAMEA
A[15:0]
DCIA
DAC2
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
B[15:0]
DAC3
DAC4
DAC3
DAC4
DAC3
DAC4
DAC3
DAC4
08910-045
DAC1
Figure 45. Timing Diagram for Dual-Port Mode, One DCI
DAC3
DAC4
DAC1
DAC2
DAC3
DAC4
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
DAC3
DAC4
DAC3
DAC4
DAC3
DAC4
DAC3
DAC4
Each data sample, by default, is expected to be formatted as MSB
sent to Bit 15 and LSB sent to Bit 0. When the bus swap bit is set
(Register 0x03[4]), the MSB should be sent to Bit 0, and the LSB
should be sent to Bit 15 for each port.
The FRAME signal is sampled with the same internal signal as
the data and has the same set-up and hold timing relative to DCI. If
desired, only the first FRAME pulse needs to be generated. This
initializes the internal clock phases inside the device, and data
latches just as if the periodic FRAME signal were sent.
DCIA
08910-046
DCIB
B[15:0]
DAC2
Figure 47. Timing Diagram for Single-Port Mode
A[15:0]
A[15:0]
DAC1
08910-047
The AD9148 can operate in three data input modes: dual-port
mode, single-port mode, and byte mode. In dual-port mode,
DAC 1 and DAC 2 receive data from Port A, and DAC 3 and
DAC 4 receive data from Port B. In single-port mode, all four
DACs receive data from Port A. In byte mode, all four DACs
receive data from Port A, but the port is split into two 8-bit wide
buses. In all modes, the data input timing is relative to a DCI signal
provided along with the data.
Figure 46. Timing Diagram for Dual-Port Mode, Two DCI
Rev. PrA | Page 39 of 73
AD9148
Preliminary Technical Data
BYTE MODE
In byte mode, a FRAME signal must be provided along with the
DCI signal and the data. The most significant byte of the data
should correspond with DCI being high, and the least significant
byte of the data should correspond with DCI being low. The
FRAME signal indicates to which DAC the data is intended.
When FRAME is high, data on the top half of the port (A[15:8])
is sent to DAC 1 and data on the bottom half of the port (A[7:0]) is
sent to DAC 3. When the FRAME is low, data on the top half of
the port is sent to DAC 2 and data on the bottom half of the
port is sent to DAC 4. This pattern continuously repeats as
shown in Figure 48.
The AD9148 also includes a byte swap feature. By default, the
bytes should be formatted as MSB sent to Bit 15 on Bus 1 and
Bit 7 on Bus 2. When byte swap is enabled (Register 0x03[2]),
MSB should be sent to Bit 8 on Bus 1 and Bit 0 on Bus 2. This is
described in Table 14.
Table 14. Byte Swap Formatting
Byte Swap
0
0
1
1
Byte
MSB
LSB
MSB
LSB
A[15:8]
Data Set 1[15:8]
Data Set 1[7:0]
Data Set 1[8:15]
Data Set 1[0:7]
A[7:0]
Data Set 2[15:8]
Data Set 2[7:0]
Data Set 2[8:15]
Data Set 2[0:7]
DATA INTERFACE OPTIONS
DCIA
To enable optimization of the data interface, some additional
options have been provided in the following registers:
A[15:8]
DAC1H
DAC1L
DAC2H
DAC2L
DAC1H
DAC1L
DAC2H
DAC2L
A[7:0]
DAC3H
DAC3L
DAC4H
DAC4L
DAC3H
DAC3L
DAC4H
DAC4L
Figure 48. Timing Diagram for Byte Mode
08910-048
FRAMEA
•
•
•
Data format (Register 0x03)
Data receiver control (Register 0x14)
Data receiver status (Register 0x15)
Depending on the data rate and DCI vs. data skew, the internal
DCI can be inverted to make the valid data timing window.
Rev. PrA | Page 40 of 73
Preliminary Technical Data
AD9148
FIFO OPERATION
32 BITS
REG 0
REG 1
32
DATA
PORT A
INPUT
LATCH
REG 2
DATA
ASSEMBLER
REG 3
32
DATA
PATHS
32
REG 4
DAC1
AND
DAC2
REG 5
REG 6
32
REG 7
WRITE PTR A
WRITE PTR
RESET
LOGIC
FIFO A
OFS[2:0]
FRAME A
READ
PTR
RESET
FIFO RATE/
WRITE PTR
RESET
32 BITS
WRITE PTR B
DCIB
ONE
DCI
READ POINTER B
SYNC
LOGIC
FRAME B
REG 0
REG 1
REG 2
DATA
PORT B
INPUT
LATCH
DACCLK
÷INT
FIFO B
OFS[2:0]
DATA RATE
READ POINTER A
DCIA
DATA
ASSEMBLER
32
REG 3
REG 4
32
DATA
PATHS
32
DAC3
AND
DAC4
INTERFACE
MODE
REG 6
REG 7
08910-049
REG 5
Figure 49. Block Diagram of FIFO
The AD9148 contains two 32-bit wide, 8-word deep FIFOs (one
per dual DAC) designed to relax the timing relationship between
the data arriving at the DAC input ports and the internal DAC
data rate clock. The FIFOs can also be used to provide an adjustable
pipeline delay between the DCIx clocks and the DACCLK
allowing re-alignment of data input in a multichip system. This
significantly increases the timing budget of the interface.
Figure 49 shows the block diagram of the data path through the
FIFO. The data is latched into the device, is formatted, and is
then written into the FIFO register determined by the FIFO
write pointer. The value of the write pointer is incremented
every time a new word is loaded into the FIFO. Meanwhile, data
is read from the FIFO register determined by the read pointer
and fed into the digital data path. The value of the read pointer
is updated every time data is read into the data path from the
FIFO. This happens at the data rate that is the DACCLK rate
divided by the interpolation ratio. The difference between the
write and read pointers represent the FIFO pipeline delay and
are important to take into account when understanding the
overall pipeline delay of the AD9148.
In single port and byte interface modes, the incoming digital
data is sampled at twice the data rate (DCIA). The data is then
assembled based on the interface mode. At the output of the
data assembler block, the data samples for DAC 1 and DAC 2 are
written to FIFO A and the data samples for DAC 3 and DAC 4 are
written to FIFO B at the data rate.
Valid data is transmitted through the FIFO as long as the FIFO
does not overflow or become empty. An overflow or empty
condition of the FIFO is the same as the write pointer and the
read pointer being equal. When both pointers are equal, an attempt
is made to read and write a single FIFO register simultaneously.
This simultaneous register access leads to unreliable data transfer
through the FIFO and must be avoided.
Rev. PrA | Page 41 of 73
AD9148
Preliminary Technical Data
To avoid any concurrent read and write to the same FIFO address
and assure a fixed pipeline delay, it is important to reset the
state of the FIFOs pointers to known states. The pipeline delay
in the AD9148 comes from two sources, FIFO delay and the
delay though the signal processing in the DAC.
To assure a fixed and predictable pipeline delay in the signal
processing, the FIFO read operation is synchronized with the
DACCLK and, more importantly, in case of interpolation, its
divided down version so that the same edge of the slowest clock
in the signal processing reads the same data in the FIFO. The
synchronization is performed by resetting the FIFO read
pointer to a known state relative to the slowest clock used in the
signal processing. This synchronization is enabled by setting
Bit 7 in Register 0x10 to 1, and it uses the REFCLK/SYNC
signal for its reference.
To manage the FIFO pipeline delay, the FIFO write pointer needs
to be synchronized with the read pointer to avoid concurrent
access to the FIFO and to potentially compensate for any data
input phase mismatch. This synchronization can be performed
either at the data rate (see the Data Rate Synchronization section)
or at the FIFO rate (see the FIFO Rate Synchronization section).
FIFO Synchronization Modes
To benefit from the advantages of the FIFO functionality in the
different modes of operations, PLL on/off, standalone, or multichip synchronization, the FIFO can operate in the following
ways:
•
•
•
Synchronization at the data rate
Synchronization at the FIFO rate (data rate/FIFO depth)
No synchronization
As discussed in the Input Data Ports section, in single-port
mode and byte mode, the FRAME input is used as a data select
signal that indicates to which DAC the input data is intended to
be written. When synchronization is needed, the FRAME signal
is given another function, initializing the FIFO write pointer
address. When the FRAME signal is asserted high for at least the
time interval needed to load complete data to the four DACs
(which correspond to one DCI period in dual-port mode and
two DCI periods in single-port mode or byte mode) the FIFO
write pointer is reset to a value dependent on the synchronization
mode selected and the FIFO phase offset bits of the corresponding
FIFO Status/Control Port x register, Register 0x17 or Register 0x19.
In this mode, the REFCLK/SYNC signal is used to reset the
FIFO read pointer to 0. The edge of the CLK used to sample the
SYNC signal is selected by Bit 3 of Register 0x10. If the PLL is
used, REFCLK is used as a SYNC signal and the FIFO read
pointer is reset at the REFCLK rate divided by 64. The data rate
synchronization is selected by setting Bit 6 of Register 0x10 to 0.
As previously mentioned, the FRAME signal is used to reset the
FIFO write pointer. When the FRAME is asserted, the FIFO
write pointer is reset to the address defined in Bits[2:0] of the
corresponding FIFO Status/Control Port x register (Register 0x17
or Register 0x19) the next time the read pointer becomes 0, see
Figure 50.
The data rate synchronization, the write pointer of the FIFO,
and the read pointer of the FIFO are synchronized at the SYNC
rate and have a fixed phase offset.
SYNC
RDPTRA
3
RDPTRB
3
4
5
6
7
0
4
5
6
7
0
FIFO_A WRITE
RESET
7
0
1
2
3
4
1
2
4
5
6
1
2
3
4
5
6
1
2
6
7
0
RESET VALUE FOR
REGISTER 0x19[2:0] = 0b100
FRAMEB
0
3
5
FIFO_B WRITE
RESET
WRPTRB
2
RESET VALUE FOR
REGISTER 0x17[2:0] = 0b100
FRAMEA
WRPTRA
1
3
4
4
5
6
7
0
1
08910-050
SYNCHRONIZING AND RESETTING THE FIFO
Data Rate Synchronization
2
Figure 50. Timing of the FRAME Input vs. Write Pointer Value in Data Rate
Synchronization
FIFO Rate Synchronization
In this mode, the REFCLK/SYNC signal is used to reset the FIFO
read pointer to 0. The edge of the CLK used to sample the SYNC
signal is selected by Bit 3 of Register 0x10. As previously
mentioned, the FRAME signal is used to reset the FIFO write
pointer. In the FIFO rate synchronization mode, the FIFO write
pointer is reset immediately after the FRAME signal is asserted
high for at least the time interval needed to load complete data to
the four DACs, and the FIFO write pointer is reset to the address
defined in Bits[2:0] of the corresponding FIFO Status/Control
Port x register, Address 0x17 or Address 0x19, see Figure 51.
SYNC
FIFO_A AND FIFO_B
READ RESET
RDPTRA
0
1
2
3
4
5
6
7
0
1
2
3
RDPTRB
0
1
2
3
4
5
6
7
0
1
2
3
2
3
4
5
6
4
5
6
FRAMEA
WRPTRA
FIFO_A WRITE
RESET
4
4
5
RESET VALUE FOR
REGISTER 0x17[2:0] = 0b100
6
7
FIFO_B WRITE
RESET
FRAMEB
WRPTRB
2
3
4
6
7
0
1
RESET VALUE FOR
REGISTER 0x19[2:0] = 0b110
0
1
2
3
Figure 51. Timing of the FRAME Input vs. Write Pointer Value in
FIFO Rate Synchronization
Rev. PrA | Page 42 of 73
08910-051
Nominally, data is written to the FIFO at the same rate as data is
read from the FIFO. This keeps the data level in the FIFO constant.
If data is written to the FIFO faster than data is read, the data
level in the FIFO increases. If the data is written to the device
slower than data is read, the data level in the FIFO decreases. For
maximum timing margin, the FIFO level should be maintained
near half full, which is the same as maintaining a difference of
four between the write pointer and read pointer values.
Preliminary Technical Data
AD9148
4.
No Synchronization
In this mode, Bit 7 in Register 0x10 is set to 0, the pipeline delay
in the signal processing is not controlled, and the read pointer
of the FIFO is never reset. However, to assure that the FIFO can
operate safely and there is no concurrent access to FIFO from
the write and read pointer to the same address, it is important to
ensure that the phase offset between the two pointers is greater
than 2. In consequence, the only FIFO reset that can be used
safely is the data rate synchronization, Bit 6 of Register 0x10 set
to 0, where the FIFO is reset with a fixed offset of 4 between the
write and read pointers. As there is no SYNC signal, the reset of
the FIFO write pointer can only be done by a FRAME signal or
an SPI command.
FIFO Reset Commands
Depending on the configuration of the system, the FIFO reset
could be done manually or periodically for a multichip system.
The AD9148 provides two ways to resetting the FIFO pointers:
SPI interface or periodic reset using the FRAME signal.
The SPI also gives access to each FIFO phase offset in Bits [2:0]
of the corresponding FIFO status/control registers, Address 0x17
and Address 0x19. The value in these three bits corresponds
either to the offset between the write and read pointer in the
data rate synchronization or to the absolute address of the FIFO
write pointer in the FIFO rate synchronization.
The FIFO SPI aligned flag in the Event Flag 0 register, Bit 2
in Register 0x06, is set when the reset of the write pointer has
been realized. Bit 4 in Register 0x17 or Bit 4 in Register 0x19 is
reset to 0 to indicate which FIFO has generated this flag.
Note that the SPI writes to Register 0x17 or Register 0x19
should be done while maintaining a constant value in the FIFO
phase offset bits.
FIFO Reset Using FRAME Signal
The FIFO pointers can also be reset using the FRAME signals.
If only one DCI is used, only the FRAMEA signal is used for the
FIFO reset. This mode is enabled by setting Bit 6 in Register 0x10.
As discussed in the FIFO Synchronization Modes section, the
FRAME input is used to initialize the FIFO data level value.
When the FRAME signal is asserted high for at least the time
interval needed to load the complete data to the four DACs, the
write pointer is reset depending on the mode of synchronization
chosen:
•
•
Data rate synchronization (default), Bit 6 of Register 0x10,
is set to 0. Write pointer reset to FIFO offset phase when
read pointer reaches 0.
FIFO rate synchronization, Bit 6 of Register 0x10, is set to 1.
Write pointer reset to FIFO start level on rising edge of
FRAME signal.
SPI Command for Manual Reset
MONITORING THE FIFO STATUS
If a manual reset is acceptable, the FIFO pointer addresses can
be reset using the SPI interface.
The FIFO initialization and status can be read from Register 0x17.
This register provides information about the FIFO initialization
method and whether the initialization was successful. The MSB
of Register 0x17 is a FIFO warning flag that can optionally trigger a
device IRQ. This flag is an indication that the FIFO is close to
emptying (FIFO level is 1) or overflowing (FIFO level is 7). This
is an indication that the data may soon be corrupted, and action
should be taken.
To initialize the FIFO data level through the SPI, Bit 3 of
Register 0x17 (FIFO Port A) or Bit 3 of Register 0x19 (FIFO
Port B) should be toggled from 0 to 1 and back. When the
write to the register is complete, the corresponding FIFO data
level is initialized.
The recommended procedure for a SPI FIFO data level
initialization is:
1.
2.
3.
Request FIFO Port A or FIFO Port B level reset by setting
Bit 3 in Register 0x17 or Bit 3 in Register 0x19 to Logic 1. The
FIFO phase offset, Bits [2:0] in Register 0x17 or Bits [2:0] in
Register 0x19 should also be written at the same time to set
the desired value of offset between the FIFO write and read
pointers.
Verify the part acknowledges the request by ensuring Bit 4
in Register 0x17 or Bit 4 in Register 0x19 is set to Logic 1.
Remove the request by resetting Bit 3, Register 0x17 or
Bit 3, Register 0x19 to 0.
The FIFO data level can be read from Register 0x18 at any time.
The SPI reported FIFO data level is denoted as a 7-bit thermometer
code of the write counter state relative to the absolute read counter
being 0. The optimum FIFO data level of four is, therefore,
reported as a value of 00001111 in the status register.
Note that, depending on the timing relationship between DCI
and the main DACCLK, the FIFO level value can be off by a ±1
count. Therefore, it is important to keep the difference between the
read and write points to at least two.
Rev. PrA | Page 43 of 73
AD9148
Preliminary Technical Data
DEVICE SYNCHRONIZATION
SYNCHRONIZING MULTIPLE DEVICES
System demands may require that the outputs of multiple DACs
be synchronized with each other or with a system clock. Systems
that support transmit diversity or beam-forming, where multiple
antennas are used to transmit a correlated signal, require multiple
DAC outputs to be phase aligned with each other. Systems with
a time-division multiplexing transmit chain may require one or
more DACs to be synchronized with a system-level reference clock.
Multiple devices are considered synchronized to each other
when the state of the clock generation state machines is identical
for all parts and time aligned data is being read from the FIFOs
of all parts simultaneously. Devices are considered synchronized to
a system clock when there is a fixed and known relationship
between the clock generation state machine and the data being
read from the FIFO and a particular clock edge of the system
clock. The AD9148 has provisions for enabling multiple devices to
be synchronized to each other or to a system clock.
The AD9148 supports synchronization in two different modes,
data rate mode and FIFO rate mode. The two modes are
distinguished by the lowest rate clock that the synchronization
logic attempts to synchronize. In data rate mode, the input data
rate represents the lowest synchronized clock. In FIFO rate mode,
the FIFO rate, which is the data rate divided by the FIFO depth
of 8, represents the lowest rate clock. The advantage of the FIFO
rate synchronization is increased setup and hold times of DCI
relative to the CLK input. When in data rate synchronization
mode, the elasticity of the FIFO is not used to absorb timing
variations between the data source and DAC, resulting in
tighter setup and hold time requirements.
The method chosen for providing the DAC sampling clock directly
impacts the synchronization methods available. When the device
clock multiplier is used, only data rate synchronization is
available. When the DAC sampling clock is sourced directly,
both data rate mode and FIFO rate mode synchronization are
available.
SYNCHRONIZATION WITH CLOCK MULTIPLICATION
When using the clock multiplier to generate the DACCLK, the
REFCLK/SYNC input signal acts as both the reference clock for
the PLL-based clock multiplier and as the synchronization
signal. To synchronize devices, the REFCLK/ SYNC signal must
be distributed with low skew to all of the devices to be
synchronized. Skew between the REFCLK/SYNC signals of
different devices show up directly as a timing mismatch at the
DAC outputs.
The frequency of the REFCLK/SYNC signal is typically equal to
the input data rate. The FRAME signal and DCI signals can be
created in the FPGA along with the data. A circuit diagram of a
typical configuration is shown in Figure 52.
MATCHED
LENGTH TRACES
REFCLK/SYNC
FRAME
DCI
SYSTEM CLOCK
OUT1
LOW SKEW
CLOCK DRIVER
REFCLK/SYNC
FRAME
FPGA
OUT2
MATCHED
LENGTH TRACES
Figure 52. Typical Circuit Diagram for Synchronizing Devices with Clock Multiplication Enabled
Rev. PrA | Page 44 of 73
08910-052
DCI
Preliminary Technical Data
AD9148
The following procedure outlines the steps required to
synchronize multiple devices. The procedure assumes that the
REFCLK/SYNC signal is applied to all of the devices and the
PLL of each device is phase locked to it. Each individual device
must follow this procedure.
The procedure for synchronization when using the PLL follows:
2.
3.
Configure for data rate, periodic synchronization by
writing 0xC0 to the sync control register (Register 0x10).
Read the sync status register (Register 0x12) and verify that
the sync locked bit (Bit 6) is set high indicating that the
device achieved back-end synchronization and that the
sync lost bit (Bit 7) is low. These levels indicate that the
clocks are running with a constant and known phase
relative to the sync signal.
Reset the FIFO by strobing the FRAME signal high for at
least the time interval needed to load complete data to the
four DACs. Resetting the FIFO ensures that the correct
data is being read from the FIFO. This completes the
synchronization procedure, and at this stage, all devices
should be synchronized.
The example in Figure 53 shows a REFCLK/SYNC frequency equal
to the data rate. While this is the most common situation, it is not
strictly required for proper synchronization. Any REFCLK/SYNC
frequency that satisfies the following equations is acceptable:
fSYNC = fDACCLK/2N and fSYNC ≤ fDATA
where N = 1, 2, 3, or 4.
For example, a configuration with 4× interpolation and clock
frequencies of fVCO = 1600 MHz, fDACCLK = 800 MHz, and
fDATA = 200 MHz, fSYNC = 100 MHz would be a viable solution.
tSKEW
REFCLK(1)
REFCLK(2)
tSU_DCI
tH_DCI
DCI(2)
08910-053
1.
To maintain synchronization, the skew between REFCLK/SYNC
signals of the devices must be less than tSKEW nanoseconds. There
is also a setup and hold time to be observed between the DCI and
data of each device and the REFCLK/SYNC signal. When resetting
the FIFO, the FRAME signal must be held high for at least the
time interval needed to load complete data to the four DACs
(one DCI period for dual-port mode and two DCI periods for
single-port or byte mode). A timing diagram of the input signals is
shown in Figure 53.
FRAME(2)
Figure 53. Timing Diagram Required for Synchronizing Two Devices
Rev. PrA | Page 45 of 73
AD9148
Preliminary Technical Data
LOW SKEW
CLOCK DRIVER
CLK
REFCLK/SYNC
OUT1
FRAME
SAMPLE RATE CLOCK
DCI
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
CLK
REFCLK/SYNC
OUT2
FRAME
SYNC CLOCK
DCI
MATCHED
LENGTH TRACES
08910-054
FPGA
Figure 54. Typical Circuit Diagram for Synchronizing Devices to a System Clock
SYNCHRONIZATION WITH DIRECT CLOCKING
When directly sourcing the DAC sample rate clock to CLK, a
separate SYNC input signal is required for synchronization. To
synchronize devices, the CLK signals and the SYNC signals
must be distributed with low skew to all of the devices being
synchronized. This configuration is shown below in Figure 54.
Data Rate Mode Synchronization
The following procedure outlines the steps required to synchronize
multiple devices in data rate mode. The procedure assumes that
the CLK and SYNC signals are applied to all of the devices.
Each individual device must follow the procedure.
The procedure for data rate synchronization when directly
sourcing the DAC sampling clock follows:
2.
3.
tSKEW
Configure for data rate, periodic synchronization by
writing 0xC0 to the sync control register (Register 0x10).
Additional synchronization options are available (see the
Additional Synchronization Features section).
Poll the sync locked bit (Bit 6, Register 0x12) to verify that
the device is back-end synchronized. A high level on this
bit indicates that the clocks are running with a constant
and known phase relative to the sync signal.
Reset the FIFO by strobing the FRAME signal for at least the
time interval needed to load complete data to the four DACs
Resetting the FIFO ensures that the correct data is being
read from the FIFO of each of the devices simultaneously.
This completes the synchronization procedure, and at this
stage, all devices should be synchronized.
CLK(1)
CLK(2)
tSU_DCI tH_DCI
tSU_SYNC tH_SYNC
SYNC(2)
DCI(2)
FRAME(2)
08910-055
1.
To ensure that each of the DACs are updated with the correct
data on the same DACCLK edge, two timing relationships must
be met on each DAC. DCI (and data) must meet the setup and
hold times with respect to the rising edge of CLK, and REFCLK/
SYNC must also meet the setup and hold time with respect to
the rising edge of CLK. When resetting the FIFO, the FRAME
signal must be held high for at least the time interval needed to
load complete data to the four DACs (one DCI period for dualport mode and two DCI periods for single-port or byte mode).
When these conditions are met, the outputs of the DACs will be
updated within tSKEW + tOUTDLY nanoseconds of each other. A
timing diagram that illustrates the timing requirements of the
input signals is shown in Figure 55.
Figure 55. Synchronization Signal Timing Requirements in Data Rate Mode,
2× Interpolation
Rev. PrA | Page 46 of 73
Preliminary Technical Data
AD9148
Figure 55 shows the synchronization signal timing with 2×
interpolation, so that fDCI = ½ × fCLK. The SYNC input is shown
equal to the DCI rate. The maximum frequency at which the device
can be resynchronized in data rate mode can be expressed as
f DATA
2N
CLK(2)
tSU_SYNC tH_SYNC
for any positive integer, N.
SYNC(2)
Generally, for values of N equal to or greater than 3, the FIFO
rate synchronization mode is chosen.
FIFO Rate Mode Synchronization
The procedure for FIFO rate synchronization when directly
sourcing the DAC sampling clock follows:
2.
3.
DCI(2)
FRAME(2)
The following procedure outlines the steps required to synchronize
multiple devices in FIFO rate mode. The procedure assumes
that the CLK and REFCLK/SYNC signals are applied to all of the
devices. Each individual device must follow the procedure.
1.
CLK(1)
08910-056
f SYNC =
tSKEW
Configure for FIFO rate, periodic synchronization by writing
0x80 to the sync control register (Register 0x10). Additional
synchronization options are available and are described in
the Additional Synchronization Features section.
Poll the sync locked bit (Bit 6, Register 0x12) to verify that
the device is back-end synchronized. A high level on this
bit indicates that the clocks are running with a constant
and known phase relative to the sync signal.
Reset the FIFO by strobing the FRAME signal high for at
least the time interval needed to load complete data to the
four DACs. Resetting the FIFO ensures that the correct
data is being read from the FIFO of each of the devices
simultaneously. This completes the synchronization
procedure, and at this stage, all devices should be
synchronized.
To ensure that each of the DACs are updated with the correct
data on the same DACCLK edge, two timing relationships must
be met on each DAC. DCI (and data) must meet the setup and
hold times with respect to the rising edge of CLK, and REFCLK/
SYNC must also meet the setup and hold time with respect to
the rising edge of CLK. When resetting the FIFO, the FRAME
signal must be held high for at least the time interval needed to
load complete data to the four DACs (one DCI period for dualport mode, and two DCI periods for single-port or byte mode).
When these conditions are met, the outputs of the DACs will be
updated within tSKEW + tOUTDLY nanoseconds of each other. A
timing diagram that illustrates the timing requirements of the
input signals is shown in Figure 56.
Figure 56. Synchronization Signal Timing Requirements in FIFO Rate Mode,
2× Interpolation
Figure 56 shows the synchronization signal timing with 2×
interpolation, so that fDCI = ½ × fCLK. The SYNC input is shown
equal to the FIFO rate. The maximum frequency at which the
device can be resynchronized in FIFO rate mode can be expressed as
f SYNC =
f DATA
8 × 2N
for any positive integer, N.
ADDITIONAL SYNCHRONIZATION FEATURES
The synchronization logic incorporates additional features that
provide means for querying the status of the synchronization
and for improving the robustness of the synchronization. For
more information on these features, see the Sync Status Bits
section and the Timing Optimization section.
Sync Status Bits
When the sync locked bit (Bit 6, Register 0x12) is set, it indicates
that the synchronization logic has reached alignment. This is
determined when the clock generation state machine phase is
constant. This takes between (11 + Averaging) × 64 and (11 +
Averaging) × 128 DACCLK cycles. This bit may optionally trigger
an IRQ, as described in the Interrupt Request Operation section.
When the sync lost bit (Bit 7, Register 0x12) is set, it indicates a
previously synchronized device has lost alignment. This bit is
latched and remains set until cleared by overwriting the register.
This bit may optionally trigger an IRQ as described in the
Interrupt Request Operation section.
The sync phase readback bits (Bits [7:0], Register 0x13) report
the current clock phase in 6.2 format. Bits[7:2] report which of
the 64 states (0 to 63) the clock is currently in. When averaging
is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, and
¾). The lower two bits give an indication of timing margin
issues that may exist. If the sync sampling is error free, the
fractional clock state should be 00.
Rev. PrA | Page 47 of 73
AD9148
Preliminary Technical Data
Timing Optimization
The SYNC signal is sampled by a version of the DACCLK. If
sampling errors are detected, the opposite sampling edge can be
selected to improve the sampling point. The sampling edge can be
selected by setting Bit 3, Register 0x10 (1 = rising and 0 = falling).
The synchronization logic resynchronizes when a phase change
between the SYNC signal and the state of the clock generation
state machine exceeds a threshold. To mitigate the effects of
jitter and prevent erroneous resynchronizations, the relative
phase can be averaged. The amount of averaging is set by the
Sync Averaging[2:0] bits (Bits[2:0], Register 0x10) and can be
set from 1 to 128. The higher the number of averages, the more
slowly the device recognizes and resynchronizes to a legitimate
phase correction. Generally, the averaging should be made as
large as possible while still meeting the allotted resynchronization
time interval.
Rev. PrA | Page 48 of 73
Preliminary Technical Data
AD9148
INTERFACE TIMING
The timing diagram for the digital interface port is shown in
Figure 58. The sampling point of the data bus nominally occurs
TBD ps after each edge of the DCI signal and has an uncertainty of
± TBD ps, as illustrated by the sampling interval. The data and
FRAME signals must be valid throughout this sampling interval.
The data and FRAME signals may change at any time between
sampling intervals.
SAMPLING
INTERVAL
DCI
The setup (tS) and hold (tH) times with respect to the edges are
shown in Figure 58. The minimum setup and hold times are
shown in Table 15.
tHDCI
Minimum Hold
Time, tH (ns)
TBD
TBD
TBD
TBD
Figure 57. Timing Diagram for Input Data Port (Data Rate Mode with Sync On)
Table 16. DCI to DACCLK Setup and Hold Times vs. DCI
Delay Value
DCI Delay
(Register 0x72[1:0])
00
01
10
11
The data interface timing can be verified by using the SED
circuitry. See the Interface Timing Validation section for details.
In data rate mode with synchronization enabled, a second timing
constraint between DCI and DACCLK must be met in addition
to the DCI-to-data timing shown in Table 16. In data rate mode,
only one FIFO slot is being used. The DCI to DACCLK timing
restriction is required to prevent data being written to and read
from the FIFO slot at the same time. The required timing
between DCI and DACCLK is shown in Figure 57.
Minimum Setup
Time, tSDCI (ns)
TBD
TBD
TBD
TBD
tDATA
SAMPLING
INTERVAL
SAMPLING
INTERVAL
tS
tH
Figure 58. Timing Diagram for Input Data Ports
Rev. PrA | Page 49 of 73
08910-058
Minimum Setup
Time, tS (ns)
TBD
TBD
TBD
TBD
08910-057
tSDCI
Table 15. Data Port Setup and Hold Times
DCI Delay
(Register 0x72[1:0])
00
01
10
11
tDATA
DACCLK/
REFCLK
Minimum Hold
Time, tHDCI (ns)
TBD
TBD
TBD
TBD
AD9148
Preliminary Technical Data
DIGITAL DATA PATH
The block diagram in Figure 59 shows the functionality of the
complex digital data path. The digital processing includes a
premodulation block, a programmable complex filter, three
half-band interpolation filters with built-in coarse modulation,
a quadrature modulator with a fine resolution NCO as well as
phase, gain, and offset adjustment blocks.
HB1
HB2
HB3
DIGITAL
PHASE/GAIN/
OFFSET ADJ
H (z ) =
y I + j × yQ
x I + j × xQ
= H I + j×HQ
= c 0 + c 1 × z −1 + c 2 × z −2 + c 3 × z −3 + c 4 × z − 4
+c 3 × z −5 + c 2 × z − 6 + c 1 × z −7 + c 0 × z − 8
Figure 59. Block Diagram of Digital Data Path
There are two complex digital data paths that feed the four DACs.
Each digital data path accepts I and Q data streams and processes
them as a quadrature data stream, resulting in two quadrature
data streams. All of the signal processing blocks can be used
when the input data stream is represented as complex data.
The data path can be used to process an input data stream
representing four independent real data streams as well; however,
the functionality is somewhat restricted. The premodulation
block can be used, as well as any of the nonshifted interpolation
filter modes.
where:
xI and xQ are the in-phase (real) and quadrature (imaginary)
filter input, respectively.
yI and yQ are the in-phase (real) and quadrature (imaginary)
filter output, respectively.
HI and HQ are the in-phase (real) and quadrature (imaginary)
filter coefficients, respectively.
c0, c1, c2, c3, and c4 are the complex filter coefficient, and cX their
complex conjugate.
The filter coefficients need to be calculated and programmed
into the AD9148 registers to perform the operation desired.
Filter Implementation
PREMODULATION
The half-band interpolation filters have selectable pass bands
that allow the center frequencies to be moved in increments of
½ of their input data rate. The premodulation block provides a
digital upconversion of the incoming waveform by ½ of the
incoming data rate, fDATA. Functionally, the premodulation
multiplies the incoming data samples alternatively by +1 and −1.
This can be used to frequency shift baseband input data to the
center of the interpolation filters pass band.
To perform the complex filtering of the complex input, the filter
is divided in four filters working in parallel, two sets of HI and
two sets of HQ (see Figure 60).
(
)(
y I + j × yQ = H I + j × H Q ⋅ xi + j × xQ
(
)
= H I × x I − H Q × xQ + j ⋅ H Q × x I + H I × xQ
+
XI
YI
HI
–
HQ
PROGRAMMABLE INVERSE SINC FILTER
)
+
YQ
+
The AD9148 provides a programmable inverse sinc filter to
compensate the DAC roll-off over frequency. As this filter is
implemented before the interpolation filter, its coefficients need
to be changed depending on the interpolation rate and DAC
output center frequency.
XQ
HI
HQ
08910-060
PROG
SINC–1
FILTER
The programmable inverse sinc filter is a 9-tap complex FIR
filter using complex conjugate coefficients. The z-transfer
function is:
08910-059
PREMOD
fS/2
Filter Structure
Figure 60. Complex Filter Implementation
The coefficients for the filter are stored in SPI Register 0x20 to
Register 0x27 in twos-complement format. They have variable
length, 3 bits to 10 bits.
Rev. PrA | Page 50 of 73
Preliminary Technical Data
AD9148
Table 17. Programmable Inverse Sinc Filter Coefficient Widths and Ranges
Coefficient
c0 in-phase (real)
Width
3
c0 quadrature (imaginary)
3
c1 in-phase (real)
4
c1 quadrature (imaginary)
4
c2 in-phase (real)
5
c2 quadrature (imaginary)
5
c3 in-phase (real)
7
c3 quadrature (imaginary)
7
c4 in-phase (real)
10
c4 quadrature (imaginary)
10
Minimum
100b
−4
0100b
−4
1000b
−8
1000b
−8
10000b
−16
10000b
−16
1000000b
−64
1000000b
−64
1000000000b
−1024
1000000000b
−1024
When there is no interpolation used, the real filter coefficients
can be fixed at (no imaginary coefficients):
The real and imaginary filters are implemented using the
structure described in Figure 61 and Figure 62.
z –1
z –1
z –1
z –1
c0REAL
c1REAL
c2REAL
c3REAL
+
+
+
+
+
+
+
+
+
z –1
+
+
z –1
+
z –1
c4REAL
+
+
C0 = 2
C1 = −4
C2 = 10
C3 = −35
C4 = 401
z –1
+
c5REAL
+
+
+
+
+
OUTPUT n
08910-061
INPUT n
z –1
Figure 61. Real Filter implementation
z –1
z –1
c0IMG
c1IMG
+
+
–
–
z –1
c2IMG
+
+
z –1
z –1
+
z –1
z –1
c3IMG
–
+
z –1
+
c4IMG
+
+
–
+
+
c5IMG
–
+
+
+
+
OUTPUT n
08910-062
INPUT n
z –1
Figure 62. Imaginary Filter implementation
The AD9148 evaluation tools provide software that allow for
the processing of the filter coefficients based on the DAC
sampling frequency, the amount of interpolation used
(combination of HB1, HB2 and HB3), and the desired center
frequency. This center frequency is limited to
[−(fDAC/2, fDAC/2/INT); fDAC/2, fDAC/2/INT]
where INT is the interpolation rate.
Maximum
011b
3
011b
3
0111b
7
0111b
7
01111b
15
01111b
15
0111111b
63
0111111b
63
0111111111b
1023
0111111111b
1023
;
;
;
;
C8 = 2
C7 = −4
C6 = 10
C5 = −35
INTERPOLATION FILTERS
The transmit path contains three interpolation filters. Each of
the three interpolation filters provides a 2× increase in output
data rate. The filters can be cascaded to provide 2×, 4×, or 8×
interpolation ratios. Each of the half-band filter stages offers a
different combination of bandwidths and operating modes.
The bandwidth of the three half-band filters with respect to the
data rate at the filter input is as follows:
•
•
•
Bandwidth of HB1 = 0.8 × fIN1
Bandwidth of HB2 = 0.5 × fIN2
Bandwidth of HB3 = 0.4 × fIN3
The usable bandwidth is defined as the frequency over which
the filters have a pass-band ripple of less than ±0.001 dB and an
image rejection of greater than +85 dB. As is discussed in the
Half-Band Filter 1 (HB1) section, the image rejection usually sets
the usable bandwidth of the filter, not the pass-band flatness.
The half-band filters operate in several modes, providing
programmable pass-band center frequencies as well as signal
modulation. The HB1 filter has four modes of operation, and
the HB2 and HB3 filters each have eight modes of operation.
Rev. PrA | Page 51 of 73
AD9148
Preliminary Technical Data
0.02
Half-Band Filter 1 (HB1)
MODE 0
MODE 2
MODE 1
0
–0.02
(dB)
HB1 has four modes of operation, as shown in Figure 63. The
shape of the filter response is identical in each of the four modes.
The four modes are distinguished by two factors, the filter center
frequency and whether or not the input signal is modulated by
the filter.
0
–20
–0.08
–40
–0.10
0
08910-064
–0.06
0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40
(× fIN1)
–60
Figure 64. Pass-Band Detail of HB1
Table 19. HB1 Pass-Band and Stop-Band Performance by
Bandwidth
–100
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
(× fIN1)
2.0
Figure 63. HB1 Filter Modes
As is shown in Figure 63, the center frequency in each mode is
offset by ½ of the input data rate (fIN1) of the filter. Mode 0 and
Mode 1 do not modulate the input signal. Mode 2 and Mode 3
modulate the input signal by fIN1. When operating in Mode 0
and Mode 2, the I and Q paths operate independently and no
mixing of the data between channels occurs. When operating
in Mode 1 and Mode 3, mixing of the data between the I and Q
paths occurs; therefore, the data input into the filter is assumed
complex. Table 18 summarizes the HB1 modes.
Table 18. 2× Interpolation Filter Modes (Register 0x1C to
Register 0x1E)
Interpolation
Factor
2
2
2
2
Filter Modes
Pre Mod
HB1
HB2
0
0
Off
1
1
Off
0
2
Off
1
3
Off
HB3
Off
Off
Off
Off
Stop-Band
Rejection (dB)
85
80
70
60
50
40
Half-Band Filter 2 (HB2)
HB2 has eight modes of operation, as shown in Figure 65 and
Figure 66. The shape of the filter response is identical in each of
the eight modes. The eight modes are distinguished by two factors,
the filter center frequency and whether the input signal is
modulated by the filter.
MODE 0
0
fCENTER
(fDAC)
0
fDAC/4
fDAC/2
−fDAC/4
Pass-Band
Flatness (dB)
0.001
0.0012
0.0033
0.0076
0.0271
0.1096
Bandwidth (% of fIN1)
80
80.4
81.2
82.0
83.6
85.6
MODE 4
MODE 2
MODE 6
–20
(dB)
0
08910-063
–80
Figure 64 shows the pass-band filter response for HB1. In most
applications, the usable bandwidth of the filter is limited by the
image suppression provided by the stop-band rejection and not
by the pass-band flatness. Table 19 shows the pass-band flatness
and stop-band rejection the HB1 filter supports at different
bandwidths.
–40
–60
–80
–100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
(× fIN2)
Figure 65. HB2, Even Filter Modes
Rev. PrA | Page 52 of 73
1.6
1.8
2.0
08910-065
(dB)
–0.04
MODE 3
Preliminary Technical Data
MODE 1
0
MODE 3
AD9148
0.02
MODE 5 MODE 7
0
–20
–40
(dB)
(dB)
–0.02
–0.04
–60
–0.06
–80
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
(× fIN2)
1.8
2.0
–0.10
08910-066
–100
0
0.12
0.16
0.20
0.24
0.28
0.32
Figure 67. Pass-Band Detail of HB2
As shown in Figure 65 and Figure 66, the center frequency in
each mode is offset by ¼ of the input data rate (fIN2) of the filter.
Mode 0 through Mode 3 do not modulate the input signal. Mode 4
through Mode 7 modulate the input signal by fIN2. When operating
in Mode 0 and Mode 4, the I and Q paths operate independently,
and no mixing of the data between channels occurs. When
operating in the other six modes, mixing of the data between
the I and Q paths occurs; therefore, the data input to the filter
is assumed complex. Table 20 summarizes the HB2 modes.
Table 20. 4× Interpolation Filter Modes (Register 0x1C to
Register 0x1E)
Filter Modes
Pre Mod
HB1 HB2
0
0
0
1
1
1
0
2
2
1
3
3
0
0
4
1
1
5
0
2
6
1
3
7
0.08
(× fIN2)
Figure 66. HB2, Odd Filter Modes
Interpolation
Factor
4
4
4
4
4
4
4
4
0.04
08910-067
–0.08
HB3
Off
Off
Off
Off
Off
Off
Off
Off
fCENTER
(fDAC)
0
fDAC/8
fDAC/4
3fDAC/8
fDAC/2
−3fDAC/8
−fDAC/4
−fDAC/8
Figure 67 shows the pass-band filter response for HB2. In most
applications, the usable bandwidth of the filter is limited by the
image suppression provided by the stop-band rejection and not
by the pass-band flatness. Table 21 shows the pass-band flatness
and stop-band rejection the HB2 filter supports at different
bandwidths.
Table 21. HB2 Pass-Band and Stop-Band Performance by
Bandwidth
Bandwidth (% of fIN2)
50
50.8
52.8
56.0
60
64.8
Pass-Band
Flatness (dB)
0.001
0.0012
0.0028
0.0089
0.0287
0.1877
Stop-Band
Rejection (dB)
85
80
70
60
50
40
Half-Band Filter 3 (HB3)
HB3 has eight modes of operation that function the same as HB2.
The primary difference between HB2 and HB3 are the filter
bandwidths. Table 22 summarizes the filter modes for HB3.
Table 22. 8× Interpolation Filter Modes (Register 0x1C to
Register 0x1E)
Interpolation
Factor
8
8
8
8
8
8
8
8
Rev. PrA | Page 53 of 73
Filter Modes
Pre Mod
HB1 HB2
0
0
0
0
2
2
0
0
4
0
2
6
0
0
0
0
2
2
0
0
4
0
2
6
HB3
0
1
2
3
4
5
6
7
fCENTER
(fDAC)
0
fDAC/8
fDAC/4
3fDAC/8
fDAC/2
−3fDAC/8
−fDAC/4
−fDAC/8
AD9148
Preliminary Technical Data
0.02
0
×2 MODE
×4 MODE
×8 MODE
0.4
COMPLEX BW (×fDAC)
Figure 68 shows the pass-band filter response for HB3. In most
applications, the usable bandwidth of the filter is limited by the
image suppression provided by the stop-band rejection and not
by the pass-band flatness. Table 23 shows the pass-band flatness
and stop-band rejection the HB3 filter supports at different
bandwidths.
0.3
0.2
0.15
0.1
0.075
0.0375
–0.04
–3/8
–1/4
–1/8
DC
1/8
1/4
CARRIER FREQUENCY
1/2 fC (×fDAC )
3/8
Figure 69. Complex Signal Bandwidth as a Function of Output Frequency
FINE MODULATION
–0.06
–0.10
0
0.04
0.08
0.12
0.16
0.20
(× fIN3)
0.24
0.28
08910-068
–0.08
Figure 68. Pass-Band Detail of HB3
Table 23. HB3 Pass-Band and Stop-Band Performance by
Bandwidth
Bandwidth (% of fIN3)
40
40.8
42.4
45.6
49.8
55.6
Pass-Band
Flatness (dB)
0.001
0.0014
0.002
0.0093
0.03
0.1
The fine modulation makes use of a numerically controlled oscillator,
a phase shifter, and a complex modulator to provide a means for
modulating the signal by a programmable carrier signal. A block
diagram of the fine modulator is shown in Figure 70. The fine
modulator allows the signal to be placed anywhere in the output
spectrum with very fine frequency resolution.
I DATA
Stop-Band
Rejection (dB)
85
80
70
60
50
40
The maximum bandwidth can be achieved if the signal carrier
frequency is placed directly at the center of one of the filter pass
bands. In this case, the entire quadrature bandwidth of the
interpolation filter (0.8 × fDATA) is available. The available signal
bandwidth decreases as the carrier frequency of the signal moves
away from the center frequency of the filter. The worst-case
carrier frequency is one that falls directly between the center
frequency of two adjacent filters. Figure 69 shows how the
signal bandwidth changes as a function of placement in the
spectrum and interpolation rate.
INTERPOLATION
COSINE
FTW[31:0]
NCO
NCO PHASE OFFSET
WORD [15:0]
OUT_I
SINE
–
OUT_Q
+
–1
SPECTRAL
INVERSION
Q DATA
0
1
INTERPOLATION
08910-070
(dB)
–1/2
08910-069
0
–0.02
Figure 70. Fine Modulator Block Diagram
The quadrature modulator is used to mix the carrier signal
generated by the NCO with the I and Q signal. The NCO produces
a quadrature carrier signal to translate the input signal to a new
center frequency. A complex carrier signal is a pair of sinusoidal
waveforms of the same frequency, offset 90° from each other.
The frequency of the complex carrier signal is set via the
FTW[31:0] value in Register 0x54 through Register 0x57.
Rev. PrA | Page 54 of 73
Preliminary Technical Data
AD9148
The NCO operating frequency, fNCO, is at the DAC rate. The
frequency of the complex carrier signal can be set from dc up to
fDAC/2. The frequency tuning word (FTW) is calculated as
FTW =
f CENTER
f DAC
× 2 32
The generated quadrature carrier signal is mixed with the I and Q
data. The quadrature products are then summed into the I and
Q data paths, as shown in Figure 70.
When using the fine modulator, the maximum signal bandwidth of
0.8 × fDATA is always achieved.
Phase Offset Adjustment
A 16-bit phase offset may be added to the output of the phase
accumulator via the serial port. This static phase adjustment
results in an output signal that is offset by a constant angle
relative to the nominal signal. This allows the user to phase
align the NCO output with some external signal, if necessary.
This can be especially useful when NCOs of multiple AD9148s
are programmed for synchronization. The phase offset allows
for the adjustment of the output timing between the devices.
The static phase adjustment is sourced from the NCO Phase Offset
Word[15:0] value located in Register 0x58 and Register 0x59.
Updating the Frequency Tuning Word
The frequency tuning word registers do not get updated
immediately upon writing as the other configuration registers
do. After loading the FTW registers with the desired values,
Bit 2 of Register 0x5A must transition from 0 to 1 for the new
FTW to take effect.
Rev. PrA | Page 55 of 73
AD9148
Preliminary Technical Data
CLOCK GENERATION
DAC INPUT CLOCK CONFIGURATIONS
DRIVING THE CLK_x AND REFCLK_x INPUTS
The AD9148 DAC sample clock (DACCLK) can be sourced
directly or by clock multiplying. Clock multiplying employs
the on-chip, phased-locked loop (PLL) that accepts a reference
clock (REFCLK_x) operating at a submultiple of the desired
DACCLK rate, most commonly the data input frequency.
The PLL then multiplies the reference clock up to the desired
DACCLK frequency, which can then be used to generate all the
internal clocks required by the DAC. The clock multiplier
provides a high quality clock that meets the performance
requirements of most applications. Using the on-chip clock
multiplier removes the burden of generating and distributing
the high speed DACCLK.
The REFCLK_x and CLK_x differential inputs share similar
clock receiver input circuitry. Figure 1 shows a simplified circuit
diagram of the input, along with a recommended drive circuit.
The on-chip clock receiver has a differential input impedance of
about 10 kΩ. It is self-biased to a common-mode voltage of about
1.25 V. The recommended circuit for driving the input is a pair
of ac coupling capacitors and a differential 100 Ω termination.
The second mode bypasses the clock multiplier circuitry and
allows DACCLK to be sourced directly through the CLK_x
pins. This mode enables the user to source a very high quality
clock directly to the DAC core. Sourcing the DACCLK directly
through the CLK_x pins may be necessary in demanding
applications that require the lowest possible DAC output noise,
particularly at higher output frequencies.
The minimum input drive level to either of the clock inputs is
100 mV ppd. The optimal performance is achieved when the clock
input signal is between 500 mV ppd and 1.6 V ppd. Whether using
the on-chip clock multiplier or sourcing the DACCLK directly,
it is necessary that the input clock signal to the device has low
jitter and fast edge rates to optimize the DAC noise performance.
DIRECT CLOCKING
When a high quality, sample rate clock is connected to the AD9148,
it provides the lowest noise spectral density at the DAC outputs.
To select the differential CLK inputs as the source for the DAC
sampling clock, set the PLL enable bit to 0 (Register 0x0A, Bit 7).
By setting this bit to 0, it powers down the internal PLL clock
multiplier and selects the input from the CLK_x pins as the
source for the internal DACCLK.
The device also has duty-cycle correction circuitry and differential
input level correction circuitry. Enabling these circuits may provide
improved performance in some cases. The control bits for these
functions can be found in Register 0x08.
DAC
200Ω
5kΩ
100Ω
5kΩ
200Ω
1000pF
CLK_P/
REFCLK_P
1000pF
1.25V
5kΩ
LVPECL
DRIVER
CLK_N/
REFCLK_N
100Ω
5kΩ
1000pF
1.25V
CLK_N/
REFCLK_N
Figure 71. Clock Receiver Circuitry and Recommended Drive Circuitry using LVPECL (Left) and LVDS (Right)
Rev. PrA | Page 56 of 73
08910-071
CLK_P/
REFCLK_P
1000pF
LVPECL
DRIVER
DAC
Preliminary Technical Data
AD9148
0x06[7:6]
PLL LOCK
PLL LOCK LOST
PHASE
DETECTION
LOOP
FILTER
VCO
÷N1
÷N0
0x0D[1:0]
N1
0x0D[3:2]
N0
DACCLK
CLK_P/CLK_N
(PIN B6 AND PIN A6)
÷N2
0x0A[7]
PLL ENABLE
0x0D[7:6]
N2
08910-072
REFCLK_P/REFCLK_N
(PIN B9 AND PIN A9)
0x0E[3:0]
PLL CONTROL
VOLTAGE
ADC
PC_CLK
Figure 72. PLL Clock Multiplication Circuit
CLOCK MULTIPLICATION
Configuring the VCO Tuning Band
The on-chip PLL clock multiplier circuit can be used to generate
the DAC sample rate clock from a lower frequency reference clock.
When the PLL clock multiplier is enabled (Register 0x0A[7] = 1),
the clock multiplication circuit generates the DAC sample clock
from the lower rate REFCLK input. The functional diagram of
the clock multiplier is shown in Figure 72.
The PLL VCO has a valid operating range from approximately
1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands.
For any desired VCO output frequency, there may be several
valid PLL band select values. The frequency bands of a typical
device are shown in Figure 73. Device-to-device variations and
operating temperature affect the actual band frequency range.
Therefore, it is required that the optimal PLL band select value
be determined for each individual device.
The clock multiplication circuit operates such that the VCO
outputs a frequency, fVCO, equal to the REFCLK input signal
frequency multiplied by N0 × N1.
0
4
8
fVCO = fREFCLK × (N0 × N1)
12
The DAC sample clock frequency, fDACCLK, is equal to
16
The output frequency of the VCO must be chosen to keep fVCO in
the optimal operating range of 1.0 GHz to 2.1 GHz. The frequency
of the reference clock and the values of N1 and N0 must be chosen
so that the desired DACCLK frequency can be synthesized and
the VCO output frequency is in the correct range.
PLL BAND
20
fDACCLK = fREFCLK × N1
24
28
32
36
40
44
48
52
56
PLL Bias Settings
There are four bias settings for the PLL circuitry that should be
programmed to their nominal values. The PLL values shown in
Table 24 are the recommended settings for these parameters.
1000
1200
1400
1600
1800
2000
2200
VCO FREQUENCY (MHz)
Figure 73. PLL Lock Range Overtemperature for a Typical Device
Table 24. PLL Settings
Address
PLL SPI Control
PLL Loop Bandwidth
PLL Control 1 Register[4:0]
PLL Cross Control Enable
PLL Ctrl (Test) Register[7:0]
Register
0x0C
0x0C
0x0D
0x79
Rev. PrA | Page 57 of 73
Bit
[7:5]
[4:0]
[4]
[7:0]
Optimal Setting
110
01001
1
11111111
08910-073
60
AD9148
Preliminary Technical Data
Automatic VCO Band Select
The device has an automatic VCO band select feature on chip;
using this feature is a simple and reliable method for configuring
the VCO frequency band. To use the automatic VCO band select
feature, enable the PLL by writing 0xC0 to Register 0x0A and
enable the auto band select mode by writing 0x80 to Register 0x0A.
When this value is written, the device executes an automated
routine that determines the optimal VCO band setting for the
device. The setting selected by the device ensures that the PLL
remains locked over the full −40°C to +85°C operating temperature
range of the device without further adjustment. (The PLL remains
locked over the full temperature range even if the temperature
during initialization is at one of the temperature extremes.)
Manual VCO Band Select
The device also has a manual band select mode that allows the
user to select the VCO tuning band. When in manual mode
(enabled by setting Bit 6, Register 0x0A to 1), the VCO band is
set directly with the value written to the manual VCO band bit
enabled (Bits[5:0], Register 0x0A). To properly select the VCO
band, do the following sequence:
1.
2.
3.
4.
Put device in manual band select mode.
Sweep the VCO band over a range of bands that result in
the PLL being locked.
Verify that the PLL is locked and read the VCO control
voltage for each band.
Select the band that results in the control voltage being
closest to the center of the range (that is, 1000). See Table 25
for more details.
The resulting VCO band should be the optimal setting for the
device. This band should be written to the manual VCO band
register value.
If desired, an indication of where the VCO is within the
operating frequency band can be determined by querying the
VCO control voltage. Table 25 shows how to interpret the VCO
control voltage value.
Table 25. VCO Control Voltage Range Indications
VCO Control Voltage
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Rev. PrA | Page 58 of 73
Indication
Move to higher VCO band
VCO is operating in the higher end of
frequency band
VCO is operating with an optimal region
of the frequency band
VCO is operating in the lower end of
frequency band
Move to lower VCO band
Preliminary Technical Data
AD9148
ANALOG OUTPUTS
For nominal values of VREF (1.2 V), RSET (10 kΩ), and DAC
gain (512), the full-scale current of the DAC is typically 20.16 mA.
The DAC full-scale current can be adjusted from 8.66 mA to
31.66 mA by setting the DAC gain parameter setting as shown
in Figure 74.
TRANSMIT DAC OPERATION
Figure 75 shows a simplified block diagram of one pair of the
transmit path DACs. The DAC core consists of a current source
array, switch core, digital control logic, and full-scale output
current control. The DAC full-scale output current (IOUTFS) is
nominally 20 mA. The output currents from the IOUTx_P and
IOUTx_N pins are complementary, meaning that the sum of
the two currents always equals the full-scale current of the DAC.
The digital input code to the DAC determines the effective
differential current delivered to the load.
35
30
IOUTFS (mA)
25
The DAC has a 1.2 V band gap reference with an output impedance
of 5 kΩ. The reference output voltage appears on the VREF pin.
When using the internal reference, the VREF pin should be
decoupled to AVSS with a 0.1 μF capacitor. The internal reference
should only be used for external circuits that draw dc currents
of 2 μA or less. For dynamic loads or static loads greater than
2 μA, the VREF pin should be buffered. If desired, an external
reference (between 1.10 V to 1.30 V) can be applied to the
VREF pin.
0
400
800
1000
Transmit DAC Transfer Function
The output currents from the IOUTx_P and IOUTx_N pins are
complementary, meaning that the sum of the two currents always
equals the full-scale current of the DAC. The digital input code
to the DAC determines the effective differential current delivered
to the load. IOUTx_P provides the maximum output current
when all bits are high. The output currents vs. DACCODE for
the DAC outputs are expressed as
DACCODE ⎤
I OUT _ P = ⎡⎢
⎥⎦ × I OUTFS
2N
⎣
(1)
IOUT_N = IOUTFS – IOUT_P
(2)
N
where DACCODE = 0 to 2 − 1.
I DAC GAIN
IOUT1_P/IOUT3_P
I DAC
5kΩ
VREF
IOUT1_N/IOUT3_N
CURRENT
SCALING
Q DAC
10kΩ
IOUT2_P/IOUT4_P
Q DAC GAIN
Figure 75. Simplified Block Diagram of DAC Core
Rev. PrA | Page 59 of 73
08910-075
IOUT2_N/IOUT4_N
RSET
600
Figure 74. DAC Full-Scale Current vs. DAC Gain Code
where DAC gain is set individually for the I and Q DACs in
Register 0x30, Register 0x31, Register 0x34, and Register 0x35,
respectively.
I120
200
DAC GAIN CODE
VREF ⎛
3
⎞
× ⎜ 72 + ⎛⎜ × DAC gain ⎞⎟ ⎟
16
RSET ⎝
⎝
⎠⎠
0.1µF
0
08910-074
5
The full-scale current can be calculated by
1.2V
15
10
A 10 kΩ external resistor, RSET, must be connected from the
RESET pin to AVSS. This resistor, along with the reference
control amplifier, sets up the correct internal bias currents for
the DAC. Because the full-scale current is inversely proportional to
this resistor, the tolerance of RSET is reflected in the full-scale
output amplitude.
I OUTFS =
20
AD9148
Preliminary Technical Data
Transmit DAC Output Configurations
Transmit DAC Linear Output Signal Swing
The optimum noise and distortion performance of the AD9148
is realized when it is configured for differential operation. The
common-mode error sources of the DAC outputs are reduced
significantly by the common-mode rejection of a transformer
or differential amplifier. These common-mode error sources
include even-order distortion products and noise. The
enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases and/or its amplitude increases. This is due
to the first-order cancellation of various dynamic commonmode distortion mechanisms, digital feedthrough, and noise.
The DAC outputs have a linear output compliance voltage range
of ±1 V that must be adhered to in order to achieve optimum
performance. The linear output signal swing is dependent on
the full-scale output current, IOUTFS, and the common mode
level of the output.
IOUT1_P/IOUT3_P
VIP +
RO
VOUTI
RO
VQP +
RO
VQN –
IOUT2_P/IOUT4_P
08910-076
VOUTQ
RO
Figure 76. Basic Transmit DAC Output Circuit
Figure 76 shows the most basic DAC output circuitry. A pair of
resistors, RO, are used to convert each of the complementary
output currents to a differential voltage output, VOUT. Because
the current outputs of the DAC are high impedance, the differential
driving point impedance of the DAC outputs, ROUT, is equal to
2 × RO. Figure 77 illustrates the output voltage waveforms.
VP
The AD9148 has four 10-bit auxiliary DACs (AUX1, AUX2,
AUX3, and AUX4). The full-scale output current on these DACs is
derived from the 1.2 V band gap reference and external resistor.
The gain scale from the reference amplifier current, IREF, to the
auxiliary DAC reference current is 16.67 with the auxiliary DAC
gain set to full-scale. This gives a full-scale current of approximately
2 mA for each auxiliary DAC.
The magnitude of the AUX1 DAC current is controlled via
Bits[1:0], Register 0x33 (MSBs) and Bits[7:0], Register 0x32 (LSBs)
when DAC SPI select = 0 (Bit 4, Register 0x00). The magnitude
of the AUX2 DAC current is controlled via Bits[1:0], Register 0x37
(MSBs) and Bits[7:0], Register 0x36 (LSBs) when DAC SPI select = 0
(Bit 4, Register 0x00). Likewise the magnitudes of AUX3 DAC
current and AUX4 DAC current are controlled via Register 0x33 to
Register 0x32 and Register 0x37 to Register 0x36, respectively
when DAC SPI Select = 1 (Reg.0x00[4]).
VIN –
IOUT1_N/IOUT3_N
IOUT2_N/IOUT4_N
AUXILIARY DAC OPERATION
VN
The auxiliary DAC structure is shown in Figure 78. There are
two output signals on each auxiliary DAC. One signal is P, and
the other is N. The auxiliary DAC outputs are not differential.
Only one side of the auxiliary DAC (P or N) is active at one
time. The inactive side goes into a high impedance state
(100 kΩ). Control of the P side and N side for the auxiliary
DACs is via Bit 7, Register 0x33 and Bit 7, Register 0x37 (DAC
SPI select is 0 to control AUX1 and AUX2, and DAC SPI select
is 1 to control AUX3 and AUX4).
VPEAK
VB
0mA TO 2mA
(SOURCE)
VOM
0mA TO 2mA
(SINK)
AUXDAC[9:0]
TIME
AUXDAC
DIRECTION
(SOURCE/SINK)
08910-077
AUXDAC
SIGN
(P/N)
Figure 77. Voltage Output Waveforms
AUX_P
The common-mode signal voltage, VCM, is calculated by
VCM
AUX_N
I
= FS × RO
2
Figure 78. Auxiliary DAC Structure
The peak output voltage, VPEAK, is calculated by
VPEAK = IFS × RO
With this circuit configuration, the single-ended peak voltage is
the same as the peak differential output voltage.
Rev. PrA | Page 60 of 73
08910-078
VP
Preliminary Technical Data
AD9148
Baseband Filter Implementation
In addition, the P or N output can act as a current source or a
current sink. When sourcing current, the output compliance
voltage is 0 V to 1.6 V. When sinking current, the output compliance
voltage is 0.8 V to 1.6 V. The auxiliary DAC current direction is
programmable via Bit 6, Register 0x33 and Bit 6, Register 0x37
(DAC SPI select is 0 to control AUX1 and AUX2, and DAC SPI
select is 1 to control AUX3 and AUX4). The choice of sinking or
sourcing should be made at circuit design time. There is no
advantage to switching between sourcing and sinking current
after the circuit is in place.
Most applications require a baseband anti-imaging filter between
the DAC and modulator to filter out Nyquist images and broadband
DAC noise. The filter can be inserted between the I-to-V resistors
at the DAC output and the signal level setting resistor across the
modulator input. Doing this establishes the input and output
impedances for the filter.
Figure 81 shows a fifth-order low-pass filter. A common-mode
choke is used between the I-to-V resistors and the remainder of
the filter. This removes the common-mode signal produced by
the DAC and prevents the common-mode signal from being
converted to a differential signal, which would appear as unwanted
spurious signals in the output spectrum. The common-mode
choke or balun may not be needed if the layout between the
DAC and IQ modulator is optimized and balanced. Splitting the
second filter capacitor into two and grounding the center point
creates a common-mode low-pass filter providing additional
common-mode rejection of high frequency signals. A purely
differential filter will pass common-mode signals.
These auxiliary DACs can be used for local oscillator (LO)
cancellation when the DAC output is followed by a quadrature
modulator. More information and example application circuits
are given in the Interfacing to Modulators section.
INTERFACING TO MODULATORS
The AD9148 interfaces to the ADL537x family of with a minimal
number of components. An example of the recommended
interface circuitry is shown in Figure 79.
ADL537x
IOUT1_P
Driving the ADL5375-15 with the AD9148
IBBP
RBIN
50Ω
The ADL5375-15 requires a 1500 mV dc bias and therefore
requires a slightly more complex interface than most other
Analog Devices, Inc., modulators. It is necessary to level shift
the DAC output from a 500 mV dc bias to the 1500 mV dc bias
that the ADL5375-15 requires. Level shifting can be achieved
with a purely passive network, as shown in Figure 80. In this
network, the dc bias of the DAC remains at 500 mV, while the
input to the ADL5375-15 is 1500 mV. Note that this passive
level shifting network introduces approximately 2 dB of loss in
the ac signal.
RLI
100Ω
IBBN
IOUT1_N
IOUT2_N
QBBN
RBQP
50Ω
RLQ
100Ω
QBBP
IOUT2_P
08910-079
RBQN
50Ω
Figure 79. Typical Interface Circuitry Between the AD9148 and ADL537x
Family of Modulators
AD9148
The baseband inputs of the ADL537x family require a dc bias of
500 mV. The nominal midscale output current on each output
of the DAC is 10 mA (1/2 the full-scale current). Therefore, a
single 50 Ω resistor to ground from each of the DAC outputs
results in the desired 500 mV dc common-mode bias for the
inputs to the ADL537x. The signal level can be reduced by the
addition of the load resistor in parallel with the modulator
inputs (RLI, RLQ). The peak-to-peak voltage swing of the
transmitted signal is
IBBP
RBIP
45.3Ω
RLIP
3480Ω
RBIN
45.3Ω
RLIN
RSIP
1kΩ 3480Ω
IOUT1_N
5V
IBBN
RSQN
1kΩ
IOUT2_N
QBBN
RBQN
45.3Ω
RLQN
3480Ω
RBQP
45.3Ω
RSQP RLQP
1kΩ 3480Ω
IOUT2_P
[2 × RB × RL ]
VSIGNAL = I FS ×
[2 × RB + RL ]
ADL5375-15
RSIN
1kΩ
IOUT1_P
5V
QBBP
Figure 80. Passive Level Shifting Network for Biasing ADL5375-15 from AD9148
50Ω
22pF
MABACT0043
(OPTIONAL)
IDAC
OR
QDAC
33nH
56nH
33nH
56nH
2pF
50Ω
3pF
6pF
22pF
100Ω ADL537x
3pF
Figure 81. DAC Modulator Interface with Fifth-Order, Low Pass Filter
Rev. PrA | Page 61 of 73
08910-080
RBIP
50Ω
08910-081
AD9148
AD9148
Preliminary Technical Data
Reducing LO Leakage and Unwanted Sidebands
Analog Devices modulators can introduce unwanted signals at
the LO frequency due to dc offset voltages in the I and Q baseband
inputs as well as feedthrough paths from the LO input to the
output. The LO feedthrough can be nulled by applying the correct
dc offset voltages at the DAC output. This can be done either by
using the auxiliary DACs (Register 0x32, Register 0x33,
Register 0x36, and Register 0x37) or by using the digital dc
offset adjustments (Register 0x2C to Register 0x2F). Using the
auxiliary DACs has the advantage that none of the main DAC
dynamic range is used for performing the dc offset adjustment.
The disadvantage is that the common-mode level of the output
signal changes as a function of the auxiliary DAC current. The
opposite is true when the digital offset adjustment is used.
Good sideband suppression requires both gain and phase matching
of the I and Q signals. The phase adjust (Register 0x28 to
Register 0x2B) and gain control (Register 0x50 and Register 0x51)
registers can be used to calibrate I and Q transmit paths to optimize
the sideband suppression. As an alternative to the digital gain
scaling, the DAC full-scale output current (Register 0x30,
Register 0x31, Register 0x34, and Register 0x35) can also be
adjusted to calibrate the I and Q transmit paths; however, changing
the DAC full-scale output current affects the common-mode
voltage level.
For more information on correcting imperfections in IQ
modulators to improve RF signal fidelity, refer to Application
Note AN-1039.
Rev. PrA | Page 62 of 73
Preliminary Technical Data
AD9148
DEVICE POWER DISSIPATION
3.25
The AD9148 has four supply rails: AVDD33, IOVDD, DVDD18,
and CVDD18.
1×
2×
4×
8×
2.75
POWER DISSIPATION (W)
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
2.50
1×
2×
4×
8×
2.00
1.75
1.50
1.50
300
08910-083
280
260
240
220
200
180
160
140
120
80
100
1.00
0.75
0.50
0.25
fDATA (MSPS)
08910-084
300
280
260
240
220
200
180
160
140
120
100
80
60
0
Figure 84. DVDD18 Power Dissipation vs. fDATA with Coarse Modulation, PLL,
and Inverse Sinc Filter Disabled
2.50
1×
2×
4×
8×
2.25
2.00
1.75
1.50
1.25
1.00
0.75
1.25
0.50
1.00
0.25
0.75
300
280
260
240
220
08910-082
fDATA (MSPS)
200
180
160
140
120
80
100
60
40
20
0
300
280
260
240
220
08910-085
fDATA (MSPS)
0.25
200
180
160
140
120
100
80
60
40
0
0
0.50
0
60
1.25
20
POWER DISSIPATION (W)
2.25
1×
2×
4×
8×
1.75
POWER DISSIPATION (W)
2.75
2.00
40
Figure 82 to Figure 87 detail the power dissipation of the AD9148
under a variety of operating conditions. All of the graphs are
taken with data being supplied to all four DACs. The power
consumption of the device does not vary significantly with
changes in the coarse modulation mode selected or analog
output frequency. Graphs of the total power dissipation are
shown along with the power dissipation of the DVDD18 and
CVDD18 supplies.
40
0
The CVDD18 supply powers the clock receiver and clock
distribution circuitry. The power consumption from this
supply varies directly with the operating frequency of the
device. CVDD18 also powers the PLL. The power dissipation
of the PLL is typically 140 mW.
fDATA (MSPS)
Figure 83. Total Power Dissipation vs. fDATA with Fine Modulation, PLL, and
Inverse Sinc Filter Disabled
0
The DVDD18 supply powers all of the digital signal processing
blocks of the device. The power consumption from this supply
is a function of which digital blocks are enabled and the frequency
at which the device is operating.
20
0
POWER DISSIPATION (W)
The IOVDD voltage supplies the serial port I/O pins (SCLK,
SDIO, SDO, CSB, TCK, TDI, TDO, TMS), the RESET pin, and
the IRQ pin. The voltage applied to the IOVDD pin can range
from 1.8 V to 3.3 V. The current drawn by the IOVDD supply
pin is typically 1 mA.
20
The AVDD33 supply powers the DAC core circuitry. The power
dissipation of the AVDD33 supply rail is independent of the digital
operating mode and sample rate. The current drawn from the
AVDD33 supply rail is typically 98 mA (320 mW) when the
full-scale current of the four main DACs (DAC 1, DAC 2, DAC
3, and DAC 4) is set to the nominal value of 20 mA. Changing
the full-scale current directly impacts the supply current drawn
from the AVDD33 rail. For example, if the full-scale current of
the four main DACs is changed to 10 mA, the AVDD33 supply
current drops by 40 mA to 58 mA.
3.00
Figure 85. DVDD18 Power Dissipation vs. fDATA with Fine Modulation, PLL,
and Inverse Sinc Filter Disabled
Figure 82. Total Power Dissipation vs. fDATA with Coarse Modulation, PLL, and
Inverse Sinc Filter Disabled
Rev. PrA | Page 63 of 73
AD9148
Preliminary Technical Data
0.25
0.35
0.23
0.30
0.20
POWER (W)
0.18
0.20
0.15
0.15
0.13
0.10
0.08
0.10
0.05
0.05
0.03
0
Figure 86. CVDD18 Power Dissipation vs. fDAC, PLL Disabled
300
280
260
240
08910-087
fDATA (MSPS)
220
fDAC (MSPS)
200
1000
180
900
160
800
140
700
120
600
80
500
100
400
60
300
40
200
0
100
20
0
0
08910-086
POWER (W)
0.25
Figure 87. DVDD18 Power Dissipation vs. fDATA due to Inverse Sinc Filter
Rev. PrA | Page 64 of 73
Preliminary Technical Data
AD9148
TEMPERATURE SENSOR
The AD9148 has a diode-based temperature sensor for measuring
the temperature of the die. The temperature reading is accessed
by Register 0x5E and Register 0x5F. The temperature of the die
can be calculated as
TDIE =
(DieTemp[15 : 0] − 46875)
126.9
where TDIE is the die temperature in degrees Celsius. The
temperature accuracy is ±5°C typical over TBD range.
Estimates of the ambient temperature can be made if the power
dissipation of the device is known. For example, if the device power
dissipation is 800 mW and the measured die temperature is 50°C,
then the ambient temperature can be calculated as
TA = TDIE – PD × TJA = 50 – 0.8 × 19.1 = 34.7°C
where:
TA is the ambient temperature in degrees Celsius.
TJA is the thermal resistance from junction to ambient of the
AD9148 as shown in Table 7.
To use the temperature sensor, it must be enabled by setting
Bit 0, Register 0x5C to 0. Before the temperature sensor data can
be readback, it must be latched by toggling Bit 1, Register 0x5C
from 0 to 1. In addition, to get accurate readings, the range
control register (Register 0x5D) should be set to 0x02.
Rev. PrA | Page 65 of 73
AD9148
Preliminary Technical Data
INTERRUPT REQUEST OPERATION
The AD9148 provides an interrupt request output signal (Pin H4,
IRQ) that can be used to notify an external host processor of
significant device events. Upon assertion of the interrupt, the
device should be queried to determine the precise event that
occurred. The IRQ pin is an open-drain, active low output. Pull
the IRQ pin high external to the device. This pin may be tied to
the interrupt pins of other devices with open-drain outputs to
wired-OR these pins together.
E
A
A
The latched version of an event flag (the interupt_source signal)
can be cleared in two ways. The recommended way is by writing 1
to the corresponding event flag bit. A hardware or software reset
also clears the interupt_source.
E
A
A
INTERRUPT SERVICE ROUTINE
E
A
A
Ten different event flags provide visibility into the device. These
10 flags are located in the two event flag registers (Register 0x06
and Register 0x07). The behavior of each of the event flags is
independently selected in the interrupt enable registers
(Register 0x04 and Register 0x05). When the flag interrupt
enable is active, the event flag latches and triggers an external
interrupt. When the flag interrupt is disabled, the event flag
simply monitors the source signal and the external IRQ remains
inactive.
Interrupt request management starts by selecting the set of event
flags that require host intervention or monitoring. Those events
that require host action should be enabled so that the host is
notified when they occur. For events requiring host intervention,
upon IRQ activation, run the following routine to clear an
interrupt request:
E
•
•
Read the status of the event flag bits that are being
monitored.
Set the interupt enable bit low so that the unlatched
event_flag_source can be monitored directly.
Perform any actions that may be required to quiet the
event_source_flag. In many cases, no specific actions may
be required.
Read the event flag to verify the actions taken have quieted
the event_flag_source.
Clear the interrupt by writing 1 to the event flag bit.
Set the interrupt enable bits of the events to be monitored.
E
A
A
Figure 88 shows the IRQ-related circuitry. Figure 88 shows how the
event flag signals propagate to the IRQ output. The interupt_enable
signal represents one bit from the interrupt enable register. The
event_flag signal represents one bit from the event flag register.
The event_flag_source signal represents one of the device signals
that can be monitored such as the PLL_locked signal from the
PLL phase detector or the FIFO Warning 1 signal from the
FIFO controller.
•
E
A
A
E
A
A
When an interrupt enable bit is set high, the corresponding
event flag bit reflects a positively tripped (that is, latched on the
rising edge of the event_source) version of the event_flag_source
signal. This signal also asserts the external IRQ. When an
interrupt enable bit is set low, the event flag bit reflects the
current status of the event_flag_source signal, and the event flag
has no effect on the external IRQ.
A
A
•
•
•
Noted that some of the event_flag_source signals are latched
signals. These are cleared by writing to the corresponding event
flag bit. Details of each of the event flags can be found in Table 12.
E
A
A
E
A
A
0
EVENT_FLAG
1
IRQ
INTERRUPT_ENABLE
EVENT_FLAG_SOURCE
INTERRUPT
SOURCE
OTHER
INTERRUPT
SOURCES
08910-088
WRITE_1_TO_EVENT_FLAG
DEVICE_RESET
Figure 88. Simplified Schematic of IRQ Circuitry
E
A
Rev. PrA | Page 66 of 73
A
Preliminary Technical Data
AD9148
INTERFACE TIMING VALIDATION
The AD9148 provides on-chip sample error detection (SED)
circuitry that simplifies verification of the input data interface.
The SED compares the input data samples captured at the digital
input pins with a set of comparison values. The comparison values
are loaded into registers through the SPI port. Differences between
the captured values and the comparison values are detected and
stored. Options are available for customizing SED test sequencing
and error handling.
SED OPERATION
The SED circuitry operates on a two data sets, one for each data
port, each made up of four 16-bit input words, denoted as S0,
S1, S2, and S3. To properly align the input samples, the first
data-word (that is, S0) is indicated by asserting FRAME for at
least one complete input sample.
Figure 89 shows the input timing of the interface for each port.
The FRAME signal can be issued once at the start of the data
transmission, or it can be asserted repeatedly at intervals coinciding
with the S0 and S1 data-words.
A[15:0]/
B[15:0]
S0
S1
S2
S3
S0
S1
08910-089
FRAMEA/
FRAMEB
Figure 89. Timing Diagram of Extended FRAME Signal Required to Align
Input Data for SED
The SED has five flag bits (Register 0x40, Bit 0, Bit 1, Bit 2, Bit 5
and Bit 6) that indicate the results of the input sample comparisons.
The sample error detected bit (Bit 5, Register 0x40 for Port A
and Bit 6, Register 0x40 for Port B) is set when an error is
detected and remains set until cleared. The SED also provides
registers that indicate which input data bits experienced errors
(Register 0x41 through Register 0x44). These bits are latched
and indicate the accumulated errors detected until cleared.
The autoclear mode has two effects: it activates the compare fail
bits and the compare pass bit (Register 0x40, Bit 2, Bit 1 and Bit 0)
and changes the behavior of Register 0x41 through Register 0x44.
The compare pass bit sets if the last comparison indicated the
sample was error free. The compare fail bit sets if an error is
detected. The compare fail bit is cleared automatically by the
reception of eight consecutive error-free comparisons. When
auto-clear mode is enabled (Bit 3, Register 0x40), Register 0x41
through Register 0x44 accumulate errors as previously described
but reset to all 0s after eight consecutive error-free sample
comparisons are made.
The sample error, compare pass, and compare fail flags can be
configured to trigger an IRQ when active, if desired. This is
done by enabling the appropriate bits in the event flag register
(Register 0x07).
SED EXAMPLE
Normal Operation
The following example illustrates the SED configuration for
continuously monitoring the input data and assertion of an IRQ
when a single error is detected.
1. Write to the following registers to enable the SED and load
the comparison values:
Register 0x40 → 0x80
Register 0x00[4] → 0 (to configure Port A SED)
Register 0x38 → S0[7:0]
Register 0x39 → S0[15:8]
Register 0x3A → S1[7:0]
Register 0x3B → S1[15:8]
Register 0x3C → S2[7:0]
Register 0x3D → S2[15:8]
Register 0x3E → S3[7:0]
Register 0x3F → S3[15:8]
Register 0x00[4] → 1 (to configure Port B SED)
Register 0x38 → S0[7:0]
Register 0x39 → S0[15:8]
Register 0x3A → S1[7:0]
Register 0x3B → S1[15:8]
Register 0x3C → S2[7:0]
Register 0x3D → S2[15:8]
Register 0x3E → S3[7:0]
Register 0x3F → S3[15:8]
Comparison values can be chosen arbitrarily; however,
choosing values that require frequent bit toggling provides
the most robust test.
2. Enable the SED error detect flag to assert the IRQ pin.
Register 0x05 → 0x04
3. Begin transmitting the input data pattern.
If IRQ is asserted, read Register 0x40 and Register 0x41 through
Register 0x44 with Bit 4, Register 0x00 = 0 for Port A and with
Bit 4, Register 0x00 = 1 for Port B, to verify that a SED error was
detected and determine which input bits were in error. The bits in
Register 0x41 through Register 0x44 are latched; therefore, the bits
indicate any errors that occurred on those bits throughout the test
and not just the errors that caused the error detected flag to be set.
Note that the FRAME signal is not required during normal
operation when the device is configured for dual-port mode. To
enable the alignment of the S0 sample as previously described
requires the use of both the FRAMEA and FRAMEB signals.
The timing diagram for single-port and byte mode is the same as
during normal operation and are shown in Figure 47 and Figure 48,
respectively. For single-port and byte mode, only FRAMEA and
the IRQs for Port A should be used. The FRAMEA rising edge
should always be aligned with the first sample of the data transmission. There should not be another rising edge until four complete
words of data are received. This means four data samples for dualport mode and eight data samples for single-port and byte modes.
Rev. PrA | Page 67 of 73
AD9148
Preliminary Technical Data
TEST ACCESS PORT
The AD9148 incorporates a test access port (TAP) and
boundary scan architecture. The TAP has four pins that provide
access into the device for performing the boundary scan testing:
•
•
•
•
Table 26. Instruction Code Register Definition
TAP Instruction
EXTEST
IDCODE
SAMPLE/PRELOAD
BYPASS
TMS ,test mode select input
TCK , test clock input
TDI , test data input
TDO , test data output
Instruction Code
00000
00001
00010
11111
Data Register
Selected
Boundary scan
IDCODE
Boundary scan
Bypass
The boundary scan register is the main test register. It provides
the means for moving data from and to the device pins. The
bypass register is a single bit register that passes data from TDI
to TDO. The IDCODE register contains the ID code and
revision number for the device. This information allows the
device to be linked to its boundary scan description language
(BSDL) file. The file contains details of the boundary scan
configuration for the device.
The instruction register holds the current instruction used by the
TAP controller to decide what to do with the test signals that are
received. Most commonly, the content of the instruction register
defines to which of the data registers signals should be passed.
Table 26 shows the supported instructions, the instruction code,
and the data register selected. All instruction codes that are not
listed in Table 26 are reserved.
The content of the 32-bit IDCODE register is 0x227E51CB.
The TAP controller is reset to an inactive state by the internal
power-on-reset. Figure 90 shows the basic timing diagram of
the controller signals.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
08910-090
tDSYS
SYSTEM
OUTPUTS
Figure 90. Basic Timing Diagram of the TAP Controller Signals
Table 27.
Parameter
TIMING CHARACTERISTICS
tTCK
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
Description
Minimum
TCK period
TDI, TMS setup before TCK high
TDI, TMS hold after TCK high
System inputs setup before TCK high
System inputs hold after TCK high
TRST pulse width (measured in TCK cycles)
20
4
4
4
5
4
SWITCHING CHARACTERISTICS
tDTDO
tDSYS
TDO delay from TCK low
System output delay after TCK low
0
Rev. PrA | Page 68 of 73
Maximum
Unit
ns
ns
ns
ns
ns
TCK
10
12
ns
ns
Preliminary Technical Data
AD9148
When loading and unloading the AD9148 scan chain, note that:
A total of 79 pins can be accessed thru the boundary scan
register. They are as follows:
•
•
•
•
A[15:0]_P, A[15:0]_N, B[15:0]_P, B[15:0]_N
DCIA_P, DCIA_N, DCIB_P, DCIB_N,
FRAMEA_P, FRAMEA_N, FRAMEB_P, FRAMEB_N
RESET
CSB, SCLK, SDIO, SDO
IRQ
PLL_LOCK
E
•
Figure 91 shows the basic connection between the device pins
and the boundary scan chain. The boundary scan allows
connectivity checks of the device pins but does not allow for
stimulating or querying the device core.
•
When unloading the scan chain, if DCIA or FRAMEA are
set on the pins, there is two bits set for each (Bit 42 and
Bit 44 for DCIA and Bit 41 and Bit 43 for FRAMEA). If
DCIB or FRAMEB are set on the pins, there is one bit set
for each (Bit 42 for DCIB and Bit 41 for FRAMEB).
If the scan chain is used to load the output pins (IRQ, SDO,
or PLL_LOCK), two bits are set when each output pin is
read back. The two bits include the output pin of interest
and the bit that is two locations lower on the scan chain
(for example, to read back IRQ both Bit 4 and Bit 2 are set).
The SDIOEN signal cannot be read back. Also, when read
back begins, the values of the RESET, CSB, SCLK, and
SDIO input pins are resampled. If the inputs have changed
value since the sampling with the TAP PRELOAD command,
this affects the read back results. The order of the scan
chain readback is: SDOENA, SDO, PLL_LOCK, IRQ,
SDI_preload, SDIO_current, SCLK_current, CSB_current,
RESET_current, PortB data, PortA data, DCIs, and
FRAMES.
E
E
(SCAN OUT)
SERIAL OUT (TDO)
OUTPUT
PAD
CHIP CORE
INPUT
PAD
INPUT
BSR
UPDT_OUT
SCAN OUT
SERIAL IN (TDI)
(SCAN IN)
OUTPUT BSR
Figure 91. Basic Connections Between Device Pins and the Boundary Scan Chain
Rev. PrA | Page 69 of 73
08910-091
•
•
•
•
AD9148
Preliminary Technical Data
For the order of loading and unloading the scan chain, refer to
Table 28.
Table 28. TAP Load and Read Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
TAP Load Sequence
SDIOEN
SDOEN
SDO
PLL_LOCK
IRQ
SDIO
SCLK
CSB
RESET
B15_P
B14_P
B13_P
B12_P
B11_P
B10_P
B9_P
B8_P
B7_P
B6_P
B5_P
B4_P
B3_P
B2_P
B1_P
B0_P
A15_P
A14_P
A13_P
A12_P
A11_P
A10_P
A9_P
A8_P
A7_P
A6_P
A5_P
A4_P
A3_P
A2_P
A1_P
A0_P
FRAMEB_P
DCIB_P
FRAMEA_P
DCIA_P
E
TAP Unload Sequence
SDOEN
SDO
PLL_LOCK
IRQ
SDIO, preload
SDIO, current
SCLK, current
CSB, current
RESET, current
B15_P
B14_P
B13_P
B12_P
B11_P
B10_P
B9_P
B8_P
B7_P
B6_P
B5_P
B4_P
B3_P
B2_P
B1_P
B0_P
A15_P
A14_P
A13_P
A12_P
A11_P
A10_P
A9_P
A8_P
A7_P
A6_P
A5_P
A4_P
A3_P
A2_P
A1_P
A0_P
FRAMEB_P
DCIB_P
FRAMEA_P
DCIA_P
E
Rev. PrA | Page 70 of 73
Preliminary Technical Data
AD9148
EXAMPLE START-UP ROUTINE
To ensure reliable start-up of the AD9148, certain sequences
should be followed. An example start-up routine using the
following device configuration is used for this example:
START-UP SEQUENCE
•
•
•
•
•
•
•
•
•
•
•
The power clock and register write sequencing for reliable
device start-up follows:
fDATA = 122.88 MSPS
Interpolation = 4×, using HB1 = ’00’ and HB2 = ’000’
Input data = baseband data
Dual port mode with 1 DCI
fOUT = 140 MHz
fREFCLK = 122.88 MHz
PLL = enabled
Fine NCO = enabled
Inverse SINC Filter = disabled
Synchronization = enabled
•
•
•
•
DERIVED PLL SETTINGS
The following PLL settings can be derived from the device
configuration:
•
•
•
•
fDACCLK = fDATA × Interpolation = 491.52 MHz
fVCO = 4 × fDACCLK = 1966.08 MHz (1 GHz < fVCO < 2 GHz)
N1 = fDACCLK/fREFCLK = 4
N0 = fVCO/fDACCLK = 4
DERIVED NCO SETTINGS
The following NCO settings can be derived from the device
configuration:
•
•
•
fOUT = 140 MHz
fDACCLK = fDATA × Interpolation = 491.52 MHz
FTW = 140/(491.52) × 232 = 0x48, EAAAAA
Power up the device (no specific power supply sequence is
required)
Apply stable REFCLK input signal.
Apply stable DCI input signal.
Issue hardware reset (optional)
Configure device registers with the following write
sequence:
0x0C → 0xC9
0x0D → 0xD9
0x0A → 0xC0
0x0A → 0x80
0x10 → 0x48
0x14 → 0x40
0x17 → 0x80
0x17 → 0x00
0x19 → 0x80
0x19 → 0x00
0x1C → 0x40
0x1D → 0x00
0x1E → 0x01
0x54 → 0xAA
0x55 → 0xAA
0x56 → 0xEA
0x57 → 0x48
0x5A → 0x01
0x5A → 0x00
DEVICE VERIFICATION SEQUENCE
The following device polling can be conducted to verify the
device is working properly:
•
•
•
•
Read 0x06, Expect Bit 7 = 0, Bit 6 = 1, Bit 5 = 0, Bit 4 = 1,
Bit 2 = 1
Read 0x12, Expect Bit 6 = 1
Read 0x18, Expect 0x0F (0x07 is also normal)
Read 0x1A, Expect 0x0F (0x07 is also normal)
Rev. PrA | Page 71 of 73
AD9148
Preliminary Technical Data
OUTLINE DIMENSIONS
12.10
12.00 SQ
11.90
A1 BALL
CORNER
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
10.40
BSC SQ
0.80
BSC
0.80
REF
TOP VIEW
*1.30
1.16
1.02
BOTTOM VIEW
DETAIL A
0.65
REF
DETAIL A
0.24
REF
SEATING
PLANE
0.53
COPLANARITY
0.48
0.12
0.43
BALL DIAMETER
*COMPLIANT TO JEDEC STANDARDS MO-219
WITH EXCEPTION TO PACKAGE HEIGHT.
Figure 92. 196-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]
(BC-196-7)
Dimensions shown in millimeters
Rev. PrA | Page 72 of 73
0.96
0.89
0.82
0.38
0.33
0.28
03-02-2010-A
A1 BALL
CORNER
Preliminary Technical Data
12.10
12.00 SQ
11.90
11.20
REF SQ
8.20 SQ
TOP VIEW
1.50
1.32
1.17
A1 BALL
PAD CORNER
14 13 12 11 10 9 8 7 6 5 4 3 2 1
10.40
BSC SQ
0.80
BSC
0.80 REF
DETAIL A
0.75
REF
A
B
C
D
E
F
G
H
J
K
L
M
N
P
DETAIL A
BOTTOM VIEW
1.09
0.99
0.89
0.38
0.33
0.28
0.24 REF
SEATING
PLANE
0.53
0.48
0.43
BALL DIAMETER
COPLANARITY
0.12
COMPLIANT TO JEDEC STANDARDS MO-192.
03-02-2010-A
A1 BALL
PAD CORNER
AD9148
Figure 93. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_EP]
(BP-196-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9148BBCZ
AD9148BBCZRL
AD9148BBPZ
AD9148BBPZRL
AD9148BPCZ
AD9148BPCZRL
AD9148-EBZ
AD9148-M5372-EBZ
AD9148-M5375-EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
196-Ball Ball Grid Array, Thermally Enhanced [BGA_EP]
196-Ball Ball Grid Array, Thermally Enhanced [BGA_EP]
196-Ball Ball Grid Array, Thermally Enhanced [BGA_EP]
196-Ball Ball Grid Array, Thermally Enhanced [BGA_EP]
DAC Only Evaluation Board
AD9148 + ADL5372 Evaluation Board
AD9148 + ADL5375-0.5 Evaluation Board
Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR08910-0-4/10(PrA)
Rev. PrA | Page 73 of 73
Package Option
BC-196-7
BC-196-7
BP-196-1
BP-196-1
BP-196-1
BP-196-1