APW8804 3A 5V 1MHz Synchronous Buck Converter Features General Description • High Efficiency up to 95% APW8804 is a 3A synchronous buck converter with inte- - Automatic PFM/PWM Mode Operation grated 65mΩ high side and 55mΩ low side power MOSFETs. The APW8804, design with a current-mode • Adjustable Output Voltage from 0.6V to VPVDD • Integrated 65mΩ High Side / 55mΩ Low Side control scheme, can convert wide input voltage of 2.6V to 6V to the output voltage adjustable from 0.6V to 6V to MOSFETs • Low Dropout Operation: 100% Duty Cycle • Stable with Low ESR Ceramic Capacitors • Power-On-Reset Detection on VDD and PVDD • Integrated Soft-Start and Soft-Stop • Over-Temperature Protection • Over-Voltage Protection • Under-Voltage Protection • High/ Low Side Current Limit • Power Good Indication • Enable/Shutdown Function • Small TDFN3x3-10 and SOP-8P Packages • Lead Free and Green Devices Available provide excellent output voltage regulation. The APW8804 is equipped with an automatic PFM/PWM mode operation. At light load , the IC operates in the PFM mode to reduce the switching losses. At heavy load, the IC works in PWM mode. At PWM mode, the switching frequency is set by the external resistor. The APW8804 is also equipped with Power-on-reset, softstart, soft-stop, and whole protections (under-voltage, over-voltage, over-temperature and current-limit) into a single package. This device, available TDFN3x3-10 and SOP-8P, provides a very compact system solution external components and PCB area. Simplified Application Circuit (RoHS Compliant) Applications • • Notebook Computer & UMPC • Set-Top Box • DSL, Switch HUBr • Portable Instrument VIN VOUT LCD Monitor/TV PVDD LX VDD FB (option) APW8804 POK ON OFF GND EN ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 1 www.anpec.com.tw APW8804 Ordering and Marking Information Package Code KA : SOP-8P QB : TDFN3x3-10 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW8804 Assembly Material Handling Code Temperature Range Package Code APW8804 KA : APW8804 XXXXX XXXXX - Date Code APW8804 QB : APW 8804 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration APW8804 NC 1 LX 2 LX 3 POK 4 EN 5 11 GND APW8804 10 PVDD 9 PVDD 8 VDD 7 NC 6 FB LX LX POK EN 1 2 3 4 TDFN 3X3-10 (Top View) 8 PVDD 7 VDD 6 GND 5 FB 9 GND SOP-8P (Top View) 11 GND Exposed pad 9 Exposed pad GND The pin 6 must be connected to the pin 9 (exposed pad) Absolute Maximum Ratings (Note 1) Symbol VPVDD, VVDD VLX Parameter Rating Input Supply Voltage LX to GND Voltage POK, FB, EN to GND Voltage PD Power Dissipation TJ Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds Unit -0.3 ~ 6.5 V <30ns pulse width -3 ~VPVDD+3 V >30ns pulse width -1 ~VPVDD+0.3 V -0.3 ~ 6.5 V 2 W 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 2 www.anpec.com.tw APW8804 Thermal Characteristics Symbol θJA θJC Parameter Junction-to-Ambient Resistance in Free Air Typical Value Unit (Note 2) SOP-8P TDFN3x3-10 60 50 o SOP-8P TDFN3x3-10 20 10 o C/W Junction-to-Case Resistance in Free Air (Note 3) C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P or TDFN3x3-10 is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P or TDFN3x3-10 package. Recommended Operating Conditions (Note 4) Parameter Symbol VVDD Control and Driver Supply Voltage VPVDD Input Supply Voltage VOUT L IOUT Range Unit 2.6~ 6 V 2~6 V Converter Output Voltage 0.6~6 V Inductance 1~3.3 µH Converter Output Current 0~3 A TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o C C Note 4: Refer to the typical application circuit. Electrical Characteristics Unless otherwise specified, these specifications apply over VVDD=VPVDD=5V, VOUT=3.3V, TA=25oC. Symbo Parameter APW8804 Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT VDD Supply Current VFB=0.7V - 460 - µA IVDD_SDH VDD Shutdown Supply Current EN=GND - - 1 µA 2.3 2.4 2.5 V - 0.2 - V 1.5 1.7 1.9 V - 0.2 - V IVDD POWER-ON-RESET (POR) VDD POR Voltage Threshold VVDD Rising VDD POR Hysteresis PVDD POR Voltage Threshold PVDD POR Hysteresis REFERENCE VOLTAGE VREF Reference Voltage All temperature Output Accuracy Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 IOUT=10mA~3A, VVDD=2.6~5V 3 - 0.6 - V -1 - +1 % -1.5 - +1.5 % www.anpec.com.tw APW8804 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VVDD=VPVDD=5V, VOUT=3.3V, TA=25oC. Symbo Parameter APW8804 Test Conditions Unit Min. Typ. Max. 0.85 1 1.15 MHz - 100 - % - 100 - ns - 65 80 mΩ - 55 75 mΩ - - 1 µA - 550 - µA/V - 80 - dB Current Sense Transresistance - 400 - mΩ Dead Time - 20 - ns 4 4.5 5 A Over-Temperature Trip Point - 150 - °C Over-Temperature Hysteresis - 30 - °C Over-Voltage Protection Threshold 120 - 135 %VREF Under-Voltage Protection Threshold 45 50 55 %VREF - 1 - ms - - 1.4 V 0.5 - - V - 500 - kΩ 87 90 93 %VOUT POK Low Hysteresis (POK Goes Low) - 5 - %VOUT POK in from Higher (POK Goes High) 122 125 128 %VOUT - 5 - %VOUT - 100 - Ω OSCILLATOR AND DUTY CYCLE FOSC Oscillator Frequency Maximum Converter’s Duty VFB=0.7V Minimum on Time POWER MOSFET High Side P-MOSFET Resistance Low Side N-MOSFET Resistance VVDD=5V, ILX=0.5A, TA=25oC o VVDD=5V, ILX=0.5A, TA=25 C High/Low Side MOSFET Leakage Current CURRENT-MODE PWM CONVERTER Gm Error Amplifier Transconductance Error Amplifier DC Gain TD COMP=NC PROTECTIONS ILIM TOTP MOSFET Current-Limit Peak Current SOFT-START, ENABLE, AND INPUT CURRENTS Soft-Start Time EN Enable Threshold VEN rising voltage to enable device EN Shutdown Threshold VEN falling voltage to shutdown device EN Pull Low Resistance POK in from Lower (POK Goes High) POK Threshold POK High Hysteresis (POK Goes Low) Power Good Pull Low Resistance Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 4 www.anpec.com.tw APW8804 Typical Operating Characteristics Refer to the “Typical Application Circuit”. The test condition is VVDD=5V, TA= 25oC unless otherwise specified. Efficiency vs. Load Current 100 90 90 Efficiency (%) Efficiency (%) Efficiency vs. Load Current 100 80 VVDD=5V 70 60 80 70 VVDD=5V VVDD=3.3V 60 VOUT=3.3V VOUT=1.8V 50 50 0 1 2 Load Current, IOUT(A) 3 0 Efficiency vs. Load Current 1 2 Load Current, IOUT(A) 3 Output Voltage vs. Load Current 100 1.9 1.88 Output Voltage, VOUT(V) Efficiency (%) 90 80 70 VVDD=5V VVDD=3.3V 60 1.86 1.84 1.82 1.8 1.78 1.76 1.74 1.72 VOUT=1.05V 1.7 50 0 1 2 Load Current, IOUT(A) 0 3 1 1.5 2 Load Current, IOUT(A) 2.5 3 Supply Voltage vs. MOSFET On Supply Voltage vs. P-FET Current Limit Resistance 100 MOSFET On Resistance, RON(mΩ) 6 P-FET Current Limit, ILIM(A) 0.5 5 4 3 2 1 90 80 70 60 50 40 P-FET 30 N-FET 20 10 0 0 2 3 4 5 Supply Voltage, VVDD(V) Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 2 6 5 3 4 5 Supply Voltage, VVDD(V) 6 www.anpec.com.tw APW8804 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. Shutdown Enable without Loading 1 VEN VEN 1 2 2 VPOK , 5V/Div VPOK , 5V/Div VOUT , 1V/Div, DC 3 3 4 VOUT , 1V/Div, DC 4 IL , 1A/Div IL , 1A/Div TIME: 200µs/Div TIME: 200µs/Div Enable with 1.8A Loading 1 Shutdown VEN VEN VPOK , 5V/Div 1 2 2 VPOK , 5V/Div VOUT , 1V/Div, DC VOUT , 1V/Div, DC 3 3 IL , 1A/Div 4 4 IL , 1A/Div TIME: 200µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 TIME: 200µs/Div 6 www.anpec.com.tw APW8804 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. Load Transient Response Load Transient Response 1.5A 2.5A 1A IOUT , 1A/Div 10mA IOUT , 1A/Div 1 1 2 2 VOUT , 100mV/Div, AC VOUT , 100mV/Div, AC TIME: 20µs/Div TIME: 50µs/Div Over Voltage Protection Normal Operating Waveform VLX , 5V/Div 1 VPOK , 5V/Div 1 VOUT , 20mV/Div, DC VOUT , 1V/Div, DC 2 2 3 IL , 1A/Div IL , 1A/Div 3 TIME: 20µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 TIME: 1µs/Div 7 www.anpec.com.tw APW8804 Pin Description PIN FUNCTION NO. NAME TDFN3X3-10 SOP-8P 1 - NC No Connection. 2,3 1,2 LX Power Switching Output. LX is the Junction of the high-side and low-side Power MOSFETs to supply power to the output LC filter. 4 3 POK Power Good Output. This pin is open-drain logic output that is pulled to the ground when the output voltage is out of regulation point. 5 4 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. 6 5 FB Output Feedback Input. The APW8804 senses the feedback voltage via FB and regulates the voltage at 0.6V. Connecting FB with a resistor-divider from the converter’s output sets the output voltage. 7 - NC No connection. 8 7 VDD Signal Input. VDD supplies the control circuitry, gate drivers. Connecting a ceramic bypass capacitor from VDD to GND to eliminate switching noise and voltage ripple on the input to the IC. 9,10 8 PVDD Power Input. PVDD supplies the step-down converter switches. Connecting a ceramic bypass capacitor from PVDD to GND to eliminate switching noise and voltage ripple on the input to the IC. 11 9 - 6 GND Ground and Exposed pad. Connect the exposed pad to the system ground plan (Exposed Pad) with large copper area for dissipating heat into the ambient air. GND Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 Ground. Power and signal ground. 8 www.anpec.com.tw APW8804 Block Diagram PVDD VDD Current Sense Amplifier LOC Over Temperature Protection Power-OnReset Current Limit Zero Crossing Comparator POR 125%VREF OTP OVP Fault Logics 50%VREF UVP Inhibit 125%VREF Gate Control LX POK 90%VREF Current Compartor Error Amplifier FB Gate Driver Gate Gm Soft-start VREF 0.6V Slope Compensation Oscillator Shutdown EN LOC Current Sense Amplifier GND POK Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 9 www.anpec.com.tw APW8804 Typical Application Circuit L1 1µH VIN 5V PVDD R3 100k CIN 22µF LX C1 (option) VDD VOUT 1.8V/3A R1 24k FB APW8804 R2 12k POK ON GND EN OFF L1 1µH VIN 2~6V PVDD C1 (option) VDD CVDD 1µF R3 100k APW8804 ON Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 R1 10k FB COUT 22µFx2 R2 15k POK OFF VOUT 1V/3A LX CIN 22µF VDD 2.6~6V COUT 22µFx2 GND EN 10 www.anpec.com.tw APW8804 Function Description VDD and PVDD Power-On-Reset (POR) with a 50oC hysteresis to lower the average TJ during The APW8804 keeps monitoring the voltage on VDD and PVDD pins to prevent wrong logic operations which may continuous thermal overload conditions, increasing lifetime of the APW8804. occur when VDD or PVDD voltage is not high enough for internal control circuitry to operate. The VDD POR rising Current-Limit Protection The APW8804 monitors the output current, flows through the high-side and low-side power MOSFETs, and limits threshold is 2.4V (typical) with 0.2V hysteresis and PVDD POR rising threshold is 1.7V with 0.2V hysteresis. the current peak at current-limit level to prevent the IC from damaging during overload, short-circuit and over- During start-up, the VDD and PVDD voltage must exceed the enable voltage threshold. Then, the IC starts a start- voltage conditions. Typical high side power MOSFET current limit is 4.5A, and low side MOSFET current limit is up process and ramps up the output voltage to the voltage target. 1.9A. Output Under-Voltage Protection (UVP) Soft-Start In the operational process, if a short-circuit occurs, the output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the re- The APW8804 has a built-in soft-start to control the rise rate of the output voltage and limit the input current surge quired regulation range. The under-voltage continually monitors the FB voltage after soft-start is completed. If a during start-up. During soft-start, an internal voltage ramp connected to one of the positive inputs of the error load step is strong enough to pull the output voltage lower than the under-voltage threshold, the IC starts soft-stop amplifier, rises up to replace the reference voltage (0.6V) until the voltage ramp reaches the reference voltage. Dur- function and shuts down converter’s output. ing soft-start without output over-voltage, the APW8804 converter’s sinking capability is disabled until the output The under-voltage threshold is 50% of the nominal output voltage. The under-voltage comparator has a built-in voltage reaches the voltage target. 3µs noise filter to prevent the chips from wrong UVP shutdown being caused by noise. APW8804 will be latched Soft-Stop after under-voltage protection. At the moment of shutdown controlled by EN signal, under-voltage event or over-voltage event, the APW8804 ini- Over-Voltage Protection (OVP) tiates a soft-stop process to discharge the output voltage in the output capacitors. Certainly, the load current also The over-voltage function monitors the output voltage by discharges the output voltage. During soft-stop, the internal voltage ramp (VRAMP) falls down to replace the refer- FB pin. When the FB voltage increases over 125% of the reference voltage due to the high-side MOSFET failure or ence voltage. The low side MOSFET turns on each cycle to discharge the output voltage. Therefore, the output volt- for other reasons, the over-voltage protection comparator will trigger soft-stop function and shutdown the converter output. age falls down slowly at the light load. After the soft-stop interval elapses, the soft-stop process ends and the IC Over-Temperature Protection (OTP) turns off. The over-temperature circuit limits the junction temperature of the APW8804. When the junction temperature ex- Enable and Shutdown Driving EN to ground places the APW8804 in shutdown. ceeds TJ=+160oC, a thermal sensor turns off the both power MOSFETs, allowing the devices to cool. The ther- In shutdown mode, the internal N-Channel power MOSFET turns off, all internal circuitry shuts down and mal sensor allows the converters to start a start-up process and to regulate the output voltage again after the the quiescent supply current reduces to less than 1µA. junction temperature cools by 50oC. The OTP is designed Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 11 www.anpec.com.tw APW8804 Function Description (Cont.) Powr Good Indicator POK is actively held low in shutdown and soft-start status. In the soft-start process, the POK is an open-drain. When the soft-start is finished, the POK is released. In normal operation, the POK window is from 90% to 125% of the converter reference voltage. When the output voltage has to stay within this window, POK signal will become high. When the output voltage outruns 90% or 125% of the target voltage, POK signal will be pulled low immediately. In order to prevent false POK drop, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 12 www.anpec.com.tw APW8804 Application Information shown in “Typical Application Circuits”. A suggestion of maximum value of R2 is 20kΩ to keep the minimum cur- Input Capacitor Selection Because buck converters have a pulsating input current, a low ESR input capacitor is required. This results in the rent that provides enough noise rejection ability through the resistor divider. The output voltage can be calculated best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. as below: R1 R1 VOUT = VREF ⋅ 1 + = 0.6 ⋅ 1 + R2 R2 Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For good input voltage filtering, usually a 22µF input capacitor is sufficient. It can be increased without any limit for better VOUT input-voltage filtering. Ceramic capacitors show better performance because of the low ESR value, and they are R1≤80kΩ less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input capacitor as FB R2 ≤ 20kΩ APW8804 close as possible to the input and GND pin of the device for better performance. GND Inductor Selection Output Capacitor Selection For high efficiencies, the inductor should have a low DC The current-mode control scheme of the APW8804 allows the use of tiny ceramic capacitors. The higher ca- resistance to minimize conduction losses. Especially at high-switching frequencies, the core material has a pacitor value provides the good load transients response. Ceramic capacitors with low ESR values have the lowest higher impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher output voltage ripple and are recommended. If required, tantalum capacitors may be used as well. The output inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value de- ripple is the sum of the voltages across the ESR and the ideal output capacitor. termines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient ∆VOUT response. A reasonable starting point for setting ripple current, ∆IL, is 40% of maximum output current. The rec- V VOUT ⋅ 1 − OUT VIN ≅ FSW ⋅ L 1 ⋅ ESR + ⋅ 8 F SW ⋅ COUT When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These ommended inductor value can be calculated as below: dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. V VOUT 1 − OUT VIN L≥ FSW ⋅ ∆IL IL(MAX) = IOUT(MAX) + 1/2 x ∆IL VIN IIN To avoid the saturation of the inductor, the inductor should be rated at least for the maximum output current of the IP-FET IL converter plus the inductor ripple current. CIN IOUT P-FET VOUT SW Output Voltage Setting N-FET In the adjustable version, the output voltage is set by a resistive divider. The external resistive divider is con- ESR COUT nected to the output, allowing remote voltage sensing as Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 13 www.anpec.com.tw APW8804 Application Information (Cont.) Output Capacitor Selection (Cont.) CIN ILIM VDD IL LX IPEAK L1 ∆IL IOUT VOUT GND IP-FET R1 R2 COUT Via To VOUT TDFN3x3-10 CIN VDD Layout Consideration LX For all switching power supplies, the layout is an important step in the design; especially at high peak currents L1 and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. VOUT GND COUT Via To VOUT with short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GND to capacitor less than 2mm respectively is recommended. R1 R2 1. The input capacitor should be placed close to the PVDD and GND. Connecting the capacitor and PVDD/GND SOP-8P APW8804 Layout Consideration 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the LX pin to minimize the noise coupling into other circuits. 3. The output capacitor should be place closed to LX and GND. 4. Since the feedback pin and network is a high impedance circuit the feedback network should be routed away from the inductor. The feedback pin and feedback network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. 5. A star ground connection or ground plane minimizes ground shifts and noise is recommended. Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 14 www.anpec.com.tw APW8804 Application Information (Cont.) 0.6 7 6 5 1.8 8 ThermalVia diameter 12mil X 5 0.75 Ground plane for ThermalPAD 0.275 0.3 2.70 5.3 2.95 3.45 0.5 1 2 1.25 3 4 1.75 TDFN3x3-10 Unit : mm Unit: mm APW8804 Recommended Footprint Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 15 www.anpec.com.tw APW8804 Package Information SOP-8P D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE θ L VIEW A S Y M B O L SOP-8P INCHES MILLIMETERS MAX. MIN. A MIN. MAX. 1.60 A1 0.00 A2 1.25 b 0.31 0.063 0.000 0.15 0.006 0.049 0.51 0.012 0.020 0.010 c 0.17 0.25 0.007 D 4.80 5.00 0.189 0.197 D1 2.50 3.50 0.098 0.138 0.244 E 5.80 6.20 0.228 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 0.118 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0o C 8o C 0 0oC 8oC Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 16 www.anpec.com.tw APW8804 Package Information TDFN3x3-10 A b E D Pin 1 A1 D2 A3 L E2 Pin 1 Corner e S Y M B O L TDFN3x3-10 MILLIMETERS MAX. 0.80 0.028 0.031 0.05 0.000 0.002 0.007 MAX. A 0.70 A1 0.00 A3 INCHES MIN. MIN. 0.20 REF 0.008 REF 0.012 b 0.18 0.30 D 2.90 3.10 0.114 0.122 0.087 0.106 D2 2.20 2.70 E 2.90 3.10 0.114 0.122 1.75 0.055 0.069 E2 1.40 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.012 0.50 0.020 0.008 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 17 www.anpec.com.tw APW8804 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-8P Application TDFN3x3-10 A H T1 C d D 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 W E1 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 W E1 F 12.0±0.30 1.75±0.10 F 5.5±0.05 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 A H T1 C d D 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 12.0±0.30 1.75±0.10 5.5±0.05 (mm) Devices Per Unit Package Type SOP-8P TDFN3x3-10 Unit Tape & Reel Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 Quantity 2500 3000 18 www.anpec.com.tw APW8804 Taping Direction Information SOP-8P USER DIRECTION OF FEED TDFN3x3-10 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 19 www.anpec.com.tw APW8804 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 20 www.anpec.com.tw APW8804 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Dec., 2012 21 www.anpec.com.tw