TECHNICAL NOTE High-performance Regulator IC Series for PCs Ultra Low Dropout Linear Regulators for PC BD3550HFN, BD3551HFN, BD3552HFN (0.5～2.0A) ● Description BD3550HFN,BD3551HFN,BD3552HFN ultra low-dropout linear chipset regulator operates from a very low input supply, and offers ideal performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to minimize the input-to-output voltage differential to the ON resistance (RON=100mΩ <BD3552HFN>) level. By lowering the dropout voltage in this way, the regulator realizes high current output (Iomax=2.0A <BD3552HFN>) with reduced conversion loss, and thereby obviates the switching regulator and its power transistor, choke coil, and rectifier diode. Thus, BD3550HFN,BD3551HFN,BD3552HFN is designed to enable significant package profile downsizing and cost reduction. An external resistor allows the entire range of output voltage configurations between 0.65 and 2.7V, while the NRCS (soft start) function enables a controlled output voltage ramp-up, which can be programmed to whatever power supply sequence is required. ● Features 1) Internal high-precision reference voltage circuit(0.65V±1%) 2) Built-in VCC undervoltage lockout circuit 3) NRCS (soft start) function reduces the magnitude of in-rush current 4) Internal Nch MOSFET driver offers low ON resistance (100mΩ <BD3552HFN typ>) 5) Built-in current limit circuit 6) Built-in thermal shutdown (TSD) circuit 7) Variable output (0.65～2.7V) 8) Small package HSON8 : 2.9×3×0.6(mm) 9) Tracking function ● Applications Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances ● Line-up It is available to select power supply voltage and maximum output voltage. Maximum Output Voltage 0.5A 1.0A 2.0A Package HSON8 Vcc=5V BD3550HFN BD3551HFN BD3552HFN Oct. 2008 ●Absolute maximum ratings ◎BD3550HFN,BD3551HFN,BD3552HFN Parameter Input Voltage 1 Input Voltage 2 Enable Input Voltage Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Symbol BD3550HFN VCC VIN Ven Pd1 Pd2 Pd3 Topr Tstg Tjmax Limit BD3551HFN +6.0 *1 +6.0 *1 -0.3～+6.0 0.63 *2 1.35 *3 1.75 *4 -10～+100 -55～+150 +150 BD3552HFN *1 Should not exceed Pd. *2 Reduced by 5.04mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer) On less than 0.2% (percentage occupied by copper foil. *3 Reduced by 10.8mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer) On less than 7.0% (percentage occupied by copper foil. *4 Reduced by 14.0mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer) On less than 65.0% (percentage occupied by copper foil. 2/16 Unit V V V W W W ℃ ℃ ℃ ◎BD3550HFN,BD3551HFN,BD3552HFN ●Operating Voltage(Ta=25℃) Parameter Input Voltage 1 Input Voltage 2 Output Voltage Setting Range Enable Input Voltage NRCS Capacity Symbol VCC VIN Vo Ven CNRCS Min. 4.3 0.95 VFB 0 0.001 Max. 5.5 VCC-1 *5 2.7 5.5 1 Unit V V V V μF *5 VCC and VIN do not have to be implemented in the order listed. ★This product is not designed for use in radioactive environments. ●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=5V, Ven=3V, VIN=1.8V, R1=3.9KΩ, R2=3.3KΩ) Limit Parameter Symbol Unit Condition Min. Typ. Max. Bias Current ICC 0.5 1.0 mA VCC Shutdown Mode Current IST 0 10 uA Ven=0V Output Voltage VOUT 1.200 V Output Voltage Temperature Coefficient Feedback Voltage 1 Feedback Voltage 2 Tcvo - 0.01 - %/℃ VFB1 VFB2 0.643 0.637 0.650 0.650 0.657 0.663 V V Load Regulation Reg.L - 0.5 10 mV Line Regulation 1 Line Regulation 2 Standby Discharge Current [ENABLE] Enable Pin Input Voltage High Enable Pin Input Voltage Low Enable Input Bias Current [FEEDBACK] Feedback Pin Bias Current [NRCS] NRCS Charge Current NRCS Standby Voltage [UVLO] VCC Undervoltage Lockout Threshold Voltage VCC Undervoltage Lockout Hysteresis Voltage [AMP] Reg.l1 Reg.l2 Iden 1 0.1 0.1 - 0.5 0.5 - %/V %/V mA Enhi 2 - - V Enlow 0 - 0.8 V Ien - 7 10 μA IFB -100 0 100 nA Inrcs VSTB 14 - 20 0 26 50 μA mV VccUVLO 3.5 3.8 4.1 V Vcchys 100 160 220 mV Vcc:Sweep-down IGSO IGSI Io Io Io dVo dvo dVo 0.5 1.0 2.0 - 1.6 4.7 200 200 200 300 300 300 mA mA A A A mV mV mV VFB=0, VGATE=2.5V VFB=VCC, VGATE=2.5V Gate Source Current Gate Sink Current Maximum output current BD3550HFN BD3551HFN BD3552HFN Minimum dropout voltage BD3550HFN BD3551HFN BD3552HFN 3/16 Tj=-10 to 100℃ Io=0 to 1A (BD3550HFN Io=0A to 0.5A) VCC=4.3V to 5.5V VIN=1.2V to 3.3V Ven=0V, Vo=1V Ven=3V Vnrcs=0.5V Ven=0V Vcc:Sweep-up Io=0.5A, VIN=1.2V, Ta=-10 to 100℃ Io=1.0A, VIN=1.2V, Ta=-10 to 100℃ Io=2.0A, VIN=1.2V, Ta=-10 to 100℃ ●Reference Data(BD3550HFN) Vo Vo Vo 50mV/div 50mV/div 50mV/div Io Io Io 0.5A/div 0.5A/div 0.5A Io=0A→1A/μsec t(10μsec/div) Vo Vo 50mV/div Io Io 0.5A t(10μsec/div) t(100μsec/div) Vo 33mV Io 0.5A 0.5A/div Io=1A→0A/μsec t(100μsec/div) 0.5A Io=1A→0A/μsec Fig.5 Transient Response (0.5→0A) Co=47μF, Cfb=1000pF Fig.4 Transient Response (0.5→0A) Co=100μF, Cfb=1000pF t(10μsec/div) Fig.3 Transient Response (0→0.5A) Co=22μF, Cfb=1000pF 50mV/div 23mV 0.5A/div Io=1A→0A/μsec 0.5A Io=0A→1A/μsec Fig.2 Transient Response (0→0.5A) Co=47μF, Cfb=1000pF 50mV/div 14mV 0.5A/div 0.5A Io=0A→1A/μsec Fig.1 Transient Response (0→0.5A) Co=100μF, Cfb=1000pF 0.5A/div 40mV 22mV 26mV t(100μsec/div) Fig.6 Transient Response (0.5→0A) Co=22μF, Cfb=1000pF ●Reference Data(BD3551HFN) Vo Vo Vo 50mV/div 50mV/div 50mV/div 46mV 35mV Io Io 1.0A 1.0A/div t(10μsec/div) Io=0A→1A/μsec 50mV/div 36mV Fig.7 Transient Response (1.0→ 0A) 1.0A Co=100μF, Cfb=1000pF Io=1A→0A/μsec t(100μsec/div) Fig.10 Transient Response (1.0→0A) Co=100μF, Cfb=1000pF Io=0A→1A/μsec Io 1.0A/div t(10μsec/div) Fig.9 Transient Response (0→1.0A) Co=22μF, Cfb=1000pF Vo 46mV 50mV/div Io=0A→1A/μsec Io t(10μsec/div) Vo Vo 1.0A 1.0A/div Fig.8 Transient Response (0→1.0A) Co=47μF, Cfb=1000pF Fig.7 Transient Response (0→1.0A) Co=100μF, Cfb=1000pF 1.0A/div Io 1.0A 1.0A/div Io=0A→1A/μsec 50mV/div 55mV t(10μsec/div) Fig.8 Transient Response (0→ 1.0A) 1.0A Co 47μF Cfb 1000pF Io=1A→0A/μsec t(100μsec/div) Fig.11 Transient Response (1.0→0A) Co=47μF, Cfb=1000pF 4/16 56mV Io=0A→1A/μsec Io t(10μsec/div) Fig.9 Transient Response (0→ 1.0A) 1.0A 1.0A/div Io=1A→0A/μsec t(100μsec/div) Fig.12 Transient Response (1.0→0A) Co=22μF, Cfb=1000pF ●Reference Data(BD3552HFN) Vo Vo Vo 50mV/div 50mV/div 50mV/div 26mV 89mV Io Io 2.0A 2.0A/div Io=0A→1A/μsec Io=0A→1A/μsec t(10μsec/div) Vo t(10μsec/div) 2.0A 2.0A/div 83mV t(100μsec/div) 117mV Io 2.0A/div 2.0A Io=1A→0A/μsec Fig.16 Transient Response (2.0→0A) Co=100μF, Cfb=1000pF t(10μsec/div) Fig.15 Transient Response (0→2.0A) Co=22μF, Cfb=1000pF 50mV/div Io Io=1A→0A/μsec Io=0A→1A/μsec Vo Vo 50mV/div 2.0A 2.0A/div Fig.14 Transient Response (0→2.0A) Co=47μF, Cfb=1000pF 54mV Io 2.0A/div Io 2.0A 2.0A/div Fig.13 Transient Response (0→2.0A) Co=100μF, Cfb=1000pF 50mV/div 117mV t(100μsec/div) 2.0A Io=1A→0A/μsec t(100μsec/div) Fig.18 Transient Response (2.0→0A) Co=22μF, Cfb=1000pF Fig.17 Transient Response (2.0→0A) Co=47μF, Cfb=1000pF ●Reference Data(BD3551HFN) Ven Ven 2V/div 2V/div VNRCS VNRCS 2V/div 2V/div Vo Vo 1V/div 1V/div VCC Ven VIN Vo t(2msec/div) t(200μsec/div) Fig.19 Waveform at output start VCC→VIN→Ven Fig.20 Waveform at output OFF Fig.21 Input sequence VCC VCC VCC Ven Ven Ven VIN VIN VIN Vo Vo Vo VIN→VCC→Ven Fig.22 Input sequence Ven→VCC→VIN Fig.23 Input sequence 5/16 VCC→Ven→VIN Fig.24 Input sequence ●Reference Data(BD3551HFN) 1.25 VCC Ven Ven VIN VIN 1.23 Vo(V) VCC 1.21 1.19 1.17 Vo Vo 1.15 VIN→Ven→VCC -10 Ven→VIN→VCC Fig.26 Input sequence Fig.25 Input sequence 0.80 30 50 Ta(℃) 70 90 100 Fig.27 Ta-Vo (Io=0mA) 2.0 1.2 1.9 0.75 1.0 0.70 0.65 1.8 1.7 0.55 0.50 IIN(mA) 0.8 0.60 ICC(uA) ICC(mA) 10 0.6 0.4 0.45 0.40 1.6 1.5 1.4 1.3 1.2 0.2 1.1 0.35 1.0 0.0 0.30 -10 10 30 50 Ta(℃) 70 90 100 -60 -30 0 30 60 Ta(℃) 90 120 -10 150 10 Fig.29 Ta-ISTB Fig.28 Ta-ICC 30 50 Ta(℃) 70 90 100 Fig.30 Ta-IIN 25 20 24 15 23 25 30 10 22 15 10 21 IFB(nA) INRCS(uA) IIN(uA) 20 20 19 5 0 -5 18 -10 17 5 -15 16 15 0 -60 -30 0 30 60 Ta(℃) 90 120 -20 -10 150 10 Fig.31 Ta-IINSTB 30 50 Ta(℃) 70 90 100 -10 Fig.32 Ta-INRCS 10 10 30 50 Ta(℃) 70 90 100 Fig.33 Ta-IFB 150 150 140 140 130 130 8 RON(mΩ) Ien(uA) 7 6 5 4 3 2 RON(mΩ) 9 120 120 110 110 100 100 1 90 90 0 -10 10 30 50 Ta(℃) 70 Fig.34 Ta-Ien 90 100 -10 10 30 50 Ta(℃) 70 Fig.35 Ta-RON (VCC=5V/Vo=1.2V) 6/16 90 100 2 4 6 Vcc(V) Fig.36 VCC-RON 8 ●Block Diagram VCC VCC VCC UVLO EN Reference Block VIN Current Limit CL VIN VCC Vo VO CL UVLO TSD EN FB Thermal Shutdown GATE NRCS TSD NRCS GND ●Pin Layout PIN No. 1 2 3 4 5 6 7 8 reverse PIN name VCC EN GATE VIN VO FB NRCS GND FIN PIN Function Power supply pin Enable input pin Gate pin Input voltage pin Output voltage pin Reference voltage feedback pin In-rush current protection (NRCS) capacitor connection pin Ground pin Connected to heatsink and GND ●Pin Function Table ◎HSON8 2.90±0.2 1 2 3 4 1PIN MARK (0.2) 5 6 7 8 (1.8) BD3 55X Lot No. (0.2) 0.6Max. 3.00±0.2 2.80±0.2 8 7 6 5 (0.30) (0.15) (0.45) (2.2) (0.05) 0.475 0.13 +0.1 −0.05 4 3 2 1 0.32±0.10 0.65 (Unit : mm) 7/16 ●Operation of Each Block ・AMP This is an error amp that compares the reference voltage (0.65V) with Vo to drive the output Nch FET (Ron=100m Ω:BD3552HFN). Frequency optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the output. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN is OFF, or when UVLO is active, output goes LOW and the output of the NchFET switches OFF. ・EN The EN block controls the regulator’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is maintained at 0μA, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the NRCS pin Vo, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no electrical connection is required (e.g., between the VCC pin and the ESD prevention Diode), module operation is independent of the input sequence. ・UVLO To prevent malfunctions that can occur during a momentary decrease in VCC, the UVLO circuit switches the output OFF, and (like the EN block) discharges NRCS and Vo. Once the UVLO threshold voltage (TYP3.80V) is reached, the power-on reset is triggered and output continues. ・CURRENT LIMIT When output is ON, the current limit function monitors the internal IC output current against the parameter value (2.0A or more:BD3552HFN). When current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent state is eliminated, output voltage is restored to the parameter value. ・NRCS (Non Rush Current on Start-up) The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up can be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as a 20 μA (TYP) constant current source to charge the external capacitor. Output start time is calculated via formula (1) below. t=C 0.65V 20μA ・・・(1) Tracking sequence is available by connecting the output voltage of external power supply instead of external capacitor. And then, ratio-metric sequence is also available by changing the resistor division ratio of external power supply output voltage. (See the next page) ・TSD (Thermal Shut down) The shutdown (TSD) circuit automatically switches output OFF when the chip temperature gets too high, thus serving to protect the IC against “thermal runaway” and heat damage. Because the TSD circuit is provided to shut down the IC in the presence of extreme heat, in order to avoid potential problems with the TSD, it is crucial that the Tj (max) parameter not be exceeded in the thermal design. ・VIN The VIN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical connection (such as between the VCC pin and the ESD protection Diode) is necessary, VIN operates independent of the input sequence. However, since an output NchFET body Diode exists between VIN and Vo, a VIN-Vo electric (Diode) connection is present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to VIN from Vo. 8/16 ●Timing Chart EN ON/OFF VIN VCC EN 0.65V(typ) NRCS Startup Vo t VCC ON/OFF VIN UVLO Hysteresis VCC EN 0.65V(typ) NRCS Startup Vo t Tracking sequence 1.8V Output 1.2V Output DC/DC (R1=3.9kΩ, R2=3.3kΩ) NRCS Vo 1.8V Tracking sequence V0 R2 R1 1.8V 1.2V 3.3kΩ FB 3.9kΩ 1.2V Ratio-metric sequence 9/16 ●Evaluation Board ■ BD3550HFN,BD3551HFN,BD3552HFN Evaluation Board Schematic VCC GND_S 1 8 GND VCC VCC C1 SW1 R8 GND EN C12 GND 2 GND U1 BD355XHFN (HSON8) 7 NRCS C10 GND 3 6 R1 GND FB GND C11 GATE R4 C13 R2 VIN_S 4 Vo_S 5 GND Vo VIN C4 GND GND C2 C3 C7 GND GND C6 C5 GND GND R3 C8 R5 GND C9 GND 7568 4 U2 GND VCC 321 TP2 R6 TP1 R7 JPF1 GND GND GND GND JPF2 5 2 GND U3 4 3 R9 C14 ■ BD3550HFN,BD3551HFN,BD3552HFN Evaluation Board Standard Component List Component Rating Manufacturer Product Name Component Rating Manufacturer Product Name U1 - ROHM BD355XHFN C2 22uF KYOCERA CM32X5R226M10A C1 1uF MURATA GRM188B11A105KD C13 1000pF MURATA GRM188B11H102KD C10 0.01uF MURATA GRM188B11H103KD R1 3.9kΩ ROHM MCR03EZPF3301 R8 0Ω - Jumper R2 3.3kΩ ROHM MCR03EZPF3901 C5 22uF KYOCERA CM32X5R226M10A ■ BD3550HFN,BD3551HFN,BD3552HFN Evaluation Board Layout (2nd layer and 3rd layer is GND Line.) Silkscreen TOP Layer 10/16 Bottom Layer ●Recommended Circuit Example VCC EN C1 R4 1 8 2 7 3 6 GND C4 R1 FB 4 5 R2 C5 VOUT1(1.2V) VIN R1/R2 Recommended Value 3.9k/3.3k C3 22μF C1 1μF C2 22μF C4 0.01μF C5 - R4 Several kΩ ～several 10kΩ Component C3 C2 Programming Notes and Precautions IC output voltage can be set with a configuration formula using the values for the internal reference output voltage (VFB)and the output voltage resistors (R1, R2). Select resistance values that will avoid the impact of the VREF current (±100nA). The recommended total resistance value is 10KΩ. To assure output voltage stability, please be certain the Vo1, Vo2, and Vo3 pins and the GND pins are connected. Output capacitors play a role in loop gain phase compensation and in mitigating output fluctuation during rapid changes in load level. Insufficient capacitance may cause oscillation, while high equivalent series reisistance (ESR) will exacerbate output voltage fluctuation under rapid load change conditions. While a 22μF ceramic capacitor is recomended, actual stability is highly dependent on temperature and load conditions. Also, note that connecting different types of capacitors in series may result in insufficient total phase compensation, thus causing oscillation. In light of this information, please confirm operation across a variety of temperature and load conditions. Input capacitors reduce the output impedance of the voltage supply source connected to the (VCC) input pins. If the impedance of this power supply were to increase, input voltage (VCC) could become unstable, leading to oscillation or lowered ripple rejection function. While a low-ESR 1 μ F capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. In light of this information, please confirm operation across a variety of temperature and load conditions. Input capacitors reduce the output impedance of the voltage supply source connected to the (VIN) input pins. If the impedance of this power supply were to increase, input voltage (VIN) could become unstable, leading to oscillation or lowered ripple rejection function. While a low-ESR 22 μ F capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. In light of this information, please confirm operation across a variety of temperature and load conditions. The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush current from going through the load (VIN to VO) and impacting output capacitors at power supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the UVLO function is deactivated. The temporary reference voltage is proportionate to time, due to the current charge of the NRCS pin capacitor, and output voltage start-up is proportionate to this reference voltage. Capacitors with low susceptibility to temperature are recommended, in order to assure a stable soft-start time. This component is employed when the C3 capacitor causes, or may cause, oscillation. It provides more precise internal phase correction. It is recommended that a resistance (several kΩ to several 10kΩ) be put in R4, in case negative voltage is applied in EN pin. 11/16 ●Heat Loss Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed temperature limits, and thermal design should allow sufficient margin from the limits. 1. Ambient temperature Ta can be no higher than 100℃. 2. Chip junction temperature (Tj) can be no higher than 150℃. Chip junction temperature can be determined as follows: ① Calculation based on ambient temperature (Ta) Tj=Ta+θj-a×W ＜Reference values＞ θj-a:HSON8 198.4℃/W 1-layer substrate (copper foil density 0.2%) 92.4℃/W 1-layer substrate (copper foil density 7%) 71.4℃/W 2-layer substrate (copper foil density 65%) 3 Substrate size: 70×70×1.6mm (substrate with thermal via) It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in the inner layer (in using multiplayer substrate). This package is so small (size: 2.9mm×3.0mm) that it is not available to layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below). enable to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and the number is designed suitable for the actual situation.). Most of the heat loss that occurs in BD3550HFN,BD3551HFN,BD3552HFN is generated from the output Nch FET. Power loss is determined by the total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in BD3550HFN,BD3551HFN,BD3552HFN) make certain to factor conditions such as substrate size into the thermal design. Power consumption (W) = Input voltage (VIN)- Output voltage (Vo) (Vo≒VREF) ×Io(Ave) Example) Where VIN=1.8V, VO=1.2V, Io(Ave) = 1A, Power consumption (W) = 1.8(V)-1.2(V) ×1.0(A) = 0.6(W) 12/16 ●Input-Output Equivalent Circuit Diagram VCC VCC 1kΩ NRCS 1kΩ 1kΩ VIN 1kΩ 1kΩ 10kΩ 10kΩ 1kΩ VCC VCC 1kΩ VFB 1kΩ EN VO1 350kΩ 100kΩ VO2 1kΩ 50kΩ 100kΩ 10kΩ 20pF ●Reference landing pattern MIE b2 D3 e E3 L2 (Unit:mm) Lead pitch Lead pitch landing length landing pitch e 0.65 central pad length MIE 2.50 central pad pitch ≧l2 0.40 b2 0.35 D3 2.90 E3 1.90 *It is recommended to design suitable for the actual application. 13/16 ●Operation Notes 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. 3. Power supply lines Please add a protection diode when a large inductance component is connected to the output terminal, and reverse-polarity power is possible at startup or in output OFF condition. (Example) OUTPUT PIN 4. GND voltage The potential of GND pin must be minimum potential in all operating conditions. 5. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 6. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 7. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 8. ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 9. Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. TSD on temperature [°C] Hysteresis temperature [°C] (typ.) (typ.) BD3550HFN,BD3551HFN,BD3552HFN 175 15 10. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 14/16 11. Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used. Resistor Transistor (NPN) Pin A Pin B C Pin B B E Pin A N N N P+ P+ P Parasitic element N P+ P P substrate N C E Parasitic element P substrate GND Parasitic element B N P+ Parasitic element GND GND GND Other adjacent elements 12. Ground Wiring Pattern. When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. ●Heat Dissipation Characteristics ◎HSON8 [W] Power Dissipation [Pd] 2.0 (3) 1.75W 1.5 (1) Substrate (copper foil density: 0.2%…1-layer) θj-a=198.4℃/W (2) Substrate (copper foil density: 7%…1-layer) θj-a=92.4℃/W (3) Substrate (copper foil density: 65%…1-layer) θj-a=71.4℃/W (2) 1.35W 1.0 (1) 0.63W 0.5 0 0 25 50 75 100 Ambient Temperature [Ta] 125 150 [℃] 15/16 ●Type Designations (Ordering Information) B D 3 5 5 X H F N Package Type Product Name ・BD355X T - R TR Emboss tape reel opposite draw-out side: 1 pin ・HFN : HSON8 HSON8 <Dimension> <Tape and Reel information> 2.90±0.2 (1.8) 5 6 7 8 1 2 3 4 4 3 2 1 (0.30) (0.15) (0.45) (2.2) (0.05) (0.2) 0.6Max. 3.00±0.2 2.80±0.2 8 7 6 5 (0.2) 0.475 Tape Embossed carrier tape Quantity 3000pcs Direction of feed TR (The direction is the 1pin of product is at the upper light when you hold reel on the left hand and you pull out the tape on the right hand) 0.13 +0.1 −0.05 0.32±0.10 X X X X X X X 0.65 X X X X X X X X X X X X X X 1Pin X X X X X X X X X X X X X X Direction of feed Reel (Unit:mm) ※When you order , please order in times the amount of package quantity. 16/16 Catalog No.08T416A '08.10 ROHM © Appendix Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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