LINER LTC2424 4-/8-channel 20-bit upower no latency adc Datasheet

Final Electrical Specifications
LTC2424/LTC2428
4-/8-Channel 20-Bit µPower
No Latency ∆ΣTM ADCs
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DESCRIPTIO
The LTC®2424/LTC2428 are 4-/8-channel 2.7V to 5.5V
micropower 20-bit A/D converters with an integrated
oscillator, 8ppm INL and 1.2ppm RMS noise. They use
delta-sigma technology and provide single cycle digital
filter settling time (no latency delay) for multiplexed
applications. The first conversion after the channel is
changed is always valid. Through a single pin the LTC2424/
LTC2428 can be configured for better than 110dB rejection at 50Hz or 60Hz ±2%, or can be driven by an external
oscillator for a user defined rejection frequency in the
range 1Hz to 800Hz. The internal oscillator requires no
external frequency setting components.
Pin Compatible 4-/8-Channel 20-Bit ADCs
8ppm INL, No Missing Codes at 20 Bits
4ppm Full-Scale Error and 0.5ppm Offset
1.2ppm Noise
Digital Filter Settles in a Single Cycle. Each
Conversion is Accurate, Even After Changing
Channels
Fast Mode: 16-Bit Noise, 12-Bit TUE at 100sps
Internal Oscillator—No External Components
Required
110dB Min, 50Hz/60Hz Notch Filter
Reference Input Voltage: 0.1V to VCC
Live Zero—Extended Input Range Accommodates
12.5% Overrange and Underrange
Single Supply 2.7V to 5.5V Operation
Low Supply Current (200µA) and Auto Shutdown
Can Be Interchanged with 24-Bit LTC2404/LTC2408
if ZSSET Pin is Grounded
The converters accept any external reference voltage from
0.1V to VCC. With their extended input conversion range of
–12.5% VREF to 112.5% VREF (VREF = FSSET – ZSSET) the
LTC2424/LTC2428 smoothly resolve the offset and
overrange problems of preceding sensors or signal conditioning circuits.
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APPLICATIO S
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The LTC2424/LTC2428 communicate through a flexible
4-wire digital interface which is compatible with SPI and
MICROWIRETM protocols.
Weight Scales
Direct Temperature Measurement
Gas Analyzers
Strain-Gage Transducers
Instrumentation
Data Acquisition
Industrial Process Control
4-Digit DVMs
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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TYPICAL APPLICATIO
Total Unadjusted Error vs Output Code
10
0.1V TO VCC
7
MUXOUT
4
ADCIN
2.7V TO 5.5V
3
2, 8
FSSET VCC
9 CH0
10 CH1
CSADC
11 CH2
ANALOG
INPUTS
–0.12VREF TO
1.12VREF
12 CH3
13 CH4*
14 CH5*
15 CH6*
17 CH7*
CSMUX
4-/8-CHANNEL
MUX
+
20-BIT
∆∑ ADC
SCK
CLK
DIN
–
SDO
23
20
25
19
GND
1, 6, 16, 18, 22, 27, 28
MPU
21
24
VCC
LTC2424/LTC2428
5 ZSSET
SERIAL DATA LINK
MICROWIRE AND
SPI COMPATABLE
FO
26
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
VCC = 5V
VREF = 5V
TA = 25°C
FO = LOW
8
1µF
LINEARITY ERROR (ppm)
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March 2000
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FEATURES
6
4
2
0
–2
–4
–6
–8
–10
24248 TA01
*THESE PINS ARE NO CONNECTS ON THE LTC2404
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
0
8,338,608
OUTPUT CODE (DECIMAL)
16,777,215
24248 TA02
1
LTC2424/LTC2428
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ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) to GND .......................– 0.3V to 7V
Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V)
Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2424C/LTC2428C .............................. 0°C to 70°C
LTC2424I/LTC2428I ........................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER
PART NUMBER
TOP VIEW
GND
1
28 GND
VCC
2
27 GND
FSSET
3
26 FO
ADCIN
4
25 SCK
ZSSET
5
24 SDO
LTC2424CG
LTC2424IG
GND
6
23 CSADC
MUXOUT
7
22 GND
VCC
8
CH0
9
ORDER
PART NUMBER
TOP VIEW
GND
1
28 GND
VCC
2
27 GND
FSSET
3
26 FO
ADCIN
4
25 SCK
ZSSET
5
24 SDO
GND
6
23 CSADC
MUXOUT
7
22 GND
21 DIN
VCC
8
21 DIN
20 CSMUX
CH0
9
20 CSMUX
CH1 10
19 CLK
CH1 10
19 CLK
CH2 11
18 GND
CH2 11
18 GND
CH3 12
17 NC
CH3 12
17 CH7
NC 13
16 GND
CH4 13
16 GND
NC 14
15 NC
CH5 14
15 CH6
G PACKAGE
28-LEAD PLASTIC SSOP
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/W
TJMAX = 125°C, θJA = 130°C/W
LTC2428CG
LTC2428IG
Consult factory for Military grade parts.
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CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, (Note 5)
●
Integral Nonlinearity
VREF = 2.5V (Note 6)
VREF = 5V (Note 6)
●
●
4
8
10
20
ppm of VREF
ppm of VREF
Integral Nonlinearity (Fast Mode)
2.5V < VREF < VCC, 100 Samples/Second, fO = 2.048MHz
●
40
250
ppm of VREF
Offset Error
2.5V ≤ VREF ≤ VCC
●
0.5
10
ppm of VREF
Offset Error (Fast Mode)
2.5V < VREF < 5V, 100 Samples/Second, fO = 2.048MHz
Offset Error Drift
2.5V ≤ VREF ≤ VCC
Full-Scale Error
2.5V ≤ VREF ≤ VCC
Full-Scale Error (Fast Mode)
2.5V < VREF < 5V, 100 Samples/Second, fO = 2.048MHz
Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC
2
MIN
TYP
MAX
20
Bits
3
ppm of VREF
0.04
●
UNITS
4
10
0.04
ppm of VREF/°C
15
ppm of VREF
ppm of VREF
ppm of VREF/°C
LTC2424/LTC2428
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CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Total Unadjusted Error
VREF = 2.5V
VREF = 5V
MIN
TYP
MAX
UNITS
Output Noise
VIN = 0V, VREF = 5V (Note 13)
6
µVRMS
Output Noise (Fast Mode)
VREF = 5V, 100 Samples/Second, fO = 2.048MHz
20
µVRMS
Normal Mode Rejection 60Hz ±2%
(Note 7)
●
110
130
dB
Normal Mode Rejection 50Hz ±2%
(Note 8)
●
110
130
dB
Power Supply Rejection, DC
VREF = 2.5V, VIN = 0V
100
dB
Power Supply Rejection, 60Hz ±2%
VREF = 2.5V, VIN = 0V, (Notes 7, 16)
110
dB
Power Supply Rejection, 50Hz ±2%
VREF = 2.5V, VIN = 0V, (Notes 8, 16)
110
dB
8
16
ppm of VREF
ppm of VREF
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A ALOG I PUT A D REFERE CE
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIN
Input Voltage Range
(Note 14)
MIN
TYP
VREF
Reference Voltage Range
CS(IN)
Input Sampling Capacitance
CS(REF)
Reference Sampling Capacitance
IIN(LEAK)
Input Leakage Current
CS = VCC
●
–100
1
IREF(LEAK)
Reference Leakage Current
VREF = 2.5V, CS = VCC
●
– 100
1
IIN(MUX)
On Channel Leakage Current
VS = 2.5V (Note 15)
●
RON
MUX On-Resistance
IOUT = 1mA, VCC = 2.7V
IOUT = 1mA, VCC = 5V
●
●
MAX
UNITS
●
– 0.125 • VREF
1.125 • VREF
V
●
0.1
VCC
V
1
pF
1.5
pF
250
120
100
nA
100
nA
±20
nA
300
250
Ω
Ω
MUX ∆RON vs Temperature
0.5
%/°C
∆RON vs VS (Note 15)
20
%
IS(OFF)
MUX Off Input Leakage
Channel Off, VS = 2.5V
●
±20
nA
ID(OFF)
MUX Off Output Leakage
Channel Off, VD = 2.5V
●
±20
nA
tOPEN
MUX Break-Before-Make Interval
tON
Enable Turn-On Time
tOFF
Enable Turn-Off Time
QIRR
MUX Off Isolation
QINJ
Charge Injection
CS(OFF)
Input Off Capacitance (MUX)
CD(OFF)
Output Off Capacitance (MUX)
290
ns
VS = 1.5V, RL = 3.4k, CL = 15pF
490
ns
VS = 1.5V, RL = 3.4k, CL = 15pF
190
ns
VIN = 2VP-P, RL = 1k, f = 100kHz
70
dB
RS = 0Ω, CL = 1000pF, VS = 1V
±1
pC
10
pF
10
pF
3
LTC2424/LTC2428
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
●
VIL
Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
●
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
●
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
●
IIN
Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC
●
IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9)
●
CIN
Digital Input Capacitance
CS, FO
CIN
Digital Input Capacitance
SCK
(Note 9)
VOH
High Level Output Voltage
SDO
IO = – 800µA
●
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
●
VOH
High Level Output Voltage
SCK
IO = – 800µA (Note 10)
●
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 10)
●
IOZ
High-Z Output Leakage
SDO
VIN HMUX
MUX High Level Input Voltage
MUX Low Level Input Voltage
VIN LMUX
MIN
MAX
UNITS
2.5
2.0
V
V
0.8
0.6
V
V
2.5
2.0
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
10
pF
10
pF
VCC – 0.5V
V
0.4V
V
VCC – 0.5V
●
–10
V + = 3V
●
2
V+
●
= 2.4V
TYP
V
0.4V
V
10
µA
V
0.8
V
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current (Pin 2)
Conversion Mode
Sleep Mode
ICC(MUX)
4
Multiplexer Supply Current (Pin 8)
CONDITIONS
MIN
●
TYP
2.7
MAX
UNITS
5.5
V
CS = 0V (Note 12)
CS = VCC (Note 12)
●
●
200
20
300
30
µA
µA
All Logic Inputs Tied Together
VIN = 0V or 5V
●
15
40
µA
LTC2424/LTC2428
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TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
fEOSC
External Oscillator Frequency Range
20-Bit Effective Resolution
12-Bit Effective Resolution
MIN
TYP
MAX
UNITS
tHEO
tLEO
tCONV
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
fESCK
External SCK Frequency Range
(Note 9)
●
tLESCK
External SCK Low Period
(Note 9)
●
250
ns
tHESCK
External SCK High Period
(Note 9)
●
250
ns
tDOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
1.23
tDOUT_ESCK
External SCK 24-Bit Data Output Time
(Note 9)
●
t1
CS ↓ to SDO Low Z
●
0
150
ns
t2
CS ↑ to SDO High Z
●
0
150
ns
t3
CS ↓ to SCK ↓
(Note 10)
●
0
150
ns
t4
CS ↓ to SCK ↑
(Note 9)
●
50
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
●
15
ns
t5
SCK Set-Up Before CS ↓
●
50
ns
t6
SCK Hold After CS ↓
●
●
●
2.56
2.56k
307.2
2.048M
kHz
Hz
External Oscillator High Period
●
0.5
390
µs
External Oscillator Low Period
●
0.5
390
µs
●
●
●
130.66
133.33
136
156.80
160
163.20
20480/fEOSC (in kHz)
19.2
fEOSC/8
45
(Note 5)
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7 to 5.5V unless otherwise specified, source input
is 0Ω. CSADC = CSMUX = CS. VREF = FSSET – ZSSET.
Note 4: Internal Conversion Clock source with the FO pin tied
to GND or to VCC or to external conversion clock source with
fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
kHz
kHz
55
%
2000
kHz
1.25
1.28
192/fEOSC (in kHz)
ms
ms
24/fESCK (in kHz)
ms
ns
200
●
ms
ms
ms
50
ns
ns
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: For reference voltage values VREF > 2.5V the extended input
of – 0.125 • VREF to 1.125 • VREF is limited by the absolute maximum
rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF ≤
0.267V + 0.89 • VCC the input voltage range is – 0.3V to 1.125 • VREF.
For 0.267V + 0.89 • VCC < VREF ≤ VCC the input voltage range is – 0.3V
to VCC + 0.3V.
Note 15: VS is the voltage applied to a channel input. VD is the voltage
applied to the MUX output.
Note 16: VCC(DC) = 4.1V, VCC(AC) = 2.8VP-P.
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LTC2424/LTC2428
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PIN FUNCTIONS
GND (Pins 1, 6, 16, 18, 22, 27, 28): Ground. Should be
connected directly to a ground plane through a minimum
length trace or it should be the single-point-ground in a
single-point grounding system.
VCC (Pins 2, 8): Positive Supply Voltage. 2.7V ≤ VCC ≤
5.5V. Bypass to GND with a 10µF tantalum capacitor in
parallel with 0.1µF ceramic capacitor as close to the part
as possible.
FSSET (Pin 3): Full-Scale Set Input. This pin defines the
full-scale input value. When VIN = FSSET, the ADC outputs
full scale (FFFFFH). The total reference voltage (VREF) is
FSSET – ZSSET.
ADCIN (Pin 4): Analog Input. The input voltage range is
– 0.125 • VREF to 1.125 • VREF. For VREF > 2.5V the input
voltage range may be limited by the pin absolute maximum rating of – 0.3V to VCC + 0.3V.
ZSSET (Pin 5): Zero-Scale Set Input. This pin defines the
zero-scale input value. When VIN = ZSSET, the ADC outputs
zero scale (00000H). For pin compatibility with the LTC2404/
LTC2408 this pin must be grounded.
MUXOUT (Pin 7): MUX Output. This pin is the output of the
multiplexer. Tie to ADCIN for normal operation.
CH0 (Pin 9): Analog Multiplexer Input.
CH1 (Pin 10): Analog Multiplexer Input.
CH2 (Pin 11): Analog Multiplexer Input.
CH3 (Pin 12): Analog Multiplexer Input.
CH4 (Pin 13): Analog Multiplexer Input. No connect on the
LTC2424.
CH5 (Pin 14): Analog Multiplexer Input. No connect on the
LTC2424.
CH6 (Pin 15): Analog Multiplexer Input. No connect on the
LTC2424.
CH7 (Pin 17): Analog Multiplexer Input. No connect on the
LTC2424.
CLK (Pin 19): Shift Clock for Data In. This clock synchronizes the serial data transfer into the MUX. For normal
operation, drive this pin in parallel with SCK.
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CSMUX (Pin 20): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.
DIN (Pin 21): Digital Data Input. The multiplexer address
is shifted into this input on the last four rising CLK edges
before CSMUX goes low.
CSADC (Pin 23): ADC Chip Select Input. A low on this pin
enables the SDO digital output and following each conversion, the ADC automatically enters the Sleep mode and
remains in this low power state as long as CSADC is high.
A high on this pin also disables the SDO digital output. A
low-to-high transition on CSADC during the Data Output
state aborts the data transfer and starts a new conversion.
For normal operation, drive this pin in parallel with CSMUX.
SDO (Pin 24): Three-State Digital Output. During the data
output period this pin is used for serial data output. When
the chip select CSADC is high (CSADC = VCC), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin can be used as a conversion status
output. The conversion status can be observed by pulling
CSADC low.
SCK (Pin 25): Shift Clock for Data Out. This clock synchronizes the serial data transfer of the ADC data output. Data
is shifted out of SDO on the falling edge of SCK. For normal
operation, drive this pin in parallel with CLK.
FO (Pin 26): Digital input which controls the ADC’s notch
frequencies and conversion time. When the FO pin is
connected to VCC (FO = VCC), the converter uses its internal
oscillator and the digital filter first null is located at 50Hz.
When the FO pin is connected to GND (FO = OV), the
converter uses its internal oscillator and the digital filter
first null is located at 60Hz. When FO is driven by an
external clock signal with a frequency fEOSC, the converter
uses this signal as its clock and the digital filter first null is
located at a frequency fEOSC/2560. The resulting output
word rate is fEOSC /20480.
LTC2424/LTC2428
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INTERNAL
OSCILLATOR
VCC
GND
AUTOCALIBRATION
AND CONTROL
8-CHANNEL MUX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
∫
∫
FO
(INT/EXT)
∫
∑
SDO
SERIAL
INTERFACE
ADC
ZSSET
SCK
CSADC
FSSET
DECIMATING FIR
CSMUX
CHANNEL
SELECT
DAC
DIN
CLK
24248 BD
TEST CIRCUITS
VCC
3.4k
SDO
3.4k
SDO
CLOAD = 20pF
CLOAD = 20pF
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
24248 TC01
24248 TC02
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Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
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APPLICATIONS INFORMATION
Converter Operation Cycle
The LTC2424/LTC2428 are low power, 4-/8-channel deltasigma analog-to-digital converters with easy-to-use
4-wire interfaces. Their operation is simple and made up
of four states. The converter operation begins with the
conversion, followed by a low power sleep state and
concluded with the data output (see Figure 1). Channel
selection may be performed while the device is in the sleep
state or at the conclusion of the data output state. The
interface consists of serial data output (SDO), serial clock
(CLK/SCK), chip select (CSADC/CSMUX) and data input
(DIN). By tying SCK to CLK and CSADC to CSMUX, the
interface requires only four wires.
Initially, the LTC2424 or LTC2428 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, power consumption
is reduced by an order of magnitude. The part remains in
the sleep state as long as CSADC is logic HIGH. The
conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
Channel selection for the next conversion cycle is performed while the device is in the sleep state or at the end
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LTC2424/LTC2428
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APPLICATIONS INFORMATION
CONVERT
CHANNEL SELECT
(SLEEP)
SLEEP
1
Conversion Clock
CSADC
AND
SCK
0
DATA OUTPUT
(CHANNEL SELECT)
24248 F01
Figure 1. LTC2428 State Transition Diagram
of the data output state. A specific channel is selected by
applying a 4-bit serial word to the DIN pin on the rising edge
of CLK while CSMUX is HIGH, see Figure 4 and Table 3. The
channel is selected based on the last four bits clocked into
the DIN pin before CSMUX goes low. If DIN is all 0’s, the
previous channel remains selected.
In the example, Figure 4, the MUX channel is selected
during the sleep state, just before the data output state
begins. Once the channel selection is complete, the device
remains in the sleep state as long as CSADC remains
HIGH.
Once CSADC is pulled low, the device begins outputting
the conversion result. There is no latency in the conversion
result. Since there is no latency, the first conversion
following a change in input channel is valid and corresponds to that channel. The data output corresponds to
the conversion just performed. This result is shifted out on
the serial data output pin (SDO) under the control of the
serial clock (SCK). Data is updated on the falling edge of
SCK allowing the user to reliably latch data on the rising
edge of SCK, see Figure 4. The data output state is
concluded once 24 bits are read out of the ADC or when
CSADC is brought HIGH. The device automatically initiates
a new conversion and the cycle repeats.
Through timing control of the CSADC and SCK pins, the
LTC2424/LTC2428 offer two modes of operation: internal
8
or external SCK. These modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
A major advantage delta-sigma converters offer over
conventional type converters is an on-chip digital filter
(commonly known as Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50 or 60Hz plus
their harmonics. In order to reject these frequencies in
excess of 110dB, a highly accurate conversion clock is
required. The LTC2424/LTC2428 incorporate an on-chip
highly accurate oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2424/
LTC2428 reject line frequencies (50 or 60Hz ±2%) a
minimum of 110dB.
Ease of Use
The LTC2424/LTC2428 data output has no latency, filter
settling or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
an analog input voltage is easy.
The LTC2424/LTC2428 perform offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage change and temperature
drift.
Power-Up Sequence
The LTC2424/LTC2428 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 2.2V. When the VCC voltage rises
above this critical threshold, the converter creates an
internal power-on-reset (POR) signal with duration of
approximately 0.5ms. The POR signal clears all internal
registers within the ADC and initiates a conversion. At
LTC2424/LTC2428
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power-up, the multiplexer channel is disabled and should
be programmed once the device enters the sleep state.
The results of the first conversion following a POR are not
valid since a multiplexer channel was disabled.
Reference Voltage Range
The LTC2424/LTC2428 can accept a reference voltage
from 0V to VCC. The converter output noise is determined
by the thermal noise of the front-end circuits, and as such,
its value in microvolts is nearly constant with reference
voltage. A decrease in reference voltage will not significantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
overall converter INL performance. The recommended
range for the LTC2424/LTC2428 voltage reference is
100mV to VCC.
Input Voltage Range
The converter is able to accommodate system level offset
and gain errors as well as system level overrange
situations due to its extended input range, see Figure 2.
The LTC2424/LTC2428 converts input signals within the
extended input range of – 0.125 • VREF to 1.125 • VREF
(VREF = FSSET – ZSSET).
For large values of VREF this range is limited to a voltage
range of – 0.3V to (VCC + 0.3V). Beyond this range the input
ESD protection devices begin to turn on and the errors due
to the input leakage current increase rapidly.
Input signals applied to VIN may extend below ground by
– 300mV and above VCC by 300mV. In order to limit any fault
current, a resistor of up to 5k may be added in series with
VCC + 0.3V
9/8VREF
VREF
1/2VREF
NORMAL
INPUT
RANGE
EXTENDED
INPUT
RANGE
ABSOLUTE
MAXIMUM
INPUT
RANGE
any channel input pin (CH0 to CH7) without affecting the
performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between this series resistance and the channel input
pin as low as possible; therefore, the resistor should be
located as close as practical to the channel input pin. The
effect of the series resistance on the converter accuracy can
be evaluated from the curves presented in the Analog Input/Reference Current section. In addition, a series resistor will introduce a temperature dependent offset error due
to the input leakage current. A 1nA input leakage current
will develop a 1ppm offset error on a 5k resistor if VREF =
5V. This error has a very strong temperature dependency.
Output Data Format
The LTC2424/LTC2428 serial output data stream is 24 bits
long. The first 4 bits represent status information indicating the sign, input range and conversion state. The next 20
bits are the conversion result, MSB first.
The LTC2424/LTC2428 can be interchanged with the
LTC2404/LTC2408. The two devices are designed to allow
the user to incorporate either device in the same design as
long as ZSSET of the LTC2424/LTC2428 is tied to ground.
While the LTC2424/LTC2428 output word lengths are 24
bits (as opposed to the 32-bit output of the LTC2404/
LTC2408), their output clock timing can be identical to the
LTC2404/LTC2408. As shown in Figure 3, the LTC2424/
LTC2408 data output is concluded on the falling edge of the
24th serial clock (SCK). In order to maintain drop-in compatibility with the LTC2404/LTC2408, it is possible to clock
the LTC2424/LTC2428 with an additional 8 serial clock
pulses. This results in 8 additional output bits which are
always logic HIGH.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
0
–1/8VREF
–0.3V
24248 F02
Figure 2. LTC2424/LTC2428 Input Range
Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW. The sign bit changes state during the zero code.
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CSADC
8
8
8
8 (OPTIONAL)
SCK
SDO
EOC = 0
EOC = 1
DATA OUT
4 STATUS BITS 20 DATA BITS
CONVERSION
CONVERSION
SLEEP
EOC = 1
LAST 8 BITS ALWAYS 1
DATA OUTPUT
24248 F03
Figure 3. LTC2424/LTC2428 Compatible Timing with the LTC2404/LTC2408
Bit 20 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0␣ ≤␣ VIN ≤ VREF, this bit is LOW. If the input is outside the
normal input range, VIN > VREF or VIN < 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2424/LTC2428 Status Bits
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
EXR
VIN > VREF
0
0
1
1
0 < VIN ≤ VREF
0
0
1
0
VIN = 0+/0 –
0
0
1/0
0
VIN < 0
0
0
0
1
Input Range
Bit 19 (fifth output bit) is the most significant bit (MSB).
Bits 19-0 are the 20-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 4. Whenever CSADC is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device,
CSADC must first be driven LOW. EOC is seen at the SDO
pin of the device once CSADC is pulled LOW. EOC changes
real time from HIGH to LOW at the completion of a
conversion. This signal may be used as an interrupt for an
external microcontroller. Bit 23 (EOC) can be captured on
the first rising edge of SCK. Bit 22 is shifted out of the
device on the first falling edge of SCK. The final data bit (Bit
0) is shifted out on the falling edge of the 23rd SCK and
may be latched on the rising edge of the 24th SCK pulse.
On the falling edge of the 24th SCK pulse, SDO goes HIGH
10
indicating a new conversion cycle has been initiated. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the VIN pin is maintained within
the – 0.3V to (VCC + 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from – 0.125 • VREF to 1.125 • VREF. For input voltages
greater than 1.125 • VREF, the conversion result is clamped
to the value corresponding to 1.125 • VREF. For input
voltages below – 0.125 • VREF, the conversion result is
clamped to the value corresponding to – 0.125 • VREF.
Channel Selection
Typically, CSADC and CSMUX are tied together or CSADC
is inverted and drives CSMUX. SCK and CLK are tied
together and driven with a common clock signal. During
channel selection, CSMUX is HIGH. Data is shifted into the
DIN pin on the rising edge of CLK, see Figure 4. Table 3
shows the bit combinations for channel selection. In order
to enable the multiplexer output, CSMUX must be pulled
LOW. The multiplexer should be programmed after the
previous conversion is complete. In order to guarantee the
conversion is complete, the multiplexer addressing should
be delayed a minimum tCONV (approximately 133ms for a
60Hz notch) after the data out is read.
While the multiplexer is being programmed, the ADC is in
a low power sleep state. Once the MUX addressing is
complete, the data from the preceding conversion can be
read. A new conversion cycle is initiated following the data
read cycle with the analog input tied to the newly selected
channel.
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tCONV
CSMUX/CSADC
SDO
Hi-Z
EOC
“0”
SIG
EXT
MSB
Hi-Z
LSB
BIT 23 BIT 22
BIT 0
SCK/CLK
DIN
EN
D2
D1
DON’T CARE
D0
24248 F04
Figure 4. Typical Data Input/Output Timing
Table 2. LTC2424/LTC2428 Output Data Format
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
EXR
Bit 19
MSB
Bit 18
Bit 17
Bit 16
Bit 15
…
Bit 0
LSB
VIN > 9/8 • VREF
0
0
1
1
0
0
0
1
1
...
1
9/8 • VREF
0
0
1
1
0
0
0
1
1
...
1
VREF + 1LSB
0
0
1
1
0
0
0
0
0
...
0
VREF
0
0
1
0
1
1
1
1
1
...
1
Input Voltage
3/4VREF + 1LSB
0
0
1
0
1
1
0
0
0
...
0
3/4VREF
0
0
1
0
1
0
1
1
1
...
1
1/2VREF + 1LSB
0
0
1
0
1
0
0
0
0
...
0
1/2VREF
0
0
1
0
0
1
1
1
1
...
1
1/4VREF + 1LSB
0
0
1
0
0
1
0
0
0
...
0
1/4VREF
0
0
1
0
0
0
1
1
1
...
1
0+/0 –
0
0
1/0*
0
0
0
0
0
0
...
0
–1LSB
0
0
0
1
1
1
1
1
1
...
1
–1/8 • VREF
0
0
0
1
1
1
1
0
0
...
0
VIN < –1/8 • VREF
0
0
0
1
1
1
1
0
0
...
0
*The sign bit changes state during the 0 code.
Table 3. Logic Table for Channel Selection
Frequency Rejection Selection (FO Pin Connection)
CHANNEL STATUS
EN
D2
D1
D0
All Off
0
X
X
X
CH0
1
0
0
0
CH1
1
0
0
1
CH2
1
0
1
0
CH3
1
0
1
1
CH4*
1
1
0
0
CH5*
1
1
0
1
CH6*
1
1
1
0
CH7*
1
1
1
1
*Not used for the LTC2424.
The LTC2424/LTC2428 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz ±2% or 60Hz ±2%. For
60Hz rejection, FO (Pin 26) should be connected to GND
(Pin 1) while for 50Hz rejection the FO pin should be
connected to VCC (Pin␣ 2).
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
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When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2424/
LTC2428 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the FO pin and turns off the internal
oscillator. The frequency fEOSC of the external signal must
be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods tHEO and tLEO are observed.
converter uses an external serial clock. If the change
occurs during the conversion state, the result of the
conversion in progress may be outside specifications but
the following conversions will not be affected. If the
change occurs during the data output state and the
converter is in the Internal SCK mode, the serial clock duty
cycle may be affected but the serial data stream will
remain valid.
Table 4 summarizes the duration of each state as a
function of FO.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2424/LTC2428 provide better
than 110dB normal mode rejection in a frequency range
fEOSC/2560 ±4% and its harmonics. The normal mode
rejection as a function of the input frequency deviation
from fEOSC/2560 is shown in Figure 5.
Whenever an external clock is not present at the F O pin the
converter automatically activates its internal oscillator
and enters the Internal Conversion Clock mode. The
LTC2424/LTC2428 operation will not be disturbed if the
change of conversion clock source occurs during the
sleep state or during the data output state while the
–60
–70
–80
REJECTION (dB)
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
–90
–100
–110
–120
–130
–140
–12
–8
–4
0
4
8
12
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
24248 F05
Figure 5. LTC2424/LTC2428 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
Table 4. LTC2424/LTC2428 State Duration
State
Operating Mode
CONVERT
Internal Oscillator
External Oscillator
Duration
FO = LOW (60Hz Rejection)
133ms
FO = HIGH (50Hz Rejection)
160ms
FO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
20480/fEOSC (In Seconds)
SLEEP
DATA OUTPUT
As Long As CSADC = HIGH Until CSADC = 0 and SCK
Internal Serial Clock
External Serial Clock with
Frequency fSCK kHz
MAXIMUM OUTPUT
WORD RATE (OWR)
12
FO = LOW/HIGH
(Internal Oscillator)
As Long As CSADC = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
FO = External Oscillator with
Frequency fEOSC kHz
As Long As CSADC = LOW But Not Longer Than 256/fEOSCms
(32 SCK cycles)
As Long As CSADC = LOW But Not Longer Than 32/fSCKms
(32 SCK cycles)
1
OWR =
in Hz
tCONVERT + tDATAOUTPUT
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Operation at Higher Data Output Rates
The LTC2424/LTC2428 typically operate with an internal
oscillator of 153.6kHz. This corresponds to a notch frequency of 60Hz and an output rate of 7.5 samples/second.
The internal oscillator is enabled if the FO pin is logic LOW
(logic HIGH for a 50Hz notch). It is possible to drive the FO
pin with an external oscillator for higher data output rates.
As shown in Figure 6, an external clock of 2.048MHz
applied to the FO pin results in a notch frequency of 800Hz
with a data output rate of 100 samples/second.
Figure 7 shows the total unadjusted error (Offset Error +
Full-Scale Error + INL + DNL) as a function of the output
data rate with a 5V reference. The relationship between the
output data rate (ODR) and the frequency applied to the FO
pin (FO) is:
ODR = FO/20480
For output data rates up to 50 samples/second, the total
unadjusted error (TUE) is better than 16 bits, and better
than 12 bits at 100 samples/second. As shown in Figure 8,
for output data rates of 100 samples/second, the TUE is
better than 15 bits for VREF below 2.5V. Figure 9 shows an
unaveraged total unadjusted error for the LTC2424 or
LTC2428 operating at 100 samples/second with VREF =
2.5V. Figure 10 shows the same device operating with a 5V
reference and an output data rate of 7.5 samples/second.
LTC2424
4
5
6
7
8
9
10
11
12
13
14
GND
VCC
GND
FSSET
FO
ADCIN
SCK
SDO
ZSSET
GND
CSADC
MUXOUT GND
VCC
DIN
CH0
CSMUX
CH1
CLK
CH2
GND
CH3
NC
NC
GND
NC
NC
28
R9 1k
27
10k
26
C8 5pF
24
23
C9
0.1µF 5V
22
HCO4
21
+
C6
270pF
HCO4
5
6
20
19
R7 5k
R6 47k
10 TVEN POT
SWITCH
25
3 2
4
12
13
10
11
8
9
1
7
C7
10pF
18
17
256
R8 1k
OUTPUT RATE = 100sps
TOTAL UNADJUSTED ERROR (ppm)
3
GND
192
160
13 BITS
128
96
14 BITS
64
15 BITS
32
16
15
12 BITS
224
0
1.0
1.5
2.0 2.5 3.0 3.5 4.0
REFERENCE VOLTAGE (V)
4.5
5.0
24248 F08
24248 F06
Figure 8. Total Error vs VREF (Output Rate = 100sps)
Figure 6. Selectable 100 Sample/Second Turbo Mode
10
256
VREF = 5V
TOTAL UNADJUSTED ERROR (ppm)
2
TOTAL UNADJUSTED ERROR (ppm)
1
12 BITS
224
192
160
13 BITS
128
96
14 BITS
64
32
0
50
100
0
–5
–10
–15
–20
–25
–30
–35
–40
16 BITS
0
VCC = 5V
VREF = 2.5V
5
0
150
2.5
INPUT VOLTAGE (V)
24248 F09
OUTPUT RATE (SAMPLES/SEC)
24248 F07
Figure 7. Total Error vs Output Rate (VREF = 5V)
Figure 9. Total Unadjusted Error at
100 Samples/Second (No Averaging)
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TOTAL UNADJUSTED ERROR (ppm)
6
300mVP-P input signal at 2Hz). The exceptional DC
performance of the LTC2424/LTC2428 enables signals to
be digitized independent of a large DC offset. Figures 12a
and 12b show the dynamic performance with a 15Hz
signal superimposed on a 2V DC level. The same signal
with no DC level is shown in Figures 12c and 12d.
VCC = 5V
VREF = 5V
4
2
0
–2
–4
–6
SERIAL INTERFACE
–8
–10
5
0
INPUT VOLTAGE (V)
24248 F10
Figure 10. Total Unadjusted Error at
7.5 Samples/Second (No Averaging)
At 100 samples/second, the LTC2424/LTC2428 can be
used to capture transient data. This is useful for monitoring settling or auto gain ranging in a system. The LTC2424/
LTC2428 can monitor signals at an output rate of 100
samples/second. After acquiring 100 samples/second data,
the FO pin may be driven LOW enabling 60Hz rejection to
110dB and the highest possible DC accuracy. The no
latency architecture of the LTC2424/LTC2428 allows consecutive readings (one at 100 samples/second the next at
7.5 samples/second) without interaction between the two
readings.
As shown in Figure 11, the LTC2424/LTC2428 can capture transient data with 90dB of dynamic range (with a
ADC Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 25) is used to
synchronize the data transfer. Each bit of data is shifted out
of the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2424/LTC2428 creates its own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as
input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CSADC pin. If SCK is HIGH or
0
0.20
2Hz
100sps
0V OFFSET
fIN = 2Hz
500ms
0.15
–20
0.10
MAGNITUDE (dB)
ADC OUTPUT (NORMALIZED TO VOLTS)
The LTC2424/LTC2428 transmit the conversion results,
program the channel selection, and receive the start of
conversion command through a synchronous 4-wire interface (SCK = CLK, CSADC = CSMUX). During the conversion and sleep states, this interface can be used to assess
the converter status. While in the sleep state this interface
may be used to program an input channel. During the data
output state, it is used to read the conversion result.
0.05
0
–0.05
–40
–60
–80
–0.10
–100
–0.15
–120
–0.20
0.5
1
1.5
TIME (SEC)
2
2.5
0
24248 F11a
Figure 11a. Digitized Waveform
Figure 11. Transient Signal Acquisition
14
25
FREQUENCY (Hz)
Figure 11b. Output FFT
50
24248 F11b
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VIN = 300mVP-P + 2V DC
2.15
–20
2.05
2.00
1.95
–40
–60
–80
1.90
–100
1.85
–120
1.80
0.5
1
1.5
2
TIME (SEC)
0.20
0
2.5
24248 F12a
Figure 12a. Digitized Waveform with 2V DC Offset
25
FREQUENCY (Hz)
50
24248 F12b
Figure 12b. FFT Waveform with 2V DC Offset
0
VIN = 300mVP-P + 0V DC
0.15
15Hz
100sps
0V OFFSET
–20
0.10
MAGNITUDE (dB)
ADC OUTPUT (NORMALIZED TO VOLTS)
15Hz
100sps
2V OFFSET
2.10
MAGNITUDE (dB)
ADC OUTPUT (NORMALIZED TO VOLTS)
2.20
0.05
0.00
–0.05
–40
–60
–80
–0.10
–100
–0.15
–120
–0.20
0.5
1
1.5
2
TIME (SEC)
2.5
24248 F12c
Figure 12c. Digitized Waveform with No Offset
0
25
FREQUENCY (Hz)
50
24248 F12d
Figure 12d. FFT Waveform with No Offset
Figure 12. Using the LTC2424/LTC2428’s High Accuracy Wide Dynamic Range
to Digitize a 300mVP-P 15Hz Waveform with a Large DC Offset (VCC = 5V, VREF = 5V)
floating at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.
Multiplexer Serial Input Clock (CLK)
Generally, this pin is externally tied to SCK for 4-wire operation. On the rising edge of CLK (Pin 19) with CSMUX held
HIGH, data is serially shifted into the multiplexer. If CSMUX
is LOW the CLK input will be disabled and the channel
selection unchanged.
is used as an end of conversion indicator during the
conversion and sleep states.
When CSADC (Pin 23) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CSADC is LOW during the
convert or sleep state, SDO will output EOC. If CSADC is
LOW during the conversion phase, the EOC bit appears
HIGH on the SDO pin. Once the conversion is complete,
EOC goes LOW. The device remains in the sleep state until
the first rising edge of SCK occurs while CSADC = 0.
ADC Chip Select Input (CSADC)
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 24), drives the serial
data during the data output state. In addition, the SDO pin
The active LOW chip select, CSADC (Pin 23), is used to test
the conversion status and to enable the data output
transfer as described in the previous sections.
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In addition, the CSADC signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2424/LTC2428 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CSADC pin after the converter has entered the data output
state (i.e., after the first rising edge of SCK occurs with
CSADC = 0).
External Serial Clock (SPI/MICROWIRE Compatible)
Multiplexer Chip Select (CSMUX)
The serial clock mode is selected on the falling edge of
CSADC. To select the external serial clock mode, the serial
clock pin (SCK) must be LOW during each CSADC falling
edge.
For 4-wire operation, this pin is tied directly to CSADC or
the output of an inverter tied to CSADC. CSMUX (Pin 20)
is driven HIGH during selection of a multiplexer channel.
On the falling edge of CSMUX, the selected channel is
enabled and drives MUXOUT.
Data Input (DIN)
The data input to the multiplexer, DIN (Pin 21), is used to
program the multiplexer. The input channel is selected by
serially shifting a 4-bit input word into the DIN pin under
the control of the multiplexer clock, CLK. Data is shifted
into the multiplexer on the rising edge of CLK. Table 3
shows the logic table for channel selection. In order to
select or change a previously programmed channel, an
enable bit (DIN = 1) must proceed the 3-bit channel select
serial data. The user may set DIN = 0 to continually convert
on the previously selected channel.
SERIAL INTERFACE TIMING MODES
The LTC2424/LTC2428’s 4-wire interface is SPI and
MICROWIRE compatible. This interface offers two modes
of operation. These include an internal or external serial
clock. The following sections describe both of these serial
interface timing modes in detail. For both cases the
converter can use the internal oscillator (FO = LOW or FO
= HIGH) or an external oscillator connected to the FO pin.
Refer to Table 5 for a summary.
This timing mode uses an external serial clock (SCK) to
shift out the conversion result, see Figure 13. This same
external clock signal drives the CLK pin in order to program the multiplexer. A single CS signal drives both the
multiplexer CSMUX and converter CSADC inputs. This
common signal is used to monitor and control the state of
the conversion as well as enable the channel selection.
The serial data output pin (SDO) is HI-Z as long as CSADC
is HIGH. At any time during the conversion cycle, CSADC
may be pulled LOW in order to monitor the state of the
converter. While CSADC is LOW, EOC is output to the SDO
pin. EOC = 1 while a conversion is in progress and EOC =
0 if the device is in the sleep state. Independent of CSADC,
the device automatically enters the low power sleep state
once the conversion is complete.
While the device is in the sleep state, prior to entering the
data output state, the user may program the multiplexer.
As shown in Figure 13, the multiplexer channel is selected
by serial shifting a 4-bit word into the DIN pin on the rising
edge of CLK (CLK is tied to SCK). The first bit is an enable
bit that must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the falling edge of CSMUX, the new channel is
selected and will be valid for the first conversion performed
following the data output state. Clock signals applied to the
CLK pin while CSMUX is LOW (during the data output
state) will have no effect on the channel selection. Furthermore, if DIN is held LOW or CLK is held LOW during the
sleep state, the channel selection is unchanged.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift register.
Table 5. LTC2424/LTC2428 Interface Timing Modes
Configuration
External SCK
Internal SCK
16
SCK
Source
External
Internal
Conversion
Cycle
Control
CSADC and SCK
CSADC ↓
Data
Output
Control
CSADC and SCK
CSADC ↓
Connection
and
Waveforms
Figures 7, 8, 9
Figures 10, 11
LTC2424/LTC2428
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2.7V TO 5.5V
VCC
VCC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
FO
LTC2424/LTC2428
0.1V
TO VCC
–0.12VREF
TO 1.12VREF
FSSET
CSMUX
CH0
TO CH7
CSADC
MUXOUT
SCK
CS
SCK
CLK
ADCIN
DIN
ZSSET
SDO
GND
CSADC/
CSMUX
SCK/CLK
TEST EOC
BIT23
TEST EOC
BIT22 BIT21 BIT20 BIT19 BIT18
SDO
SIG
Hi-Z
DIN
DON’T CARE
BIT4
BIT0
LSB
EXR MSB
TEST EOC
Hi-Z
Hi-Z
EN
D2
D1
D0
DON’T CARE
24248 F13
Figure 13. External Serial Clock Timing Diagram
The device remains in the sleep state until the first rising
edge of SCK is seen while CSADC is LOW. Data is shifted
out the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 24th rising edge of SCK. On the 24th falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
While the device is performing the internal calibration, it is
sensitive to ground current disturbances. Error currents
flowing in the ground pin may lead to offset errors. If the
SCK pin is toggling during the calibration, these ground
disturbances will occur. The solution is to either drive the
multiplexer clock input (CLK) separately from the ADC
clock input (SCK), or program the multiplexer in the first
1ms following the data output cycle. The remaining 65ms
may be used to allow the input signal to settle.
At the conclusion of the data cycle, CSADC may remain
LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CSADC may be driven HIGH setting
SDO to HI-Z. As described above, CSADC may be pulled
LOW at any time in order to monitor the conversion status.
For each of these operations, CSMUX may be tied to
CSADC without affecting the selected channel.
Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first rising edge
and the 24th falling edge of SCK, see Figure 15. On the
rising edge of CSADC, the device aborts the data output
state and immediately initiates a new conversion. This is
useful for systems not requiring all 24 bits of output data,
aborting an invalid conversion cycle or synchronizing the
start of a conversion.
At the conclusion of the data output cycle, the converter
enters a user transparent calibration cycle prior to actually
performing a conversion on the selected input channel.
This enables a 66ms (for 60Hz notch frequency) look ahead
time for the multiplexer input. Following the data output
cycle, the multiplexer input channel may be selected any
time in this 66ms window by pulling CSADC HIGH and
serial shifting data into the DIN pin, see Figure 14.
Internal Serial Clock
This timing mode uses an internal serial clock to shift out
the conversion result and program the multiplexer, see
Figure 16. A CS signal directly drives the CSADC input,
while the inverse of CS drives the CSMUX input. The CS
17
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CSADC/
CSMUX
SCK/CLK
TEST EOC
BIT23 BIT22
TEST EOC
BIT21 BIT20 BIT19 BIT18
SDO
BIT4
BIT0
LSB
SIG EXR MSB
Hi-Z
DIN
DON’T CARE
CONVERTER
STATE
CONV
SLEEP
EN
D2
DATA OUTPUT
D1
D0
DON’T CARE
INTERNAL CALIBRATION
66ms LOOK AHEAD
CONVERSION ON SELECTED CHANNEL
66ms CONVERT
133ms CONVERSION CYCLE (OUTPUT RATE = 7.5Hz)
24248 F14
Figure 14. Use of Look Ahead to Program Multiplexer After Data Output
2.7V TO 5.5V
VCC
VCC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
FO
LTC2424/LTC2428
0.1V
TO VCC
–0.12VREF
TO 1.12VREF
FSSET
CSMUX
CH0
TO CH7
CSADC
SCK
MUXOUT
CS
SCK
CLK
ADCIN
DIN
ZSSET
SDO
GND
CSADC/
CSMUX
SCK/CLK
TEST EOC
BIT23
TEST EOC
SDO
SIG
Hi-Z
DIN
BIT22 BIT21 BIT20 BIT19 BIT18
DON’T CARE
BIT9
BIT8
EXR MSB
Hi-Z
EN
D2
D1
D0
DON’T CARE
24248 F15
Figure 15. External Serial Clock with Reduced Data Output Length Timing Diagram
signal is used to monitor and control the state of the
conversion cycles as well as enable the channel selection.
The multiplexer is programmed during the data output
state. The internal serial clock (SCK) generated by the ADC
is applied to the multiplexer clock input (CLK).
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (HI-Z) or pulled
HIGH prior to the falling edge of CSADC. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CSADC. An internal weak pull-up
18
resistor is active on the SCK pin during the falling edge of
CSADC; therefore, the internal serial clock timing mode is
automatically selected if SCK is not externally driven.
The serial data output pin (SDO) is HI-Z as long as CSADC
is HIGH. At any time during the conversion cycle, CSADC
may be pulled LOW in order to monitor the state of the
converter. Once CSADC is pulled LOW, SCK goes LOW
and EOC is output to the SDO pin. EOC = 1 while a
conversion is in progress and EOC = 0 if the device is in the
sleep state.
LTC2424/LTC2428
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2.7V TO 5.5V
VCC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
FO
VCC
LTC2424/LTC2428
0.1V
TO VCC
–0.12VREF
TO 1.12VREF
FSSET
CSMUX
CH0
TO CH7
CSADC
SCK
MUXOUT
CS
10k
CLK
ADCIN
DIN
ZSSET
SDO
GND
CSMUX
tEOCtest
CSADC
SCKCLK
TEST EOC
BIT23 BIT22 BIT21 BIT20 BIT19 BIT18
TEST EOC
SDO
Hi-Z
DIN
BIT4 BIT3 BIT2 BIT1
BIT0
TEST EOC
LSB
SIG EXR MSB
Hi-Z
Hi-Z
DON’T CARE
EN
D2
D1
D0
DON’T CARE
24248 F16
Figure 16. Internal Serial Clock Timing Diagram
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CSADC remains LOW. In order to prevent the
device from exiting the low power sleep state, CSADC
must be pulled HIGH before the first rising edge of SCK. In
the internal SCK timing mode, SCK goes HIGH and the
device begins outputting data at time tEOCtest after the
falling edge of CSADC (if EOC = 0) or tEOCtest after EOC
goes LOW (if CSADC is LOW during the falling edge of
EOC). The value of tEOCtest is 23µs if the device is using its
internal oscillator (F0 = logic LOW or HIGH). If FO is driven
by an external oscillator of frequency fEOSC, then tEOCtest is
3.6/fEOSC. If CSADC is pulled HIGH before time tEOCtest, the
device remains in the sleep state. The conversion result is
held in the internal static shift register.
If CSADC remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
While operating in the internal serial clock mode, the SCK
output of the ADC may be used as the multiplexer clock
(CLK). DIN is latched into the multiplexer on the rising
edge of CLK. As shown in Figure 16, the multiplexer
channel is selected by serial shifting a 4-bit word into the
DIN pin on the rising edge of CLK. The first bit is an enable
bit which must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the rising edge of CSADC (falling edge of
CSMUX), the new channel is selected and will be valid for
the next conversion. If DIN is held LOW during the data
output state, the previous channel selection remains valid.
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Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first and 24th
rising edge of SCK, see Figure 17. On the rising edge of
CSADC, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 24 bits of output data, aborting
an invalid conversion cycle, or synchronizing the start of
a conversion. If CSADC is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not
available to restore SCK to a logic HIGH state. This will
cause the device to exit the internal serial clock mode on
the next falling edge of CSADC. This can be avoided by
adding an external 10k pull-up resistor to the SCK pin or
by never pulling CSADC HIGH when SCK is LOW.
mode. However, certain applications may require an external driver on SCK. If this driver goes HI-Z after outputting
a LOW signal, the LTC2424/LTC2428’s internal pull-up
remains disabled. Hence, SCK remains LOW. On the next
falling edge of CSADC, the device is switched to the
external SCK timing mode. By adding an external 10k pullup resistor to SCK, this pin goes HIGH once the external
driver goes HI-Z. On the next CSADC falling edge, the
device will remain in the internal SCK timing mode.
A similar situation may occur during the sleep state when
CSADC is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state
(EOC = 0), SCK will go LOW. Once CSADC goes HIGH
(within the time period defined above as tEOCtest), the
internal pull-up is activated. For a heavy capacitive load
on the SCK pin, the internal pull-up may not be adequate
to return SCK to a HIGH level before CSADC goes LOW
again. This is not a concern under normal conditions
Whenever SCK is LOW, the LTC2424/LTC2428’s internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
2.7V TO 5.5V
VCC
VCC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
FO
LTC2424/LTC2428
0.1V
TO VCC
–0.12VREF
TO 1.12VREF
FSSET
CSMUX
CH0
TO CH7
CSADC
SCK
MUXOUT
CS
10k
CLK
ADCIN
DIN
ZSSET
SDO
GND
CSMUX
tEOCtest
CSADC
SCKCLK
TEST EOC
BIT23 BIT22 BIT21 BIT20 BIT19 BIT18
TEST EOC
SDO
BIT8
TEST EOC
SIG EXR MSB
Hi-Z
DIN
BIT12 BIT11 BIT10 BIT9
Hi-Z
DON’T CARE
Hi-Z
EN
D2
D1
D0
DON’T CARE
24248 F17
Figure 17. Internal Serial Clock with Reduced Data Output Length Timing Diagram
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where CSADC remains LOW after detecting EOC = 0. This
situation is easily avoided by adding an external 10k pullup resistor to the SCK pin.
DIGITAL SIGNAL LEVELS
The LTC2424/LTC2428’s digital interface is easy to use.
Its digital inputs (FO, CSADC, CSMUX, CLK, DIN and SCK
in External SCK mode of operation) accept standard TTL/
CMOS logic levels and can tolerate edge rates as slow as
100µs. However, some considerations are required to take
advantage of exceptional accuracy and low supply current.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
In order to preserve the accuracy of the LTC2424/LTC2428,
it is very important to minimize the ground path impedance which may appear in series with the input and/or
reference signal and to reduce the current which may flow
through this path. The ZSSET pin (Pin 6) should be connected directly to the signal ground.
The power supply current during the conversion state
should be kept to a minimum. This is achieved by restricting the number of digital signal transitions occurring
during this period.
While a digital input signal is in the 0.5V to (VCC␣ –␣ 0.5V)
range, the CMOS input receiver draws additional current
from the power supply. It should be noted that, when any
one of the digital input signals (FO, CSADC, CSMUX, DIN,
CLK and SCK in External SCK mode of operation) is within
this range, the LTC2424/LTC2428 power supply current
may increase even if the signal in question is at a valid logic
level. For micropower operation and in order to minimize
the potential errors due to additional ground pin current,
it is recommended to drive all digital input signals to full
CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)].
Severe ground pin current disturbances can also occur
due to the undershoot of fast digital input signals. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition
time of an external control signal is less than twice the
propagation delay from the driver to LTC2424/LTC2428.
For reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/inch for internal
traces and 170ps/inch for surface traces. Thus, a driver
generating a control signal with a minimum transition
time of 1ns must be connected to the converter pin
through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.
Parallel termination near the LTC2424/LTC2428 input
pins will eliminate this problem but will increase the driver
power dissipation. A series resistor between 27Ω and 56Ω
placed near the driver or near the LTC2424/LTC2428 pin
will also eliminate this problem without additional power
dissipation. The actual resistor value depends upon the
trace impedance and connection topology.
Driving the Input and Reference
The analog input and reference of the typical delta-sigma
analog-to-digital converter are applied to a switched capacitor network. This network consists of capacitors switching between the analog input (ADCIN), ZSSET (Pin 6) and
the reference (FSSET). The result is small current spikes
seen at both ADCIN and VREF. A simplified input equivalent
circuit is shown in Figure 18.
The key to understanding the effects of this dynamic input
current is based on a simple first order RC time constant
model. Using the internal oscillator, the internal switched
capacitor network of the LTC2424/LTC2428 is clocked at
153,600Hz corresponding to a 6.5µs sampling period.
Fourteen time constants are required each time a capacitor
is switched in order to achieve 1ppm settling accuracy.
Therefore, the equivalent time constant at VIN and VREF
should be less than 6.5µs/14 = 460ns in order to achieve
1ppm accuracy.
Input Current (VIN)
If complete settling occurs on the input, conversion results will be unaffected by the dynamic input current. If the
settling is incomplete, it does not degrade the linearity
performance of the device. It simply results in an offset/
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ADCVCC
(PIN 2)
RSW
5k
IREF
FSSET
IREF
SELECTED
CHANNEL I
IN(MUX)
MUXVCC
(PIN 8)
±IDC
RSW
75Ω
CHX
MUXOUT
ADCVCC
(PIN 2)
IIN(LEAK)
AVERAGE INPUT CURRENT:
IDC = 0.25(VIN – 0.5 • VREF) • f • CEQ
RSW
5k
ADCIN
IIN(MUX)
CEQ
1pF (TYP)
IIN(LEAK)
RSW
5k
fOUT = 50Hz, INTERNAL OSCILLATOR: f = 128kHz
fOUT = 60Hz, INTERNAL OSCILLATOR: f = 153.6kHz
EXTERNAL OSCILLATOR: 2.56kHz ≤ f ≤ 307.2kHz
24248 F18
ZSSET
Figure 18. LTC2424/LTC2428 Equivalent Analog Input Circuit
full-scale shift, see Figure 19. To simplify the analysis of
input dynamic current, two separate cases are assumed:
large capacitance at VIN (CIN > 0.01µF) and small capacitance at VIN (CIN < 0.01µF).
If the total capacitance at VIN (see Figure 20) is small
(< 0.01µF), relatively large external source resistances (up
to 20k for 20pF parasitic capacitance) can be tolerated
without any offset/full-scale error.
ANTIALIASING
One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2424/LTC2428 significantly simplify antialiasing filter requirements.
The digital filter provides very high rejection except at
integer multiples of the modulator sampling frequency
(fS), see Figure 21. The modulator sampling frequency is
256 • FO, where FO is the notch frequency (typically 50Hz
or 60Hz). The bandwidth of signals not rejected by the
digital filter is narrow (≈ 0.2%) compared to the bandwidth
of the frequencies rejected.
TUE
0
–20
0
VREF/2
VREF
VIN
24248 F19
REJECTION (dB)
–40
–60
–80
–100
Figure 19. Offset/Full-Scale Shift
–120
–140
RSOURCE
INTPUT
SIGNAL
SOURCE
CIN
CPAR
≅ 20pF
CH0 TO
CH7
LTC2424/
LTC2428
24248 F20
Figure 20. An RC Network at CH0 to CH7
22
0
fS/2
fS
INPUT FREQUENCY
24248 F21
Figure 21. Sync4 Filter Rejection
LTC2424/LTC2428
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can be configured into a resistive ladder, using the LTC2428
to sense each node. This approach allows a single excitation current passed through the entire ladder, reducing
total supply current consumption. In addition, this approach requires only one high precision resistor, thereby
reducing cost. A group of up to seven temperatures can be
measured as a group by a single LTC2428 in a loop-powered remote acquisition unit. In the example shown in
Figure 22, the excitation current is 240µA at 0°C. The
LTC2428 requires 300µA, leaving nearly 3.5mA for the
remainder of the remote transmitter.
As a result of the oversampling ratio (256) and the digital
filter, minimal (if any) antialias filtering is required in front
of the LTC2424/LTC2428. If passive RC components are
placed in front of the LTC2424/LTC2428, the input dynamic current should be considered. In cases where large
effective RC time constants are used, an external buffer
amplifier may be required to minimize the effects of input
dynamic current.
The modulator contained within the LTC2424/LTC2428
can handle large-signal level perturbations without saturating. Signal levels up to 40% of VREF do not saturate the
analog modulator. These signals are limited by the input
ESD protection to 300mV below ground and 300mV above
VCC.
The resistance of any of the RTDs (PT1 to PT7) is determined from the voltage across it, as compared to the
voltage drop across the reference resistor (R1). This is a
ratiometric implementation where the voltage drop across
R1 is given by VREF – VCH1. Channel 7 is used to measure
the voltage on a representative length of wire. If the same
type and length of wire is used for all connections, then
errors associated with the voltage drops across all wiring
can be removed in software. The contribution of wiring
drop can be scaled if wire lengths are not equal.
The LTC2428’s Resolution and Accuracy Allows You
to Measure Points in a Ladder of Sensors
In many industrial processes, for example, cracking towers in petroleum refineries, a group of temperature measurements must be related to one another. A series of
platinum RTDs that sense slow changing temperatures
5V
300µA
+
R2
6
47µF
3
4
5
+
7
6
LTC1050
2
R1
20.1k
0.1%
UP TO SEVERAL
HUNDRED FEET.
ALL SAME
WIRE TYPE
PT1
100Ω
PLATINUM
RTD
R2
5V
OPTIONAL
PROTECTION
RESISTORS
5k MAX
7
MUXOUT
3
2, 8
FSSET VCC
1µF
9 CH0
CSADC
11 CH2
CSMUX
14 CH5
PT7
4
ADCIN
10 CH1
13 CH4
TO PT3-PT6
4
R3
12 CH3
PT2
–
0.1µF
OPTIONAL
GAIN
BLOCK
5V
LTC1634-2.5
15 CH6
17 CH7
8-CHANNEL
MUX
+
20-BIT
∆∑ ADC
SCK
CLK
DIN
–
SDO
23
20
25
19
21
24
VCC
LTC2428
5 ZSSET
GND
1, 6, 16, 18, 22, 27, 28
FO
26
24248 F22
Figure 22. Measuring Up to Seven RTD Temperatures with One Reference Resistor and One Reference Current
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Gain can be added to this circuit as the total voltage drop
across all the RTDs is small compared to ADC full-scale
range. The maximum recommended gain is 50, as limited
by both amplifier noise contribution, as well as the maximum voltage developed at CH0 when all sensors are at the
maximum temperature specified for platinum RTDs.
Adding gain requires that one of the resistors (PT1 to PT7)
be a precision resistor in order to eliminate the error associated with the gain setting resistors R2 and R3. Note, that
if a precision (100Ω to 400Ω) resistor is used in place of
one of the RTDs (PT7 recommended), R1 does not need
to be a high precision resistor. Although the substitution
of a precision reference resistor for an RTD to determine
gain may suggest that R2 and R3 (and R1) need not be
precise, temperature fluctuations due to airflow may appear as noise that cannot be removed in firmware. Consequently, these resistors should be low temperature coefficient devices. The use of higher resistance RTDs is not
recommended in this topology, although the inclusion of
one 1000Ω RTD at the top on the ladder will have minimal
impact on the lower elements. The same caveat applies to
fast changing temperatures. Any fast changing sensors
should be at the top of the ladder.
The LTC2428’s Uncommitted Multiplexer Finds Use in
a Programmable Gain Scheme
If the multiplexer in the LTC2428 is not committed to
channel selection, it can be used to select various signalprocessing options such as different gains, filters or attenuator characteristics. In Figure 23, the multiplexer is
shown selecting different taps on an R/2R ladder in the
feedback loop of an amplifier. This example allows selection of gain from 1 to 128 in binary steps. Other feedback
networks could be used to provide gains tailored for
specific purposes. (For example, 1x, 1.1x, 1.41x, 2x,
2.028x, 5x, 10x, 40x, etc.) Alternatively, different bandpass
characteristics or signal inversion/noninversion could be
selected. The R/2R ladder can be purchased as a network
to ensure tight temperature tracking. Alternatively, resistors in a ladder or as separate dividers can be assembled
from discrete resistors. In the configuration shown, the
channel resistance of the multiplexer does not contribute
much to the error budget, as only input op amp current
24
flows through the switch. The LTC1050 was chosen for
its low input current and offset voltage, as well as its
ability to drive the input of a ∆Σ ADC.
Insert Gain or Buffering After the Multiplexer
Separate MUXOUT and ADCIN terminals permit insertion
of a gain stage between the MUX and the ADC. If passive
filtering is used at the input to the ADC, a buffer amplifier
is strongly recommended to avoid errors resulting from
the dynamic ADC input current. If antialiasing is required,
it should be placed at the input to the MUX. If bandwidth
limiting is required to improve noise performance, a filter
with a –3dB point at 1500Hz will reduce the effective total
noise bandwidth of the system to 15Hz. A roll-off at 1500Hz
eliminates all higher order images of the base bandwidth
of 6Hz. In the example shown, the optional bandwidthlimiting filter has a – 3dB point at 1450Hz. This filter can be
inserted after the multiplexer provided that higher source
impedance prior to the multiplexer does not reduce the
– 3dB frequency, extending settling time, and resulting in
charge sharing between samples. The settling time of this
filter to 20+ bits of accuracy is less than 2ms. In the presence of external wideband noise, this filter reduces the
apparent noise by a factor of 5. Note that the noise bandwidth for noise developed in the amplifier is 150Hz. In the
example shown, the gain of the amplifier is set to 40, the
point at which amplifier noise gain dominates the LTC2428
noise. Input voltage range as shown is then 0V to 125mV
DC. The recommended capacitor at C2 for a gain of 40
would be 560pF.
An 8-Channel DC-to-Daylight Digitizer
The circuit in Figure 25 shows an example of the LTC2428’s
flexibility in digitizing a number of real-world physical
phenomena—from DC voltages to ultraviolet light. All of
the examples implement single-ended signal conditioning. Although differential signal conditioning is a preferred approach in applications where the sensor is a
bridge-type, is located some distance from the ADC or
operates in a high ambient noise environment, the
LTC2428’s low power dissipation allows circuit operation
in close proximity to the sensor. As a result, conditioning
the sensor output can be greatly simplified through the
LTC2424/LTC2428
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APPLICATIONS INFORMATION
5V
VIN
3
AV = 1, 2, 4...128
+
6
LTC1050
2
–
5V
0.1V TO VCC
10k
20k
7
MUXOUT
2
20k
10k
8
20k
32
8-CHANNEL
MUX
+
20-BIT
∆∑ ADC
23
20
25
SCK
19
CLK
21
DIN
–
17 CH7
24
SDO
VCC
LTC2428
5 ZSSET
64
10k
CSMUX
14 CH5
10k
20k
11 CH2
15 CH6
10k
10k
CSADC
13 CH4
10k
20k
10 CH1
12 CH3
16
20k
1µF
9 CH0
10k
4
20k
3
2, 8
FSSET VCC
4
ADCIN
26
FO
GND
1, 6, 16, 18, 22, 27, 28
24248 F23
128
Figure 23. Using the Multiplexer to Produce Programmable Gains of 1 to 128
5V
OPTIONAL
BANDWIDTH
LIMIT
3
+
7
6
LTC1050
2
C1
0.022µF
R1
5.1k
–
4
R3
200k
R4
5K
MAY BE REQUIRED BY OTHER
AMPLIFIERS (IS REQUIRED BY
BIPOLAR AMPLIFIERS)
R2
5.1K
C2
OPTIONAL GAIN
AND ROLL-OFF
7
MUXOUT
ANALOG
INPUTS
9
CH0
10
CH1
11
CH2
12
CH3
13
CH4
14
CH5
15
CH6
17
CH7
5
ZSSET
5V
4
ADCIN
3
2, 8
FSSET VCC
10µF
CSADC
CSMUX
8-CHANNEL
MUX
+
20-BIT
∆∑ ADC
SCK
CLK
DIN
–
SDO
23
20
25
19
21
24
VCC
LTC2428
GND
1, 6, 16, 18, 22, 27, 28
FO
26
24248 F24
Figure 24. Inserting Gain Between the Multiplexer and the ADC Input
25
LTC2424/LTC2428
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APPLICATIONS INFORMATION
use of single-ended arrangements. In those applications
where differential signal conditioning is required, chopper
amplifier-based or self-contained instrumentation amplifiers (also available from LTC) can be used with the
LTC2428.
With the resistor network connected to CH0, the LTC2428
is able to measure DC voltages from 1mV to 1kV in a single
range without the need for autoranging. The 990k resistor
should be a 1W resistor rated for high voltage operation.
Alternatively, the 990k resistor can be replaced with a
series connection of several lower cost, lower power metal
film resistors.
The circuit connected to CH1 shows an LT1793 FET input
operational amplifier used as an electrometer for high
impedance, low frequency applications such as measuring pH. The circuit has been configured for a gain of 21;
thus, the input signal range is –15mV ≤ VIN ≤ 250mV. An
amplifier circuit is necessary in these applications because high output impedance sensors cannot drive
switched-capacitor ADCs directly. The LT1793 was chosen for its low input bias current (10pA, max) and low
noise (8nV/√Hz) performance. As shown, the use of a
driven guard (and TeflonTM standoffs) is recommended in
high impedance sensor applications; otherwise, PC board
surface leakage current effects can degrade results.
The circuit connected to CH2 illustrates a precision halfwave rectifier that uses the LTC2428’s internal ∆Σ ADC as
an integrator. This circuit can be used to measure 60Hz,
120Hz or from 400Hz to 1kHz with good results. The
LTC2428’s internal sinc4 filter effectively eliminates any
frequency in this range. Above 1kHz, limited amplifier
gain-bandwidth product and transient overshoot behavior
can combine to degrade performance. The circuit’s dynamic range is limited by operational amplifier input offset
voltage and the system’s overall noise floor. Using an
LTC1050 chopper-stabilized operational amplifier with a
VOS of 5µV, the dynamic range of this application covers
approximately 5 orders of magnitude. The circuit configuration is best implemented with a precision, 3-terminal,
2-resistor 10kΩ network (for example, an IRC PFC-D
network) for R6 and R7 to maintain gain and temperature
stability. Alternatively, discrete resistors with 0.1% initial
26
tolerance and 5ppm/°C temperature coefficient would
also be adequate for most applications.
Two channels (CH3 and CH4) of the LTC2428 are used to
accommodate a 3-wire 100Ω, Pt RTD in a unique circuit
that allows true RMS/RF signal power measurement from
audio to gigahertz (GHz) frequencies. The unique feature
of this circuit is that the signal power dissipated in the 50Ω
termination in the form of heat is measured by the 100Ω
RTD. Two readings are required to compensate for the
RTD’s lead-wire resistance. The reading on CH4 is multiplied by 2 and subtracted from the reading on CH3 to
determine the exact value of the RTD.
While the LTC2428 is capable of measuring signals over a
range of five decades, the implementation (mechanical,
electrical and thermal) of this technique ultimately determines the performance of the circuit. The thermal resistance of the assembly (the 50Ω/RTD mass to its enclosure)
will determine the sensitivity of the circuit. The dynamic
range of the circuit will be determined by the maximum
temperature the assembly is rated to withstand, approximately 850°C. Details of the implementation are quite
involved and are beyond the scope of this document.
Please contact LTC directly for a more comprehensive
treatment of this implementation.
In the circuit connected to the LTC2428’s CH5 input, a
thermistor is configured in a half-bridge arrangement that
could be used to measure the case temperature of the
RTD-based thermal power measurement scheme described
previously. In general, thermistors yield very good resolution over a limited temperature range. For the half-bridge
arrangement shown, the LTC2428 can measure temperature changes over nearly 5 orders of magnitude.
Connected to the LTC2428’s CH6 input, an infrared thermocouple (Omega Engineering OS36-1) can be used in
limited range, noncontact temperature measurement applications or applications where high levels of infrared
light must be measured. Given the LTC2428’s 1.2ppmRMS
noise performance, measurement resolution using infrared thermocouples is approximately 0.25°C—equivalent
to the resolution of a conventional Type J thermocouple.
Teflon is a trademark of Dupont Company.
LTC2424/LTC2428
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APPLICATIONS INFORMATION
These infrared thermocouples are self-contained: 1) they
do not require external cold junction compensation; 2)
they cannot use conventional open thermocouple detection schemes; and 3) their output impedances are high,
approximately 3kΩ. Alternatively, conventional thermocouples can be connected directly to the LTC2428 (not
shown) and cold junction compensation can be provided
by an external temperature sensor connected to a different
channel (see the thermistor circuit on CH5) or by using the
LT1025, a monolithic cold-junction compensator IC.
The photodiode chosen (Hammatsu S1336-5BK) produces an output of 500mA per watt of optical illumination.
The output of the photodiode is dependent on two factors:
active detector area (2.4mm • 2.4mm) and illumination
intensity. With the 5k resistor, optical intensities up to
368W/m2 at 960nM (direct sunlight is approximately
1000W/m2) can be measured by the LTC2428. With a
resolution of 1nA, the optical dynamic range covers 5
orders of magnitude.
The components connected to CH7 are used to sense
daylight or photodiode current with a resolution of 300pA.
In the figure, the photodiode is biased in photoconductive mode; however, the LTC2428 can accommodate
either photovoltaic or photoconductive configurations.
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PACKAGE DESCRIPTIO
The application circuits shown connected to the LTC2428
demonstrate the mix-and-match capabilities of this multiplexed-input, high resolution ∆Σ ADC. Very low level
signals and high level signals can be accommodated with
a minimum of additional circuitry.
Dimensions in millimeters (inches) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
10.07 – 10.33*
(0.397 – 0.407)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
7.65 – 7.90
(0.301 – 0.311)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
0° – 8°
0.13 – 0.22
(0.005 – 0.009)
0.55 – 0.95
(0.022 – 0.037)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
0.65
(0.0256)
BSC
0.25 – 0.38
(0.010 – 0.015)
0.05 – 0.21
(0.002 – 0.008)
G28 SSOP 1098
27
LTC2424/LTC2428
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TYPICAL APPLICATION
GUARD RING
5V
ELECTROMETER
INPUT
(pH, PIEZO)
3
7
+
2
R5
5k, 1%
6
LT1793
DC
VOLTMETER
INPUT
1mV TO 1000V
R1
900k
0.1%, 1W, 1000 WVDC
R2
4.7k
0.1%
–
0V TO 5V
4
–5V
5V
REF
+
R4
1k
–60mV TO 4V
R3, 10k
C1, 0.1µF
5V
MAX
LT1236CS8-5
6
2
OUT IN
+
3-WIRE R-PACK
60Hz
+
AC
INPUT
R6
10k, 0.1%
100µF
R7
10k, 0.1%
5V
5V
1µF
2
RT
7
–
IN914
3
R9
1k
1%
IN914
R10
5k
1%
6
LTC1050
9
13 CH4
CSADC
8-CHANNEL
MUX
20-BIT
∆∑ ADC
CLK
DIN
–
17 CH7
SDO
FO
GND
1, 6, 16, 18, 22, 27, 28
SERIAL DATA LINK
MICROWIRE AND
SPI COMPATABLE
23
20
19, 25
MPU
21
24
LTC2428
ZSSET
<1mV
J1
+
15 CH6
5
1µF
CSMUX
14 CH5
60Hz–RF
RF POWER
J2
3
2, 8
FSSET VCC
CH0
12 CH3
R11
24.9k, 0.1% V
REF
5V
100Ω
Pt RTD
(3-WIRE)
4
ADCIN
11 CH2
20mV TO 80mV
–5V
7
MUXOUT
10 CH1
R8
100Ω, 5%
+
4
50Ω
8V
+
GND
4
10µF
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INTERNAL OSC
SELECTED FOR
60Hz REJECTION
24248 F25
FORCE SENSE
2.7V AT 0°C
0.9V AT 40°C
50Ω LOAD
BONDED TO
RTD ON
INSULATED
MOUNTING
–2.2mV to 16mV
R12
24.9k, 0.1% V
REF
5V
J3
LOCAL
TEMP
THERMISTOR
10kΩ NTC
0V to 4V
5V
DAYLIGHT
HAMAMATSU
PHOTODIODE
S1336-5BK
OMEGA
0S36-01
INFRARED
INFRARED
THERMOCOUPLE
R13
5k
0.1%
Fiugre 25. Measure DC to Daylight Using the LTC2428
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1050
Precision Chopper Stabilized Op Amp
No External Components, 5µV Offset, 1.6µVP–P
LT1236
Precision Bandgap Reference
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1461-2.5
Precision, Low Power, Low Drift Reference
50µA, 0.04%, 3ppm/°C Drift
LT1793
Low Noise JFET Input Op Amp
10pA Max Input Bias Current, Low Voltage Noise: 8nV
LTC2400
24-Bit Micropower ∆Σ ADC in SO-8
<4ppm INL, No Missing Codes, 4ppm Full Scale
LTC2404/LTC2408
4/8 Channel, 24-Bit ∆Σ ADCs
< 4ppm INL, No Missing Codes, Interchangeable with the
LTC2424/LTC2428 if ZSSET is grounded
28
Linear Technology Corporation
24248f LT/TP 0300 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 2000