AD AD5066BRUZ-1REEL7 Fully accurate 16-bit unbuffered vout dac spi interface 2.7 v to 5.5 v in a tssop Datasheet

Fully Accurate 16-Bit UnBuffered VOUT DAC SPI
Interface 2.7 V to 5.5 V in a TSSOP
AD5066
Preliminary Technical Data
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Low power Quad 16 bit DAC, ± 1LSB INL
Individual reference pins
2.7 V to 5.5 V power supply
Unbuffered voltage output capable of driving 60KΩ
Fast Settling time of 4 us typically
Power-on reset to zero scale or mid-scale
Per channel power-down
3 power-down functions
Low glitch on power up
Hardware LDAC with LDAC override function
CLR Function to programmable code
Small 16 lead TSSOP
Figure 1.AD5066
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Table 1. Related Devices
Part No.
AD5666
AD5065/45/25
AD5064/44/24
AD5063/62
AD5061
AD5060/40
Description
Quad,16-bit buffered D/A,16 LSB INL, TSSOP
Quad,16-bit buffered D/A,1 LSB INL, TSSOP
Quad 16-bit nanoDAC, 1 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL, MSOP
16-/14bit nanoDAC, 4 LSB INL, SOT-23
16-/14bit nanoDAC, 1 LSB INL, SOT-23
GENERAL DESCRIPTION
The AD5066 is a low power, 16-bit quad-channel, unbuffered
voltage-out DAC offering relative accuracy specs of 1LSB INL
with individual reference pin and can operate from a single
2.7V to 5.5V. The AD5066 parts also offer a differential
accuracy specification of ±1 LSB. Reference buffers are also
provided on-chip. The parts use a versatile 3-wire, low power
Schmitt trigger serial interface that operates at clock rates up to
50 MHz and is compatible with standard SPI®, QSPI™,
MICROWIRE™, and DSP interface standards. The AD5066
incorporates a power-on reset circuit that ensures the DAC
output powers up zero scale or midscale and remains there until
a valid write takes place to the device. The AD5066 contain a
power-down feature that reduces the current consumption of
the device to typically 330 nA at 5 V and provides software
selectable output loads while in power-down mode. The part
can be placed into power-down mode over the serial interface.
Total unadjusted error for the part is <0.8 mV. Both parts
exhibit very low glitch on power-up.
The outputs of all DACs can be updated simultaneously using
the LDAC function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an
asynchronous CLR that clears all DACs to a software-selectable
code - 0 V, midscale, or full scale.
PRODUCT HIGHLIGHTS
1.
Quad channel available in 16-lead TSSOP package.
2.
Individual voltage reference pins
3.
16 bit accurate, 1 LSB INL.
4.
Low glitch on power-up.
5.
High speed serial interface with clock speeds up to 50 MHz.
6.
Three power-down modes available to the user.
7.
Reset to known output voltage (zero scale).
Rev. PrB
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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www.analog.com
Fax: 781.461.3113
© 2007 Analog Devices, Inc. All rights reserved.
AD5066
Preliminary Technical Data
TABLE OF CONTENTS
REVISION HISTORY
Rev. PrB | Page 2 of 20
Preliminary Technical Data
AD5066
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 2.2V ≤VREFIN ≤. VDD unless otherwise specified. All specifications TMIN to
TMAX, unless otherwise noted.
Table 2.
A Grade 1 2
Parameter
STATIC PERFORMANCE 3
Resolution
Relative Accuracy
Min
Total Unadjusted Error
(TUE)
Offset Error
Offset Error Temperature
Coefficient
Full-Scale Error
Gain Error
Gain Temperature Coefficient
DC Power Supply Rejection
Ratio
DC Crosstalk
(External Reference)
DC PSRR
Wideband SFDR
REFERENCE INPUTS
Reference Input Range
Reference Current
Reference Input Impedance
LOGIC INPUTS4
Input Current 5
Input Low Voltage, VINL
Input High Voltage, VINH
Typ
Max
Typ
Max
±0.5
±0.5
±0.5
±0.5
±500
±4
±4
±1
±1
±800
±0.5
±0.5
±0.5
±0.5
±500
±1
±1.5
±1
±1
800
±500
0.05
±0.5
±800
0.1
±500
0.05
±0.5
800
0.1
μV
±mV
μV/°C
AD5066 TA = -40°C to +125°C
All 0s loaded to DAC register
±500
±800
±500
800
μV
±500
±0.01
±800
±0.02
±1
±500
±0.01
800
±0.02
±1
TA = -40°C to +105°C All 1s loaded to DAC
register
TA = -40°C to +125°C
16
Differential Nonlinearity
OUTPUT CHARACTERISTICS 4
Output Voltage Range
DC Output Impedance
(Normal mode)
DC Output Impedance
(output connected to 100kΩ
network)
(output connected to 1kΩ
network)
Power-Up Time
B Grade1
Min
16
Conditions/Comments
Bits
LSB
AD5066
AD5066
AD5066
AD5066
AD5066
AD5066
LSB
μV
TA = -40°C to +105°C
TA = -40°C to +125°C
TA = -40°C to +105°C
TA = -40°C to +125°C
TA = -40°C to +105°C
–80
–80
μV
% FSR
ppm
dB
0.5
0.5
LSB
0.5
0.5
0.5
0.5
LSB/m
A
LSB
Due to powering down (per channel)
8
V
kΩ
Output impedance tolerance ±10%
100
kΩ
DAC in Power Down mode
Output impedance tolerance ± 20kΩ
1
kΩ
Output impedance tolerance ± 400Ω
4.5
4.5
μs
-92
-67
-92
-67
dB
dB
All DACs coming out of power-down mode
VDD = 5 V
VDD±10%, DAC = full scale
Output frequency = 10Khz
VDD
50
V
μA
KΩ
Per DAC channel
Per DAC channel
±3
0.8
μA
V
V
All digital inputs
VDD = 5 V
VDD = 5 V
0
VDD
0
8
2
40
120
VDD
50
VDD
2
40
120
±3
0.8
2
Unit
2
Rev. PrB | Page 3 of 20
Ppm Of FSR/°C
VDD ± 10%
Due to single-channel full-scale output
change,
RL = 2 kΩ to GND or VDD
Due to load current change
AD5066
Preliminary Technical Data
A Grade 1 2
Parameter
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode) 6
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes) 7
VDD = 4.5 V to 5.5 V
Min
Typ
4
2.7
B Grade1
Max
Min
5.5
2.7
Typ
4
Max
Unit
pF
Conditions/Comments
5.5
V
All digital inputs at 0 or VDD
DAC active, excludes load current
VIH = VDD and VIL = GND
3
4
3
4
mA
0.4
1
0.4
1
μA
1
Temperature range is −40°C to +105°C, typical at 25°C.
A grade offered in AD5064 only
Linearity calculated using a reduced code range of 512 to 65,024. Output unloaded.
4
Guaranteed by design and characterization; not production tested.
5
Total current flowing into all pins.
6
. Interface inactive. All DACs active. DAC outputs unloaded
7
. All four DACs powered down
2
3
Rev. PrB | Page 4 of 20
VIH = VDD and VIL = GND
Preliminary Technical Data
AD5066
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = 4.096 unless otherwise specified. All specifications TMIN to TMAX,
unless otherwise noted.
Table 3.
Parameter 1, 2
Output Voltage Settling Time
Min
Typ
5
Max
Unit
μs
Output Voltage Settling Time
14
μs
Slew Rate
Digital-to-Analog Glitch Impulse
Reference Feedthrough
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
AC Crosstalk
AC PSRR
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
1.5
4
−90
0.1
0.5
6
6.5
6
TBD
340
−80
64
60
6
V/μs
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
Output Noise
kHz
dB
nV/√Hz
nV/√Hz
μV p-p
Conditions/Comments 3
¼ to ¾ scale settling to ±1 LSB,RL = 5kΩ single channel update
including DAC calibration sequence
¼ to ¾ scale settling to ±1 LSB,RL = 5kΩ all channel update including
DAC calibration sequence
1 LSB change around major carry
VREF = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz
VREF = 2 V ± 0.2 V p-p
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = 0x8400, 1 kHz
DAC code = 0x8400, 10 kHz
0.1 Hz to 10 Hz
1
Guaranteed by design and characterization; not production tested.
See the Terminology section.
3
Temperature range is −40°C to + 105°C, typical at 25°C.
2
Rev. PrB | Page 5 of 20
AD5066
Preliminary Technical Data
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 4. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
t1 1
t2
t3
t4
t5
t6
t7
t8
t8
t9
t10
t11
t12
t13
t14
t15
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
us min
us min
ns min
ns min
ns min
ns min
ns min
ns min
us min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (single channel update)
Minimum SYNC high time ( all channel update)
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2mA
TO OUTPUT
PIN
IOL
VOH (MIN)
CL
50pF
2mA
IOH
05298-002
1
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
10
10
16.5
5
5
0
1.9
10.5
16.5
0
20
20
10
10
10.6
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. PrB | Page 6 of 20
Preliminary Technical Data
AD5066
t10
t1
t9
SCLK
t8
t3
t4
t2
t7
SYNC
t5
DIN
t6
DB23
DB0
t14
t11
LDAC1
t12
LDAC2
VOUT
t13
t15
05858-002
CLR
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 3. Serial Write Operation
Rev. PrB | Page 7 of 20
AD5066
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUT to GND
VREF to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ MAX)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
Reflow Soldering Peak Temperature
SnPb
Pb Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
+150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
(TJ MAX − TA)/θJA
150.4°C/W
240°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 8 of 20
Preliminary Technical Data
AD5066
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. 16-Lead TSSOP (RU-16)
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
LDAC
Description
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
2
SYNC
3
VDD
4
5
6
7
8
VREFB
VREFA
VOUTA
VOUTC
POR
9
10
VREFC
CLR
11
12
13
14
15
VREFD
VOUTD
VOUTB
GND
DIN
16
SCLK
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on
the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge
of SYNC acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Dac B reference input .This is the reference voltage input pin for Dac B.
Dac A reference input .This is the reference voltage input pin for Dac A.
Unbuffered analog output voltage from DAC A.
Unbuffered analog output voltage from DAC C.
Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up
the part to midscale.
Dac B reference input .This is the reference voltage input pin for Dac C.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
Dac A reference input .This is the reference voltage input pin for Dac D.
Unbuffered analog output voltage from DAC D.
Unbuffered analog output voltage from DAC B.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Rev. PrB | Page 9 of 20
AD5066
Preliminary Technical Data
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer
function. Error! Reference source not found. shows a plot of
typical INL vs. code.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Error! Reference source not found. shows a
plot of typical DNL vs. code.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Error! Reference source not found. and Error! Reference
source not found..
Offset Error
Offset error is a measure of the difference between the actual
VOUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
AD5066 with Code xxx loaded into the DAC register. It can be
negative or positive and is expressed in millivolts.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V, and VDD is varied ±10%.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5066, because the output of the DAC cannot go below 0
V. It is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in millivolts.
Error! Reference source not found. shows a plot of typical
zero-code error vs. Supply.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Digital-to-Analog Glitch Impulse
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is, LDAC is high). It is expressed in
decibels.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-s and measured with a
full-scale change on the digital input pins, that is, from all 0s to
all 1s or vice versa.
Rev. PrB | Page 10 of 20
Preliminary Technical Data
AD5066
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping LDAC
high, and then pulsing LDAC low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
Total Harmonic Distortion (THD)
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-s.
Rev. PrB | Page 11 of 20
AD5066
Preliminary Technical Data
THEORY OF OPERATION
D/A SECTION
R
The AD5066 are Quad 16-bit, serial input, voltage output
DACs. The parts operate from supply voltages of 2.7 V to 5.5 V.
Data is written to the AD5066 in a 32-bit word format via a 3wire serial interface. The AD5066 incorporates a power-on reset
circuit that ensures the DAC output powers up to a known output state (midscale or zero-scale, see the Ordering Guide). The
devices also have a software power-down mode that reduces the
typical current consumption to less than 1 μa.
R
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
R
D
VOUT = VREFIN × ⎛⎜ N ⎞⎟
⎝2 ⎠
Figure 7. Resistor String
D
VOUT = 2 × V REFOUT × ⎛⎜ N ⎞⎟
⎝2 ⎠
SERIAL INTERFACE
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register. 0 to 65,535 for AD5066 (16 bits).N = the DAC
resolution.
The AD5066 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as most DSPs. See Figure 3 for a
timing diagram of a typical write sequence.
DAC ARCHITECTURE
STANDALONE MODE
The DAC architecture of the AD5066 consists of two matched
DAC sections. A simplified circuit diagram is shown in Figure
5. The four MSBs of the 16-bit data word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one of
15 matched resistors to either GND or VREF buffer output. The
remaining 12 bits of the data word drive switches S0 to S11 of a
12-bit voltage mode R-2R ladder network.
VOUT
2R
2R
2R
2R
2R
2R
S0
S1
S11
E1
E2
E15
047762-027
VREF
12-BIT R-2R LADDER
05298-024
R
The ideal output voltage when using and internal reference is
given by
2R
TO OUTPUT
AMPLIFIER
R
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 6. Dac Ladder Structure
REFERENCE BUFFER
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5066 compatible with high speed
DSPs. On the 32nd falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change
in DAC register contents and/or a change in the mode of
operation. At this stage, the SYNC line can be kept low or be
brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when VIN = 2 V
than it does when VIN = 0.8 V, SYNC should be idled low
between write sequences for even lower power operation of the
part. As is mentioned previously, however, SYNC must be
brought high again just before the next write sequence.
The AD5066 operates with an external reference. Each of the
four onboard dac’s will have a dedicated voltage reference pin.
In either case the reference input pin has an input range of 2 V
to VDD. This input voltage is then used to provide a buffered
reference for the DAC core.
Rev. PrB | Page 12 of 20
Preliminary Technical Data
AD5066
Table 7. Command Definitions
C3
0
0
0
0
0
0
0
0
1
1
1
Command
C2 C1
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
C0
0
1
0
1
0
1
0
1
0
1
1
Description
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Set up DCEN register (Daisy chain enable)
Set up DIO direction and Value
Reserved
Table 8. Address Commands
Address (n)
A3
0
0
0
0
1
A2
0
0
0
0
1
A1
0
0
1
1
1
A0
0
1
0
1
1
Selected DAC
Channel
DAC A
DAC B
Reserved
Reserved
All DACs
Rev. PrB | Page 13 of 20
AD5066
Preliminary Technical Data
INPUT SHIFT REGISTER
SYNC INTERRUPT
The AD5066 input shift register is 32 bits wide (see Figure 8).
The first four bits are don’t cares. The next four bits are the
command bits, C3 to C0 (see Table 8), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 9) and finally the bit
data-word. The data-word comprises of 16-bit input code
followed by 4 don’t care bits for the AD5066 (see Figure 8).
These data bits are transferred to the DAC register on the 32nd
falling edge of SCLK.
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if SYNC is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Error! Reference
source not found.).
DB31 (MSB)
X
X
DB0 (LSB)
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
COMMAND BITS
05298-025
DATA BITS
ADDRESS BITS
Figure 8. AD5066 Input Register Content
POWER-ON RESET
The AD5066 contains a power-on reset circuit that controls the
output voltage during power-up. By connecting the POR pin
low, the AD5066 output powers up to 0 V; by connecting the
POR pin high, the AD5066 output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
(see Table 7). Any events on LDAC or CLR during power-on
reset are ignored.
When both Bit DB9 and Bit DB8, in the control register are set to
0, the part works normally with its normal power consumption
of TBD at 5 V. However, for the three power-down modes, the
supply current falls to TBD at 5 V (TBD at 3 V). Not only does
the supply current fall, but the output stage is also internally
switched from the output of the Dac to a resistor network of
known values. This has the advantage that the output
impedance of the part is known while the part is in powerdown mode. There are three different options. The output is
connected internally to GND through either a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-state). The output
stage is illustrated in Figure 9.
POWER-DOWN MODES
The bias generator, resistor string, and other associated linear
circuitry are shut down when the power-down mode is activated.
However, the contents of the DAC register are unaffected when
in power-down. The time to exit power-down is typically 2.5 μs
for VDD = 5 V and VDD = 3 V (see Error! Reference source not
found.).
The AD5066 contains four separate modes of operation.
Command 0100 is reserved for the power-down function (see
Table 7). These modes are software-programmable by setting
two bits, Bit DB9 and Bit DB8, in the control register (refer to
Table 12). Table 11 shows how the state of the bits corresponds
to the mode of operation of the device. Any or all DACs (DAC
A - DAC D) can be powered down to the selected mode by
setting the corresponding four bits (DB3, DB2, DB1, DB0) to 1.
See Table 12 for the contents of the input shift register during
power-down/
power-up operation.
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (LDAC Low) or to the value in the
DAC register before powering down (LDAC high).
Rev. PrB | Page 14 of 20
Preliminary Technical Data
AD5066
Table 9. DCEN (Daisy-Chain Enable) Register
(DB1)
0
1
(DB0)
0
0
Action
Standalone mode (default)
DCEN mode
Table 10. 32-Bit Input Shift Register Contents for Daisy-Chain Enable and Reference Set-Up Function
MSB
DB31 to DB28
X
Don’t cares
DB27
DB26
DB25
DB24
1
0
0
0
Command bits (C3 to C0)
DB23
X
DB22
DB21
DB20
X
X
X
Address bits (A3 to A0)
DB2 to DB19
X
Don’t cares
LSB
DB1
DB0
1/0
1/0
DCEN
register
Table 11. Modes of Operation
DB9
0
DB8
0
0
1
1
1
0
1
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
Table 12. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function
MSB
DB31 to
DB28
X
Don’t
cares
LSB
DB27
DB26
DB25
DB24
0
1
0
0
Command bits (C2 to C0)
DB23
DB22
DB21
DB20
X
X
X
X
Address bits (A3 to A0)—
don’t cares
DB10 to
DB19
X
Don’t
cares
DB9
DB8
PD1
PD0
Power-down
mode
Figure 9. Output Stage During Power-Down
Rev. PrB | Page 15 of 20
DB4 to
DB7
X
Don’t
cares
DB3
DB2
DB1
DB0
DAC D
DAC C
DAC B
DAC A
Power-down/power-up channel selection—
set bit to 1 to select
AD5066
Preliminary Technical Data
CLEAR CODE REGISTER
The AD5066 has a hardware CLR pin that is an asynchronous
clear input. The CLR input is falling edge sensitive. Bringing the
CLR line low clears the contents of the input register and the
DAC registers to the data contained in the user-configurable
CLR register and sets the analog outputs accordingly. (see Table
13) This function can be used in system calibration to load zero
scale, midscale, or full scale to all channels together. These clear
code values are user-programmable by setting two bits, Bit DB1
and Bit DB0, in the control register (see Table 13). The default
setting clears the outputs to 0 V. Command 0101 is reserved for
loading the clear code register (see Table 7).
The part exits clear code mode on the 32nd falling edge of the
next write to the part. If CLR is activated during a write
sequence, the write is aborted.
The CLR pulse activation time—the falling edge of CLR to when
the output starts to change—is typically TBD ns. However, if
outside the DAC linear region, it typically takes TBD ns after
executing CLR for the output to start changing (see Error!
Reference source not found.).
See Table 14 for contents of the input shift register during the
loading clear code register operation
LDAC FUNCTION
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin.
Synchronous LDAC: After new data is read, the DAC registers
are updated on the falling edge of the 32nd SCLK pulse. LDAC
can be permanently low or pulsed as in Figure 3
Asynchronous LDAC: The outputs are not updated at the same
time that the input registers are written to. When LDAC goes
low, the DAC registers are updated with the contents of the
input register.
Alternatively, the outputs of all DACs can be updated
simultaneously using the software LDAC function by writing to
Input Register n and updating all DAC registers. Command
0010 is reserved for this software LDAC function.
An LDAC register gives the user extra flexibility and control
over the hardware LDAC pin. This register allows the user to
select which combination of channels to simultaneously update
when the hardware LDAC pin is executed. Setting the LDAC bit
register to 0 for a DAC channel means that this channel’s update
is controlled by the LDAC pin. If this bit is set to 1, this channel
updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the LDAC pin.
It effectively sees the LDAC pin as being tied low. (See Table 15
for the LDAC register mode of operation.) This flexibility is
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
Writing to the DAC using command 0110 loads the 4-bit LDAC
register (DB3 to DB0). The default for each channel is 0; that is,
the LDAC pin works normally. Setting the bits to 1 means the
DAC channel is updated regardless of the state of the LDAC
pin. See Table 16 for the contents of the input shift register
during the load LDAC register mode of operation.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5066 should
have separate analog and digital sections. If the AD5066 is in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the AD5066.
The power supply to the AD5066 should be bypassed with 10 μF
and 0.1 μF capacitors. The capacitors should physically be as
close as possible to the device, with the 0.1 μF capacitor ideally
right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), such as is typical of common ceramic types of
capacitors. This 0.1 μF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique, where the component side of the
board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a 2-layer board.
Rev. PrB | Page 16 of 20
Preliminary Technical Data
AD5066
Table 13. Clear Code Register
DB1
CR1
0
0
1
1
Clear Code Register
DB0
CR0
0
1
0
1
Clears to Code
0x0000
0x8000
0xFFFF
No operation
Table 14. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
DB31 to DB28
X
Don’t cares
DB27
DB26
DB25
DB24
0
1
0
1
Command bits (C3 to C0)
DB23
X
DB22
DB21
DB20
X
X
X
Address bits (A3 to A0)
DB2 to DB19
X
Don’t cares
LSB
DB1
DB0
1/0
1/0
Clear code register
(CR1 to CR0)
Table 15. LDAC Overwrite Definition
Load DAC Register
LDAC Bits (DB3 to DB0)
LDAC Pin
LDAC Operation
0
1
Determined by LDAC pin
DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0.
1/0
X—don’t care
Table 16. 32-Bit Input Shift Register Contents for LDAC Overwrite Function
MSB
DB31
to
DB28
X
Don’t
cares
LSB
DB27
0
DB26
DB25
DB24
1
1
0
Command bits (C3 to C0)
DB23
DB22
DB21
X
X
X
Address bits (A3 to A0)—
don’t cares
DB20
X
Rev. PrB | Page 17 of 20
DB4
to
DB19
X
Don’t
cares
DB3
DB2
DB1
DB0
DAC D
DAC C
DAC B
DAC A
Setting LDAC bit to 1 override LDAC pin
AD5066
Preliminary Technical Data
MICROPROCESSOR INTERFACING
AD5066 to 80C51/80L51 Interface
AD5066 to Blackfin® ADSP-BF53X Interface
Figure 12 shows a serial interface between the AD5066 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/ 80L51 drives SCLK of the AD5066,
and RxD drives the serial data line of the part. The SYNC signal
is again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to the
AD5066, P3.3 is taken low. The 80C51/80L51 transmit data in
8-bit bytes only; thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left low after the
first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 output
the serial data in a format that has the LSB first. The AD5066
must receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
ADSP-BF53x1
TFS0
AD5066
1
SYNC
DTOPRI
DIN
TSCLK0
SCLK
1ADDITIONAL
0000-049
80C51/80L511
PINS OMITTED FOR CLARITY.
Figure 10. AD5066 to Blackfin ADSP-BF53X Interface
AD5066 to 68HC11/68L11 Interface
Figure 11 shows a serial interface between the AD5066 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5066, and the MOSI output drives
the serial data line of the DAC.
AD5066
1
P3.3
SYNC
TxD
SCLK
RxD
DIN
1ADDITIONAL
PINS OMITTED FOR CLARITY.
0000-052
Figure 10 shows a serial interface between the AD5066 and the
Blackfin ADSP-BF53X microprocessor. The ADSP-BF53X
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5066, the setup for the interface is as follows: DT0PRI
drives the DIN pin of the AD5066, while TSCLK0 drives the
SCLK of the parts. The SYNC is driven from TFS0.
Figure 12. AD5066 to 80C512/80L51 Interface
AD5066 to MICROWIRE Interface
AD5066
PC7
SYNC
SCK
SCLK
DIN
1ADDITIONAL PINS OMITTED FOR CLARITY.
MICROWIRE1
CS
SYNC
SK
DIN
SO
SCLK
Figure 11. AD5066 to 68HC11/68L11 Interface
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/ 68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5066, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
Rev. PrB | Page 18 of 20
AD5066
1ADDITIONAL
PINS OMITT ED FOR CLARITY.
Figure 13. AD5066/45/654 to MICROWIRE Interface
0000-049
MOSI
Figure 13 shows an interface between the AD5066 and any
MICROWIRE-compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the
AD5025/45/65 on the rising edge of the SCLK.
1
0000-050
68HC11/68L111
Preliminary Technical Data
AD5066
APPLICATIONS
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD5066
+5 V output.
Because the supply current required by the AD5066 is extremely
low, an alternative option is to use a voltage reference to supply
the required voltage to the parts (see Figure 14). This is
especially useful if the power supply is quite noisy or if the
system supply voltages are at some value other than 5 V or 3 V,
for example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5066. If the low dropout REF195 is used, it
must supply 500 μA of current to the AD5066, with no load on
the output of the DAC. When the DAC output is loaded, the
REF195 also needs to supply the current to the load. The total
current required (with a 5 kΩ load on the DAC output) is
+5V
R2 = 10kΩ
+5V
AD820/
OP295
VDD
10µF
SCLK
–5V
0000-053
USING THE AD5066 WITH A
GALVANICALLY ISOLATED INTERFACE
In process control applications in industrial environments,
it is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where
the DAC is functioning. iCoupler® provides isolation in excess
of 2.5 kV. The AD5066 uses a 3-wire serial logic interface, so the
ADuM1300 three-channel digital isolator provides the required
isolation (see Figure 16). The power supply to the part also
needs to be isolated, which is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5066.
15V
SYNC
AD5066
Figure 15. Bipolar Operation with the AD5066
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 3 ppm (15 μV) error for the 1.5 mA current
drawn from it. This corresponds to a 0.196 LSB error.
5V
VDD
AD5066
VOUT = 0V TO 5V
DIN
0000-053
THREE-WIRE
SERIAL
INTERFACE
0.1µF
±5V
VOUT
THREE-WIRE
SERIAL
INTERFACE
500 μA + (5 V/5 kΩ) = 1.5 mA
REF195
R1 = 10kΩ
5V
REGULATOR
10µF
POWER
0.1µF
Figure 14. REF195 as Power Supply to the AD5025/45/65
BIPOLAR OPERATION USING THE AD5066
The AD5066 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 15. The circuit gives an output voltage range of ±5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
SCLK
VIA
VOA
ADuM1300
SCLK
VDD
AD5066
SDI
VIB
VOB
SYNC
DATA
VIC
VOC
DIN
VOUT
0000-055
GND
⎡
⎛ D ⎞ ⎛ R1 + R2 ⎞
⎛ R2 ⎞⎤
VO = ⎢VDD × ⎜
⎟×⎜
⎟⎥
⎟ − VDD × ⎜
65
,
536
R1
⎝ R1 ⎠⎦
⎠
⎝
⎝
⎠
⎣
Figure 16. AD5025/45/65 with a Galvanically Isolated Interface
where D represents the input code in decimal (0 to 65,535).
With VDD = 5 V, R1 = R2 = 10 kΩ,
⎛ 10 × D ⎞
VO = ⎜
⎟ −5V
⎝ 65,536 ⎠
This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a
Rev. PrB | Page 19 of 20
AD5066
Preliminary Technical Data
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 17. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5066BRUZ-1 1
AD5066BRUZ-1REEL7
AD5066ARUZ
AD5066ARUZ-REEL7
Eval-AD5066 EBZ
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation board
Package
Option
RU-16
RU-16
RU-16
RU-16
Power-On
Reset to Code
Zero
Zero
Zero
Zero
Accuracy
±1 LSB INL
±1 LSB INL
±4 LSB INL
±4 LSB INL
Resolution
16 bits
16 bits
16 bits
16 bits
Z = Pb-free part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06845-0-6/07(PrB)
T
T
Rev. PrB | Page 20 of 20