Flexible Clock Translator for GPON, Base
Station, SONET/SDH, T1/E1, and Ethernet
AD9553
FEATURES
GENERAL DESCRIPTION
Input frequencies from 8 kHz to 710 MHz
Output frequencies up to 810 MHz
Preset pin-programmable frequency translation ratios cover
popular wireline and wireless frequency applications,
including xDSL, T1/E1, BITS, SONET, and Ethernet.
Arbitrary frequency translation ratios via SPI port
On-chip VCO
Accepts a crystal resonator for holdover applications
Two single-ended (or one differential) reference input(s)
Two output clocks (independently programmable as LVDS,
LVPECL, or CMOS)
SPI-compatible, 3-wire programming interface
Single supply (3.3 V)
Very low power: <450 mW (under most conditions)
Small package size (5 mm × 5 mm)
Exceeds Telcordia GR-253 Category II OC-48 jitter
generation, transfer, and tolerance specifications
The AD9553 is a phase-locked loop (PLL) based clock translator
designed to address the needs of passive optical networks (PON)
and base stations. The device employs an integer-N PLL to
accommodate the applicable frequency translation requirements.
The user supplies up to two single-ended input reference signals
or one differential input reference signal via the REFA and REFB
inputs. The device supports holdover applications by allowing the
user to connect a 25 MHz crystal resonator to the XTAL input.
The AD9553 is pin programmable, providing a matrix of
standard input/output frequency translations from a list of 15
possible input frequencies to a list of 51 possible output frequency
pairs (OUT1 and OUT2). The device also has a 3-wire SPI
interface, enabling the user to program custom input-to-output
frequency translations.
The AD9553 output is compatible with LVPECL, LVDS, or
single-ended CMOS logic levels, although the AD9553 is
implemented in a strictly CMOS process.
APPLICATIONS
The AD9553 operates over the extended industrial temperature
range of −40°C to +85°C.
Cost effective replacement of high frequency VCXO, OCXO,
and SAW resonators
Extremely flexible frequency translation for SONET/SDH,
Gb Ethernet, Fibre Channel, DRFI/DOCSIS, and
PON/EPON/GPON
Wireless infrastructure
Test and measurement (including handheld devices)
BASIC BLOCK DIAGRAM
AD9553
REFA
REFB
INPUT
FREQUENCY
SOURCE
SELECTOR
PLL
OUTPUT
CIRCUITRY
OUT2
OUT1
XTAL
08565-001
PIN-DEFINED AND SERIAL PROGRAMMING
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD9553
TABLE OF CONTENTS
Features .............................................................................................. 1
Preset Frequencies .......................................................................... 14
Applications ....................................................................................... 1
Device Control Modes ................................................................... 17
General Description ......................................................................... 1
Theory of Operation ...................................................................... 19
Basic Block Diagram ........................................................................ 1
General Description ................................................................... 19
Revision History ............................................................................... 2
Description of Functional Blocks............................................. 19
Specifications..................................................................................... 3
Jitter Tolerance ............................................................................ 25
Power Consumption .................................................................... 3
Output/Input Frequency Relationship .................................... 25
Logic Input Pins ............................................................................ 3
Calculating Divider Values ....................................................... 26
Logic Output Pins......................................................................... 3
Low Dropout (LDO) Regulators .............................................. 27
RESET Pin ..................................................................................... 4
Automatic Power-On Reset ...................................................... 27
Reference Clock Input Characteristics ...................................... 4
Applications Information .............................................................. 28
VCO Characteristics .................................................................... 5
Thermal Performance ................................................................ 28
Crystal Input Characteristics ...................................................... 5
Serial Control Port ......................................................................... 29
Output Characteristics ................................................................. 6
Serial Control Port Pin Descriptions ....................................... 29
Jitter Characteristics ..................................................................... 7
Operation of the Serial Control Port ....................................... 29
Serial Control Port ....................................................................... 8
Instruction Word (16 Bits) ........................................................ 30
Serial Control Port Timing ......................................................... 8
MSB/LSB First Transfers ........................................................... 30
Absolute Maximum Ratings............................................................ 9
Register Map ................................................................................... 32
ESD Caution .................................................................................. 9
Register Map Descriptions ........................................................ 34
Pin Configuration and Function Descriptions ........................... 10
Outline Dimensions ....................................................................... 41
Typical Performance Characteristics ........................................... 11
Ordering Guide .......................................................................... 41
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
AD9553
SPECIFICATIONS
POWER CONSUMPTION
Table 1.
Parameter
TOTAL CURRENT
Min
Typ
162
Max
185
Unit
mA
93
106
mA
35
36
29
41
42
34
mA
mA
mA
35
36
29
41
42
34
mA
mA
mA
Typ
Max
Unit
Test Conditions/Comments
V
For the CMOS inputs, a static Logic 1 results
from either a pull-up resistor or no connection.
VDD CURRENT BY PIN
Pin 18
Pin 21
LVDS Configured Output
LVPECL Configured Output
CMOS Configured Output
Pin 28
LVDS Configured Output
LVPECL Configured Output
CMOS Configured Output
Test Conditions/Comments
Tested with both output channels active at
maximum output frequency. LVPECL and
LVDS outputs use a 100 Ω termination
between both pins of the output driver.
Tested with both output channels active at
maximum output frequency. LVPECL and
LVDS outputs use a 100 Ω termination
between both pins of the output driver.
LOGIC INPUT PINS
Table 2.
Parameter
INPUT CHARACTERISTICS 1
Logic 1 Voltage, VIH
Min
1.02
Logic 0 Voltage, VIL
Logic 1 Current, IIH
Logic 0 Current, IIL
1
0.64
3
17
V
μA
μA
The A[3:0] and Y[5:0] pins have 100 kΩ internal pull-up resistors. The OM[2:0] pins have 40 kΩ pull-up resistors when the device is not in SPI mode.
LOGIC OUTPUT PINS
Table 3.
Parameter
OUTPUT CHARACTERISTICS
Output Voltage High, VOH
Output Voltage Low, VOL
Min
Typ
Max
Unit
Test Conditions/Comments
0.19
V
V
Tested at 1 mA load current
Tested at 1 mA load current
2.7
Rev. 0 | Page 3 of 44
AD9553
RESET PIN
Table 4.
Parameter
INPUT CHARACTERISTICS 1
Input Voltage High, VIH
Input Voltage Low, VIL
Input Current High, IINH
Input Current Low, IINL
MINIMUM PULSE WIDTH LOW
1
Min
Typ
Max
Unit
Test Conditions/Comments
0.3
31
0.85
12.5
43
V
V
μA
μA
μs
Tested with an active source driving the RESET pin.
Max
Unit
Test Conditions/Comments
250
710
MHz
MHz
769
mV
1.96
150
The RESET pin has a 100 kΩ internal pull-up resistor.
REFERENCE CLOCK INPUT CHARACTERISTICS
Table 5.
Parameter
DIFFERENTIAL INPUT
Input Frequency Range
Common-Mode Internally Generated
Input Voltage
Differential Input Voltage Sensitivity
Min
0.008
613
Pulse Width Low
Pulse Width High
2× FREQUENCY MULTIPLIER
692
250
Differential Input Resistance
Differential Input Capacitance
Duty Cycle
Pulse Width Low
Pulse Width High
Pulse Width Low
Pulse Width High
CMOS SINGLE-ENDED INPUT
Input Frequency Range
Input High Voltage 1
Input Low Voltage1
Input High Current
Input Low Current
Input Capacitance
Duty Cycle
Typ
mV p-p
5
3
kΩ
pF
1.6
1.6
0.64
0.64
ns
ns
ns
ns
0.008
1.05
Assumes minimum LVDS input level and requires
bypassing of the /5 divider and 2× multiplier.
Use ac coupling to preserve the internal dc bias of the
differential input.
Capacitive coupling required; can accommodate singleended input by ac grounding unused input; the
instantaneous voltage on either pin must not exceed the
3.3 V dc supply rails.
200
0.98
0.04
0.03
3
Pulse width high and pulse width low establish the
bounds for duty cycle.
Up to 250 MHz.
Up to 250 MHz.
Beyond 250 MHz, up to 710 MHz.
Beyond 250 MHz, up to 710 MHz.
MHz
V
V
μA
μA
pF
Pulse width high and pulse width low establish the
bounds for duty cycle.
2
2
125
ns
ns
MHz
1
To avoid excessive reference spurs, the 2× multiplier
requires 48% to 52% duty cycle. Reference clock input
frequencies greater than 125 MHz require the use of the
/5 divider.
The single-ended CMOS input is 3.3 V compatible. In the case of ac-coupling, the user must bias the input at 1.0 V dc.
Rev. 0 | Page 4 of 44
AD9553
VCO CHARACTERISTICS
Table 6.
Parameter
FREQUENCY RANGE
VCO GAIN
VCO TRACKING RANGE
VCO CALIBRATION TIME
Min
3350
Typ
Max
4050
45
±300
Unit
MHz
MHz/V
ppm
Test Conditions/Comments
As measured from completion of the VCO calibration
command (the rising edge of CS (Pin 12)) until the rising
edge of LOCKED (Pin 20).
Applies for A[3:0] = 0001 to 1100 or for A[3:0] = 1111.
Low BW Setting (170 Hz)
13.3 kHz PFD Frequency
16 kHz PFD Frequency
High BW Setting (75 kHz)
2.64 MHz PFD Frequency
4.86 MHz PFD Frequency
PLL LOCK TIME
214
176
ms
ms
1.46
0.80
ms
ms
Applies for A[3:0] = 1101 to 1110.
Using the pin selected frequency settings. Lock time is
from the rising edge of the RESET pin to the rising edge of
the LOCKED pin.
Applies for A[3:0] = 0001 to 1100 or for A[3:0] = 1111.
Low BW Setting (170 Hz)
13.3 kHz PFD Frequency
16 kHz PFD Frequency
High BW Setting (75 kHz)
2.64 MHz PFD Frequency
4.86 MHz PFD Frequency
214
176
ms
ms
1.50
0.89
ms
ms
Applies for A[3:0] = 1101 to 1110.
CRYSTAL INPUT CHARACTERISTICS
Table 7.
Parameter
CRYSTAL FREQUENCY
Range
Tolerance
CRYSTAL MOTIONAL RESISTANCE
CRYSTAL LOAD CAPACITANCE
Min
Typ
Max
Unit
Test Conditions/Comments
10
25
52
MHz
When using the pin selected frequency settings, the device
requires a 25 MHz crystal to support holdover functionality.
20
100
ppm
Ω
pF
10
Rev. 0 | Page 5 of 44
Using a crystal with a specified load capacitance other than 10 pF
(8 pF to 24 pF) is possible, but necessitates using the SPI port.
AD9553
OUTPUT CHARACTERISTICS
Table 8.
Parameter
LVPECL MODE
Differential Output Voltage
Swing
Common-Mode Output
Voltage
Frequency Range
Duty Cycle
Rise/Fall Time 1 (20% to 80%)
LVDS MODE
Differential Output Voltage
Swing
Balanced, VOD
Unbalanced, ΔVOD
Offset Voltage
Common Mode, VOS
Common-Mode Difference,
ΔVOS
Short-Circuit Output Current
Frequency Range
Duty Cycle
Rise/Fall Time1 (20% to 80%)
CMOS MODE
Output Voltage High, VOH
IOH = 10 mA
IOH = 1 mA
Output Voltage Low, VOL
IOL = 10 mA
IOL = 1 mA
Frequency Range
Duty Cycle
Rise/Fall Time1 (20% to 80%)
1
Min
Typ
Max
Unit
Test Conditions/Comments
690
800
890
mV
Output driver static (for dynamic performance, see Figure 13).
VDD − 1.66
VDD − 1.34
VDD − 1.01
V
Output driver static.
255
810
60
305
MHz
%
ps
Up to 805 MHz output frequency.
100 Ω termination between the output driver pins.
0
40
Output driver static (for dynamic performance, see Figure 13).
297
398
8.3
mV
mV
Voltage swing between output pins; output driver static.
Absolute difference between voltage swing of normal pin and
inverted pin; output driver static.
1.17
1.35
7.3
V
mV
Output driver static.
Voltage difference between output pins; output driver static.
24
810
60
355
mA
MHz
%
ps
Up to 805 MHz output frequency.
100 Ω termination between the output driver pins.
17
0
40
285
Output driver static; standard drive strength setting.
2.8
2.8
V
V
Output driver static; standard drive strength setting.
0
45
500
0.5
0.3
200
V
V
MHz
55
745
%
ps
The listed values are for the slower edge (rise or fall).
Rev. 0 | Page 6 of 44
3.3 V CMOS; standard drive strength setting. Output toggle
rates in excess of the maximum are possible, but with reduced
amplitude (see Figure 12).
At maximum output frequency.
3.3 V CMOS; standard drive strength setting; 10 pF load.
AD9553
JITTER CHARACTERISTICS
Table 9.
Parameter
JITTER GENERATION
12 kHz to 20 MHz
LVPECL Output
LVDS Output
CMOS Output
LVPECL Output
LVDS Output
CMOS Output
Min
Typ
1.31
1.32
1.24
1.28
1.29
1.26
Max
Unit
Test Conditions/Comments
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
Input = 122.88 MHz, output = 155.52 MHz.
Input = 122.88 MHz, output = 155.52 MHz.
Input = 122.88 MHz, output = 155.52 MHz.
Input = 19.44 MHz, output = 245.76 MHz.
Input = 19.44 MHz, output = 245.76 MHz.
Input = 19.44 MHz, output = 245.76 MHz. See Figure 12 regarding
CMOS toggle rates above 250 MHz.
50 kHz to 80 MHz
LVPECL Output
LVDS Output
CMOS Output
LVPECL Output
LVDS Output
CMOS Output
0.44
0.45
0.39
0.75
0.76
0.44
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
Input = 122.88 MHz, output = 155.52 MHz.
Input = 122.88 MHz, output = 155.52 MHz.
Input = 122.88 MHz, output = 155.52 MHz.
Input = 122.88 MHz, output = 155.52 MHz.
Input = 19.44 MHz, output = 245.76 MHz.
Input = 19.44 MHz, output = 245.76 MHz.
Input = 19.44 MHz, output = 245.76 MHz. See Figure 12 regarding
CMOS toggle rates above 250 MHz.
JITTER TRANSFER BANDWIDTH
Low BW Setting
High BW Setting
JITTER TRANSFER PEAKING
Low BW Setting
High BW Setting
170
Hz
75
kHz
1.3
dB
0.08
dB
See the Typical Performance Characteristics section.
Applies to all input frequency pin programming configurations that
use 170 Hz loop bandwidth per Table 17.
Applies to all input frequency pin programming configurations that
use 75 kHz loop bandwidth per Table 17.
See the Typical Performance Characteristics section
Applies to all input frequency pin programming configurations that
use 170 Hz loop bandwidth per Table 17.
Applies to all input frequency pin programming configurations that
use 75 kHz loop bandwidth per Table 17.
Rev. 0 | Page 7 of 44
AD9553
SERIAL CONTROL PORT
Table 10.
Parameter
CS
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO
Input
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Output
Output Logic 1 Voltage
Output Logic 0 Voltage
Min
Typ
Max
1.6
0.5
0.03
2
2
1.6
0.5
2
0.03
2
1.6
0.5
1
1
2
2.8
0.3
Unit
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
SERIAL CONTROL PORT TIMING
Table 11.
Parameter
SCLK
Clock Rate, 1/tCLK
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO, tDV
CS to SCLK Setup (tS) and Hold (tH)
CS Minimum Pulse Width High
Limit
Unit
50
3
3
4
0
13
0
6.4
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns min
Rev. 0 | Page 8 of 44
Test Conditions/Comments
1 mA load current
1 mA load current
AD9553
ABSOLUTE MAXIMUM RATINGS
ESD CAUTION
Table 12.
Parameter
Supply Voltage (VDD)
Maximum Digital Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
3.6 V
−0.5 V to VDD + 0.5 V
−65°C to +150°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 9 of 44
AD9553
32
31
30
29
28
27
26
25
Y3
Y2
Y1
Y0
VDD
OUT1
OUT1
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD9553
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
GND
OUT2
OUT2
VDD
LOCKED
LDO
VDD
LDO
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
08565-002
XTAL
XTAL
SEL REFB
OM2/CS
OM1/SCLK
OM0/SDIO
RESET
FILTER
9
10
11
12
13
14
15
16
Y4
Y5
A0
A1
A2
A3
REFA
REFB/REFA
Figure 2. Pin Configuration
Table 13. Pin Function Descriptions
Pin No.
29, 30, 31,
32, 1, 2
3, 4, 5, 6
Mnemonic
Y0, Y1, Y2, Y3,
Y4, Y5
A0, A1, A2, A3
Type 1
I
7
REFA
I
8
REFB/REFA
I
9, 10
XTAL
I
11
SEL REFB
I
12
OM2/CS
I
13
OM1/SCLK
I
14
OM0/SDIO
I/O
15
RESET
I
16
FILTER
I/O
17, 19
18, 21, 28
20
26, 22
27, 23
24, 25
EP
LDO
VDD
LOCKED
OUT1, OUT2
OUT1, OUT2
GND
Exposed die pad
P/O
P
O
O
O
P
1
I
Description
Control Pins. These pins select one of 51 preset output frequency combinations for OUT1 and
OUT2. Note that when all six control pins are Logic 0, SPI programming is active.
Control Pins. These pins select one of 15 preset input reference frequencies. Note that when all four
control pins are Logic 0, SPI programming is active.
Reference Clock Input. Connect this pin to a single-ended active clock input signal. Alternatively,
this pin is the noninverted part of a differential clock input signal.
Reference Clock Input. Connect this pin to a single-ended active clock input signal. Alternatively,
this pin is the inverted part of a differential clock input signal.
Crystal Resonator Input. Connect a crystal resonator across these pins. When using the preset
input/output frequencies via the Y[5:0] and A[3:0] pins, the crystal must have a resonant frequency
of 25 MHz with a specified load capacitance of 10 pF.
Control Pin. This pin allows manual selection of REFA (Logic 0) or REFB (Logic 1) as the active
reference assuming that the desired reference signal is present. Note that this pin is nonfunctional
when Register 0x29[5] = 1.
Digital Input. When the device is not in SPI mode, this pin is an output mode control pin (OM2) with
an internal 40 kΩ pull-up resistor. The OM2 pin, in conjunction with the OM0 and OM1 pins, allows
the user to select 1-of-8 output configurations (see Table 21). In SPI mode, this pin is an active low
chip select (CS) with no internal pull-up resistor.
Digital Input. When the device is not in SPI mode, this pin is an output mode control pin (OM1) with
an internal 40 kΩ pull-up resistor. The OM1 pin, in conjunction with the OM0 and OM2 pins, allows
the user to select 1-of-8 output configurations (see Table 21). In SPI mode, this pin is the serial data
clock (SCLK) with no internal pull-up resistor.
Digital Input/Output. When the device is not in SPI mode, this pin is an input only and functions as
an output mode control pin (OM0) with an internal 40 kΩ pull-up resistor. The OM0 pin, in
conjunction with the OM1 and OM2 pins, allows the user to select 1-of-8 output configurations (see
Table 21). In SPI mode, this pin is the serial data input/output (SDIO) with no internal pull-up
resistor.
Digital Input, Active Low with a 100 kΩ Internal Pull-Up Resistor. Resets the internal logic to default
states (see the Automatic Power-On Reset section).
Loop Filter Node for the PLL. Connect external loop filter components (see Figure 22) from this pin
to Pin 17 (LDO).
LDO Decoupling Pins. Connect a 0.47 μF decoupling capacitor from each of these pins to ground.
Power Supply Connection: 3.3 V Analog Supply.
Active High Locked Status Indicator for the PLL.
Complementary Square Wave Clocking Outputs.
Square Wave Clocking Outputs.
Ground.
The exposed die pad must be connected to GND.
I = input, I/O = input/output, O = output, P = power, and P/O = power/output.
Rev. 0 | Page 10 of 44
AD9553
TYPICAL PERFORMANCE CHARACTERISTICS
–30
–30
JITTER BANDWIDTH JITTER (rms)
12kHz TO 20MHz
1.30ps
50kHz TO 80MHz
0.62ps
–40
–50
–50
–80
–90
–100
–110
–120
–70
–80
–90
–100
–110
–120
–130
–130
–140
–140
–150
–150
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
–160
10
100
–30
JITTER BANDWIDTH JITTER (rms)
12kHz TO 20MHz
1.25ps
50kHz TO 80MHz
0.63ps
–40
–50
–50
10M
100M
–90
–100
–110
–120
–70
–80
–90
–100
–110
–120
–130
–130
–140
–140
–150
–150
100
1k
10k
100k
1M
10M
100M
–160
10
100
Figure 4. Phase Noise, Pin Programmed
(fREF = 61.44 MHz, fOUT1 = 122.88 MHz)
–70
10k
100k
1M
10M
100M
Figure 7. Phase Noise, Pin Programmed
(fREF = 8 kHz, fOUT1 = 155.52 MHz)
5
JITTER BANDWIDTH JITTER (rms)
12kHz TO 20MHz
0.73ps
50kHz TO 80MHz
0.51ps
–80
1k
FREQUENCY OFFSET FROM CARRIER (Hz)
08565-207
PHASE NOISE (dBc/Hz)
–80
FREQUENCY OFFSET FROM CARRIER (Hz)
0
JITTER TRANSFER
–90
–5
–120
–130
2
–10
–15
–20
–140
–25
–150
–160
100
1
JITTER PEAKING
0
–1
–2
–3
0
1k
10k
100k
1M
10M
FREQUENCY OFFSET FROM CARRIER (Hz)
100M
Figure 5. Phase Noise, Pin Programmed
(fREF = 77.76 MHz, fOUT1 = 622.08 MHz)
–30
10
25
50 75 100 125 150 175
FREQUENCY OFFSET (Hz)
100
FREQUENCY OFFSET (Hz)
Figure 8. Jitter Transfer, Loop Bandwidth = 170 Hz
Rev. 0 | Page 11 of 44
1k
08565-028
–110
MAGNITUDE (dB)
MAGNITUDE (dB)
–100
08565-205
PHASE NOISE (dBc/Hz)
1M
–60
–70
08565-204
PHASE NOISE (dBc/Hz)
100k
JITTER BANDWIDTH JITTER (rms)
12kHz TO 20MHz
1.27ps
50kHz TO 80MHz
0.54ps
–40
–60
–160
10
10k
Figure 6. Phase Noise, Pin Programmed
(fREF = 19.44 MHz, fOUT1 = 155.52 MHz)
Figure 3. Phase Noise, Pin Programmed
(fXTAL = 25 MHz, fOUT1 = 156.25 MHz)
–30
1k
FREQUENCY OFFSET FROM CARRIER (Hz)
08565-206
PHASE NOISE (dBc/Hz)
–60
–70
08565-203
PHASE NOISE (dBc/Hz)
–60
–160
10
JITTER BANDWIDTH JITTER (rms)
12kHz TO 20MHz
1.26ps
50kHz TO 80MHz
0.49ps
–40
AD9553
5
4.0
0
3.5
–5
5pF
OUTPUT VOLTAGE (V p-p)
JITTER TRANSFER
1
–25
–30
–35
JITTER PEAKING
0
–1
–2
–3
10
–40
–45
10
2.0
20pF
1.5
1.0
0.5
20 30 40 50 60 70
FREQUENCY OFFSET (kHz)
80
100
1k
FREQUENCY OFFSET (kHz)
0
08565-029
–20
10pF
2.5
0
200
300
400
500
600
FREQUENCY (MHz)
Figure 9. Jitter Transfer, Loop Bandwidth = 75 kHz
Figure 12. Peak-to-Peak Output Voltage vs. Frequency,
CMOS
35
1800
LVPECL
1600
30
LVPECL
LVDS STRONG
OUTPUT VOLTAGE (mV p-p)
SUPPLY CURRENT (mA)
100
08565-211
–15
MAGNITUDE (dB)
MAGNITUDE (dB)
–10
3.0
25
20
LVDS WEAK
15
10
1400
1200
LVDS STRONG
1000
800
LVDS WEAK
600
400
5
100
200
300
400
500
600
700
800
900
FREQUENCY (MHz)
0
08565-209
0
0
100
200
300
400
500
600
700
800
900
FREQUENCY (MHz)
Figure 10. Supply Current vs. Output Frequency,
LVPECL and LVDS (10 pF Load)
08565-212
200
0
Figure 13. Peak-to-Peak Output Voltage vs. Frequency,
LVPECL and LVDS (100 Ω Load)
30
51
10pF
20pF
50
25
DUTY CYCLE (%)
20
5pF
15
10
48
5pF
20pF
47
46
45
44
5
0
0
100
200
300
400
500
FREQUENCY (MHz)
600
Figure 11. Supply Current vs. Output Frequency,
CMOS (10 pF Load)
42
0
100
200
300
400
500
FREQUENCY (MHz)
Figure 14. Duty Cycle vs. Output Frequency, CMOS
Rev. 0 | Page 12 of 44
600
08565-213
43
08565-210
SUPPLY CURRENT (mA)
49
10pF
AD9553
60
59
LVPECL
58
LVDS
STRONG
DUTY CYCLE (%)
57
56
2
55
LVDS WEAK
54
53
51
0
100
200
300
400
500
600
700
800
900
FREQUENCY (MHz)
500ps/DIV
08565-214
125mV/DIV
50
08565-216
52
Figure 17. Typical Output Waveform, LVDS
(800 MHz, 3.5 mA Drive Current)
Figure 15. Duty Cycle vs. Output Frequency,
LVPECL and LVDS (100 Ω Load)
2
500ps/DIV
500mV/DIV
Figure 16. Typical Output Waveform, LVPECL (800 MHz)
1.25ns/DIV
Figure 18. Typical Output Waveform, CMOS
(250 MHz, 10 pF Load)
Rev. 0 | Page 13 of 44
08565-217
200mV/DIV
08565-215
2
AD9553
PRESET FREQUENCIES
The frequency selection pins (A[3:0] and Y[5:0]) allow the user
to hardwire the device for preset input and output frequencies
based on the pin logic states (see Figure 20). The pins decode
ground or open connections as Logic 0 or Logic 1, respectively.
The same settings apply to both the REFA and REFB input
paths. Furthermore, the /5, ×2, and R values cause the PLL
input frequency to be either 16 kHz or 40/3 kHz. The exceptions are A[3:0] = 1101 and 1110, which yield a PLL input
frequency of 155.52/59 MHz and 4.86 MHz, respectively.
Note that the XTAL input is not available for holdover
functionality in the A[3:0] = 1101 and 1110 configurations,
thus the undefined RXO value.
In order to have access to the device control registers via the SPI
port, the user must select Y[5:0] = 000000 and/or A[3:0] = 0000.
Doing so causes Pin 12 through Pin 14 to function as SPI port
control pins instead of output mode control pins (see the Output
Driver Mode Control section). Note that after selecting SPI
mode, the user must write a Logic 1 to Bit 0 of Register 0x32 and
Register 0x34 to enable the registers as the source of the OUT1 and
OUT2 mode control bits (see Figure 23 and the Output Driver
Mode Control section).
The Y[5:0] pins allow the user to select one of 51 output
frequency combinations (fOUT1 and fOUT2) per Table 15.
The device sets the appropriate P0, P1, and P2 settings based
on the logic levels applied to the Y[5:0] pins. Note, however,
that selections 101101 through 110010 require A[3:0] = 1101
and selection 110011 requires A[3:0] = 1110.
The A[3:0] pins allow the user to select one of fifteen input
reference frequencies as shown in Table 14. The device sets the
appropriate divide-by-5 (/5A, /5B), multiply-by-2 (×2A, ×2B),
and input divider (RA, RB, RXO) values based on the logic levels
applied to the A[3:0] pins.
The value (N) of the PLL feedback divider and the control
setting for the charge pump current (CP) depend on a
combination of both the A[3:0] and Y[5:0] pin settings as
shown in Table 16.
Table 14. Pin-Configured Input Frequency 1
Pins A[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101 2
1110 3
1111
1
2
3
fREFA, fREFB (MHz)
/5A, /5B
×2A, ×2B
0.008
1.536
2.048
16.384
19.44
25
38.88
61.44
77.76
122.88
125
1.544
155.52
77.76
200/3
–
–
–
–
–
–
–
–
–
–
On
–
–
–
–
On
–
–
–
–
On
–
–
–
–
On
On
–
–
–
RA, RB (Decimal)
SPI mode
1
96
128
1024
1215
3125
2430
3840
4860
7680
3125
193
59
16
5000
For /5 and ×2 frequency scalers, – indicates bypassed and On indicates active.
Pins A[3:0] = 1101 only works with Pins Y[5:0] =101101 through 110010.
Pins A[3:0] = 1110 only works with Pins Y[5:0] =110011.
Rev. 0 | Page 14 of 44
RXO (Decimal)
3125
3125
3125
3125
3125
3125
3125
3125
3125
3125
3125
3125
Undefined
Undefined
3750
AD9553
Table 15. Pin-Configured Output Frequency
Pins Y[5:0]
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100 to 111111
1
fOUT1 (MHz)
fOUT2 (MHz)
P0
P1
P2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Undefined
3
3
3
3
3
3
6
6
6
6
6
12
12
12
12
45
45
45
360
360
480
4
4
4
5
5
25
4
4
4
8
8
32
4
4
4
4
4
6
6
6
12
12
400
1
1
1
2
2
4
1
Undefined
3
6
12
45
360
480
6
12
45
360
480
12
45
360
480
45
360
480
360
480
480
4
5
25
5
25
25
4
8
32
8
32
32
4
5
10
300
400
6
12
24
12
24
400
1
2
4
2
4
4
1
Undefined
SPI mode
245.76
245.76
245.76
245.76
245.76
245.76
122.88
122.88
122.88
122.88
122.88
61.44
61.44
61.44
61.44
16.384
16.384
16.384
2.048
2.048
1.536
156.25
156.25
156.25
125
125
25
155.52
155.52
155.52
77.76
77.76
19.44
153.6
153.6
153.6
153.6
153.6
100
100
100
50
50
1.544
Fo 1
Fo1
Fo1
Fo/21
Fo/21
Fo/41
622.08
Undefined
245.76
122.88
61.44
16.384
2.048
1.536
122.88
61.44
16.384
2.048
1.536
61.44
16.384
2.048
1.536
16.384
2.048
1.536
2.048
1.536
1.536
156.25
125
25
125
25
25
155.52
77.76
19.44
77.76
19.44
19.44
153.6
122.88
61.44
2.048
1.536
100
50
25
50
25
1.544
Fo1
Fo/21
Fo/41
Fo/21
Fo/41
Fo/41
622.08
Undefined
Fo = 39,191.04/59 MHz.
Rev. 0 | Page 15 of 44
AD9553
Table 16. Pin Configuration vs. N 1 and CP 2
Pins A[3:0]
0001 to 1100
1101
1110
1111
1
2
Pins Y[5:0]
000001 to 010101
010110 to 011011
011100 to 100001
100010 to 100110
100111 to 101011
101100
101101 to 111111
000001 to 101100
101101 to 110010
110010 to 111111
000001 to 110010
110011
110100 to 111111
000001 to 010101
010110 to 011011
011100 to 100001
100010 to 100110
100111 to 101011
101100
101101 to 111111
N
230,400
234,375
233,280
230,400
225,000
231,600
Undefined
Undefined
Undefined
Undefined
255
Undefined
Undefined
121
Undefined
145
145
145
145
145
145
Undefined
1512
Undefined
Undefined
768
Undefined
276,480
281,250
279,936
276,480
270,000
277,920
Undefined
PLL feedback divider value (decimal).
Charge pump register value (decimal).
Rev. 0 | Page 16 of 44
CP
121
121
121
121
121
121
AD9553
DEVICE CONTROL MODES
from time to time, or for applications that require parameters
not available with any of the pin control options. The block
diagram (see Figure 19) shows how the SPI and pin control
modes interact.
The AD9553 provides two modes of control: pin control and
register control. Pin control, via the frequency selection pins
(A[3:0] and Y[5:0]) as described in the Preset Frequencies
section, is the simplest. Typically, pin control is for applications
requiring only a single set of operating parameters (assuming
that one of the options available via the frequency selection
pins provides the parameters that satisfy the application
requirements). Register control is typically for applications that
require the flexibility to program different operating parameters
The SPI/OM[2:0] label in Figure 19 refers to Pin 12, Pin 13 ,and
Pin 14 of the AD9553. Furthermore, the SPI mode signal is
Logic 1 when A[3:0] = 0000 and/or Y[5:0] = 000000; otherwise,
it is Logic 0.
SPI/OM[2:0]
A[3:0]
3
1
3
4
6
FREQUENCY
SELECTION
PINS DECODER
SPI MODE
0
Y[5:0]
3
OUTPUT
MODE
CONTROL
DECODER
SPI CONTROLLER
3
OUTPUT
MODE
CONTROL
FUNCTION
BITS
ENABLE SPI CONTROL
OF OUTPUT MODE
0
3
1
OUTPUT MODE
CONTROL
FUNCTION
ENABLE SPI CONTROL
OF OUTPUT ABC BITS
FUNCTION
ABC BITS
0
1
FUNCTION
ABC
ENABLE SPI CONTROL
OF FUNCTIONING XYZ
0
1
FUNCTION
MUXES
REGISTER MAP
Figure 19. Control Mode Diagram
Rev. 0 | Page 17 of 44
FUNCTION
XYZ
08565-100
FUNCTION
XYZ BITS
AD9553
The SPI/OM[2:0] pins serve double duty (as either SPI pins or
output mode control pins). A mux (controlled by the SPI mode
signal) selects whether the three signals associated with the
SPI/OM[2:0] pins connect to the output mode control decoder
or to the SPI controller. Note that the SPI mode signal
originates from the frequency selection pins decoder.
To enable communication with the SPI controller (SPI
mode), the user must apply the appropriate logic pattern
to the frequency selection pins (A[3:0] = 0000 and/or
Y[5:0] = 000000). Note that as long as the frequency selection
pins are set to invoke SPI mode, the user cannot establish
output mode control via the output mode control decoder.
Conversely, when the frequency selection pins are set to
anything other than SPI mode, the user cannot communicate
with the device via the SPI controller.
In Figure 19, note that some of the functions internal to the
AD9553 are controlled by function bits that originate either
from the two pin decoders or from within the register map.
Specifically, each function receives its function bits from a
function mux; and each function mux, in turn, receives its
control signal from a single enable SPI control bit in the
register map.
to the selected function the instant that the enable SPI control
bit becomes Logic 1. Thus, it is a good idea to program the
function bits to the desired state prior to writing Logic 1 to
the corresponding enable SPI control bit.
Although the SPI and pin control modes are functionally
independent, it is possible to mix the control modes. For
example, suppose that pin control satisfies all of the requirements for an application except for the value of the P2 divider
(which is associated with OUT2). The user could do the
following:
•
•
•
•
•
Be aware that the default values within the register map are such
that all enable SPI control bits are Logic 0. Thus, the default
state of the device is such that each function mux selects the pin
decoders (not the register map) as the source for all control
functions.
In order to switch a function mux so that it selects function
bits from the register map, the user must first set the frequency
selection pins to SPI mode. Then, write a Logic 1 to the appropriate enable SPI control bit in the register map. Be aware that
the function mux routes the function bits in the register map
Activate SPI mode via the frequency selection pins.
Program the desired P0, P1, and P2 values in the register
map (Register 0x15 to Register 0x18).
Set the enable SPI control bit for the output dividers
(Register 0x14[2] = 1).
Calibrate the VCO by enabling SPI control of VCO
calibration (Register 0x0E[2] = 1), then issue a calibrate
command (Register 0x0E[7] = 1). Be sure to program the
N divider, R dividers, /5 dividers, and ×2 multipliers to the
values defined by the A[3:0] and Y[5:0] pin settings prior
to calibrating the VCO.
Restore the original settings to the frequency selection pins
to invoke the desired frequency selection.
In this way, the function muxes that control P0, P1, and P2 select
the appropriate register bits as the source for controlling the
dividers, while all the other function muxes select the pin
decoders as the source for controlling the other functions. Note
that the dividers remain under register control until the user
activates SPI mode and writes Register 0x14[2] = 0, thereby
causing the function mux to use the frequency selection pins
decoder as the source for controlling the dividers, instead of the
register map.
Rev. 0 | Page 18 of 44
AD9553
THEORY OF OPERATION
LOCKED
FILTER
TEST
SEL REFB
1 0
CLOCK MUX
UP/2
FPFD/2
FDBK/2
XO
HOLD
REF DET DET DET
SEL A
B
XO
DET A
REFA
×2
0
1
÷5
REF
DIFF
0
1
1
0
DET
LOCK
DETECT
PLL
÷RA
FPFD
P
F
D
×2A
RA
UP
LOOP
FILTER
CHARGE
PUMP
×2
REFB/REFA
÷5
0
1
1
0
3350MHz
TO
4050MHz
5 OR 6
VCO
P0
P2
DN
3
DET XO
XO
DCXO
CTRL
TUNING
CONTROL
XTAL
FDBK
÷RB
×2
2
P1
P0
P1
OUTPUT
MODE
CONTROL
20
3
1 0
N
RB
DET
÷RXO
14
RXO
OUT1
10
÷N
14
×2B
÷5B
XTAL
DET
OUT2
10
HOLD
DET B
2
P2
CLOCK
MUX
14
÷5A
AD9553
3
RA, ×2A, ÷5A
RB, ×2B, ÷5B
RXO, DCXO CTRL
N, P0, P1, P2
REF SEL
TEST
REF DIFF
REGISTER BANK
3
3
OUTPUT MODE/
SERIAL PORT
SPI CTRL
4
1
0
PRECONFIGURED
DIVIDER SETTINGS
6
A[3:0]
Y[5:0]
08565-101
REFERENCE
SWITCHOVER
CONTROL
Figure 20. Detailed Block Diagram
GENERAL DESCRIPTION
The AD9553 can receive up to two input reference clocks, REFA
and REFB. Both input clock paths include an optional divideby-5 (/5) prescaler, an optional 2× frequency multiplier, and
a 14-bit programmable divider. Alternatively, the user can
program the device to operate with one differential input clock
(instead of two single-ended input clocks) via the serial I/O
port. In the differential operating mode, the REFB path is
inactive.
The AD9553 also has a dedicated XTAL input for direct
connection of an optional 25 MHz crystal resonator. This allows
for a backup clock signal useful for holdover operation in case
both input references fail. The XTAL clock path includes a fixed
2× frequency multiplier and a 14-bit programmable divider.
The AD9553 includes a switchover control block that automatically handles switching from REFA to REFB (or vice versa)
in the event of a reference failure. If both REFA and REFB fail,
however, then the switchover control block automatically enters
holdover mode by selecting the XTAL clock signal (assuming
the presence of a crystal resonator at the XTAL input).
Generally, the clock signals that appear at the input to the clock
multiplexer (see Figure 20) all operate at the same frequency.
Thus, the frequency at the input to the PLL (FPFD in Figure 20)
is the same regardless of the signal selected by the clock
multiplexer. The PLL converts FPFD to a frequency within the
operating range of the VCO (3.35 GHz to 4.05 GHz) based on
the value of the feedback divider (N). The VCO prescaler (P0)
reduces the VCO output frequency by a factor of either 5 or 6,
resulting in an intermediate frequency in the range of 558 MHz
to 810 MHz. The 10-bit P1 and P2 dividers can further reduce
the P0 output frequency to yield the final output clock frequencies at OUT1 and OUT2, respectively.
Thus, the frequency translation ratio from the reference input
to the output depends on the selection of the /5 prescalers; the
2× frequency multipliers; the values of the three R dividers; the
N divider; and the P0, P1, and P2 dividers. The user can set all
of these parameters automatically by using the preconfigured
divider settings available via the A[3:0] and Y[5:0] pins (see the
Preset Frequencies section). Alternatively, the user can custom
program these parameters via the serial I/O port (see the Serial
Control Port and Register Map sections), allowing the device to
accommodate custom frequency translation ratios.
DESCRIPTION OF FUNCTIONAL BLOCKS
Reference Inputs
The default configuration of the AD9553 provides up to two
single-ended input clock receivers, REFA and REFB, which are
high impedance CMOS inputs. In applications that require
redundant reference clocks with switchover capability, REFA
is the primary reference and REFB the secondary reference.
Alternatively, the user can configure the input (via the serial I/O
port) as a single differential receiver. In this case, the REFB
input functions as REFA (the complementary input of REFA).
Note that in this configuration the device operates with only
one reference input clock, eliminating the need for switchover
functionality.
Rev. 0 | Page 19 of 44
AD9553
XTAL Input
The AD9553 accepts an optional 25 MHz crystal resonator
connected across the XTAL pins. Unless otherwise programmed,
the device expects the crystal to have a specified load capacitance of
10 pF (default). The AD9553 provides the necessary load capacitance internally. The internal load capacitance consists of a fixed
component of 8 pF and a variable (programmable) component of
0 pF to 15.75 pF.
After applying power to the AD9553 (or after a device reset),
the programmable component defaults to 2 pF. This establishes
the default load capacitance of 10 pF (8 pF fixed plus 2 pF
programmable).
To accommodate crystals with a specified load capacitance other
than 10 pF (8 pF to 23.75 pF), the user can adjust the programmable capacitance in 0.25 pF increments via Register 0x1B[5:0].
Note that when the user sets Register 0x1B[7] to 0 (enabling SPI
control of the XTAL tuning capacitors), the variable capacitance
changes from 2 pF (its default power-up value) to 15.75 pF
due to the default value of Register 0x1B[5:0]. This causes the
crystal load capacitance to be 23.75 pF until the user overwrites
the default contents of Register 0x1B[5:0].
A noncomprehensive, alphabetical list of crystal manufacturers
includes the following:
•
•
•
•
•
•
AVX/Kyocera
ECS
Epson Toyocom
Fox Electronics
NDK
Siward
Although these crystals meet the load capacitance and motional
resistance requirements of the AD9553 according to their data
sheets, Analog Devices, Inc., does not guarantee their operation
with the AD9553, nor does Analog Devices endorse one supplier
of crystals over another.
Input Frequency Prescalers (/5A, /5B)
The /5 prescalers provide the option to reduce the input
reference frequency by a factor of five. Note that the prescalers
physically precede the 2× frequency multipliers. This allows
the prescalers to bring a high frequency reference clock down
to a frequency that is within the range of the 2× frequency
multipliers.
Input 2× Frequency Multipliers (x2A, x2B)
The 2× frequency multipliers provide the option to double the
frequency at their input. This allows the user to take advantage
of a higher frequency at the input to the PLL (FPFD), which
allows for greater separation between the frequency generated
by the PLL and the modulation spur associated with FPFD.
However, increased reference spur separation comes at the
expense of the harmonic spurs introduced by the frequency
multiplier. As such, beneficial use of the frequency multiplier is
application specific. Note that the maximum input frequency
to the 2× frequency multipliers must not exceed 125 MHz.
Input Clock Detectors
The three clock input sections (REFA, REFB, and XTAL) include
a dedicated monitor circuit that detects signal presence at the
input. The detectors provide input to the switchover control
block to support automatic reference switching and holdover
operation.
Switchover/Holdover
The AD9553 supports automatic reference switching and holdover functions. It also supports manual reference switching via
an external pin (SEL REFB) or via program control using the
serial I/O port. A block diagram of the switchover/holdover
capability appears in Figure 21. Note that the mux selects one
of the three input signals (REFA, REFB, or XTAL) routing it to
the input of the PLL. The selection of an input signal depends
on which signals are present along with the contents of
Register 0x29[7:6] and the logic level at the SEL REFB pin.
Note that each input signal has a dedicated signal presence
detector. Each detector uses the feedback signal from the PLL
as a sampling clock (which is always present due to the freerunning VCO). This allows the detectors to determine the
presence or absence of the input signals reliably. Note that the
mux control logic uses the detector signals directly in order to
determine the need for a switch to holdover operation.
Holdover occurs whenever the mux control logic determines that
both the REFA and REFB signals are not present, in which case the
device selects the XTAL signal if it is present. The exception is
when Register 0x29[7:6] = 10 or 11, which disables the holdover
function. If none of the three input signals is present, the device
waits until at least one signal becomes present and selects according
to the device settings (Register 0x29[7:6] and the logic level at the
SEL REFB pin).
When the device is reset (or following a power-up), the internal
logic defaults to revertive switchover mode (Register 0x29[7:6] =
00). In revertive switchover mode, the device selects the REFA
signal whenever it is present. If REFA is not present, then the device
selects the REFB signal, if present, but returns to REFA whenever it
becomes available. That is, in revertive switchover mode, the device
favors REFA. If both REFA and REFB are not present, the device
switches to holdover mode.
When programmed for nonrevertive switchover mode
(Register 0x29[7:6] = 01), the device selects the REFA signal if
it is present. If REFA is not present, then the device selects the
REFB signal (if present). Even if REFA becomes available, the
device continues to use REFB until REFB fails. That is, in nonrevertive switchover mode, the switch to REFB is permanent
unless REFB fails (or unless both REFA and REFB fail, in which
case the device switches to holdover mode).
Rev. 0 | Page 20 of 44
AD9553
RA DIVIDER
FROM REFA
INPUT
÷
RB DIVIDER
FROM REFB
INPUT
FROM XTAL
INPUT
TO
PLL
÷
RXO DIVIDER
÷
CLOCK
MUX
XTAL PRESENT
SIGNAL
REFB PRESENT
DETECTOR
REFA PRESENT
FDBK
MUX
CONTROL
LOGIC
11
SEL
REFB
REG 0x29[7:6]
00
NON-REVERTIVE
01
SELECT REFA
10
SELECT REFB
SEL B/A
REVERTIVE/
NON-REVERTIVE
LOGIC
SEL B/A
SPI SELECT REFA/B
LOGIC
SEL B/A
SEL B/A
REFA/B
SELECTION LOGIC
08565-102
REVERTIVE
11
Figure 21. Switchover/Holdover Block Diagram
The user can override the automatic switchover functions
(revertive and nonrevertive) and manually select the REFA
or REFB signal by programming Register 0x29[7:6] = 10 or 11,
respectively. Note, however, that the desired signal (REFA or
REFB) must be present for the device to select it.
The user can also force the device to switch to REFB by
applying a Logic 1 to the external SEL REFB pin. This overrides
a REFA selection invoked by either the revertive/nonrevertive
logic or when Register 0x29[7:6] = 10. Note, however, that
REFB must be present to be selected by the device.
PLL (PFD, Charge Pump, VCO, Feedback Divider)
The PLL (see Figure 20) consists of a phase-frequency detector
(PFD), a partially integrated analog loop filter (see Figure 22),
an integrated voltage-controlled oscillator (VCO), and a 20-bit
programmable feedback divider. The PLL generates a 3.35 GHz
to 4.05 GHz clock signal based on the frequency of FPFD (see
Figure 20) and the feedback divider value, which is phaselocked to the input reference signal.
The PFD of the PLL drives a charge pump that increases,
decreases, or holds constant the charge stored on the loop filter
capacitors (both internal and external). The stored charge results
in a voltage that sets the output frequency of the VCO. The
feedback loop of the PLL causes the VCO control voltage to
vary in such a way as to phase lock the PFD input signals. Note
that the PFD supports input frequencies spanning 13.3 kHz to
100 MHz (implying that input frequencies between 8 kHz and
13.3 kHz must use the 2× frequency multiplier in the input path).
The PLL has a VCO with 128 frequency bands spanning a range
of 3350 MHz to 4050 MHz (3700 MHz nominal). However, the
actual operating frequency within a particular band depends on
the control voltage that appears on the loop filter capacitor. The
control voltage causes the VCO output frequency to vary linearly
within the selected band. This frequency variability allows the
control loop of the PLL to synchronize the VCO output signal
with the reference signal applied to the PFD.
Typically, selection of the VCO frequency band (as well as gain
adjustment) occurs automatically as part of the device’s automatic
VCO calibration process, which initiates at power up (or reset).
Alternatively, the user can force VCO calibration by first
enabling SPI control of VCO calibration (Register 0x0E[2] = 1)
and then writing a 1 to the calibrate VCO bit (Register 0x0E[7]).
To facilitate system debugging, the user can override the VCO
band setting by first enabling SPI control of VCO band
(Register 0x0E[0] = 1) and then writing the desired value to
Register 0x10[7:1].
The feedback divider (N-divider) sets the frequency multiplication factor of the PLL in integer steps over a 20-bit range.
However, the N-divider has a lower limit of 32, which sets a
minimum PLL multiplication factor of 32.
Rev. 0 | Page 21 of 44
AD9553
Loop Filter
The charge pump in the PFD delivers current to the loop filter
(see Figure 22). The main components of the loop filter are
external and connect between Pin 16 and Pin 17. Note that to
achieve the best jitter performance in applications requiring a loop
bandwidth of less than 1 kHz, C1 and C2 must have an insulation
resistance of at least 500 ΩF.
The output of the P0 divider independently drives the P1 divider
and the P2 divider. The P1 divider establishes the frequency at
OUT1 and the P2 divider establishes the frequency at OUT2.
The P1 and P2 dividers are each programmable over a range of
1 to 1023, which results in a frequency at OUT1 or OUT2 that
is an integer submultiple of the frequency at the output of the P0
divider.
Output Driver Configuration
FROM
CHARGE
PUMP
AD9553
3kΩ
The user has complete control over all configurable parameters
of the OUT1 and OUT2 drivers via the OUT1 and OUT2 driver
control registers (Register 0x32 and Register 0x34, respectively,
as shown in Figure 23). To alter the parameters from their
default values, the user must use the SPI port to program the
driver control registers as desired.
TO
VCO
5pF
16
17
FILTER
LDO
R
The OUT1 and OUT2 drivers are configurable in terms of the
following parameters:
C2
•
•
08565-103
C1
EXTERNAL LOOP FILTER
COMPONENTS
Figure 22. External Loop Filter
•
•
•
There are two recommended sets of external loop filter components (see Table 17) based on the A[3:0] pin configuration.
Table 17. External Loop Filter Components
Pins A[3:0]
0001 to
1100
1101 to
1110
1111
R (kΩ) C1
C2
6.8
47 nF 1 μF
Loop Bandwidth (kHz)
0.17
12
51 pF 220 nF
75
6.8
47 nF
0.17
1 μF
PLL Locked Indicator
The PLL provides a status indicator that appears at Pin 20
(LOCKED). When the PLL acquires phase lock, the LOCKED
pin switches to a Logic 1 state.
Alternatively, the LOCKED pin serves as a test port allowing the
user to monitor one-of-four internal clocks. Register 0x17[3:1]
controls the test port as shown in Table 18.
Table 18: LOCKED Pin Output Control
Register
0x17[3:1]
0XX
100
101
110
111
LOCKED Pin Output
PLL locked indication (default)
Crystal oscillator clock signal
PFD pump-up clock divided-by-2
PFD reference input clock divided-by-2
PLL feedback to PFD clock divided-by-2
Output Dividers
The output divider section consists of three dividers: P0, P1, and P2.
The P0 divider (or VCO frequency prescaler) accepts the VCO
frequency and reduces it by a factor of 5 or 6 (selectable). This
brings the frequency down to a range between 558 MHz and
810 MHz.
Logic family (via mode control)
Pin function (via mode control but only applies to the
CMOS family)
Polarity (only applies to the CMOS family)
Drive current
Power-down
Output Driver Mode Control
Three mode control bits establish the logic family and pin
function of the output drivers. The three bits originate either
from Bits[5:3] of Register 0x32 and Register 0x34 or from the
decode logic associated with the OM[2:0] pins as shown in
Figure 23. Note that Bit 0 of Register 0x32 and Register 0x34
determines the source of the three mode control bits for the
associated output driver. Specifically, when Bit 0 of the register
is Logic 0 (default), the source of the mode control bits for the
associated driver is the OM[2:0] pin decoder. When Bit 0 is
Logic 1, the source of the mode control bits is from Bits[5:3] of
Register 0x32 and Register 0x34.
The mode control bits establish the logic family and output pin
function of the associated output driver per Table 19. The logic
families include LVDS, LVPECL, and CMOS. Because both
output drivers support the LVDS and LVPECL logic families,
each driver has two pins to handle the differential signals
associated with these two logic families. The OUT1 driver uses
the OUT1 and OUT1 pins and the OUT2 driver uses the OUT2
and OUT2 pins. However, the CMOS logic family handles only
single-ended signals, thereby requiring only one pin. Even
though CMOS only requires one pin, both pins of OUT1 and
both pins of OUT2 have a dedicated CMOS driver.
The user has the option to disable (that is, tristate) either or
both of the pins for OUT1 and/or OUT2 via the mode control
bits (see Table 19, Bit Patterns 001, 010, and 011). Alternatively,
the user can make both pins active (see Table 19, Bit Pattern
000) to produce two single-ended CMOS output clocks at
OUT1 and/or OUT2.
Rev. 0 | Page 22 of 44
AD9553
Table 19. Output Mode Control Bits
Mode Control
Bits
000
001
Logic
Family
CMOS
CMOS
010
CMOS
011
100
101
110
111
CMOS
LVDS
LVPECL
Unused
Unused
Pin Function of the Output
Driver
Both pins active
Positive pin active, negative
pin tristate
Positive pin tristate, negative
pin active
Both pins tristate
Both pins active
Both pins active
Unused
Unused
Note that the pin decoder for the OM[2:0] pins generates two
sets of mode control bits: one set for the OUT1 driver and
another set for the OUT2 driver. The relationship between the
logic levels applied to the OM[2:0] pins and the resulting mode
control bits appears in Table 20.
This decoding scheme allows the OM[2:0] pins to establish a
matrix of logic family selections for the OUT1 and OUT2 drivers
as shown in Table 21. Note that when the OM[2:0] pins select the
CMOS logic family, only the positive pin active, negative pin tristate
output driver pin function option is available.
Table 21. Logic Family Assignment via the OM[2:0] Pins
Pins OM[2:0]
000
001
010
011
100
101
110
111
Table 20. OM[2:0] Pin Decoder
Pins OM[2:0]
000
001
010
011
100
101
110
111
OUT1
101
101
100
101
100
100
001
001
Mode Control Bits
OUT2
101
100
101
001
100
001
100
001
Rev. 0 | Page 23 of 44
OUT1
LVPECL
LVPECL
LVDS
LVPECL
LVDS
LVDS
CMOS
CMOS
Logic Family
OUT2
LVPECL
LVDS
LVPECL
CMOS
LVDS
CMOS
LVDS
CMOS
AD9553
REGISTER 0x32
BITS
[5:3]
BIT 0
BIT 7
0
1
101
MODE
CONTROL
BIT 6
BITS
[2:1]
0
00
POWER- CMOS
DOWN
POLARITY
DRIVE
STRENGTH
ENABLE
SPI
CONTROL
2
3
REGISTER
DEFAULT VALUES
SHOWN IN RED
3
1
3
OUTPUT
CONTROL
0
3
PIN
DECODE
LOGIC
OUT1
MODE
CONTROL
3
2
DRIVER
OUT2
3
0
OUTPUT
CONTROL
3
1
2
ENABLE
SPI
CONTROL
MODE
CONTROL
DRIVE
STRENGTH
101
BITS
[5:3]
0
1
BIT 0
BIT 7
POWER- CMOS
DOWN
POLARITY
0
BIT 6
REGISTER 0x34
Figure 23. Output Driver Control
Rev. 0 | Page 24 of 44
00
BITS
[2:1]
08565-104
OM[2:0]
2
DRIVER
3
AD9553
Output Driver Polarity (CMOS)
OUTPUT/INPUT FREQUENCY RELATIONSHIP
When the mode control bits indicate the CMOS logic family
(see Table 19), the user has control of the logic polarity associated with each CMOS output pin. Driver polarity defines how
the logic level (Logic 1 or Logic 0) at a CMOS output pin relates
to the logic state (Logic True or Logic False). Normal polarity
equates Logic 1/Logic 0 to Logic True/Logic False, while
inverted polarity equates Logic 0/Logic 1 to Logic True/Logic
False. Bits[2:1] of the OUT1 and OUT2 driver control registers
control the CMOS polarity of the associated output driver (see
Figure 23).
The frequency at OUT1 and OUT2 depends on the frequency
at the input to the PLL, the PLL feedback divider value (N), and
the output divider values (P0, P1, and P2). The equations that
define the frequency at OUT1 and OUT2 (fOUT1 and fOUT2,
respectively) are as follows:
Output Drive Strength (CMOS or LVDS)
When the mode bits indicate the CMOS or LVDS logic family
(see Table 19), the user can select whether the output driver
uses weak or strong drive capability. Bit 7 of the OUT1 and
OUT2 driver control registers control the drive strength of the
associated output driver (see Figure 23). In the case of the
CMOS family, the strong setting allows for driving increased
capacitive loads. In the case of the LVDS family, the nominal
weak and strong drive currents are 3.5 mA and 7 mA,
respectively.
Output Power Down
The AD9553 supports the option of independent power-down
of the output drivers. Bit 6 of the OUT1 and OUT2 driver control
registers controls the power-down function (see Figure 23). When
Bit 6 is Logic 0, the associated output driver is active. When Bit 6 is
Logic 1, the associated output driver is in power-down mode.
JITTER TOLERANCE
Jitter tolerance is the ability of the AD9553 to maintain lock in
the presence of sinusoidal jitter. The AD9553 meets the input
jitter tolerance mask per Telcordia GR-253-CORE (see Figure 24).
The acceptable jitter tolerance is the region above the mask. The
trace showing the performance of the AD9553 in Figure 24
represents the limitations of the test equipment because the
AD9553 did not indicate loss of lock, even with the test
equipment injecting its maximum jitter level.
⎛ N ⎞
⎟
f OUT 1 = FPFD⎜
⎜ P0 × P1 ⎟
⎝
⎠
⎛ N
f OUT 2 = FPFD⎜
⎜ P0 × P2
⎝
⎞
⎟
⎟
⎠
where:
FPFD is the frequency at the reference input of the PFD.
N is the feedback divider value.
P0 is the VCO prescaler divider value.
P1 is the OUT1 divider value.
P2 is the OUT2 divider value.
The operating frequency range of the PFD places a limitation
on FPFD as follows:
13.3 kHz ≤ FPFD ≤ 100 MHz
Note that for applications using the frequency selection pins in
conjunction with the XTAL input for the holdover function, the
maximum value of FPFD is 50 MHz (twice the 25 MHz default
crystal frequency).
FPFD depends on the input frequency to the AD9553, the
configuration of the multiplexers for the /5 prescaler and 2×
frequency multiplier, and the value of the RX divider (either RA,
RB, or RXO) as follows:
FPFD = f X ×
K
RX
where:
fX is equal to fREFA, fREFB, or fXTAL.
K is the scale factor per Table 22.
FPFD is the frequency at the input to the phase frequency
detector.
1k
Input
REFA
100
AD9553
10
REFB
MASK
1
XTAL
0.1
0.01
0.1
1
10
100
JITTER FREQUENCY (kHz)
1k
10k
08565-030
INPUT JITTER AMPLITUDE (ULPP)
Table 22. K as a Function of Input Multiplexer Configuration
Figure 24. Jitter Tolerance
Rev. 0 | Page 25 of 44
/5
Bypassed
Active
Bypassed
Active
Bypassed
Active
Bypassed
Active
N/A
2×
Bypassed
Bypassed
Active
Active
Bypassed
Bypassed
Active
Active
N/A
K
1
1/5
2
2/5
1
1/5
2
2/5
2
AD9553
fREF = 125 MHz
This leads to the complete frequency translation formula
f OUT 1
⎛ K
= f X ⎜⎜
⎝ RX
⎞⎛ N ⎞
⎟
⎟⎜
⎟⎜ P × P ⎟
⎠⎝ 0 1 ⎠
f OUT 2
⎛ K
= f X ⎜⎜
⎝ RX
⎞⎛ N
⎟⎜
⎟⎜ P × P
⎠⎝ 0 2
fOUT1 = 155.52 MHz
Follow these steps to calculate the divider values.
⎞
⎟
⎟
⎠
1.
Determine the output divide factor (ODF).
Note that the VCO frequency (fVCO) spans 3350 MHz to
4050 MHz. The ratio, fVCO/fOUT1, indicates the required
ODF. Given the specified value of fOUT1 (155.52 MHz)
and the range of fVCO, the ODF spans a range of 21.54 to
26.04. The ODF must be an integer, which means that ODF
is 22, 23, 24, 25, or 26.
2.
Determine suitable values for P0, P1 and fVCO.
The ODF is the product of the two output dividers P0 and
P1 (ODF = P0P1). However, P0 is constrained to 5 or 6 (see
the Output/Input Frequency Relationship section), which
means that there are only two possibilities for ODF in this
example: ODF = 24 (P0 = 6, P1 = 4) and ODF = 25 (P0 = 5,
P1 = 5). These two ODF values result in the only VCO
frequencies that satisfy the 155.52 MHz requirement for
OUT1 (3732.48 MHz for ODF = 24 and 3888 MHz for
ODF = 25). The results appear below. Note that the first
result agrees with Table 15 in the Preset Frequencies
section).
Specific numeric constraints apply as follows. Note that the
symbol ∈ indicates that the constraint is an element of one in
the series from the list within the curly brackets.
K∈
{15 , 52 , 1, 2}
R X ∈ {1, 2,L,16384}
N ∈ {32, 33,L,1048576}
P0 ∈ {5, 6}
P1 ∈ {1, 2,L, 63}
P2 ∈ {1, 2,L, 63}
Additional constraints apply. One constraint is related to the
VCO and the other to the 2× frequency multipliers in the REFA
and REFB paths. The VCO constraint is a consequence of its
limited bandwidth. However, the 2× frequency multiplier
constraint only applies when the /5 prescalers are bypassed, but
it also requires that RA and RB are large enough to satisfy the
FPFD constraint. The additional constraints are as follows:
P0 = 6, P1 = 4 (fVCO = 3732.48 MHz)
P0 = 5, P1 = 5 (fVCO = 3888 MHz)
3350 MHz ≤ fOUT1 × P0 × P1 ≤ 4050 MHz
3.
3350 MHz ≤ fOUT2 × P0 × P2 ≤ 4050 MHz
fREFA/B ≤ 125 MHz (2× multiplier with /5 bypassed)
Generally, the AD9553 is for applications in which fREFA and fREFB
are the same frequency, so the multiplexers in the REFA and
REFB paths share identical configurations. This, in conjunction
with the crystal frequency (fXTAL), results in the following
relationship between the RA and RXO dividers (here K is the scale
factor for the REFA path).
R
2 × f XTAL
= K × XO
f REFA
RA
Determine the boundary conditions on N, K, and R.
Because of the architecture of the PLL, FPFD must be an
integer submultiple of the VCO frequency as shown in the
following equation. Note that N is an integer and is the
20-bit value of the N-divider.
FPFD =
fVCO
N
This relationship leads to boundary conditions on N
because N must be an integer that satisfies N = fVCO/FPFD.
The limits on FPFD (13.3 kHz to 100 MHz) combined with
the results for fVCO from Step 2 yield
N = 38...280,637 (for fVCO = 3732.48 MHz)
Note that for pin-programmed holdover applications using the
crystal, the crystal frequency must be 25 MHz. Under these
circumstances, the above equation simplifies as follows:
R
50 × 10 6
= K × XO
f REFA
RA
CALCULATING DIVIDER VALUES
This section describes the process of calculating the divider
values when given a specific fOUT1/fREF ratio (fREF is the frequency
of either the REFA or REFB input signal source or the external
crystal resonator). This description is in general terms, but it
includes a specific example for clarity. The example assumes
a frequency control pin setting of A[3:0] = 1011 (see Table 14)
and Y[5:0] = 011100 (see Table 15), yielding the following:
Rev. 0 | Page 26 of 44
N = 39...292,330 (for fVCO = 3888 MHz)
Note that FPFD also relates to the input frequency, fREF, per
the following equation. Here, R is the 14-bit integer division factor of the input divider (RA or RB), while K is the
scale factor associated with the optional 2× multiplier and
divide-by-five functions. Note that K can only be one of
four values: 1/5, 2/5, 1, or 2.
⎛K⎞
FPFD = f REF ⎜ ⎟
⎝R⎠
This relationship leads to boundary conditions on R because
R/K = fREF/FPFD where R must be an integer and K can only
be 1/5, 2/5, 1, or 2. The limits on FPFD (13.3 kHz to 100
MHz) combined with the given value of fREF yield the
following bounds on R. Note that for K = 2, the upper bound
on R is limited by its 14-bit range.
AD9553
If one chooses fVCO = 3888 MHz, then a possible solution is
R = 1...1,879 (for K = 1/5)
R = 1...3,759 (for K = 2/5)
R = 2...9,398 (for K = 1)
R = 3...16,384 (for K = 2)
P0 = 5
P1 = 5
N = 3888
Relate N, K, and R to the frequency requirements.
The two FPFD equations in Step 3 show that fVCO and fREF
relate as
R = 125
K=1
FPFD = 1 MHz
fVCO NK
=
f REF
R
6.
Note that fREF is a known quantity (125 MHz) and the VCO
frequencies were determined in Step 2 as 3732.48 MHz and
3888 MHz. Based on these values of fREF and fVCO
3732.48 NK
=
125
R
5.
or
⎛ 50 × 10 6
R XO = ⎜⎜
⎝ f REF
3888 NK
=
125
R
⎞⎛ R ⎞
⎟⎜ ⎟
⎟⎝ K ⎠
⎠
Given that fREF = 125 MHz, the two results from Step 5 lead to
Determine N, K. and R.
For fVCO = 3888 MHz, an obvious solution is K = 1, R = 125
and N = 3888, which satisfies the constraint on both N and
R and yields FPFD = 1 MHz.
For fVCO = 3732.48 MHz, an obvious solution is N = 373,248,
K = 1 and R = 12,500. This choice, however, violates the constraints on both N and R in Step 3.
A simple remedy is to divide both N and R by a common factor.
In this particular case, four is the greatest common factor of N
and R. Dividing by four leads to N = 93,312, K = 1, and R =
3,125 (K = 1), satisfying the constraint on N and R, and yielding
FPFD = 40 kHz. Note that to match the values given in the
Preset Frequencies section, FPFD must be 16 kHz. To accomplish this, keep R = 3,125, but choose K = 2/5 (see Table 14).
This changes N to 233,280, which agrees with Table 16. In
summary, if one chooses fVCO = 3732.48 MHz, then the solution
set that matches the tables in the Preset Frequencies section is
P0 = 6
If applicable, determine RXO, the XTAL divider value.
The value of RXO depends on the value of fREF, K, and R
from Step 5, as follows:
RXO = 3125 (for R = 3125 and K = 2/5)
RXO = 50 (for R = 125 and K = 1)
LOW DROPOUT (LDO) REGULATORS
The AD9553 is powered from a single 3.3 V supply and contains
on-chip LDO regulators for each function to eliminate the need
for external LDOs. To ensure optimal performance, each LDO
output should have a 0.47 μF capacitor connected between its
access pin and ground.
AUTOMATIC POWER-ON RESET
The AD9553 has an internal power-on reset circuit (see Figure 25).
At power-up, an 800 pF capacitor momentarily holds a Logic 0
at the active low input of the reset circuitry. This ensures that the
device is held in a reset state (~250 μs) until the capacitor charges
sufficiently via the 100 kΩ pull-up resistor and 200 kΩ series
resistor. Note that when using a low impedance source to drive
the RESET pin, be sure that the source is either tristate or Logic 0
at power-up. Otherwise, the device may not calibrate properly.
VDD
P1 = 4
AD9553
100kΩ
N = 233,280
200kΩ
RESET 15
R = 3,125
RESET
CIRCUITRY
800pF
K = 2/5
Figure 25. Power-On Reset
FPFD = 16 kHz
Rev. 0 | Page 27 of 44
08565-105
4.
AD9553
APPLICATIONS INFORMATION
THERMAL PERFORMANCE
The AD9553 is specified for a case temperature (TCASE). To
ensure that TCASE is not exceeded, an airflow source can be used.
Use the following equation to determine the junction temperature on the application PCB:
TJ = TCASE + (ΨJT × PD)
Values of θJA are provided for package comparison and PCB design
considerations. θJA can be used for a first-order approximation
of TJ using the following equation:
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the customer
at the top center of the package.
ΨJT is the value indicated in Table 23.
PD is the power dissipation (see the Power Consumption
section).
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of θJB are provided for package comparison and PCB
design considerations.
Table 23. Thermal Parameters for the 32-Lead LFCSP Package
Symbol
θJA
θJMA
θJMA
θJB
ΨJB
θJC
ΨJT
1
Description
Junction-to-ambient thermal resistance, 0 m/sec airflow per JEDEC JESD51-2 (still air)
Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)
Junction-to-ambient thermal resistance, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air)
Junction-to-board thermal resistance, 0 m/sec airflow per JEDEC JESD51-8 (still air)
Junction-to-board characterization parameter, 0 m/sec airflow per JEDEC JESD51-6 (still air)
Junction-to-case thermal resistance
Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air)
Value 1
41.6
36.4
32.6
24.2
22.9
4.8
0.5
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine whether they are similar to those assumed in these calculations.
Rev. 0 | Page 28 of 44
AD9553
SERIAL CONTROL PORT
The AD9553 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface to many
industry-standard microcontrollers and microprocessors. Single
or multiple byte transfers are supported, as well as MSB first or
LSB first transfer formats. The AD9553 serial control port is
configured for a single bidirectional I/O pin (SDIO only). The
serial control port uses 16-bit instructions, which allows access
to the entire register address range (0x00 to 0x34).
The serial control port has two types of registers: read-only and
buffered. Read-only registers are nonbuffered and ignore write
commands. All writable registers are buffered (also referred to
as mirrored) and require an I/O update to transfer the new values
from a temporary buffer on the chip to the actual register. To
invoke an I/O update, write a 1 to the I/O update bit found in
Register 0x05[0]. Because any number of bytes of data can be
changed before issuing an update command, the update simultaneously enables all register changes occurring since any
previous update.
SERIAL CONTROL PORT PIN DESCRIPTIONS
The serial data clock (SCLK) is the serial shift clock. This pin is
an input. SCLK is used to synchronize serial control port reads
and writes. Write data bits are registered on the rising edge of
this clock, and read data bits are registered on the falling edge.
The digital serial data input/output (SDIO) pin is a dualpurpose pin that acts as input only or as an input/output. The
AD9553 defaults to bidirectional pins for I/O.
The chip select bar (CS) is an active low control that gates the read
and write cycles. When CS is high, SDIO is in a high impedance
state. See the Operation of the Serial Control Port section on the
use of the CS pin in a communication cycle.
13
AD9553
OM0/SDIO
14
SERIAL
CONTROL
PORT
OM2/CS
12
Table 24. Byte Transfer Count
Bit W1
0
0
1
1
Bit W0
0
1
0
1
Bytes to Transfer
(Excluding the 2-Byte Instruction)
1
2
3
Streaming mode
In the streaming mode (Bits[W1:W0] = 11), any number of data
bytes can be transferred in a continuous stream. The register
address is automatically incremented or decremented (see the
MSB/LSB First Transfers section). CS must be raised at the end
of the last byte to be transferred, thereby ending the stream mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9553.
The first part writes a 16-bit instruction word into the AD9553,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9553 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation (Bit I15 = 0), the
second part is the transfer of data into the serial control port
buffer of the AD9553. The length of the transfer (1, 2, or 3 bytes;
or streaming mode) is indicated by two bits (Bits[W1:W0]) in
the instruction byte. The length of the transfer indicated by
(Bits[W1:W0]) does not include the 2-byte instruction. CS can
be raised after each sequence of eight bits to stall the bus (except
after the last byte, where it ends the cycle). When the bus is stalled,
the serial transfer resumes when CS is lowered. Stalling on nonbyte
boundaries resets the serial control port.
08565-006
OM1/SCLK
the serial control port state machine enters a wait state until all
data has been sent. If the system controller decides to abort before
the complete transfer of all the data, the state machine must be reset
either by completing the remaining transfer or by returning the
CS line low for at least one complete SCLK cycle (but fewer than
eight SCLK cycles). A rising edge on the CS pin on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
Figure 26. Serial Control Port
OPERATION OF THE SERIAL CONTROL PORT
Framing a Communication Cycle with CS
The CS line gates the communication cycle (a write or a read operation). CS must be brought low to initiate a communication cycle.
The CS stall high function is supported in modes where three
or fewer bytes of data (plus instruction data) are transferred.
Bits[W1:W0] must be set to 00, 01, or 10 (see Table 24). In these
modes, CS may temporarily return high on any byte boundary,
allowing time for the system controller to process the next byte.
CS can go high on byte boundaries only and can go high during
either part (instruction or data) of the transfer. During this period,
Read
If the instruction word is for a read operation (Bit I15 = 1), the
next N × 8 SCLK cycles clock out the data from the address
specified in the instruction word, where N is 1, 2, 3, or 4, as
determined by Bits[W1:W0]. In this case, 4 is used for streaming
mode, where four or more words are transferred per read. The
data read back is valid on the falling edge of SCLK.
The default mode of the AD9553 serial control port is bidirectional mode, and the data readback appears on the SDIO pin.
Rev. 0 | Page 29 of 44
AD9553
OM0/SDIO
14
OM2/CS
SERIAL
CONTROL
PORT
12
REGISTER
UPDATE
EXECUTE AN
INPUT/OUTPUT
UPDATE
MSB/LSB FIRST TRANSFERS
The AD9553 instruction word and byte data can be MSB first or
LSB first. The default for the AD9553 is MSB first. The LSB first
mode can be set by writing a 1 to Register 0x00[6] and requires
that an I/O update be executed. Immediately after the LSB first
bit is set, all serial control port operations are changed to LSB
first order.
AD9553
CORE
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from high address to low address.
In MSB first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle.
08565-007
13
CONTROL REGISTERS
OM1/SCLK
REGISTER BUFFERS
By default, a read request reads the register value that is currently
in use by the AD9553. However, setting Register 0x04[0] = 1
causes the buffered registers to be read instead. The buffered
registers are the ones that take effect during the next I/O update.
Figure 27. Relationship Between the Serial Control Port Register Buffers
and the Control Registers
When LSB first = 1 (LSB first), the instruction and data bytes
must be written from LSB to MSB. Multibyte data transfers
in LSB first format start with an instruction byte that includes
the register address of the least significant data byte followed
by multiple data bytes. The serial control port internal byte
address generator increments for each data byte of the multibyte
transfer cycle.
INSTRUCTION WORD (16 BITS)
The MSB of the instruction word (see Table 25) is R/W, which
indicates whether the instruction is a read or a write. The next
two bits, W1 and W0, are the transfer length in bytes. The final
13 bits are the address bits (Address Bits[A12:A0]) at which the
read or write operation is to begin.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0], which is interpreted
according to Table 24.
The AD9553 serial control port register address decrements from
the register address just written toward 0x00 for multibyte I/O
operations if the MSB first mode is active (default). If the LSB
first mode is active, the serial control port register address
increments from the address just written toward 0x34 for
multibyte I/O operations.
Address Bits[A12:A0] select the address within the register map
that is written to or read from during the data transfer portion
of the communication cycle. The AD9553 uses all of the 13-bit
address space. For multibyte transfers, this address is the starting
byte address.
Unused addresses are not skipped during multibyte I/O operations.
The user should write the default value to a reserved register and
should write only zeros to unmapped registers. Note that it is more
efficient to issue a new write command than to write the default
value to more than two consecutive reserved (or unmapped)
registers.
Table 25. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
R/W
I14
W1
I13
W0
I12
A12
I11
A11
I10
A10
I9
A9
I8
A8
I7
A7
I6
A6
I5
A5
Table 26. Definition of Terms Used in Serial Control Port Timing Diagrams
Parameter
tCLK
tDV
tDS
tDH
tS
tH
tHIGH
tLOW
Description
Period of SCLK
Read data valid time (time from falling edge of SCLK to valid data on SDIO)
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Setup time between CS and SCLK
Hold time between CS and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Rev. 0 | Page 30 of 44
I4
A4
I3
A3
I2
A2
I1
A1
LSB
I0
A0
AD9553
CS
SCLK DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7
A6 A5
A4 A3 A2
A1 A0
D7 D6 D5 D4 D3
16-BIT INSTRUCTION HEADER
D2 D1 D0 D7
D6 D5
REGISTER (N) DATA
D4 D3 D2
D1 D0
DON'T CARE
REGISTER (N – 1) DATA
08565-008
SDIO DON'T CARE
DON'T CARE
Figure 28. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
CS
SCLK
DON'T CARE
SDIO
DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
08565-009
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
REGISTER (N – 3) DATA
Figure 29. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
tHIGH
tDS
tS
tDH
tH
tCLK
tLOW
CS
DON'T CARE
SDIO
DON'T CARE
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
08565-010
SCLK
Figure 30. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CS
SCLK
SDIO
DATA BIT N
08565-011
tDV
DATA BIT N – 1
Figure 31. Timing Diagram for Serial Control Port Register Read
CS
SCLK DON'T CARE
A4
A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4
16-BIT INSTRUCTION HEADER
D5 D6 D7 D0
REGISTER (N) DATA
D1 D2
D3 D4 D5
D6
D7
REGISTER (N + 1) DATA
Figure 32. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data
tS
tH
CS
tCLK
tHIGH
SCLK
tLOW
tDS
tDH
SDIO
BIT N
BIT N + 1
Figure 33. Serial Control Port Timing—Write
Rev. 0 | Page 31 of 44
DON'T CARE
08565-012
A0 A1 A2 A3
08565-013
SDIO DON'T CARE
DON'T CARE
AD9553
REGISTER MAP
A bit that labeled “aclr” is an active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns it to a
Logic 0 state upon completion of the indicated task.
Table 27. Register Map
Addr.
(Hex)
0x00
0x04
0x05
0x0A
Register
Name
Serial port
control
Readback
control
I/O update
Bit 6
LSB first
Unused
Unused
Bit 4
1
Bit 3
1
Bit 2
Soft reset
Bit 1
LSB first
Unused
Bit 5
Soft reset
(aclr)
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
PLL charge
pump and
PFD control
0x0B
VCO control
Calibrate
VCO (aclr)
Charge pump
mode[1:0]
Unused
Unused
Enable
ALC
0x0F
0x12
0x13
0x14
Disable
charge
pump
Unused
Unused
Unused
Unused
ALC threshold[2:0]
VCO level control[5:0]
0x10
0x11
Unused
Unused
Unused
Feedback divider (N) [3:0]
0x15
0x16
0x17
Readback
control
I/O update
(aclr)
PFD
feedback
input edge
control
P1 divider[1:0]
P2 divider[3:0]
Unused
Unused
PFD
reference
input edge
control
Force VCO
to midpoint
frequency
Charge pump clock div[2:0]
Unused
PLL lock
detector
powerdown
Enable SPI
Boost VCO
Enable SPI
supply
control of
control of
VCO
VCO band
calibration
setting
Unused
Unused
Unused
Unused
Default
0x18
0x00
0x00
0x80
VCO band control[6:0]
PLL and
output
frequency
control
(LSB)
Bit 0
0
Charge pump current control[7:0]
(3.5 μA granularity, ~900 μA full scale)
Enable SPI
Enable SPI
control of
control of
charge
antibackpump
lash
current
period
Unused
Unused
Antibacklash control[1:0]
0x0C
0x0D
0x0E
(MSB)
Bit 7
0
Unused
Feedback divider (N)[19:12]
Feedback divider (N)[11:4]
Enable SPI
Enable SPI
Unused
control of
control of
feedback
output
divider
dividers
P1 divider[9:2]
P2 divider[9:4]
Test mux[1:0]
Enable test
0x30
0x00
0x00
0x70
0x80
Unused
0x80
Unused
0x00
Reset PLL
(aclr)
Unused
0x80
0x00
0x00
0x20
0x00
0x01
port
0x18
0x19
0x1A
0x1B
Input
receiver and
band gap
control
XTAL
control
0x1C
0x1D
0x1E
Unused
0
Unused
Reference
reset (aclr)
P0 divider[1:0]
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Band gap voltage adjust[4:0]
(00000 = maximum, 11111 = minimum)
Unused
Unused
Unused
Unused
Unused
Enable SPI
control of
band gap
voltage
Disable SPI
control of
XTAL tuning
capacitance
Unused
Unused
0
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
XTAL tuning capacitor control[5:0]
(0.25 pF per bit, inverted binary coding)
Rev. 0 | Page 32 of 44
0x00
0x20
0x00
0x80
0x00
0x00
AD9553
Addr.
(Hex)
0x1F
0x20
Register
Name
REFA
frequency
control
0x21
0x22
Unused
0x23
REFB
frequency
control
0x24
0x25
0x26
Unused
0x27
DCXO
frequency
and
reference
switchover
control
Unused
0x28
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
REFA divider (RA)[13:6]
REFA divider (RA) [5:0]
Enable SPI
control of x2A
Select x2A
Unused
Unused
Enable SPI
control of
/5A
Unused
Bit 1
Select /5A
Unused
Unused
Enable SPI
control of RA
Unused
Unused
Unused
Unused
Unused
Select x2B
Unused
Enable SPI
control of
/5B
Unused
Select /5B
Unused
Unused
Enable SPI
control of RB
Unused
Unused
Unused
0x00
Unused
Unused
Unused
Unused
Unused
0x00
Unused
0x00
Unused
XO divider (RXO)[13:6]
0x40
Switchover mode[1:0]
REFA Diff
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
OUT1 driver
control
OUT1 drive
strength
OUT1
powerdown
0x33
Unused
Unused
Unused
0x34
OUT2 driver
control
OUT2 drive
strength
OUT2
powerdown
0x2A
to
0x31
0x32
0x00
0x80
REFB divider (RB)[5:0]
Enable SPI
control of
x2B
Unused
XO divider (RXO)[5:0]
OUT1 mode control[2:0]
Unused
Unused
Unused
OUT2 mode control[2:0]
Rev. 0 | Page 33 of 44
Default
0x40
Unused
REFB divider (RB)[13:6]
Enable SPI
control of RXO
Unused
0x29
(LSB)
Bit 0
OUT1 CMOS polarity[1:0]
Unused
Unused
OUT2 CMOS polarity[1:0]
Unused
0x00
Unused
0x00
Unused
Use Bits[5:3]
as source for
OUT1 mode
control
Unused
Use Bits[5:3]
as source for
OUT2 mode
control
0xA8
0x00
0xA8
AD9553
REGISTER MAP DESCRIPTIONS
Control bit functions are active high unless stated otherwise. Register address values are always hexadecimal unless otherwise indicated.
Serial Port Control (Register 0x00 to Register 0x05)
Table 28.
Address
0x00
0x04
0x05
Bit
7
6
Bit Name
Unused
LSB first
5
4
Soft reset
Unused
[3:0]
[7:1]
0
Unused
Unused
Readback control
[7:1]
0
Unused
I/O update
Description
Forced to Logic 0 internally, which enables 3-wire mode only.
Bit order for SPI port.
0 = most significant bit and byte first (default).
1 = least significant bit and byte first.
Software initiated reset (register values set to default). This is an autoclearing bit.
Forced to Logic 1 internally, which enables 16-bit mode (the only mode supported by
the device).
Mirrored version of the contents of Register 0x00[7:4] (that is, Bits[3:0] = Bits[7:4]).
Unused.
For buffered registers, serial port readback reads from actual (active) registers instead of
from the buffer.
0 = reads values currently applied to the internal logic of the device (default).
1 = reads buffered values that take effect on next assertion of I/O update.
Unused.
Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the internal
control registers of the device. This is an autoclearing bit.
PLL Charge Pump and PFD Control (Register 0x0A to Register 0x0D)
Table 29.
Address
0x0A
Bit
[7:0]
Bit Name
Charge pump current control
0x0B
7
Enable SPI control of charge
pump current
6
Enable SPI control of
antibacklash period
[5:4]
Charge pump mode
3
Disable charge pump
2
PFD feedback input edge
control
1
PFD reference input edge
control
0
Force VCO to midpoint
frequency
Description
These bits set the magnitude of the PLL charge pump current. The granularity is
~3.5 μA with a full-scale magnitude of ~900 μA. Default is 0x80, or ~448 μA.
Register 0x0A is ineffective unless Register 0x0B[7] = 1.
Controls the functionality of Register 0x0A.
0 = charge pump current based on A[3:0] and Y[5:0] pins per Table 16 (default).
1 = charge pump current defined by Register 0x0A.
Controls the functionality of Register 0x0D[7:6].
0 = the device automatically controls the antibacklash period (default).
1 = antibacklash period defined by Register 0x0D[7:6].
Controls the mode of the PLL charge pump.
00 = tristate.
01 = pump up.
10 = pump down.
11 = normal (default).
Disables the charge pump (functionally equivalent to Register 0x0B[5:4] = 00).
0 = normal operation (default).
1 = disable charge pump.
Selects the polarity of the active edge of the PLL’s feedback input.
0 = positive edge (default).
1 = negative edge.
Selects the polarity of the active edge of the PLL’s reference input.
0 = positive edge (default).
1 = negative edge.
Selects VCO control voltage functionality.
0 = normal VCO operation (default).
1 = force VCO control voltage to midscale.
Rev. 0 | Page 34 of 44
AD9553
Address
0x0C
Bit
[7:3]
[2:0]
Bit Name
Unused
Charge Pump Clock Div
0x0D
[7:6]
Antibacklash control
[5:1]
0
Unused
PLL lock detector powerdown
Description
Unused.
Enables the PFD clock dividers (used for test only via test mux).
000 = test clocks disabled, normal operation (default).
001 = divide feedback clock by 2.
010 = divide PFD reference input clock by 2.
011 = divide PFD reference input and feedback clocks by 2.
100 = divide pump-up clock by 2.
101 = divide pump-up and feedback clocks by 2.
110 = divide pump-up and PFD reference input clocks by 2.
111 = divide feedback, pump-up, and pump-down clocks by 2.
Controls the PFD antibacklash period of the PLL. These bits are ineffective unless
Register 0x0B[6] = 1.
00 = minimum (default).
01 = low.
10 = high.
11 = maximum.
Unused.
Controls power-down of the PLL lock detector.
0 = lock detector active (default).
1 = lock detector powered down.
VCO Control (Register 0x0E to Register 0x10)
Table 30.
Address
0x0E
Bit
7
Bit Name
Calibrate VCO
6
Enable ALC
[5:3]
ALC threshold
2
Enable SPI control of VCO
calibration
1
Boost VCO supply
0
Enable SPI control of VCO band
setting
0x0F
[7:2]
VCO level control
0x10
[1:0]
[7:1]
Unused
VCO band control
0
Unused
Description
Initiates VCO calibration (this is an autoclearing bit).
This bit is ineffective unless Register 0x0E[2] = 1.
Enables automatic level control (ALC) of the VCO.
0 = Register 0x0F[7:2] defines the VCO level.
1 = the device automatically controls the VCO level (default).
Controls the VCO ALC threshold detector level from minimum (000) to maximum
(111). The default is 110.
Enables the functionality of Register 0x0E[7].
0 = the device automatically performs VCO calibration (default).
1 = VCO calibration controlled by Register 0x0E[7].
Selects VCO supply voltage.
0 = normal supply voltage (default).
1 = increase supply voltage by 100 mV.
Controls VCO band setting functionality.
0 = the device automatically selects the VCO band (default).
1 = VCO band defined by Register 0x10[7:1].
Controls the VCO amplitude from minimum (00 0000) to maximum (11 1111). The
default is 10 0000.
These bits are ineffective unless Register 0x0E[6] = 0.
Unused.
Controls the VCO frequency band from minimum (000 0000) to maximum (111 1111).
The default is 100 0000.
These bits are ineffective unless Register 0x0E[0] = 1.
Unused.
Rev. 0 | Page 35 of 44
AD9553
PLL and Output Frequency Control (Register 0x11 to Register 0x19)
Table 31.
Address
0x11
0x12
0x13
0x14
Bit
[7:0]
[7:0]
[7:0]
[7:4]
Bit Name
Unused
Feedback divider (N)
Feedback divider (N)
Feedback divider (N)
3
Enable SPI control of
feedback divider
2
Enable SPI control of
output dividers
1
0
Unused
Reset PLL
0x15
0x16
[7:0]
[7:6]
P1 divider
P1 divider
0x17
[5:0]
[7:4]
P2 divider
P2 divider
3
Enable test port
[2:1]
Test Mux
0
7
[6:5]
Unused
Unused
P0 divider
[4:0]
[7:0]
Unused
Unused
0x18
0x19
Description
Unused.
Bits[19:12] of the 20-bit feedback divider (N).
Bits[11:4] of the 20-bit feedback divider (N).
Bits[3:0] of the 20-bit feedback divider (N). Default is N = 0x80000 (524,288).
The feedback divider bits are ineffective unless Register 0x14[3] = 1.
Enables SPI port control of the feedback divider value (N).
0 = The A[3:0] and Y[5:0] pins define N per Table 16 (default).
1 = The 20-bit value in the feedback divider register defines N.
Enables SPI port control of the output dividers P0, P1, and P2.
0 = The Y[5:0] pins define the output divider values per
Table 15 (default).
1 = The SPI port registers (0x15, 0x16, 0x18) define the output divider values.
Unused.
Controls initialization of the PLL.
0 = normal operation (default).
1 = resets the counters and logic associated with the PLL but does not affect the output dividers.
Bits[9:2] of the 11-bit P1 divider.
Bits[1:0] of the 11-bit P1 divider (the default P1 divider register value is 128 decimal).
The P1 divider bits are ineffective unless Register 0x14[2] = 1.
Bits[9:4] of the 11-bit P2 divider.
Bits[3:0] of the 11-bit P2 divider.
The P2 divider bits are ineffective unless Register 0x14[2] = 1.
Enables use of the LOCKED pin as a test port.
0 = the LOCKED pin indicates PLL status (default).
1 = the LOCKED pin outputs a test signal per Register 0x17[2:1].
Test mux select bits.
00 = crystal oscillator output (XO).
01 = PFD pump up clock divided-by-2 (UP/2).
10 = PFD reference input clock divided-by-2 (FPFD/2).
11 = PFD feedback clock divided-by-2 (FDBK/2).
Unused.
When programming this register write a Logic 0 to this bit.
Sets the P0 divider to divide-by-5 or divide-by-6.
00 = invalid.
01 = divide-by-5.
10 = divide-by-6.
11 = invalid.
The P0 divider bits are ineffective unless Register 0x14[2] = 1.
Unused.
Unused.
Rev. 0 | Page 36 of 44
AD9553
Input Receiver and Band Gap Control (Register 0x1A)
Table 32.
Address
0x1A
Bit
7
Bit Name
Receiver reset
[6:2]
Band gap voltage adjust
1
0
Unused
Enable SPI control of band
gap voltage
Description
Input receiver reset control. This is an autoclearing bit.
0 = normal operation (default).
1 = resets the reference input hardware (detectors, dividers, switchover control,
crystal oscillator and its associated frequency doubler).
Controls the band gap voltage setting from minimum (00000) to maximum (11111).
Default is 00000.
The band gap voltage adjust bits are ineffective unless Register 0x1A[0] = 1.
Unused.
Enables functionality of Register 0x1A[6:2].
0 = the device automatically selects receiver band gap voltage (default).
1 = Register 0x1A[6:2] defines the receiver band gap voltage.
XTAL Control (Register 0x1B to Register 0x1E)
Table 33.
Address
0x1B
0x1C
0x1D
0x1E
Bit
7
Bit Name
Disable SPI control of XTAL
tuning capacitance
6
[5:0]
Unused
XTAL tuning capacitor control
[7:0]
[7:0]
[7:0]
Unused
Unused
Unused
Description
Disables functionality of Register 0x1B[5:0].
0 = tuning capacitance defined by Register 0x1B[5:0].
1 = the device automatically selects XTAL tuning capacitance (default).
When programming this register write a Logic 0 to this bit.
Capacitance value coded as inverted binary (0.25 pF per bit); that is, 111111 is 0 pF,
111110 is 0.25 pF, and so on. The default value, 000000, is 15.75 pF.
The XTAL tuning capacitor bits are ineffective unless Register 0x1B[7] = 0.
Unused.
Unused.
Unused.
REFA Frequency Control (Register 0x1F to Register 0x22)
Table 34.
Address
0x1F
0x20
0x21
0x22
Bit
[7:0]
[7:2]
Bit Name
REFA divider (RA)
REFA divider (RA)
1
Enable SPI control of RA
0
7
Unused
Enable SPI control of x2A
6
Select x2A
5
Enable SPI control of /5A
4
Select /5A
[3:0]
[7:0]
Unused
Unused
Description
Bits[13:6] of the 14-bit REFA divider.
Bits[5:0] of the 14-bit REFA divider (default: RA = 2048 decimal).
The REFA divider bits are ineffective unless Register 0x20[1] = 1.
Enables SPI port control of the REFA divider value (RA).
0 = The A[3:0] pins define RA per Table 14 (default).
1 = The 14-bit value in the REFA divider register defines RA.
Unused.
Enables SPI control of the REFA 2x frequency multiplier (x2A) per 0x21[6].
0 = the device automatically selects x2A per Table 14 (default).
1 = Register 0x21[6] controls the selection of x2A.
Selects x2A.
0 = bypass x2A (default).
1 = select x2A.
This bit is ineffective unless Register 0x21[7] = 1.
Enables SPI control of the /5A prescaler per 0x21[4].
0 = the device automatically selects /5A per Table 14 (default).
1 = Register 0x21[4] controls the selection of /5A.
Selects /5A.
0 = bypass /5A (default).
1 = select /5A.
This bit is ineffective unless Register 0x21[5] = 1.
Unused.
Unused.
Rev. 0 | Page 37 of 44
AD9553
REFB Frequency Control (Register 0x23 to Register 0x26)
Table 35.
Address
0x23
0x24
0x25
0x26
Bit
[7:0]
[7:2]
Bit Name
REFB divider (RB)
REFB divider (RB)
1
Enable SPI control of RB
0
7
Unused
Enable SPI control of x2B
6
Select x2B
5
Enable SPI control of /5B
4
Select /5B
[3:0]
[7:0]
Unused
Unused
Description
Bits[13:6] of the 14-bit REFB divider.
Bits[5:0] of the 14-bit REFB divider (default: RB = 4096 decimal).
The REFB divider bits are ineffective unless Register 0x24[1] = 1.
Enables SPI port control of the REFB divider value (RB).
0 = The A[3:0] pins define RB per Table 14 (default).
1 = The 14-bit value in the REFB divider register defines RB.
Unused.
Enables SPI control of the REFB 2x frequency multiplier (x2B) per Register 0x25[6].
0 = the device automatically selects x2B per Table 14 (default).
1 =Register 0x25[6] controls the selection of x2B.
Selects x2B.
0 = bypass x2B (default).
1 = select x2B.
This bit is ineffective unless Register 0x25[7] = 1.
Enables SPI control of the /5B prescaler per Register 0x25[4].
0 = the device automatically selects /5B per Table 14 (default).
1 = Register 0x25[4] controls the selection of /5B.
Selects /5B.
0 = bypass /5B (default).
1 = select /5B.
This bit is ineffective unless Register 0x25[5] = 1.
Unused.
Unused.
DCXO Frequency and Reference Switchover Control (Register 0x27 to Register 0x31)
Table 36.
Address
0x27
0x28
0x29
0x2A to
0x31
Bit
[7:0]
[7:2]
Bit Name
XO divider (RXO)
XO divider (RXO)
1
Enable SPI control of RXO
0
[7:6]
Unused
Switchover mode
5
REFA diff
[4:0]
[7:0]
Unused
Unused
Description
Bits[13:6] of the 14-bit XO divider.
Bits[5:0] of the 14-bit XO divider (default: RXO = 2048 decimal).
The XO divider bits are ineffective unless Register 0x28[1] = 1.
Enables SPI port control of the XO divider value (RXO).
0 = The A[3:0] pins define RXO per Table 14 (default).
1 = The 14-bit value in the XO divider register defines RXO.
Unused.
Selects the switchover operating mode.
00 = revertive switchover (default).
01 = nonrevertive switchover.
10 = selects REFA as the active reference.
11 = selects REFB as the active reference.
Enables the differential input reference function.
0 = normal single-ended operation of REFA and REFB (default).
1 = REFA configured as a differential reference in which the REFA pin functions as
one differential input and the REFB/REFA pin functions as the other differential input.
In this configuration, the REFB channel and switchover functionality are both
unavailable.
Unused.
Unused.
Rev. 0 | Page 38 of 44
AD9553
OUT1 Driver Control (Register 0x32)
Table 37.
Address
0x32
Bit
7
Bit Name
OUT1 drive strength
6
OUT1 power-down
[5:3]
OUT1 mode control
[2:1]
OUT1 CMOS polarity
0
Use Bits[5:3] as source for
OUT1 mode control
Description
Controls the output drive capability of the OUT1 driver.
0 = weak.
1 = strong (default).
Controls power-down functionality of the OUT1 driver.
0 = OUT1 active (default).
1 = OUT1 powered down.
OUT1 driver mode selection.
000 = CMOS, both pins active.
001 = CMOS, positive pin active, negative pin tristate.
010 = CMOS, positive pin tristate, negative pin active.
011 = CMOS, both pins tristate.
100 = LVDS.
101 = LVPECL (default).
110 = not used.
111 = not used.
Selects the polarity of the OUT1 pins in CMOS mode.
00 = positive pin is normal polarity and negative pin is inverted polarity (default).
01 = positive pin is normal polarity and negative pin is normal polarity.
10 = positive pin is inverted polarity and negative pin logic is inverted polarity.
11 = positive pin logic is inverted polarity and negative pin is normal polarity.
These bits are ineffective unless Bits[5:3] select CMOS mode. See the Output Driver
Polarity (CMOS) section for the definition of normal and inverted polarity.
Controls OUT1 driver functionality.
0 = OUT1 mode determined by the OM[2:0] pins (default).
1 = OUT1 mode defined by Register 0x32[5:3].
Reserved (Register 0x33)
Table 38.
Address
0x33
Bit
[7:0]
Bit Name
Unused
Description
Unused.
Rev. 0 | Page 39 of 44
AD9553
OUT2 Driver Control (Register 0x34)
Table 39.
Address
0x34
Bit
7
Bit Name
OUT2 drive strength
6
OUT2 power-down
[5:3]
OUT2 mode control
[2:1]
OUT2 CMOS polarity
0
Use Bits[5:3] as source for
OUT2 mode control
Description
Controls the output drive capability of the OUT2 driver.
0 = weak.
1 = strong (default).
Controls power-down functionality of the OUT2 driver.
0 = OUT2 active (default).
1 = OUT2 powered down.
OUT2 driver mode selection.
000 = CMOS, both pins active.
001 = CMOS, positive pin active, negative pin tristate.
010 = CMOS, positive pin tristate, negative pin active.
011 = CMOS, both pins tristate.
100 = LVDS.
101 = LVPECL (default).
110 = not used.
111 = not used.
Selects the polarity of the OUT2 pins in CMOS mode.
00 = positive pin is normal polarity and negative pin is inverted polarity (default).
01 = positive pin is normal polarity and negative pin is normal polarity.
10 = positive pin is inverted polarity and negative pin logic is inverted polarity.
11 = positive pin logic is inverted polarity and negative pin is normal polarity.
These bits are ineffective unless Bits[5:3] select CMOS mode. See the Output Driver
Polarity (CMOS) section for the definition of normal and inverted polarity.
Controls OUT2 driver functionality.
0 = OUT2 mode determined by the OM[2:0] pins (default).
1 = OUT2 mode defined by Register 0x34[5:3].
Rev. 0 | Page 40 of 44
AD9553
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
0.50
BSC
TOP VIEW
0.80
0.75
0.70
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
0.50
0.40
0.30
PIN 1
INDICATOR
1
24
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
112408-A
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 34. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very, Very Thin Quad
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9553BCPZ
AD9553BCPZ-REEL7
AD9553/PCBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 41 of 44
Package Option
CP-32-7
CP-32-7
AD9553
NOTES
Rev. 0 | Page 42 of 44
AD9553
NOTES
Rev. 0 | Page 43 of 44
AD9553
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08565-0-4/10(0)
Rev. 0 | Page 44 of 44