AD AD1812JS Soundport controller Datasheet

a
SoundPort Controller
AD1812
PRODUCT OVERVIEW
FEATURES
Compatibility with:
Sound Blaster Pro*
AdLib*
Windows* Sound System
16-Bit SD Stereo Codec
MPC Level-2+ Mixer
Dual DMA/Full Duplex Operation
On-Chip FIFO Buffers
Sample Rates from 5.5 kHz to 50 kHz
ADPCM Compression/Decompression
Plug and Play Compliant
Compatible MIDI MPU-401 Port
Integrated Game Port
Free Supporting Software:
Windows 3.1 Driver
Windows 95 Driver
Control Applets
Diagnostics
Power Management Modes
Operation from +5 V Supply
16-Bit Parallel Interface to ISA Bus
24 mA Bus Drive Capability
The AD1812 SoundPort® Controller is a single chip audio subsystem for adding 16-bit stereo audio to personal computers.
The AD1812 is compatible with Sound Blaster Pro, AdLib, and
the Microsoft* Windows Sound System. The AD1812 provides
an integrated audio solution for enhanced business audio, entertainment sound effects, and multimedia applications.
The AD1812 audio subsystem combines an integrated digital
audio controller, a powerful signal processor, a mixer, and a
16-bit Σ∆ stereo codec. The DOS games register set, the Windows Sound System register set, music synthesis hardware, an
MPU-401 compatible UART interface, a game port (with
timer), and a Plug and Play ISA interface are all contained on
chip. The on-chip Plug and Play (PnP) routine provides configuration services for the internal logical devices and an external modem chipset.
The AD1812 can record compress and playback voice, sound
and music. The system provides all PC 95 audio conversion and
compatibility requirements for a multimedia enabled PC.
(continued on Page 12)
*Sound Blaster Pro is a trademark of Creative Labs, Ltd.
*AdLib is a trademark of AdLib Multimedia.
*Windows is a trademark and Microsoft is a registered trademark of
*Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
XTALI/O
A_1
B_1
A_X
B_X
A_2
B_2
A_Y
B_Y
MIDI _IN
MIDI _OUT
AD1812
JOYSTICK/GAME PORT INTERFACE
OSCILLATORS
MODEM_IRQ
MODEM_SEL
LINE
AUX1
G
M
L_OUT
MONO I/O
M
Σ
Σ
G
G
M
M
Σ
Σ
Σ
Σ
R_OUT
G
G
MONO_IN
M
M
Σ
DRQ (0, 1, 3, 5, 6, 7)
PGA
Σ ∆ A/D
CONVERTER
FORMAT
ATTN/
MUTE
Σ ∆ D/A
CONVERTER
GAME
REGISTER
SET
&
WSS
REGISTER
SET
Σ
Σ
PC_A (15:0)
AEN
DACK (0, 1, 3, 5, 6, 7)
IOR
FIFO
SBHE
IO_CH16
ROM
CONTROL
REGISTERS
PWRDWN
PLUG
AND
PLAY
REGISTERS
PnP
RAM
DACIN
Σ ∆ D/A
CONVERTER
PC_D (15:0)
PARALLEL
BUS
INTERFACE
IOW
FORMAT
G = GAIN/AMPLIFIER BLOCK
M = MUTE BLOCK
ATTN
IRQ (3, 4, 5, 7, 9, 10, 11, 12)
FIFO
DIGITAL MIX
ATTENUATE
AUX2
DACOUT
MPU-401 UART
0dB/
20dB
SELECTOR
MIC
ADSP-2171
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD1812–SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature
Digital Supply (VDD)
Analog Supply (VCC)
0
5.0
5.0
°C
V
V
Sample Rate (FS)
Input Signal
Analog Output Passband
VIH
48
1008
20 Hz to 20 kHz
2.0
kHz
Hz
VIL
VOH
VOL
0.8
2.4
0.4
V
V
V
DAC Test Conditions
Calibrated
0 dB Attenuation
Input Full Scale
16-Bit Linear Mode
10 kΩ Output Load
Mute Off
ADC Test Conditions
Calibrated
0 dB Gain
Input –1.0 dB Relative to Full Scale
Line Input Selected
16-Bit Linear Mode
V
ANALOG INPUT
Parameter
Min
Input Voltage (RMS Values Assume Sine Wave Input)
LINE, AUX1, MONO_IN, AUX2, DACIN
2.55
MIC with +20 dB Gain (MGE = 1)
0.250
MIC with 0 dB Gain (MGE = 0)
2.55
10
Input Impedance*
Input Capacitance*
Typ
1
2.83
0.1
0.283
1
2.83
17
Max
3.11
0.316
3.11
15
Units
V rms
V p-p
V rms
V p-p
V rms
V p-p
kΩ
pF
PROGRAMMABLE GAIN AMPLIFIER—ADC
Parameter
Min
Typ
Max
Units
Step Size (0 dB to 22.5 dB)
(All Steps Tested)
PGA Gain Range Span
1.3
1.5
1.7
dB
21.5
22.5
23.5
dB
AUXILIARY, LINE, MICROPHONE AND MONO INPUT ANALOG GAIN/AMPLIFIERS/ATTENUATORS
Parameter
Min
Typ
Max
Units
1.25
1
45.0
1.5
1.5
46.5
1.75
2.0
47.5
dB
dB
dB
2.5
2.2
43
3.0
3.0
45
3.6
3.85
46
dB
dB
dB
Parameter
Min
Typ
Max
Units
Passband
Passband Ripple
Transition Band
Stopband
Stopband Rejection
Group Delay
Group Delay Variation Over Passband
0
0.4 × FS
± 0.1
0.6 × FS
∞
Hz
dB
Hz
Hz
dB
sec
µs
Step Size: AUX1, AUX2, DACIN, LINE, MIC (All Steps Tested)
(+12 dB to –30 dB)
(–31.5 dB to –34.5 dB)
Input Gain/Attenuation Range: AUX1, AUX2, DACIN, LINE, MIC
Step Size: MONO_IN (All Steps Tested)
(0 dB to –39 dB)
(–42 dB to –45 dB)
Input Gain/Attenuation Range: MONO_IN
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
0.4 × FS
0.6 × FS
74
15/FS
0.0
*Guaranteed not tested.
Specifications subject to change without notice.
–2–
REV. 0
AD1812
ANALOG-TO-DIGITAL CONVERTERS
Parameter
Resolution
Dynamic Range (–60 dB Input THD+N Referenced to Full Scale,
A-Weighted)
THD+N (Referenced to Full Scale)
Min
Typ
80
16
86
Max
Units
Bits
dB
0.02
–74
%
dB
dB
–90
–90
–90
–90
–80
–80
–80
–80
± 10
± 0.5
10
dB
dB
dB
dB
%
dB
mV
Min
Typ
Max
Units
74
16
81
–78
80
Signal-to-Intermodulation Distortion* (CCIF Method)
ADC Crosstalk*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Line to MIC (Input LINE, Ground and Select MIC, Read ADC)
Line to AUX1
Line to AUX2
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error
DIGITAL-TO-ANALOG CONVERTERS
Parameter
Resolution
Dynamic Range (–60 dB Input THD+N Referenced to Full Scale,
A-Weighted)
THD+N (Referenced to Full Scale)
–77
Signal-to-Intermodulation Distortion* (CCIF Method)
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R,
Zero L, Measure L_OUT)
Total Out-of-Band Energy (Measured from 0.6 × FS to 100 kHz)*
Audible Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz)*
–90
Bits
dB
0.022
–73
90
± 15
± 0.5
–80
%
dB
dB
%
dB
dB
–60
–70
dB
dB
DAC ATTENUATOR
Parameter
Min
Typ
Max
Units
Step Size (0 dB to –22.5 dB)
Step Size (–22.5 dB to –94.5 dB)*
Output Attenuation Range Span*
Mute Attenuation of 0 dB Fundamental*
1.3
1.0
93.5
1.5
1.5
94.5
1.7
2.0
95.5
80
dB
dB
dB
dB
Parameter
Min
Typ
Max
Units
Step Size (0 dB to –22.5 dB)
Step Size (–22.5 dB to –94.5 dB)*
Digital Mix Attenuation Range Span*
1.3
1.0
93.5
1.5
1.5
94.5
1.7
2.0
95.5
dB
dB
dB
DIGITAL MIX ATTENUATOR
*Guaranteed not tested.
Specifications subject to change without notice.
REV. 0
–3–
AD1812
ANALOG OUTPUT
Parameter
Full-Scale Output Voltage
OL = 0
OL = 1
Output Impedance*
External Load Impedance
Output Capacitance*
External Load Capacitance
VREF
VREF Output Impedance
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)*
Min
Typ
Max
Units
1.8
2.5
2.0
2.8
2.2
3.11
600
±5
V p-p
V p-p
Ω
kΩ
pF
pF
V
kΩ
mV
Max
Units
1.0
±1
5
dB
LSB
Degrees
Max
Units
10
2.05
2.25
4
15
100
2.45
SYSTEM SPECIFICATIONS
Parameter
Min
Typ
System Frequency Response Ripple* (Line In to Line Out)
Differential Nonlinearity*
Phase Linearity Deviation*
STATIC DIGITAL SPECIFICATIONS
Parameter
Min
High-Level Input Voltage (VIH): Digital Inputs
Low-Level Input Voltage (VIL)
High-Level Output Voltage (VOH), IOH = 24 mA
Low-Level Output Voltage (VOL), IOL = 24 mA
Input Leakage Current
Output Leakage Current
2
Typ
0.4
10
10
V
V
V
V
µA
µA
Max
Units
5.25
5.25
250
1.25
55
195
15
1
V
V
mA
W
mA
mA
mA
mA
0.8
2.4
–10
–10
POWER SUPPLY
Parameter
Min
Power Supply Range—Analog
Power Supply Range—Digital
Power Supply Current
Power Dissipation
Analog Supply Current
Digital Supply Current
Digital Power Supply Current—Power Down
Analog Power Supply Current—Power Down
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
4.75
4.75
Typ
40
dB
CLOCK SPECIFICATIONS*
Parameter
Min
Typ
Max
Units
Input Clock Frequency
Recommended Clock Duty Cycle
Power Up Initialization Time
6
10
14.31818
50
18
90
500
MHz
%
ms
*Guaranteed not tested.
Specifications subject to change without notice.
–4–
REV. 0
AD1812
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
IOW/IOR Strobe Width
IOW/IOR Rising to IOW/IOR Falling
Write Data Setup to IOW Rising
IOR Falling to Valid Read Data
AEN Setup to IOW/IOR Falling
AEN Hold from IOW/IOR Rising
Adr Setup to IOW/IOR Falling
Adr Hold from IOW/IOR Rising
DACK Rising to IOW/IOR Falling
IOW/IOR Rising to DACK Falling
DACK Setup to IOW/IOR Falling
Data Hold from IOR Rising
Data Hold from IOW Rising
DRQ Hold from IOW/IOR Falling
DACK Hold from IOW Rising
DACK Hold from IOR Rising
tSTW
tBWDN
tWDSU
tRDDV
tAESU
tAEHD
tADSU
tADHD
tDKSU1
tDKHD1
tDKSU2
tDHD1
tDHD2
tDRHD
tDKHD2
tDKHD3
100
80
10
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
10
0
10
10
20
0
10
20
15
25
10
10
*Guaranteed, not tested.
Specifications subject to change without notice.
General Notes
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield
meaningful results for an additional device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add
up parameters to derive longer times. Note that all 8-bit DMA transfers occur on channels 0, 1, and 3, while all 16-bit DMA transfers occur on channels 5, 6, and 7.
DRQ
(0, 1, 3, 5, 6, 7)
DRQ
(0, 1, 3, 5, 6, 7)
tDKSU1
DACK
(0, 1, 3, 5, 6, 7)
tDKSU1
tDKHD1
tAESU
tDKHD1
DACK
(0, 1, 3, 5, 6, 7)
tAEHD
tAEHD
tAESU
AEN
AEN
tSTW
tSTW
IOR
IOW
tDHD1
tRDDV
PC_D (7:0) /
PC_D (15:0)
tWDSU
PC_D (7:0) /
PC_D (15:0)
tADSU
tADHD
PC_A (15:0)
DRQ
(0, 1, 3, 5, 6, 7)
Figure 2. PIO Write Cycle
DRQ
(0, 1, 3, 5, 6, 7)
tDKSU2
tDRHD
DACK
(0, 1, 3, 5, 6, 7)
tAESU
tDKHD3
DACK
(0, 1, 3, 5, 6, 7)
tAEHD
tDKSU2
tDRHD
tAESU
tDKHD2
tAEHD
AEN
AEN
tSTW
tSTW
IOW
IOR
tRDDV
tDHD1
PC_D (7:0) /
PC_D (15:0)
Figure 3. DMA Read Cycle
REV. 0
tADHD
PC_A (15:0)
Figure 1. PIO Read Cycle
PC_D (7:0) /
PC_D (15:0)
tDHD2
tADSU
tWDSU
Figure 4. DMA Write Cycle
–5–
tDHD2
AD1812
Table I. Codec Transfer 16-Bit Interface, No Byte Swap (P/CINF8 = 0, P/CBSW = 0)*
Format
Word 1 (16-Bit)
Word 0 (16-Bit)
MSB
LSB
MSB
LSB
Upper 8 Bits of
Sample 1
Lower 8 Bits of
Sample 1
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Left Channel
Left Channel
Left Channel
Left Channel
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Right Channel
Right Channel
Left Channel
Left Channel
Mono, 8-Bit
Linear PCM
m-Law PCM
A-Law PCM
Sample 3, 8 Bits
Sample 2, 8 Bits
Sample 1, 8 Bits
Sample 0, 8 Bits
Left Channel
Left Channel
Left Channel
Left Channel
Stereo, 8-Bit
Linear PCM
m-Law PCM
A-Law PCM
Sample 1, 8 Bits
Sample 1, 8 Bits
Sample 0, 8 Bits
Sample 0, 8 Bits
Right Channel
Left Channel
Right Channel
Left Channel
Mono, 16-Bit
Little Endian
Stereo, 16-Bit
Little Endian
Mono, 4-Bit
Sample 7,
4 Bits
Sample 6,
4 Bits
Sample 5,
4 Bits
Sample 4,
4 Bits
Sample 3,
4 Bits
Sample 2,
4 Bits
Sample 1,
4 Bits
Sample 0,
4 Bits
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Sample 3,
4 Bits
Sample 3,
4 Bits
Sample 2,
4 Bits
Sample 2,
4 Bits
Sample 1,
4 Bits
Sample 1,
4 Bits
Sample 0,
4 Bits
Sample 0,
4 Bits
Right
Channel
Left
Channel
Right
Channel
Left
Channel
Right
Channel
Left
Channel
Right
Channel
Left
Channel
IMA-ADPCM
Stereo, 4-Bit
IMA-ADPCM
Mono, 16-Bit
Lower 8 Bits of
Sample 1
Upper 8 Bits of
Sample 1
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Left Channel
Left Channel
Left Channel
Left Channel
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Right Channel
Right Channel
Left Channel
Left Channel
Big Endian
Stereo, 16-Bit
Big Endian
*Regardless of the data format used, the AD1812’s codec always transfers 32 bits of data (two 16-bit words).
tSTW
IOR/IOW
DATA (15:0)
tSTW
tBWDN
WORD 0
WORD 1
Figure 5. Codec Transfers 16-Bit Interface
–6–
REV. 0
AD1812
Table II. Codec Transfer 16-Bit Interface with Byte Swap (P/CINF8 = 0, P/CBSW = 1)*
Format
Word 1 (16-Bit)
Word 0 (16-Bit)
MSB
LSB
MSB
LSB
Lower 8 Bits of
Sample 1
Upper 8 Bits of
Sample 1
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Left Channel
Left Channel
Left Channel
Left Channel
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Right Channel
Right Channel
Left Channel
Left Channel
Mono, 8-Bit
Linear PCM
m-Law PCM
A-Law PCM
Sample 2, 8 Bits
Sample 3, 8 Bits
Sample 0, 8 Bits
Sample 1, 8 Bits
Left Channel
Left Channel
Left Channel
Left Channel
Stereo, 8-Bit
Linear PCM
m-Law PCM
A-Law PCM
Sample 1, 8 Bits
Sample 1, 8 Bits
Sample 0, 8 Bits
Sample 0, 8 Bits
Left Channel
Right Channel
Left Channel
Right Channel
Mono, 16-Bit
Little Endian
Stereo, 16-Bit
Little Endian
Mono, 4-Bit
Sample 5,
4 Bits
Sample 4,
4 Bits
Sample 7,
4 Bits
Sample 6,
4 Bits
Sample 1,
4 Bits
Sample 0,
4 Bits
Sample 3,
4 Bits
Sample 2,
4 Bits
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Sample 2,
4 Bits
Sample 2,
4 Bits
Sample 3,
4 Bits
Sample 3,
4 Bits
Sample 0,
4 Bits
Sample 0,
4 Bits
Sample 1,
4 Bits
Sample 1,
4 Bits
Right
Channel
Left
Channel
Right
Channel
Left
Channel
Right
Channel
Left
Channel
Right
Channel
Left
Channel
IMA-ADPCM
Stereo, 4-Bit
IMA-ADPCM
Mono, 16-Bit
Upper 8 Bits of
Sample 1
Lower 8 Bits of
Sample 1
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Left Channel
Left Channel
Left Channel
Left Channel
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Right Channel
Right Channel
Left Channel
Left Channel
Big Endian
Stereo, 16-Bit
Big Endian
*Regardless of the data format used, the AD1812’s codec always transfers 32 bits of data (two 16-bit words).
tSTW
IOR/IOW
DATA (15:0)
tSTW
tBWDN
WORD 0
WORD 1
Figure 6. Codec Transfers 16-Bit Interface
REV. 0
–7–
AD1812
Table III. Codec Transfer 8-Bit Interface (P/CINF8 = 1)*
Format
Byte 3
MSB
LSB
Byte 2
MSB
LSB
Byte 1
MSB
LSB
Byte 0
MSB
LSB
Mono, 16-Bit
Upper 8 Bits of
Sample 1
Lower 8 Bits of
Sample 1
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Left Channel
Left Channel
Left Channel
Left Channel
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Right Channel
Right Channel
Left Channel
Left Channel
Mono, 8-Bit
Linear PCM
m-Law PCM
A-Law PCM
Sample 3, 8 Bits
Sample 2, 8 Bits
Sample 1, 8 Bits
Sample 0, 8 Bits
Left Channel
Left Channel
Left Channel
Left Channel
Stereo, 8-Bit
Linear PCM
m-Law PCM
A-Law PCM
Sample 1, 8 Bits
Sample 1, 8 Bits
Sample 0, 8 Bits
Sample 0, 8 Bits
Right Channel
Left Channel
Right Channel
Left Channel
Little Endian
Stereo, 16-Bit
Little Endian
Mono, 4-Bit
Sample 7,
4 Bits
Sample 6,
4 Bits
Sample 5,
4 Bits
Sample 4,
4 Bits
Sample 3,
4 Bits
Sample 2,
4 Bits
Sample 1,
4 Bits
Sample 0,
4 Bits
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Left
Channel
Sample 3,
4 Bits
Sample 3,
4 Bits
Sample 2,
4 Bits
Sample 2,
4 Bits
Sample 1,
4 Bits
Sample 1,
4 Bits
Sample 0,
4 Bits
Sample 0,
4 Bits
Right
Channel
Left
Channel
Right
Channel
Left
Channel
Right
Channel
Left
Channel
Right
Channel
Left
Channel
IMA-ADPCM
Stereo, 4-Bit
IMA-ADPCM
Mono, 16-Bit
Lower 8 Bits of
Sample 1
Upper 8 Bits of
Sample 1
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Left Channel
Left Channel
Left Channel
Left Channel
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Lower 8 Bits of
Sample 0
Upper 8 Bits of
Sample 0
Right Channel
Right Channel
Left Channel
Left Channel
Big Endian
Stereo, 16-Bit
Big Endian
*Regardless of the data format used, the AD1812’s codec always transfers 32 bits of data (two 16-bit words).
tBWDN
IOR/IOW
DATA
(7:0)
BYTE 0
BYTE 1
LEFT
SAMPLE
BYTE 2
BYTE 3
RIGHT
SAMPLE
Figure 7. Codec Transfers 8-Bit Interface
–8–
REV. 0
AD1812
ABSOLUTE MAXIMUM RATINGS*
Parameter
Power Supplies
Digital (VDD)
Analog (VCC)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
Min
Max
Units
–0.3
–0.3
6.0
6.0
± 10.0
V CC + 0.3
VDD + 0.3
+70
+150
V
V
mA
V
V
°C
°C
–0.3
–0.3
0
–65
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD1812JS
AD1812JST
0°C to +70°C
0°C to +70°C
160-Lead PQFP
160-Lead TQFP
S-160
ST-160
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1812 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
NC
NC
NC
NC
GNDD
VDD
1
SBHE
PC_A15
PC_A14
PC_A13
PC_A12
PC_A11
PC_A10
PC_A9
PC_A8
GNDD
VDD
PC_A7
PC_A6
PC_A5
PC_A4
PC_A3
PC_A2
PC_A1
PC_A0
3
NC
NC
123 NC
122 NC
121 NC
124
125
126
128
127
129
PC_D12
PC_D13
PC_D14
PC_D15
GNDD
VDD
131
130
133
132
134
135
137
136
PC_D8
PC_D9
PC_D10
PC_D11
VDD
GNDD
GNDD
VDD
138
139
141
140
142
144
143
145
147
146
149
148
151
150
PC_D0
PC_D1
PC_D2
PC_D3
VDD
GNDD
GNDD
VDD
PC_D4
PC_D5
PC_D6
PC_D7
GNDD
VDD
152
153
154
156
155
158
157
NC
XCTL1
NC
NC
NC
GNDD
VDD
119
118
4
117
5
116
6
115
7
114
8
113
9
112
10
111
11
110
12
109
13
108
14
107
15
106
16
105
17
104
18
103
AD1812
19
102
TOP VIEW
PINS DOWN
(Not to Scale)
20
21
22
101
100
99
23
98
24
97
25
96
26
95
27
94
28
93
29
92
30
91
31
90
32
89
33
88
34
87
35
86
36
85
37
84
80
79
78
77
76
75
74
72
73
70
71
69
68
67
66
64
65
62
63
61
59
60
58
56
57
55
54
52
53
51
50
49
48
47
A_1
A_2
B_1
B_2
GNDG
A_X
A_Y
B_X
B_Y
VDDG
VCC
GNDA
R_FILT
L_FILT
R_LINE
L_LINE
R_MIC
L_MIC
VREF
VREF_X
VCC
GNDA
R_AUX1
L_AUX1
R_AUX2
L_AUX2
R_MONOIN
R_OUT
L_OUT
L_MONOIN
MONO_IN
VCC
M_OUT
GNDA
R_DACOUT
R_DACIN
L_DACIN
L_DACOUT
ADGND
ADVDD
46
81
45
40
43
82
44
83
39
41
38
NC = NO CONNECT
REV. 0
159
120
PIN 1
IDENTIFIER
42
IOR
GNDD
VDD
XTALI
XTALO
MIDI_IN
AEN
IOW
GNDD
RESET
PWRDWN
PNP
MODEM_IRQ
MODEM_EN
GVC
2
160
PQFP AND TQFP PIN LOCATIONS
–9–
NC
RESET
MODEM_SEL
GNDD
VDD
IRQ3
IRQ4
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
VDD
GNDD
GNDD
VDD
DRQ0
DRQ1
DRQ3
DRQ5
DRQ6
DRQ7
IOCH16
MIDI_OUT
XCTL0
VDD
GNDD
GNDD
VDD
DACK0
DACK1
DACK3
DACK5
GNDD
DACK6
DACK7
GNDD
GNDD
NC
AD1812
PIN DESCRIPTION
Parallel Interface
Pin Name
P/TQFP
I/O
Description
PC_D[15:0]
128–131, 136–139,
142–145, 150–153
I/O
ISA Bus PC Data. PC_D15 to PC_D8 in conjunction with an active HI
SBHE connects the AD1812 to the high byte data on the bus, while PC_D7
to PC_D0 connects to the low byte data on the bus.
IRQ(x)
108–115
O
Interrupt Request. IRQ (3, 4, 5, 7, 9, 10, 11, 12). Active HI signals indicating a
pending interrupt.
DRQ(x)
98–103
O
DMA Request. DRQ (0, 1, 3, 5, 6, 7). Active HI signals indicating a request for
DMA bus operation. DRQ0, DRQ1 and DRQ3 request 8-bit DMA operations
while DRQ5, DRQ6 and DRQ7 request 16-bit operations.
PC_A[15:0]
8–15, 18–25
I
ISA Bus PC Address. Connects the AD1812 to the ISA bus address lines.
AEN
32
I
Address Enable. Active HI signal indicates DMA transfer. Active LO signal
indicates PIO transfer.
DACK (x)
84–85, 87–90
I
DMA Acknowledge. DACK (0, 1, 3, 5, 6, 7). Active LO signal indicating that a
DMA operation can begin.
IOR
26
I
I/O Read indicates a read operation.
IOW
33
I
I/O Write indicates a write operation.
SBHE
7
I
System Byte High Enable. Active LO signal that indicates a byte is being transferred on the upper byte of the 16-bit bus.
IOCH16
97
O
IO Channel 16. Active LO signal indicating that one of the logical devices inside
the AD1812 is decoded as a 16-bit device.
RESET
35
I
Reset. Active HI.
RESET
119
I
Inverted Reset. Active LO.
Analog Signals
Pin Name
P/TQFP
I/O
Description
L_LINE
56
I
Left Line-Level Input.
R_LINE
55
I
Right Line-Level Input.
L_MIC
58
I
Left Microphone Input.
R_MIC
57
I
Right Microphone Input.
L_AUX1
64
I
Left Auxiliary #1 Line-Level Input. Also used for CD input.
R_AUX1
63
I
Right Auxiliary #1 Line-Level Input. Also used for CD input.
L_AUX2
66
I
Left Auxiliary #2 Line-Level Input. Also used for a wavetable input.
R_AUX2
65
I
Right Auxiliary #2 Line-Level Input. Also used for a wavetable input.
L_OUT
69
O
Left Line-Level Output. Left channel post-mixed output.
R_OUT
68
O
Right Line-Level Output. Right channel post-mixed output.
MONO_IN
71
I
Mono Input.
M_OUT
73
O
Mono Output. Sum of L_OUT and R_OUT.
L_DACOUT
78
O
Left DAC Out. Left channel games audio output.
R_DACOUT
75
O
Right DAC Out. Right channel games audio output.
L_DACIN
77
I
Left DAC In. When coupled to L_DACOUT, allows mixing of left channel games
audio with left channel audio converted by the codec. The post-mixed output is available on L_OUT.
R_DACIN
76
I
Right DAC In. When coupled to R_DACOUT, allows mixing of right channel games
audio with right channel audio converted by the codec. The post-mixed output is
available on R_OUT.
L_MONOIN
70
I
Left Mono In. When coupled to L_OUT, M_OUT reflects the left post-mixed output.
R_MONOIN
67
I
Right Mono In. When coupled to R_OUT, M_OUT reflects the right post-mixed output.
–10–
REV. 0
AD1812
Modem Interface Signals
Pin Name
P/TQFP
I/O
Description
MODEM_IRQ
38
I
Modem IRQ. The external modem asserts this pin HI to indicate a pending interrupt. The AD1812 converts this signal to the appropriate interrupt in either Plug
and Play (LDN = 5) or Non-Plug and Play mode.
MODEM_EN
39
I
Modem Enable. When this pin is asserted (HI), the AD1812 enables the logical
device (LDN = 5) for an external modem chipset. Otherwise, LDN = 5 does not
exist. The state of this pin should not be altered after reset.
MODEM_SEL
118
O
Modem Select. This active LO pin is a chip select for an external modem chipset.
The AD1812 decodes the (Plug & Play or Non-Plug and Play) configured ISA
bus address. AEN must be LO before asserting the MODEM_SEL pin.
Pin Name
P/TQFP
I/O
Description
A_1
41
I
Game Port A, Button #1.
A_2
42
I
Game Port A, Button #2.
A_X
46
I
Game Port A X-Axis.
A_Y
47
I
Game Port A Y-Axis.
B_1
43
I
Game Port B, Button #1.
B_2
44
I
Game Port B, Button #2.
B_X
48
I
Game Port B X-Axis.
B_Y
49
I
Game Port B Y-Axis.
Pin Name
P/TQFP
I/O
Description
MIDI_IN
31
I
RXD MIDI Input.
MIDI_OUT
96
O
TXD MIDI Output.
Game Port
MIDI Interface Signals
Miscellaneous
Pin Name
P/TQFP
I/O
Description
PNP
37
I
Plug and Play Select. When this pin is asserted (HI), the Plug and Play
mode is enabled. If PnP is LO, the AD1812 operates in legacy mode, and
the Plug and Play configuration is disabled.
XTALO
30
O
14.31818 MHz Crystal Output.
XTALI
29
I
14.31818 MHz Clock Input, can be OSC from the ISA bus.
PWRDWN
36
I
Power Down Signal. Active LO.
VREF_X
60
O
Voltage Reference.
VREF
59
I
Voltage Reference Filter.
L_FILT
54
I
Left Channel Filter Input.
R_FILT
53
I
Right Channel Filter Input.
XCTL0
95
O
External Control 0. The state of this pin (TTL HI or LO) is reflected in
codec indexed register 0x0A, Bit 6.
XCTL1
159
O
External Control 1. The state of this pin (TTL HI or LO) is reflected in
codec indexed register 0x0A, Bit 7.
GVC
40
I
Game Port Voltage Capacitor.
NC
1–4, 81, 120–125,
156–158, 160
REV. 0
No Connect.
–11–
AD1812
Power Supplies
Pin Name
P/TQFP
I/O
Description
VCC
51, 61, 72
I
Analog Supply Voltage (+5 V).
GNDA
52, 62, 74
I
Analog Ground.
VDD
6, 17, 28, 91,
94, 104, 107,
116, 126, 132,
135, 140, 146,
149, 154
I
Digital Supply Voltage (+5 V).
GNDD
5, 16, 27, 34, 82,
83, 86, 92, 93,
105, 106, 117,
127, 133, 134,
141, 147, 148,
155
I
Digital Ground.
ADVDD
80
I
Analog/Digital Supply Voltage. Connect to +5 VCC.
ADGND
79
I
Analog/Digital Ground. Connect to analog ground plane.
VDDG
50
I
Game Port Digital Voltage Supply. Connect to +5 VDD.
GNDG
45
I
Game Port Digital Ground. Connect to the digital ground plane.
(continued from Page 1)
WSS COMPATIBLE CODEC
HOST PC INTERFACE
All necessary ISA bus interface logic is completely contained onchip. This includes address decoding for all onboard resources,
control and signal interpretation, DMA selection and control
logic, IRQ selection and control logic, and all interface configuration logic (see Table IV).
The AD1812 supports a DMA request/grant architecture for
transferring data with the ISA bus. One, two, or three DMA
channels can be supported. Programmed I/O (PIO) mode is
also supported for control register accesses and for applications
lacking DMA control. The AD1812 includes dual DMA count
registers for full-duplex operation enabling simultaneous capture
and playback on separate DMA channels.
The AD1812 is fully configurable according to the Plug and
Play ISA specification. In a non-Plug and Play environment, the
built in Plug and Play protocol can be disabled. When Plug and
Play is disabled, the AD1812 operates under a fixed address
space.
Table IV. Emulated Logical Devices
Logical
Device
Number
Emulated
Device
PnP
Compatible
Device
0
1
2
3
4
5*
Windows Sound System
Sound Blaster Pro v. 2.01
OPL3 Music Synthesizer
MIDI MPU-401 Port
Game/Joystick Port
Modem
—
PNPB002
PNPB020
PNPB006
PNPB02F
PNP0501
The AD1812 contains the AD1845 SoundPort Stereo Codec for
business audio support and multimedia applications. The codec
includes stereo audio converters, complete on-chip filtering,
MPC Level-2 compliant analog mixing, programmable gain and
attenuation, a variable sample frequency generator, and FIFOs
buffering the ISA bus.
The codec includes a stereo pair of ∑∆ analog-to-digital converters and a stereo pair of ∑∆ digital-to-analog converters. Inputs to the ADC can be selected from four stereo pairs of analog
signals: line (LINE), microphone (MIC), auxiliary line #1
(AUX1), and post-mixed DAC output. In addition, an analog
mixer allows a mono input (MONO_IN), MIC, AUX1, LINE
and auxiliary line #2 (AUX2) to be mixed with the DACs’ output. A software-controlled programmable gain stage allows independent gain for each channel going into the ADC. The
ADCs’ output can be digitally mixed with the DACs’ input.
The pair of 16-bit outputs from the ADCs are available over a
16-bit bidirectional interface that also supports 16-bit digital input to the DACs and control information. The codec can accept
and generate 16-bit twos-complement PCM linear (big endian
or little endian) digital data, 4-bit IMA-ADPCM compatible
digital data, 8-bit unsigned magnitude PCM linear data, and
8-bit µ-law or A-law companded digital data.
The AD1812 includes a variable sample frequency generator,
which allows the codec to instantaneously change sample rates
from 5.5 kHz to 50 kHz with a resolution of 1 Hz. This is a superb way to create special audio effects.
*If MODEM_EN is asserted.
–12–
REV. 0
AD1812
SOUND BLASTER EMULATION
Table V. Plug and Play Registers (PNP Asserted)
Sound Blaster emulation is provided using a combination of the
embedded signal processor and dedicated hardware. All Sound
Blaster Pro version 2.01 functions are supported including
record. The hardware registers are fully implemented within the
AD1812, and the internal signal processor executes a command
controller to interpret all commands. The AD1812 uses the internal signal processor for decoding compressed files compatible
with Sound Blaster ADPCM.
Port Name
Location
ADDRESS
0x279 (Printer Status Port)
WRITE_DATA 0xA79 (Printer Status Port + 0x800)
READ_DATA Relocatable in Range 0x203 – 0x3FF
The AD1812 includes an embedded signal processor based on
Analog Devices’ 16-bit fixed-point digital signal processor family. All DSP instructions are ROM coded internally. The
Write-Only
Write-Only
Read-Only
Table VI. Non-Plug and Play Registers (PNP Deasserted)
Port Name
MUSIC SYNTHESIZER EMULATION
Type
Location
Type
ADDRESS
0x234
WRITE_DATA 0x235
READ_DATA Relocatable in Range 0x203 – 0x3FF
Write-Only
Write-Only
Read-Only
PnP AD1812 (Card) Status
For cards in PnP mode (PnP_Enable asserted), the Plug and
Play ISA Specification describes how to transfer the AD1812
from its start-up state, “Wait For Key” State, to the configuration state, “Config” State. In the configuration state, the I/O
ranges, interrupt channels, and DMA channels can be assigned.
EuSynth-1+
For non-PnP operation, no initialization protocol is needed
because the card is locked in the configuration state.
music synthesis algorithm running on the signal processor emulates the functions of industry standard OPL3 FM synthesizer
chips and delivers 20 voice polyphony. A dedicated pair of ∑∆
DACs converts the digitally synthesized music before mixing
with the AD1812 codec line output.
Configuration Register Description
The following describes only the subset of PnP Registers that
are unique to the AD1812 or necessary for non-PnP operation.
All other PnP registers are described in the Plug and Play ISA
Specification.
EuSynth-1+ was developed by EuPhonics, a research and product development company that specializes in audio processing
and electronic music synthesis.
A register is selected by performing an 8-bit I/O write to the
ADDRESS Port, followed by either a read from the READ_DATA
location or a write to the WRITE_DATA location. Successive
reads or writes to a single register can be done without rewriting
the ADDRESS register. The following are valid values for the
ADDRESS Port.
MPU-401 INTERFACE
The primary interface for communicating MIDI data to and
from the host PC is the emulated MPU-401 interface. The
MPU-401 interface includes has a built-in FIFO for communicating to the host bus.
Table VII. PnP Address Port Registers
GAME PORT INTERFACE
An IBM-compatible game port interface is provided on-chip.
The game port is capable of supporting up to two joysticks.
Connecting the game port to a 15-pin D-sub connector requires
only a few capacitors and resistors. The AD1812 includes a
built-in game port timer.
MODEM INTERFACE
Asserting the MODEM_EN pin on the AD1812 provides chip
select, interrupt handling and address decoding for an external
modem chipset. The AD1812 decodes the modem ISA bus
address and issues a modem select on the MODEM_SEL pin.
Interrupts generated by the external modem are handled on the
MODEM_IRQ pin, converted to the assigned system interrupt
by the AD1812, and posted to the ISA bus. The modem interface operates in a PnP or non-PnP enabled system.
Address
Register Name Value
RD_DATA Port 0x00
Config Control
Logical Device
Number
Powerdown
PLUG AND PLAY (PnP)
The AD1812 can be used under PnP control or in a non-PnP
mode. The non-PnP registers mimic the PnP register set, except for the user defined addresses for the PnP “ADDRESS”
and “WRITE_DATA” registers. The PnP registers are selected
by asserting the PnP pin. With the PnP pin deasserted, the
non-PnP registers are selected.
REV. 0
–13–
0x02
0x07
0x20
Type
Description
Write-Only Sets the value of the
READ_DATA Port.
Write-Only Resets all logical devices.
Read/Write Selects current logical
device.
Read/Write Manages power for
portions of the AD1812.
AD1812
Table VIII. Windows Sound System, Logical Device Number = 0
Register Name Address Type
Activate
0x30
I/O Range Check 0x31
I/O Port Base
Address
IRQ Level Select
IRQ Type Select
0x60
0x61
0x70
0x71
DMA Select 0
0x74
DMA Select 1
0x75
Description Value
I/O Port Base
0x60
Address
0x61
IRQ Level Select 0x70
IRQ Type Select 0x71
DMA Select 0
0x74
Read/Write Activates device.
Read/Write Performs conflict check
on selected I/O range.
I/O Port Base
0x60
Read/Write I/O Base [9:8].
Address
0x61
Read/Write I/O Base [7:0].
IRQ Level Select 0x70
Read/Write Selects interrupt level.
IRQ Type Select 0x71
Read-Only
Active HI, edge-sensitive (not user programmable).
Table XII. Game Port, Logical Device Number = 4
Address
Register Name Value
Type
Activate
0x30
Description
Read/Write Activates device.
Read/Write Performs conflict check
on selected I/O range.
Read/Write Activates device.
Read/Write Performs conflict check
on selected I/O range.
Read/Write I/O Base [9:8].
I/O Port Base
Address
Read/Write I/O Base [9:8].
Read/Write I/O Base [7:0].
Read/Write I/O Base [7:0].
Read/Write Selects interrupt level.
Read-Only Active HI, edge-sensitive
(not user programmable).
Read/Write Indicates which 8-bit
DMA channel.
Register Name
Address
Value
Type
Activate
0x30
0x60
0x61
Table XIII. Modem, Logical Device Number = 5
Read/Write Activates device.
Read/Write Performs conflict check
on selected I/O range.
I/O Port Base
Address
Read/Write I/O Base [9:8].
Read/Write I/O Base [7:0].
Description
Read/Write Activates device.
I/O Range Check 0x31
Read/Write Performs conflict check
on selected I/O range.
I/O Port Base
Address
Read/Write I/O Base [9:8].
Read/Write I/O Base [7:0].
0x60
0x61
IRQ Level Select 0x70
Read/Write Selects interrupt level.
IRQ Type Select 0x71
Read Only
Description
I/O Range Check 0x31
0x60
0x61
Description
I/O Range Check 0x31
Address
Register Name Value
Type
0x30
0x30
I/O Range Check 0x31
Description
Table X. Music Synthesizer, Logical Device Number = 2
Activate
Activate
Read/Write Indicates DMA playback
channel. (If DMA 0 is
not used, capture and
playback occurs on
DMA 1.)
Address
Register Name Value
Type
Activate
0x30
I/O Range Check 0x31
Address
Register Name Value
Type
Read/Write Activates device.
Read/Write Performs conflict check
on selected I/O range.
Read/Write I/O Base [15:8].
Read/Write I/O Base [7:0].
Read/Write Selects interrupt level.
Read-Only Active HI, level-sensitive
(not user programmable).
Read/Write Indicates DMA capture
channel.
Table IX. Game Registers, Logical Device Number = 1
Table XI. MIDI Port, Logical Device Number = 3
Active HI, edge-sensitive
(not user programmable).
Power-Down Control
The AD1812 contains two levels of Power-Down control. One
level of control is accessed through the embedded codec registers
and another is accessed via the PnP vendor defined registers.
The codec registers allow sections of the embedded codec to be
turned off to conserve power.
–14–
REV. 0
AD1812
Table XIV. Codec Power-Down Modes
Mode
Powered-Down Blocks
Total Power Down
Standby
Mixer Power Down
Mixer Only
ADC Power Down
DAC Power Down
ADC, DAC, Mixer, Reference
ADC, DAC, Mixer
DAC, Mixer
ADC, DAC
ADC
DAC
A write to or a read from the Indexed Data Register will access
the Indirect Register which is selected by the value most recently
written to the Index Address Register. The Status Register and
the PIO Data Register are always accessible directly, without indexing. The 32 Indirect Registers are shown in Table XVII.
Table XVII. Codec Indirect Register Map
Windows Sound System Codec
Indexed Register
The registers found in the vendor defined PnP space take precedence over any other power-down mode. You can shut down
the embedded DSP or the entire codec by writing to these
registers.
Table XV. PnP Power-Down Modes
Mode
Powered-Down Blocks
Total Power Down
DSP and SoundPort Codec
CODEC CONTROL REGISTER ARCHITECTURE
Upon Plug and Play initialization, a base address is assigned for
the Windows Sound System Compatible logical device embedded in the AD1812. The AD1812 accepts both data and control information through the 16-bit interface.
Table XVI. Codec Direct Register Map
Windows Sound System Address
Register Name
Base + 0
Base + 2
Base + 4
Base + 6
Index Address Register
Indexed Data Register
Status Register
PIO Data Registers
REV. 0
Left Input Control
Right Input Control
Left Aux #1 Input Control
Right Aux #1 Input Control
Left Aux #2 Input Control
Right Aux #2 Input Control
Left Output Control
Right Output Control
Clock and Data Format
Interface Configuration
Pin Control
Test and Initialization
Miscellaneous Information
Digital Mix/Attenuation
Upper Base Count
Lower Base Count
Alternate Feature Enable/Left
MIC Input Control
MIC Mix Enable/Right MIC
Input Control
Left Line Gain, Attenuate,
Mute, Mix
Right Line Gain, Attenuate,
Mute, Mix
Lower Timer
Upper Timer
Upper Frequency Select
Lower Frequency Select
External Status
Revision ID
Mono Control
Power-Down Control
Capture Data Format Control
Total Power-Down
Capture Upper Base Count
Capture Lower Base Count
–15–
Index
Reset State
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x80
0x80
0x9F
0x9F
0x9F
0xBF
0xBF
0x08
0x00
0x05
0x20
0xCA
0x00
0x00
0x00
0x10
0x80
0x11
0x00
0x12
0x9F
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x9F
0x00
0x00
0x2A
0xF8
0x30
0x80
0xC0
0x08
0x50
0x00
0x00
0x00
AD1812
A detailed map of all direct and indirect register contents is summarized for reference as follows:
Table XVIII. Codec Direct Registers (16-Bit Interface)
Direct Address
Bit 8
Bit 7
Bit 6
WSS Base
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
res
res
res
res
res
res
res
res
INIT
MCE TRD
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WSS Base+2
res
res
res
res
res
res
res
res
IXD7 IXD6 IXD5 IXD4 IXD3 IXD2 IXD1 IXD0
WSS Base+4
res
res
res
res
res
res
res
res
IXA4 IXA3 IXA2 IXA1 IXA0
CU/L CL/R CRDY SOUR PU/L PL/R PRDY
INT
WSS Base+6 (read) CD15 CD14 CD13 CD12 CD11 CD10 CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
WSS Base+6 (write) PD15 PD14 PD13 PD12 PD11 PD10 PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Table XIX. Codec Indirect Registers
Indirect Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Bit 7
Bit 6
Bit 5
LSS1
LSS0
LMGE
RSS1
RSS0
RMGE
LMX1
res
res
RMX1
res
res
LMX2
res
res
RMX2
res
res
LDM
res
LDA5
RDM
res
RDA5
PFMT1
PFMT0
PC/L
CPIO
PPIO
res
XCTL1
XCTL0
res
COR
PUR
ACI
MID
res
res
DMA5
DMA4
DMA3
UB7
UB6
UB5
LB7
LB6
LB5
OL
TE
LMG4
LMME
RMME
RMG4
LLM
res
res
RLM
res
res
TL7
TL6
TL5
TU7
TU6
TU5
FU7
FU6
FU5
FL7
FL6
FL5
res
TI
CI
V2
V1
V0
MIM
MOM
res
ADCPWD DACPWD MIXPWD
CFMT1
CFMT0
CC/L
res
res
res
CUB7
CUB6
CUB5
CLB7
CLB6
CLB5
Bit 4
res
res
LX1A4
RX1A4
LX2A4
RX2A4
LDA4
RDA4
PS/M
res
res
DRS
res
DMA2
UB4
LB4
LMG3
RMG3
LLG4
RLG4
TL4
TU4
FU4
FL4
PI
res
res
res
CS/M
res
CUB4
CLB4
Bit 3
LIG3
RIG3
LX1A3
RX1A3
LX2A3
RX2A3
LDA3
RDA3
PBSW
ACAL
res
ORR1
ID3
DMA1
UB3
LB3
LMG2
RMG2
LLG3
RLG3
TL3
TU3
FU3
FL3
CU
res
MIA3
res
CBSW
res
CUB3
CLB3
Bit 2
LIG2
RIG2
LX1A2
RX1A2
LX2A2
RX2A2
LDA2
RDA2
PINF8
SDC
res
ORR0
ID2
DMA0
UB2
LB2
LMG1
RMG1
LLG2
RLG2
TL2
TU2
FU2
FL2
CO
CID2
MIA2
res
CINF8
res
CUB2
CLB2
Bit 1
LIG1
RIG1
LX1A1
RX1A1
LX2A1
RX2A1
LDA1
RDA1
res
CEN
IEN
ORL1
ID1
res
UB1
LB1
LMG0
RMG0
LLG1
RLLG1
TL1
TU1
FU1
FL1
PO
CID1
MIA1
res
res
res
CUB1
CLB1
Bit 0
LIG0
RIG0
LX1A0
RX1A0
LX2A0
RX2A0
LDA0
RDA0
res
PEN
res
ORL0
ID0
DME
UB0
LB0
DACZ
res
LLG0
RLG0
TL0
TU0
FU0
FL0
PU
CID0
MIA0
res
res
TOTPWD
CUB0
CLB0
Note that the only sticky bit in any of the Codec control registers is the interrupt (INT) bit. All other bits change with every sample
period.
–16–
REV. 0
AD1812
SYSTEM TIMING AND CONTROL
10
0
–10
–20
–30
–40
dB
If the AD1812 is not connected directly to the OSC clock on the
ISA bus, a single fundamental-mode and parallel-tuned
14.31818 MHz crystal oscillator can be substituted to derive all
timing parameters. Future feature enhanced, pin-compatible
versions of the SoundPort Controller will require a 33 MHz
clock or crystal input. Analog Devices suggests developing board
layouts that can be easily modified to supply the new clock.
–50
–60
–70
–80
DATA AND CONTROL TRANSFERS
–90
The embedded SoundPort Stereo Codec supports a DMA
request/grant architecture for transferring data with the host
computer bus. One or two 8-bit or 16-bit DMA channels can
be supported. Programmed I/O (PIO) mode is also supported
for control register accesses and for applications lacking DMA
control. PIO transfers can be made on one channel while the
other is performing DMA. Transfers to and from the AD1812
are asynchronous relative to the internal data conversion clock.
Transfers are buffered by FIFOs located in the capture and
playback paths.
–100
–110
–120
0.40
0.44
0.48
0.52
0.56
0.60
SAMPLE FREQUENCY – FS
0.64
0.68 0.70
Figure 9. Analog-to-Digital Frequency Response —
Transition Band (Full-Scale Line-Level Inputs,
–1 dB Gain)
10
0
REFERENCE DESIGNS AND DEVICE DRIVERS
–20
–30
–40
dB
Reference designs and device drivers using the AD1812 are
available via Bulletin Board Service. The Computer Products
Division runs a BBS that can be reached at speeds up to 14,400
baud, no parity, 8 bits data, 1 stop bit, by dialing (617) 4614258. The BBS supports: V.32bis, error correction (V.42 and
MNP classes 2, 3, and 4), and data compression (V.42bis and
MNP class 5). Reference designs can also be found in the
AD1812 SoundPort Controller Technical Reference which can
be obtained by contacting your local Analog Devices sales representative or authorized distributor. You can also find us on the
World Wide Web at http://www.analog.com.
–10
–50
–60
–70
–80
–90
–100
–110
–120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
SAMPLE FREQUENCY – FS
0.8
0.9
1.0
Figure 10. Digital-to-Analog Frequency Response to FS
(Full-Scale Inputs, 0 dB Attenuation)
FREQUENCY RESPONSE PLOTS
10
10
0
–20
–10
–30
–20
–40
–30
–50
–40
–60
–50
dB
dB
0
–10
–70
–70
–90
–80
–100
–90
–110
–100
–120
–110
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
SAMPLE FREQUENCY – FS
0.8
0.9
1.0
–120
0.40
Figure 8. Analog-to-Digital Frequency Response to FS
(Full-Scale Line-Level Inputs, –1 dB Gain)
REV. 0
–60
–80
0.44
0.48
0.52
0.56
0.60
SAMPLE FREQUENCY – FS
0.64
0.68 0.70
Figure 11. Digital-to-Analog Frequency Response —
Transition Band (Full-Scale Inputs, 0 dB Attenuation)
–17–
AD1812
INDEX
Page
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
AD1812–SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
PROGRAMMABLE GAIN AMPLIFIER—ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
AUXILIARY, LINE, MICROPHONE AND MONO INPUT ANALOG
GAIN/AMPLIFIERS/ATTENUATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
DIGITAL DECIMATION AND INTERPOLATION FILTERS . . . . . . . . . . . . . . 2
ANALOG-TO-DIGITAL CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DIGITAL-TO-ANALOG CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DAC ATTENUATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DIGITAL MIX ATTENUATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ANALOG OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SYSTEM SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
STATIC DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CLOCK SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PQFP & TQFP PIN LOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Analog Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Modem Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Game Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MIDI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
HOST PC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
WSS COMPATIBLE CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SOUND BLASTER EMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MUSIC SYNTHESIZER EMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MPU-401 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
GAME PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MODEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PLUG AND PLAY (PnP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PnP AD1812 (Card) Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Configuration Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CODEC CONTROL REGISTER ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . 15
SYSTEM TIMING AND CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DATA AND CONTROL TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REFERENCE DESIGNS & DEVICE DRIVERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FREQUENCY RESPONSE PLOTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
–18–
REV. 0
AD1812
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
160-Lead PQFP
(S-160)
1.239 (31.45)
SQ
1.219 (30.95)
1.107 (28.10)
SQ
1.100 (27.90)
0.160 (4.07)
MAX
0.037 (0.95)
0.026 (0.65)
6°±4°
120
121
81
80
4°±4°
MAX
TOP VIEW
(PINS DOWN)
SEATING
PLANE
PIN 1
10°
0.004 (0.102)
MAX
160
41
40
1
0.070 (1.77)
0.062 (1.57)
0.070 (1.77)
0.062 (1.57)
0.014 (0.35)
0.011 (0.27)
0.030 (0.75)
0.022 (0.55)
0.145 (3.67)
0.125 (3.17)
160-Lead TQFP
(ST-160)
1.031 (26.20)
SQ
1.016 (25.80)
0.949 (24.10)
SQ
0.941 (23.90)
0.063 (1.60)
MAX
0.030 (0.75)
0.020 (0.50)
6°±4°
121
120
160
1
PIN 1
0°±5°
TOP VIEW
(PINS DOWN)
SEATING
PLANE
12°
TYP
0.003 (0.08)
MAX
0.006 (0.15)
0.002 (0.05)
0.057 (1.45)
0.053 (1.35)
REV. 0
40
41
81
80
0.010 (0.25)
0.006 (0.15)
–19–
0.020 (0.50)
BSC
–20–
PRINTED IN U.S.A.
C2100–6–1/96