IRF IR3843AM Highly efficient integrated 3a synchronous buck regulator Datasheet

PD-97509
IR3843AMPbF
SupIRBuck
HIGHLY EFFICIENT
TM
INTEGRATED 3A SYNCHRONOUS BUCK REGULATOR
Features
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Description
Wide Input Voltage Range 1.5V to 21V
Wide Output Voltage Range 0.7V to 0.9*Vin
Continuous 3A Load Capability
Integrated Bootstrap-diode
High Bandwidth E/A for excellent transient
performance
Programmable Switching Frequency up to 1.2MHz
Programmable Over Current Protection
PGood output
Hiccup Current Limit
Precision Reference Voltage (0.7V, +/-1%)
Programmable Soft-Start
Enable Input with Voltage Monitoring Capability
Enhanced Pre-Bias Start-up
Seq input for Tracking applications
-40oC to 125oC operating junction temperature
Thermal Protection
Multiple current ratings in pin compatible footprint
5mm x 6mm Power QFN Package, 0.9 mm height
Lead-free, halogen-free and RoHS compliant
The IR3843A SupIRBuckTM is an easy-to-use,
fully integrated and highly efficient DC/DC
synchronous Buck regulator. The MOSFETs copackaged with the on-chip PWM controller make
IR3843A a space-efficient solution, providing
accurate power delivery for low output voltage
applications.
IR3843A is a versatile regulator which offers
programmability of start up time, switching
frequency and current limit while operating in
wide input and output voltage range.
The switching frequency is programmable from
250kHz to 1.2MHz for an optimum solution.
It also features important protection functions,
such as Pre-Bias startup, hiccup current limit and
thermal shutdown to give required system level
security in the event of fault conditions.
Applications
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Server Applications
Storage Applications
Embedded Telecom Systems
Distributed Point of Load Power Architectures
Netcom Applications
Computing Peripheral Voltage Regulators
General DC-DC Converters
1.5V <Vin<16V
4.5V <Vcc<5.5V
Seq
Enable
Vin
Boot
Vo
Vcc
SW
PGood
PGood
OCSet
Fb
Rt
SS/ SD
Gnd
PGnd
Comp
Fig. 1. Typical application diagram
Rev 16.0
1
PD-97509
IR3843AMPbF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND unless otherwise specified)
•
Vin ……………………………………………………. -0.3V to 25V
•
Vcc ……………….….…………….……..……….…… -0.3V to 8V (Note2)
•
Boot
……………………………………..……….…. -0.3V to 33V
•
SW
…………………………………………..……… -0.3V to 25V(DC), -4V to 25V(AC, 100ns)
•
Boot to SW
•
OCSet
•
Input / output Pins
•
PGND to GND ……………...………………………….. -0.3V to +0.3V
•
Storage Temperature Range ................................... -55°C To 150°C
•
Junction Temperature Range ................................... -40°C To 150°C (Note2)
•
ESD Classification …………………………… ……… JEDEC Class 1C
•
Moisture sensitivity level………………...………………JEDEC Level 2@260 °C (Note5)
……..…………………………….…..….. -0.3V to Vcc+0.3V (Note1)
………………………………………….……. -0.3V to 30V, 30mA
……………………………….. ... -0.3V to Vcc+0.3V (Note1)
Note1: Must not exceed 8V
Note2: Vcc must not exceed 7.5V for Junction Temperature between -10oC and -40oC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications are not implied.
PACKAGE INFORMATION
SW
5mm x 6mm POWER QFN
VIN
11
12
10
PGnd
θJA = 35 o C / W
θJ -PCB = 2 o C / W
Boot
13
Enable
14
1
ORDERING INFORMATION
Rev 16.0
Seq
2
15
Gnd
3
4
5
FB COMP Gnd Rt
6
9
VCC
8
PGood
7
SS OCSet
PACKAGE
DESIGNATOR
PACKAGE
DESCRIPTION
PIN
COUNT
PARTS PER
REEL
M
IR3843AMTRPbF
15
4000
M
IR3843AMTR1PbF
15
750
2
PD-97509
IR3843AMPbF
Block Diagram
Fig. 2. Simplified block diagram of the IR3843A
Rev 16.0
3
PD-97509
IR3843AMPbF
Pin Description
Pin
Name
Description
1
Seq
Sequence pin. Use two external resistors to set Simultaneous Power up
sequencing. If this pin is not used connect to Vcc.
2
Fb
3
Comp
4
Gnd
5
Rt
Set the switching frequency. Connect an external resistor from this pin
to Gnd to set the switching frequency.
6
SS/SD
¯¯
Soft start / shutdown. This pin provides user programmable soft-start
function. Connect an external capacitor from this pin to Gnd to set the
start up time of the output voltage. The converter can be shutdown by
pulling this pin below 0.3V.
7
OCSet
Current limit set point. A resistor from this pin to SW pin will set the
current limit threshold.
8
PGood
Power Good status pin. Output is open drain. Connect a pull up resistor
from this pin to Vcc. If unused, it can be left open.
9
VCC
This pin powers the internal IC and the drivers. A minimum of 1uF high
frequency capacitor must be connected from this pin to the power
ground (PGnd).
10
PGnd
Power Ground. This pin serves as a separated ground for the MOSFET
drivers and should be connected to the system’s power ground plane.
11
SW
Switch node. This pin is connected to the output inductor.
12
VIN
Input voltage connection pin.
13
Boot
14
Enable
15
Gnd
Rev 16.0
Inverting input to the error amplifier. This pin is connected directly to the
output of the regulator via resistor divider to set the output voltage and
provide feedback to the error amplifier.
Output of error amplifier. An external resistor and capacitor network is
typically connected from this pin to Fb pin to provide loop
compensation.
Signal ground for internal reference and control circuitry.
Supply voltage for high side driver. A 0.1uF capacitor must be
connected from this pin to SW.
Enable pin to turn on and off the device. Use two external resistors to
set the turn on threshold (see Enable section). Connect this pin to Vcc if
it is not used.
Signal ground for internal reference and control circuitry.
4
PD-97509
IR3843AMPbF
Recommended Operating Conditions
Symbol
Vin
Vcc
Boot to SW
Vo
Io
Fs
Tj
Definition
Input Voltage
Supply Voltage
Supply Voltage
Output Voltage
Output Current
Switching Frequency
Junction Temperature
Min
Max
1.5
4.5
4.5
0.7
0
225
-40
21*
5.5
5.5
0.9*Vin
3
1320
125
Units
V
A
kHz
o
C
* SW must not exceed the Abs Max Rating (25V)
Electrical Specifications
Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC.
Typical values are specified at Ta = 25oC.
Parameter
Symbol
Test Condition
Min
TYP
MAX
Units
Power Loss
Power Loss
Ploss
Vcc=5V, Vin=12V, Vo =1.8V, I o=3A,
Fs=600kHz, L=2.2uH, Note4
0.682
W
MOSFET Rds(on)
Top Switch
Rds(on)_Top
Bottom Switch
R ds(on)_Bot
o
VBoo t -V sw =5V, ID =3A, Tj= 25 C
o
Vcc =5V, ID =3A, Tj=25 C
24.5
32
24.5
32
mΩ
Reference Voltage
Feedback Voltage
VFB
0.7
o
Accuracy
o
0 C<Tj<125 C
o
o
-40 C<Tj<125 C, Note3
V
-1.0
+1.0
-2.0
+2.0
%
Supply Current
VCC Supply Current (Standby)
I CC(Standby)
Vcc Supply Current (Dyn)
ICC(Dyn)
SS=0V, No Switching, Enable low
500
SS=3V, Vcc=5V, Fs=500kHz
Enable high
10
μA
mA
Under Voltage Lockout
VCC-Start-Threshold
V CC_UVLO_Start
Vcc Rising Trip Level
3.95
4.15
4.35
VCC-Stop-Threshold
V CC_UVLO_Stop
Vcc Falling Trip Level
3.65
3.85
4.05
Enable-Start-Threshold
Enable_UVLO_Start
Supply ramping up
1.14
1.2
1.36
Enable-Stop-Threshold
Enable_UVLO_Stop
Supply ramping down
0.9
1.0
1.06
Enable leakage current
Ien
Enable=3.3V
Rev 16.0
15
V
μA
5
PD-97509
IR3843AMPbF
Electrical Specifications (continued)
Unless otherwise specified, these specifications apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC.
Typical values are specified at Ta = 25oC.
Parameter
Symbol
Test Condition
Min
TYP
MAX
Units
0.665
0.7
0.735
V
Rt=59K
225
250
275
Rt=28.7K
450
500
550
1080
1200
1320
Oscillator
Rt Voltage
Frequency
FS
Rt=11.5K, Note4
Ramp Amplitude
kHz
Vramp
Note4
1.8
Vp-p
Ramp Offset
Ramp (os)
Note4
0.6
V
Min Pulse Width
Dmin(ctrl)
Note4
100
Fixed Off Time
Max Duty Cycle
Note4
130
Dmax
Fs=250kHz
92
Vos
Vfb-Vseq,
Vseq=0.8V
-10
200
ns
%
Error Amplifier
Input Offset Voltage
0
+10
Input Bias Current
IFb(E/A)
-1
+1
Input Bias Current
IVp(E/A)
-1
+1
Isink(E/A)
0.40
0.85
1.2
Isource(E/A)
8
10
13
Sink Current
Source Current
Slew Rate
Gain-Bandwidth Product
DC Gain
mV
μA
mA
SR
Note4
7
12
20
V/μs
GBWP
Note4
20
30
40
MHz
Gain
Note4
100
110
120
dB
Vcc=4.5V
3.4
3.5
3.75
V
120
220
mV
1
V
μA
Maximum Voltage
Vmax(E/A)
Minimum Voltage
Vmin(E/A)
Common Mode Voltage
Note4
0
Soft Start/SD
Soft Start Current
Soft Start Clamp Voltage
Shutdown Output Threshold
ISS
Source
Vss(clamp)
14
20
26
2.7
3.0
3.3
SD
0.3
V
Over Current Protection
OCSET Current
IOCSET
Fs=250kHz
20.8
23.6
26.4
Fs=500kHz
43
48.8
54.6
Fs=1200kHz, Note4
OC Comp Offset Voltage
SS off time
V OFFSET
Note4
μA
121.7
-10
SS_Hiccup
0
+10
4096
mV
Cycles
Bootstrap Diode
Forward Voltage
I(Boot)=30mA
180
260
470
mV
5
10
30
ns
Deadband
Deadband time
Rev 16.0
Note4
6
PD-97509
IR3843AMPbF
Electrical Specifications (continued)
Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC.
Typical values are specified at Ta = 25oC.
Parameter
SYM
Test Condition
Min
TYP
MAX
Units
Thermal Shutdown
Thermal Shutdown
Note4
140
Hysteresis
Note4
20
o
C
Power Good
Power Good upper
Threshold
Upper Threshold
Delay
Power Good lower
Threshold
Lower Threshold
Delay
Delay Comparator
Threshold
Delay Comparator
Hysteresis
PGood Voltage Low
Leakage Current
VPG(upper)
Fb Rising
VPG(upper)_Dly
Fb Rising
VPG(lower)
Fb Falling
VPG(lower)_Dly
Fb Falling
PG(Delay)
Relative to charge voltage, SS rising
Delay(hys)
Note4
PG(voltage)
0.77
0.805
256/Fs
0.560
0.595
V
s
0.630
256/Fs
V
s
2
2.1
2.3
V
260
300
340
mV
IPGood=-5mA
I leakage
0.840
0
0.5
V
10
μA
Switch Node
SW Bias Current
SW=0V, Enable=0V
Isw
SW=0V,Enable=high,SS=3V,Vseq=0V
, Note4
6
μA
Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
Note4: Guaranteed by Design but not tested in production.
Note5: Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2).
Products with prior date code of 1227 are qualified with MSL3 for Consumer market.
Rev 16.0
7
PD-97509
IR3843AMPbF
TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC) Fs=500 kHz
Icc(Dyn)
Icc(Standby)
9.5
290
9.4
270
9.3
9.2
250
[mA]
[uA]
9.1
230
210
9.0
8.9
8.8
190
8.7
170
8.6
150
8.5
-40
-20
0
20
40
60
80
100
120
-40
o
Temp[ C]
0
20
100
120
80
100
120
80
100
120
80
100
120
80
100
120
53.0
52.0
520
51.0
510
50.0
[uA]
530
500
49.0
48.0
47.0
480
46.0
470
45.0
460
44.0
43.0
450
-40
-20
0
20
40
60
80
100
-40
120
-20
0
20
60
Temp[ C]
Vcc(UVLO) Start
4.46
40
o
o
Temp[ C]
Vcc(UVLO) Stop
4.16
4.41
4.11
4.36
4.06
4.31
4.01
[V]
[V]
80
IOCSET(500kHz)
490
4.26
3.96
4.21
3.91
4.16
3.86
4.11
3.81
4.06
3.76
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
Temp[ oC]
40
60
Temp[ oC]
Enable(UVLO) Start
1.36
Enable(UVLO) Stop
1.06
1.34
1.04
1.32
1.30
1.02
1.28
1.00
1.26
[V]
[V]
60
54.0
540
1.24
0.98
1.22
0.96
1.20
0.94
1.18
0.92
1.16
1.14
0.90
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
60
Temp[ C]
ISS
26.0
40
ο
Temp[ oC]
Vfb
711
24.0
706
[mV]
22.0
[uA]
40
Temp[ oC]
FREQUENCY
550
[kHz]
-20
20.0
701
18.0
696
16.0
691
686
14.0
-40
-20
0
20
40
o
60
Temp[ C]
Rev 16.0
80
100
120
-40
-20
0
20
40
60
o
Temp[ C]
8
PD-97509
IR3843AMPbF
Rdson of MOSFETs Over Temperature at Vcc=5V
Note: Ctrl-FET and Sync-FET are identical.
36
34
Resistance [mΩ]
32
30
28
26
24
22
20
-40
-20
0
20
40
60
80
100
120
140
Temperature [°C]
Ctrl-FET/Sync-FET
Rev 16.0
9
PD-97509
IR3843AMPbF
Typical Efficiency and Power Loss Curves
Vin=12V, Vcc=5V, Io=0.3A-3A, Fs=600kHz, Room Temperature, No Air Flow
The table below shows the inductors used for each of the output voltages
in the efficiency measurement.
Vout (V)
L (uH)
P/N
DCR
(mΩ)
0.9
1.5
PCMB065T-1R5MS
6.7
1
1.5
PCMB065T-1R5MS
6.7
1.1
1.5
PCMB065T-1R5MS
6.7
1.2
1.5
PCMB065T-1R5MS
6.7
1.5
2.2
IHLP2525EZ-01 2.2uH
13
1.8
2.2
IHLP2525EZ-01 2.2uH
13
2.5
3.3
IHLP2525EZ-01 3.3uH
19.9
3.3
3.3
IHLP2525EZ-01 3.3uH
19.9
5
4.7
IHLP2525EZ-01 4.7uH
28.9
96
94
92
Efficiency (%)
90
88
86
84
82
80
78
76
74
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
Iout (A)
0.9V
1V
1.1V
1.2V
1.5V
1.8V
2.5V
3.3V
5V
0.9
0.8
Power Loss (W)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
Iout (A)
0.9V
Rev 16.0
1V
1.1V
1.2V
1.5V
1.8V
2.5V
3.3V
5V
10
PD-97509
IR3843AMPbF
Typical Efficiency and Power Loss Curves
Vin=5V, Vcc=5V, Io=0.3A-3A, Fs=600kHz, Room Temperature, No Air Flow
The table below shows the inductors used for each of the output voltages
in the efficiency measurement.
Vout (V)
L (uH)
P/N
DCR
(mΩ)
0.7
0.82
IHLP2525EZ-01 2.2uH
4.6
0.75
0.82
IHLP2525EZ-01 2.2uH
4.6
0.9
1
PCMB065T-1R0MS
5.6
1
1.5
PCMB065T-1R5MS
6.7
1.1
1.5
PCMB065T-1R5MS
6.7
1.2
1.5
PCMB065T-1R5MS
6.7
1.5
1.5
PCMB065T-1R5MS
6.7
1.8
1.5
PCMB065T-1R5MS
6.7
2.5
1.5
PCMB065T-1R5MS
6.7
3.3
1.5
PCMB065T-1R5MS
6.7
98
96
94
92
Efficiency (%)
90
88
86
84
82
80
78
76
74
72
70
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
Iout (A)
0.7V
0.75V
0.9V
1V
1.1V
0.6
0.9
1.2
1.5
1.2V
1.5V
1.8V
2.5V
3.3V
0.55
0.5
0.45
Power Loss (W)
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0.3
1.8
2.1
2.4
2.7
3
Iout (A)
0.7V
Rev 16.0
0.75V
0.9V
1V
1.1V
1.2V
1.5V
1.8V
2.5V
3.3V
11
PD-97509
IR3843AMPbF
Circuit Description
THEORY OF OPERATION
Introduction
The IR3843A uses a PWM voltage mode control
scheme with external compensation to provide
good noise immunity and maximum flexibility in
selecting inductor values and capacitor types.
The switching frequency is programmable from
250kHz to 1.2MHz and provides the capability of
optimizing the design in terms of size and
performance.
IR3843A provides precisely regulated output
voltage programmed via two external resistors
from 0.7V to 0.9*Vin.
If the input to the Enable pin is derived from the
bus voltage by a suitably programmed resistive
divider, it can be ensured that the IR3843A does
not turn on until the bus voltage reaches the
desired level. Only after the bus voltage reaches
or exceeds this level will the voltage at Enable
pin exceed its threshold, thus enabling the
IR3843A. Therefore, in addition to being a logic
input pin to enable the IR3843A, the Enable
feature, with its precise threshold, also allows the
user to implement an Under-Voltage Lockout for
the bus voltage Vin. This is desirable particularly
for high output voltage applications, where we
might want the IR3843A to be disabled at least
until Vin exceeds the desired output voltage level.
The IR3843A operates with an external bias
supply from 4.5V to 5.5V, allowing an extended
operating input voltage range from 1.5V to 21V.
The device utilizes the on-resistance of the low
side MOSFET as current sense element, this
method enhances the converter’s efficiency and
reduces cost by eliminating the need for external
current sense resistor.
IR3843A includes two low Rds(on) MOSFETs
using IR’s HEXFET technology. These are
specifically designed for high efficiency
applications.
Under-Voltage Lockout and POR
The under-voltage lockout circuit monitors the
input supply Vcc and the Enable input. It assures
that the MOSFET driver outputs remain in the off
state whenever either of these two signals drop
below the set thresholds. Normal operation
resumes once Vcc and Enable rise above their
thresholds.
The POR (Power On Ready) signal is generated
when all these signals reach the valid logic level
(see system block diagram). When the POR is
asserted the soft start sequence starts (see soft
start section).
Enable
The Enable features another level of flexibility for
start up. The Enable has precise threshold which
is internally monitored by Under-Voltage Lockout
(UVLO) circuit. Therefore, the IR3843A will turn
on only when the voltage at the Enable pin
exceeds this threshold, typically, 1.2V.
Rev 16.0
Fig. 3a. Normal Start up, Device turns on
when the Bus voltage reaches 10.2V
Figure 3b. shows the recommended start-up
sequence for the non-sequenced operation of
IR3843A.
Fig. 3b. Recommended startup sequence,
Non-Sequenced operation
Figure 3c. shows the recommended startup
sequence for sequenced operation of IR3843A
12
PD-97509
IR3843AMPbF
Fig. 5. Pre-Bias startup pulses
Soft-Start
Fig. 3c. Recommended startup sequence,
Sequenced operation
Pre-Bias Startup
IR3843A is able to start up into pre-charged
output,
which
prevents
oscillation
and
disturbances of the output voltage.
The IR3843A has a programmable soft-start to
control the output voltage rise and to limit the
current surge at the start-up. To ensure correct
start-up, the soft-start sequence initiates when
the Enable and Vcc rise above their UVLO
thresholds and generate the Power On Ready
(POR) signal. The internal current source
(typically 20uA) charges the external capacitor
Css linearly from 0V to 3V. Figure 6 shows the
waveforms during the soft start.
The output starts in asynchronous fashion and
keeps the synchronous MOSFET off until the first
gate signal for control MOSFET is generated.
Figure 4 shows a typical Pre-Bias condition at
start up.
The start up time can be estimated by:
The synchronous MOSFET always starts with a
narrow pulse width and gradually increases its
duty cycle with a step of 25%, 50%, 75% and
100% until it reaches the steady state value. The
number of these startup pulses for the
synchronous MOSFET is internally programmed.
Figure 5 shows a series of 32, 16, 8 startup
pulses.
During the soft start the OCP is enabled to
protect the device for any short circuit and over
current condition.
Fig. 4. Pre-Bias startup
Rev 16.0
Tstart =
(1.4 - 0.7) * CSS
20μA
- - - - - - - - - - - - - - - - - - - - (1)
Fig. 6. Theoretical operation waveforms
during soft-start
13
PD-97509
IR3843AMPbF
Operating Frequency
The switching frequency can be programmed
between 250kHz – 1200kHz by connecting an
external resistor from Rt pin to Gnd. Table 1
tabulates the oscillator frequency versus Rt.
Table 1. Switching Frequency and IOCSet vs.
External Resistor (Rt)
Rt (kΩ)
Fs (kHz)
Iocset (μA)
47.5
300
29.4
35.7
400
39.2
28.7
500
48.7
23.7
600
59.07
20.5
700
68.2
17.8
800
78.6
15.8
900
88.6
14.3
1000
97.9
12.7
1100
110.2
11.5
1200
121.7
I OCSet (μA ) =
1400
.......... .......... ...............( 2)
R t (kΩ)
Table 1. shows IOCSet at different switching
frequencies. The internal current source
develops a voltage across ROCSet. When the low
side MOSFET is turned on, the inductor current
flows through the Q2 and results in a voltage at
OCSet which is given by:
VOCSet = ( IOCSet ∗ ROCSet ) − ( RDS(on) ∗ I L ) ...........(3)
Fig. 7. Connection of over current sensing resistor
Shutdown
The IR3843A can be shutdown by pulling the
Enable pin below its 1 V threshold. This will tristate both, the high side driver as well as the low
side driver. Alternatively, the output can be
shutdown by pulling the soft-start pin below 0.3V.
Normal operation is resumed by cycling the
voltage at the Soft Start pin.
Over-Current Protection
The over current protection is performed by
sensing current through the RDS(on) of low side
MOSFET. This method enhances the converter’s
efficiency and reduces cost by eliminating a
current sense resistor. As shown in figure 7, an
external resistor (ROCSet) is connected between
OCSet pin and the switch node (SW) which sets
the current limit set point.
An internal current source sources current (IOCSet
) out of the OCSet pin. This current is a function
of the switching frequency and hence, of Rt.
Rev 16.0
An over current is detected if the OCSet pin goes
below ground. Hence, at the current limit
threshold, VOCset=0. Then, for a current limit
setting ILimit, ROCSet is calculated as follows:
ROCSet =
R
DS (on)
* I Limit
IOCSet
........................ (4)
An overcurrent detection trips the OCP
comparator, latches OCP signal and cycles the
soft start function in hiccup mode.
The hiccup is performed by shorting the soft-start
capacitor to ground and counting the number of
switching cycles. The Soft Start pin is held low
until 4096 cycles have been completed. The
OCP signal resets and the converter recovers.
After every soft start cycle, the converter stays in
this mode until the overload or short circuit is
removed.
The OCP circuit starts sampling current typically
160 ns after the low gate drive rises to about 3V.
This delay functions to filter out switching noise.
14
PD-97509
IR3843AMPbF
Thermal Shutdown
Temperature sensing is provided inside
IR3843A. The trip threshold is typically set to
140oC. When trip threshold is exceeded, thermal
shutdown turns off both MOSFETs and
discharges the soft start capacitor.
1.5V <Vin<16V
4.5V <Vcc<5.5V
Enable
Vin
Boot
Vo(master)
Vcc
SW
PGood
PGood
Automatic restart is initiated when the sensed
temperature drops within the operating range.
There is a 20oC hysteresis in the thermal
shutdown threshold.
OCSet
Seq
RA
Fb
Rt
RB
SS/ SD
Output Voltage Sequencing
The
IR3843A
can
accommodate
user
programmable sequencing using Seq, Enable
and Power Good pins.
Gnd
PGnd
Comp
1.5V <Vin<16V
4.5V <Vcc<5.5V
Enable
Vin
Boot
Vo(slave)
Vcc
Vo(master)
SW
PGood
Vo1
RE
PGood
OCSet
Seq
Vo2
RF
Fb
Rt
SS/ SD
RC
RD
Gnd
PGnd
Comp
Simultaneous Powerup
Fig. 8a. Simultaneous Power-up of the slave
with respect to the master.
Through these pins, voltage sequencing such as
simultaneous
and
sequential
can
be
implemented. Figure 8. shows simultaneous
sequencing configurations. In simultaneous
power-up, the voltage at the Seq pin of the slave
reaches 0.7V before the Fb pin of the master. For
RE/RF =RC/RD, therefore, the output voltage of
the slave follows that of the master until the
voltage at the Seq pin of the slave reaches 0.7 V.
After the voltage at the Seq pin of the slave
exceeds 0.85V, the internal 0.7V reference of
the slave dictates its output voltage.
It is recommended that irrespective of the
sequencing configuration used, the input voltage
should be allowed to come up to its nominal
value first, followed by Vcc and Enable, before the
sequencing signal is applied.
For non-sequenced operation, the Seq pin
should be tied to a voltage greater than 0.85V,
such as 3.3V or Vcc. Again, the input voltage
should be allowed to come up before Vcc and
Enable.
Rev 16.0
Fig. 8b. Application Circuit for Simultaneous
Sequencing
Power Good Output
The IC continually monitors the output voltage via
Feedback (Fb pin). The feedback voltage forms
an input to a window comparator whose upper
and lower thresholds are 0.805V and 0.595V
respectively. Hence, the Power Good signal is
flagged when the Fb pin voltage is within the
PGood window, i. e., between 0.595V to 0.805V,
as shown in Fig .9 The PGood pin is open drain
and it needs to be externally pulled high. High
state indicates that output is in regulation. Fig. 9a
shows the PGood timing diagram for nontracking operation. In this case, during startup,
PGood goes high after the SS voltage reaches
2.1V if the Fb voltage is within the PGood
comparator window. Fig. 9a. and Fig 9.b. also
show a 256 cycle delay between the Fb voltage
entering within the thresholds defined by the
PGood window and PGood going high.
15
PD-97509
IR3843AMPbF
TIMING DIAGRAM OF PGOOD FUNCTION
Fig.9a IR3843A Non-Tracking Operation (Seq=Vcc)
Fig.9b IR3843A Tracking Operation
Rev 16.0
16
PD-97509
IR3843AMPbF
Minimum on time Considerations
Maximum Duty Ratio Considerations
The minimum ON time is the shortest amount of
time for which the Control FET may be reliably
turned on, and this depends on the internal
timing delays. For the IR3843A, the typical
minimum on-time is specified as 100 ns.
Any design or application using the IR3843A
must ensure operation with a pulse width that is
higher than this minimum on-time and preferably
higher than 150 ns. This is necessary for the
circuit to operate without jitter and pulseskipping, which can cause high inductor current
ripple and high output voltage ripple.
A fixed off-time of 200 ns maximum is specified
for the IR3843A. This provides an upper limit on
the operating duty ratio at any given switching
frequency. It is clear that, higher the switching
frequency, the lower is the maximum duty ratio at
which the IR3843A can operate. To allow a
margin of 50ns, the maximum operating duty
ratio in any application using the IR3843A should
still accommodate about 250 ns off-time. Fig 10.
shows a plot of the maximum duty ratio v/s the
switching frequency, with 250 ns off-time.
95
D
Fs
Vout
=
Vin × Fs
In any application that uses the IR3843A, the
following condition must be satisfied:
t on (min) ≤ t on
∴ t on (min) ≤
Vout
t on(min)
The minimum output voltage is limited by the
reference voltage and hence Vout(min) = 0.7 V.
Therefore, for Vout(min) = 0.7 V,
∴ Vin × Fs ≤
85
80
75
Vout
Vin × Fs
∴ Vin × Fs ≤
90
Max Duty Cycle (%)
t on =
70
300
400
500
600
700
800
900
1000
1100
1200
Switching Frequency (kHz)
Fig. 10. Maximum duty cycle v/s switching
frequency.
Vout (min)
∴ Vin × Fs ≤
t on(min)
0.7 V
= 4.67 × 10 6 V/s
150 ns
Therefore, even at the minimum switching
frequency 250 kHz, no input voltage higher than
18.5V may be reliably converted down to 0.7V
without excessive jitter or pulse skipping over the
complete load range.
In general, practical considerations dictate that
any application that demands a pulse width
smaller than 175ns may not exhibit jitter free
operation over the entire load range.
Rev 16.0
17
PD-97509
IR3843AMPbF
when an external resistor divider is connected to
the output as shown in figure 11.
Equation (7) can be rewritten as:
Application Information
Design Example:
The following example is a typical application for
IR3843A. The application circuit is shown on
page 23.
Vin = 12 V ( 13.2V max)
⎛ V
R9 = R8 ∗ ⎜⎜ ref
⎝ V o−Vref
⎞
⎟ ..................................(8)
⎟
⎠
For the calculated values of R8
feedback compensation section.
Vo = 1.8 V
Io = 3 A
VOUT
ΔVo ≤ 54mV
IR3843A
IR3624
Fs = 600 kHz
R8
Fb
R9
Enabling the IR3843A
As explained earlier, the precise threshold of
the Enable lends itself well to implementation of
a UVLO for the Bus Voltage.
V in
IR3843A
Enable
R1
R2
For a typical Enable threshold of VEN = 1.2 V
Vin(min) *
R2
= VEN = 1.2 .......... (5)
R1 + R 2
VEN
R 2 = R1
.......... (6)
Vin( min ) − VEN
For a Vin (min)=10.2V, R1=49.9K and R2=7.5K is a
good choice.
Programming the frequency
For Fs = 600 kHz, select Rt = 23.7 kΩ, using
Table. 1.
Output Voltage Programming
Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier, which
is internally referenced to 0.7V. The divider is
ratioed to provide 0.7V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:
⎛ R ⎞
Vo = Vref ∗ ⎜⎜1 + 8 ⎟⎟ ...................................(7)
⎝ R9 ⎠
Rev 16.0
and R9 see
Fig. 11. Typical application of the IR3843A for
programming the output voltage
Soft-Start Programming
The soft-start timing can be programmed by
selecting the soft-start capacitance value. From
(1), for a desired start-up time of the converter,
the soft start capacitor can be calculated by
using:
C SS (μF) = Tstart ( ms ) × 0.02857 .......... (9)
Where Tstart is the desired start-up time (ms).
For a start-up time of 3.5ms, the soft-start
capacitor will be 0.099μF. Choose a 0.1μF
ceramic capacitor.
Bootstrap Capacitor Selection
To drive the Control FET, it is necessary to
supply a gate voltage at least 4V greater than
the voltage at the SW pin, which is connected
the source of the Control FET . This is achieved
by using a bootstrap configuration, which
comprises the internal bootstrap diode and an
external bootstrap capacitor (C6), as shown in
Fig .12. The operation of the circuit is as follows:
When the lower MOSFET is turned on, the
capacitor node connected to SW is pulled down
to ground. The capacitor charges towards Vcc
through the internal bootstrap diode, which has a
forward voltage drop VD. The voltage Vc across
the bootstrap capacitor C6 is approximately
given as
Vc ≅ Vcc − VD .......... .......... ...... (10)
When the upper MOSFET turns on in the next
cycle, the capacitor node connected to SW rises
to the bus voltage Vin. However, if the value of
C6 is appropriately chosen,
18
PD-97509
IR3843AMPbF
the voltage Vc across C6 remains approximately
unchanged and the voltage at the Boot pin
becomes
VBoot ≅ Vin + Vcc − VD ........................................ (11)
Fig. 12. Bootstrap circuit to generate
Vc voltage
A bootstrap capacitor of value 0.1uF is suitable
for most applications.
For applications with 21V input voltage, the switch
node may ring above the 25V absolute maximum
voltage rating. To prevent this, in addition to
using best layout practices, it may be necessary
to provide a 10 ohm resistor in series with the
boot capacitor.
advisable to have 1x10uF 25V ceramic capacitors
C3216X5R1E106M from TDK. In addition to
these, although not mandatory, a 1X330uF, 25V
SMD capacitor EEV-FK1E331P may also be used
as a bulk capacitor and is recommended if the
input power supply is not located close to the
converter.
Inductor Selection
The inductor is selected based on output power,
operating frequency and efficiency requirements.
A low inductor value causes large ripple current,
resulting in the smaller size, faster response to a
load transient but poor efficiency and high output
noise. Generally, the selection of the inductor
value can be reduced to the desired maximum
ripple current in the inductor (Δi ) . The optimum
point is usually found between 20% and 50%
ripple of the output current.
For the buck converter, the inductor value for the
desired operating ripple current can be
determined using the following relation:
Δi
1
; Δt = D ∗
Δt
Fs
.......... .......... .......... . (14)
Vo
L = (Vin − Vo ) ∗
Vin ∗ Δi * Fs
Vin − Vo = L ∗
Where:
Input Capacitor Selection
The ripple current generated during the on time of
the upper MOSFET should be provided by the
input capacitor. The RMS value of this ripple is
expressed by:
Vin = Maximum input voltage
Vo = Output Voltage
Δi = Inductor ripple current
F s = Switching frequency
Δt = Turn on time
D = Duty cycle
IRMS = Io ∗ D ∗ (1 − D) ........................(12)
D=
Vo
................................ (13)
Vin
If Δi ≈ 40%(Io), then the output inductor is
calculated to be 2.13μH. Select L=2.2 μH.
The PCMB065T-2R2MS from Vishay provides a
compact, low profile inductor suitable for this
application
Where:
D is the Duty Cycle
IRMS is the RMS value of the input capacitor
current.
Io is the output current.
For Io=3A and D = 0.15, the IRMS = 1.07A.
Ceramic capacitors are recommended due to
their peak current capabilities. They also feature
low ESR and ESL at higher frequency which
enables better efficiency. For this application, it is
Rev 16.0
19
PD-97509
IR3843AMPbF
Output Capacitor Selection
The voltage ripple and transient requirements
determine the output capacitors type and values.
The criteria is normally based on the value of the
Effective Series Resistance (ESR). However the
actual capacitance value and the Equivalent Series
Inductance (ESL)
are other contributing
components. These components can be described
as
ΔVo = ΔVo( ESR ) + ΔVo( ESL ) + ΔVo(C )
ΔVo(C ) =
⎞
⎟⎟ * ESL
⎠
voltage
ΔI L = Inductor
ripple
2 ∗ π Lo ∗ Co
................................ (16)
Phase
Gain
0 dB
00
-40dB/decade
ripple
current
Since the output capacitor has a major role in the
overall performance of the converter and
determines the result of transient response,
selection of the capacitor is critical. The IR3843A
can perform well with all types of capacitors.
As a rule, the capacitor must have low enough
ESR to meet output ripple and load transient
requirements.
The goal for this design is to meet the voltage
ripple requirement in the smallest possible
capacitor size. Therefore it is advisable to select
ceramic capacitors due to their low ESR and ESL
and small size. Three of the Panasonic ECJ2FB0J226ML (22uF, 6.3V, 3mOhm) capacitors is
a good choice.
Feedback Compensation
The IR3843A is a voltage mode controller. The
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed-loop transfer
function with the highest 0 dB crossing frequency
and adequate phase margin (greater than 45o).
Rev 16.0
1
.......... .......... ..... (15)
ΔI L
8 * C o * Fs
ΔVo = Output
FLC =
Figure 13 shows gain and phase of the LC filter.
Since we already have 180o phase shift from the
output filter alone, the system runs the risk of
being unstable.
ΔVo( ESR ) = ΔI L * ESR
⎛ V − Vo
ΔVo( ESL ) = ⎜⎜ in
L
⎝
The output LC filter introduces a double pole,
–40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180o
(see figure 13). The resonant frequency of the LC
filter is expressed as follows:
-1800
FLC
Frequency
FLC Frequency
Fig. 13. Gain and Phase of LC filter
The IR3843A uses a voltage-type error amplifier
with high-gain (110dB) and wide-bandwidth. The
output of the amplifier is available for DC gain
control and AC phase compensation.
The error amplifier can be compensated either in
type II or type III compensation.
Local feedback with Type II compensation is
shown in Fig. 14.
This method requires that the output capacitor
should have enough ESR to satisfy stability
requirements. In general the output capacitor’s
ESR generates a zero typically at 5kHz to 50kHz
which is essential for an acceptable phase
margin.
The ESR zero of the output capacitor is
expressed as follows:
FESR =
1
.......... .......... ....... (17)
2 ∗ π*ESR*C o
20
PD-97509
IR3843AMPbF
VOUT
Z IN
C POLE
R3
C4
R8
Zf
Fb
R9
Gain(dB)
E/A
Comp
Ve
Fz = 0.75*
FZ
F
POLE
Frequency
Fig. 14. Type II compensation network
and its asymptotic gain plot
The transfer function (Ve/Vo) is given by:
Ve
1 + sR3C4
Z
= H(s) = − f = −
.....(18)
ZIN
sR8C4
Vo
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero, expressed by:
Fz =
To cancel one of the LC filter poles, place the
zero before the LC filter resonant frequency pole:
Fz = 75%FLC
VREF
H(s) dB
H(s) =
Where:
Vin = Maximum Input Voltage
Vosc = Oscillator Ramp Voltage
Fo = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R8 = Feedback Resistor
R3
......................................(19)
R8
1
............................(20)
2π * R3 * C4
First select the desired zero-crossover frequency
(Fo):
Fo > FESR and Fo ≤ (1/5 ~ 1/10) * Fs
Vosc * Fo * FESR * R8
2
Vin * FLC
...........................(21)
FP =
.....................................(22)
1
.................................(23)
C *C
2π * R3 * 4 POLE
C4 + CPOLE
The pole sets to one half of the switching
frequency which results in the capacitor CPOLE:
CPOLE =
1
π*R3*Fs −
1
C4
≅
1
......................(24)
π*R3*Fs
For a general solution for unconditional stability
for any type of output capacitors, and a wide
range of ESR values, we should implement local
feedback with a type III compensation network.
The typically used compensation network for
voltage-mode controller is shown in figure 15.
Again, the transfer function is given by:
Ve
Z
= H(s) = − f
Vo
ZIN
By replacing Zin and Zf according to figure 15,
the transfer function can be expressed as:
H(s) = −
Rev 16.0
2π Lo * Co
Use equations (20), (21) and (22) to calculate
C4.
One more capacitor is sometimes added in
parallel with C4 and R3. This introduces one
more pole which is mainly used to suppress the
switching noise.
The additional pole is given by:
Use the following equation to calculate R3:
R3 =
1
(1 + sR3C4 )[1 + sC7 (R8 + R10 )]
⎡
⎛ C * C3 ⎞⎤
⎟⎥(1 + sR10C7 )
sR8 (C4 + C3 )⎢1 + sR3 ⎜⎜ 4
⎟
⎢⎣
⎝ C4 + C3 ⎠⎥⎦
21
....(25)
PD-97509
IR3843AMPbF
VOUT
ZIN
C3
C7
R3
R10
C4
R8
Zf
Fb
R9
Gain(dB)
E/A
Comp
Ve
FZ2
FP2
FP3
Frequency
Fig.15. Type III Compensation network and
its asymptotic gain plot
The compensation network has three poles and
two zeros and they are expressed as follows:
FP1 = 0 ..................................................................(26)
FP 2 =
1
...............................................(27)
2π * R10 * C7
1
FP3 =
FZ1
≅
1
...............(28)
2π * R3 * C3
⎛ C * C3 ⎞
⎟
2π * R3 ⎜⎜ 4
⎟
⎝ C4 + C3 ⎠
1
=
.............................................(29)
2π * R3 * C4
FZ 2 =
1
1
≅
..........(30)
2π * C7 * (R8 + R10 ) 2π * C7 * R8
Cross over frequency is expressed as:
Fo = R3 * C7 *
Vin
1
*
................................(31)
Vosc 2π * Lo * Co
Based on the frequency of the zero generated by
the output capacitor and its ESR, relative to
crossover frequency, the compensation type can
be different. The table below shows the
compensation types and location of the
crossover frequency.
Rev 16.0
FESR vs Fo
Output
Capacitor
Type II
FLC<FESR<Fo<Fs/2
Electrolytic
Tantalum
Type III
FLC<Fo<FESR
Tantalum
Ceramic
VREF
H(s) dB
FZ1
Compensator
Type
The higher the crossover frequency, the
potentially faster the load transient response.
However, the crossover frequency should be low
enough to allow attenuation of switching noise.
Typically, the control loop bandwidth or crossover
frequency is selected such that
Fo ≤ (1/5 ~ 1/10) * Fs
The DC gain should be large enough to provide
high DC-regulation accuracy. The phase margin
should be greater than 45o for overall stability.
For this design we have:
Vin=12V
Vo=1.8V
Vosc=1.8V
Vref=0.7V
Lo=2.2 uH
Co=3x22uF, ESR=3mOhm each
It must be noted here that the value of the
capacitance used in the compensator design
must be the small signal value. For instance, the
small signal capacitance of the 22uF capacitor
used in this design is 12uF at 1.8 V DC bias and
600 kHz frequency. It is this value that must be
used for all computations related to the
compensation. The small signal value may be
obtained from the manufacturer’s datasheets,
design tools or SPICE models. Alternatively, they
may also be inferred from measuring the power
stage transfer function of the converter and
measuring the double pole frequency FLC and
using equation (16) to compute the small signal
Co.
These result to:
FLC=17.88 kHz
FESR=4.4 MHz
Fs/2=300 kHz
Select crossover frequency: Fo=80 kHz
Since FLC<Fo<Fs/2<FESR, TypeIII is selected to
place the pole and zeros.
22
PD-97509
IR3843AMPbF
Detailed calculation of compensation TypeIII
Desired Phase Margin Θ = 70o
FZ2 = Fo
1 − sin Θ
= 14.11 kHz
1 + sin Θ
FP2 = Fo
1 + sin Θ
= 453.7kHz
1 − sin Θ
Select: FZ1 = 0.5 * FZ2 = 7.05 kHz and
FP3 = 0.5* Fs = 300 kHz
Programming the Current-Limit
The Current-Limit threshold can be set by
connecting a resistor (ROCSET) from the SW pin
to the OCSet pin. The resistor can be calculated
by using equation (4). This resistor ROCSET must
be placed close to the IC.
The RDS(on) has a positive temperature
coefficient and it should be considered for the
worst case operation.
ISET = IL (critical) =
ROCSet∗ IOCSet
.......................(32)
RDS(on)
RDS(on) = 24.5 mΩ *1.25 = 30.625 mΩ
ISET ≅ I o(LIM) = 3A *1.5 = 4.5 A
Select: C7 = 2.2nF
(50% over nominal output current )
IOCSet = 59.07 μA (at Fs = 600kHz)
Calculate R3, C3 and C4 :
ROCSet = 2.33 kΩ Select R7 = 2.26kΩ
2π * Fo * Lo * Co * Vosc
;R3 = 2.71 kΩ
C7 * Vin
R3 =
Select: R3 = 2.74 kΩ
C4 =
1
; C4 = 8.24 nF, Select: C4 = 8.2 nF
2π * FZ1 * R 3
C3 =
1
; C3 = 193.62pF, Select: C3 = 180 pF
2π * FP3 * R3
Setting the Power Good Threshold
A window comparator internally sets a lower
Power Good threshold at 0.6V and an upper
Power Good threshold at 0.8V. When the voltage
at the FB pin is within the window set by these
thresholds, PGood is asserted.
The PGood is an open drain output. Hence, it is
necessary to use a pull up resistor RPG from
PGood pin to Vcc. The value of the pull-up
resistor must be chosen such as to limit the
current flowing into the PGood pin, when the
output voltage is not in regulation, to less than 5
mA. A typical value used is 10kΩ.
Calculate R10, R8 and R9 :
R10 =
1
; R10 = 160 Ω, Select: R10 = 158 Ω
2π * C7 * FP2
R8 =
1
- R10; R8 = 5 kΩ,
2π * C7 * FZ2
Select: R8 = 4.99 kΩ
R9 =
Vref
* R8; R9 = 3.18 kΩ Select: R9 = 3.16 kΩ
Vo - Vref
Rev 16.0
23
PD-97509
IR3843AMPbF
Application Diagram:
Fig. 16. Application circuit diagram for a 12V to 1.8 V, 3 A Point Of Load Converter
Suggested Bill of Materials for the application circuit:
Part Reference
Cin
Lo
Co
R1
R2
Rt
Rocset
RPG
Css C6
R3
C3
C4
R8
R9
R10
C7
CVcc
U1
Rev 16.0
Quantity
1
1
1
1
3
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
Value
330uF
10uF
0.1uF
2.2uH
22uF
49.9k
7.5k
23.7k
2.26k
10k
0.1uF
2.74k
180pF
8.2nF
4.99k
3.16k
158
2200pF
1.0uF
IR3843A
Description
SMD Elecrolytic, Fsize, 25V, 20%
1206, 16V, X5R, 20%
0603, 25V, X7R, 10%
7x6.5x5mm, 20%, 8A
0805, 6.3V, X5R, 20%
Thick Film, 0603,1/10 W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
0603, 25V, X7R, 10%
Thick Film, 0603,1/10W,1%
50V, 0603, NPO, 5%
0603, 50V, X7R, 10%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
0603, 50V, X7R, 10%
0603, 16V, X5R, 20%
SupIRBuck, 3A, PQFN 5x6mm
Manufacturer
Panasonic
TDK
Panasonic
Cyntec
Panasonic
Rohm
Rohm
Rohm
Rohm
Rohm
Panasonic
Rohm
Panasonic
Panasonic
Rohm
Rohm
Rohm
Panasonic
Panasonic
International Rectifier
Part Number
EEV-FK1E331P
C3216X5R1E106M
ECJ-1VB1E104K
PCMB065T-2R2MS
ECJ-2FB0J226ML
MCR03EZPFX4992
MCR03EZPFX7501
MCR03EZPFX2372
MCR03EZPFX2261
MCR03EZPFX1002
ECJ-1VB1E104K
MCR03EZPFX2741
ECJ-1VC1H181J
ECJ-1VB1H822K
MCR03EZPFX4991
MCR03EZPFX3161
ERJ-3EKF1580V
ECJ-1VB1H222K
ECJ-BVB1C105M
IR3843AMPbF
24
PD-97509
IR3843AMPbF
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-3A, Room Temperature, No Air Flow
Fig. 17. Start up at 3A Load
Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:Enable
Fig. 18. Start up at 3A Load,
Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:VPGood
Fig. 19. Start up with 1.62V Pre
Bias, 0A Load, Ch2:Vo, Ch3:VSS
Fig. 20. Output Voltage Ripple, 3A
load Ch2: Vo
Fig. 21. Inductor node at 3A load
Ch1:LX
Fig. 22. Short (Hiccup) Recovery
Ch2:Vo , Ch3:VSS
Rev 16.0
25
PD-97509
IR3843AMPbF
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=1.8V, Io=1.5A-3A, Room Temperature, No Air Flow
Fig. 23. Transient Response, 1.5A to 3A step
2.5A/μs
Ch2:Vo, Ch4:Io
Rev 16.0
26
PD-97509
IR3843AMPbF
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=1.8V, Io=3A, Room Temperature, No Air Flow
Fig. 24. Bode Plot at 3A load shows a bandwidth of 82kHz and phase margin of 56
degrees
Rev 16.0
27
PD-97509
IR3843AMPbF
Simultaneous Tracking at Power Up and Power Down
Vin=12V, Vo=1.8V, Io=3A, Room Temperature, No Air Flow
VOUT
3.3V
4.99K
R s1
3.16K
Rs2
IR3843A
IR3624
Seq
R8 4.99K
Fb
R9 3.16K
Fig. 25: Simultaneous Tracking a 3.3V input at power-up and shut-down
Ch2: Vout Ch3:SS Ch4: Seq
Rev 16.0
28
PD-97509
IR3843AMPbF
PGnd
Feedback
trace should
be kept
away form
noise
sources
Fig. 26b. IRDC3843A demoboard layout
considerations – Bottom Layer
Analog
Ground
plane
Power
Vin
Ground
Plane
Single point
connection between
AGND & PGND,
should be close to
the SupIRBuck, kept
away from noise
sources.
AGnd
Fig. 26c. IRDC3843A demoboard layout
considerations – Mid Layer 1
Use separate traces
for connecting Boot
cap and Rocset to the
switch node and with
the minimum length
traces. Avoid big
loops.
Fig. 26d. IRDC3843A demoboard layout
considerations – Mid Layer 2
Rev 16.0
29
PD-97509
IR3843AMPbF
PCB Metal and Components Placement
Lead lands (the 11 IC pins) width should be equal to nominal part lead width. The
minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard
extension. The outboard extension ensures a large and inspectable toe fillet.
Pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to
maximum part pad length and width. However, the minimum metal to metal spacing
should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper
and no less than 0.23mm for 3 oz. Copper.
Rev 16.0
30
PD-97509
IR3843AMPbF
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder
resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure
NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder
resist onto the copper of 0.05mm to accommodate solder resist mis-alignment.
Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due
to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
Rev 16.0
31
PD-97509
IR3843AMPbF
Stencil Design
•
•
The Stencil apertures for the lead lands should be approximately 80% of the area of
the lead lads. Reducing the amount of solder deposited will minimize the
occurrences of lead shorts. If too much solder is deposited on the center pad the part
will float and the lead lands will be open.
The maximum length and width of the land pad stencil aperture should be equal to
the solder resist opening minus an annular 0.2mm pull back to decrease the
incidence of shorting the center land to the lead lands when the part is pushed into
the solder paste.
Rev 16.0
32
PD-97509
IR3843AMPbF
BOTTOM VIEW
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial market (Note5)
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 08/12
Rev 16.0
33