SN74LVC2G125-Q1 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES559B – MARCH 2004 – REVISED OCTOBER 2007 FEATURES 1 • • • • • • • • Qualified for Automotive Applications Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.3 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • • • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCT OR DCU PACKAGE (TOP VIEW) 1OE 1A 2Y GND 1 8 2 7 3 6 4 5 VCC 2OE 1Y 2A DESCRIPTION/ORDERING INFORMATION The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) (3) (4) SSOP – DCT VSSOP – DCU ORDERABLE PART NUMBER Tape and reel CLVC2G125IDCTRQ1 Tape and reel CLVC2G125IDCURQ1 TOP-SIDE MARKING (3) C25_ _ _ (4) C25_ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. Product preview FUNCTION TABLE (EACH BUFFER) INPUTS OE A OUTPUT Y L H H L L L H X Z 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2007, Texas Instruments Incorporated SN74LVC2G125-Q1 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES559B – MARCH 2004 – REVISED OCTOBER 2007 LOGIC DIAGRAM (POSITIVE LOGIC) 1 1OE 1A 2 6 1Y 7 2OE 5 3 2A 2Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) 2 DCT package 220 DCU package 227 –65 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G125-Q1 SN74LVC2G125-Q1 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES559B – MARCH 2004 – REVISED OCTOBER 2007 Recommended Operating Conditions (1) VCC Operating Supply voltage Data retention only 1.65 5.5 1.7 VCC = 3 V to 3.6 V 0.7 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 Input voltage VO Output voltage 0 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 1.65 V High-level output current VCC = 3 V Low-level output current Δt/Δv –32 VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 (1) Operating free-air temperature mA 24 VCC = 5 V ± 0.5 V TA mA –24 VCC = 3 V Input transition rise or fall rate V –8 –16 VCC = 4.5 V IOL V –4 VCC = 2.3 V IOH V 0.3 × VCC VCC = 4.5 V to 5.5 V VI V V 2 VCC = 4.5 V to 5.5 V VIL UNIT 0.65 × VCC VCC = 2.3 V to 2.7 V High-level input voltage MAX 1.5 VCC = 1.65 V to 1.95 V VIH MIN ns/V 5 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G125-Q1 Submit Documentation Feedback 3 SN74LVC2G125-Q1 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES559B – MARCH 2004 – REVISED OCTOBER 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 μA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 V 2.4 3V IOH = –24 mA 2.3 IOH = –32 mA 4.5 V IOL = 100 μA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 16 mA 3.8 0.4 3V IOL = 24 mA IOL = 32 mA UNIT VCC – 0.1 IOH = –4 mA IOH = –16 mA VOL MIN TYP (1) MAX VCC V 0.55 4.5 V 0.55 0 to 5.5 V ±5 μA Ioff VI or VO = 5.5 V 0 ±10 μA IOZ VO = 0 to 5.5 V 3.6 V 10 μA ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 μA ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 μA II A or OE inputs Data inputs Ci Control inputs Co (1) VI = 5.5 V or GND VI = VCC or GND 3.3 V VO = VCC or GND 3.3 V 3.5 pF 4 6.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A ten OE tdis OE PARAMETER VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V MIN MAX MIN MAX MIN MAX Y 3.3 9.1 1.5 4.8 1.4 Y 4 9.9 1.9 5.6 1.2 Y 1.5 11.6 1 5.8 1.4 VCC = 5 V ± 0.5 V UNIT MIN MAX 4.3 1 3.7 ns 4.7 1.2 3.8 ns 4.6 1 3.4 ns Operating Characteristics TA = 25 TEST CONDITIONS PARAMETER Cpd 4 Power dissipation capacitance Outputs enabled Outputs disabled Submit Documentation Feedback f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 19 19 20 22 2 2 2 3 UNIT pF Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G125-Q1 SN74LVC2G125-Q1 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES559B – MARCH 2004 – REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G125-Q1 Submit Documentation Feedback 5 PACKAGE OPTION ADDENDUM www.ti.com 2-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CLVC2G125IDCTRQ1 ACTIVE SM8 DCT Pins Package Eco Plan (2) Qty 8 3000 TBD Lead/Ball Finish CU MSL Peak Temp (3) Level-1-220C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion Falls within JEDEC MO-187 variation DA. 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