16-Channel DAS with 16-Bit, Bipolar Input, Dual Simultaneous Sampling ADC AD7616-P Data Sheet FEATURES APPLICATIONS 16-channel, dual, simultaneously sampled inputs Independently selectable channel input ranges True bipolar: ±10 V, ±5 V, ±2.5 V Single 5 V analog supply and 2.3 V to 3.6 V VDRIVE supply Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance 1st-order antialiasing analog filter On-chip accurate reference and reference buffer Dual 16-bit SAR ADC Throughput rate: 2 × 1 MSPS Oversampling capability with digital filter Flexible sequencer with burst mode Parallel digital interface Optional CRC error checking Hardware/software configuration Performance 92 dB SNR at 500 kSPS (2× OSR) 90.5 dB SNR at 1 MSPS −103 dB THD ±1 LSB INL (typical), ±0.99 LSB DNL (maximum) 8 kV ESD rating on analog input pins On-chip self detect function 80-lead LQFP package Power line monitoring Protective relays Multiphase motor control Instrumentation and control systems Data acquisition systems (DASs) GENERAL DESCRIPTION The AD7616-P is a 16-bit, DAS that supports dual simultaneous sampling of 16 channels. The AD7616-P operates from a single 5 V supply and can accommodate ±10 V, ±5 V, and ±2.5 V true bipolar input signals while sampling at throughput rates up to 1 MSPS per channel pair with 90.5 dB SNR. Higher signal-tonoise ratio (SNR) performance can be achieved with the on-chip oversampling mode (92 dB for an oversampling ratio (OSR) of 2). The input clamp protection circuitry tolerates voltages up to ±21 V. The AD7616-P has 1 MΩ analog input impedance, regardless of sampling frequency. The single-supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The device contains analog input clamp protection, a dual, 16-bit charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and a high speed parallel interface. FUNCTIONAL BLOCK DIAGRAM VCC CLAMP V0AGND CLAMP V7A CLAMP V7AGND CLAMP V0B CLAMP V0BGND CLAMP V7B CLAMP V7BGND CLAMP 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ AD7616-P RFB VCC ALDO 2.5V REF FIRSTORDER LPF 1.8V ALDO 1.8V DLDO 9:1 MUX PAR 16-BIT SAR FIRSTORDER LPF 16-BIT SAR OSR DIGITAL FILTER PARALLEL INTERFACE PARALLEL DB15 TO DB0 FIRSTORDER LPF 9:1 MUX FIRSTORDER LPF RESET WR/BURST SEQEN HW_RNGSEL0, HW_RNGSEL1 CHSEL2 TO CHSEL0 FLEXIBLE SEQUENCER CONTROL INPUTS 2:1 MUX CLK OSC BUSY CONVST DGND AGND 15695-001 V0A REFCAP REFINOUT REFSEL REGCAP REGCAPD VDRIVE Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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AD7616-P Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Internal/External Reference ...................................................... 25 Applications ....................................................................................... 1 Hardware Mode .......................................................................... 25 General Description ......................................................................... 1 Software Mode ............................................................................ 26 Functional Block Diagram .............................................................. 1 Reset Functionality..................................................................... 26 Revision History ............................................................................... 2 Pin Function Overview ............................................................. 26 Specifications..................................................................................... 3 Digital Interface .............................................................................. 27 Timing Specifications .................................................................. 6 Channel Selection....................................................................... 27 Absolute Maximum Ratings ............................................................ 9 Parallel Interface ......................................................................... 28 Thermal Resistance ...................................................................... 9 Sequencer......................................................................................... 30 ESD Caution .................................................................................. 9 Hardware Mode Sequencer ....................................................... 30 Pin Configuration and Function Descriptions ........................... 10 Software Mode Sequencer ......................................................... 30 Typical Performance Characteristics ........................................... 13 Burst Sequencer .......................................................................... 31 Terminology .................................................................................... 19 Diagnostics ...................................................................................... 33 Theory of Operation ...................................................................... 21 Diagnostic Channels .................................................................. 33 Converter Details........................................................................ 21 Interface Self Test ....................................................................... 33 Analog Input ............................................................................... 21 CRC .............................................................................................. 33 ADC Transfer Function ............................................................. 22 Register Summary .......................................................................... 35 Internal/External Reference ...................................................... 22 Addressing Registers .................................................................. 36 Shutdown Mode.......................................................................... 23 Configuration Register .............................................................. 37 Digital Filter ................................................................................ 23 Channel Register ........................................................................ 38 Applications Information .............................................................. 24 Input Range Registers ................................................................ 39 Functionality Overview ............................................................. 24 Sequencer Stack Registers ......................................................... 42 Power Supplies ............................................................................ 24 Status Register ............................................................................. 45 Typical Connections .................................................................. 24 Outline Dimensions ....................................................................... 46 Device Configuration ..................................................................... 25 Ordering Guide .......................................................................... 46 Operational Mode ...................................................................... 25 REVISION HISTORY 6/2017—Revision 0: Initial Version Rev. 0 | Page 2 of 46 Data Sheet AD7616-P SPECIFICATIONS VREF = 2.5 V external/internal, VCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 3.6 V, fSAMPLE = 1 MSPS, TA = −40°C to +125°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE SNR1, 2 Signal-to-Noise-and-Distortion (SINAD)1 Dynamic Range Total Harmonic Distortion (THD)1 Peak Harmonic or Spurious Noise1 Intermodulation Distortion (IMD)1 Second-Order Terms Third-Order Terms Channel to Channel Isolation1 ANALOG INPUT FILTER Full Power Bandwidth Phase Delay1, 3 Drift1, 3 Matching (Dual Simultaneous Pair)3 DC ACCURACY Resolution Differential Nonlinearity (DNL)1 Integral Nonlinearity (INL)1 Total Unadjusted Error (TUE) Positive Full-Scale (PFS) Error1, 5 External Reference Test Conditions/Comments fIN = 1 kHz sine wave, unless otherwise noted No oversampling, ±10 V range OSR = 2, ±10 V range,3 fSAMPLE = 500 kSPS OSR = 4, ±10 V range3 No oversampling, ±5 V range No oversampling, ±2.5 V range No oversampling, ±10 V range No oversampling, ±5 V range No oversampling, ±2.5 V range No oversampling, ±10 V range No oversampling, ±5 V range No oversampling, ±2.5 V range No oversampling, ±10 V range No oversampling, ±5 V range No oversampling, ±2.5 V range Min Typ 89 90.5 92 93 89.5 87 90 89 87 92 90.5 88 −103 −100 −97 −103 88 85.5 88.5 87.5 85 Max −92.5 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB fa = 1 kHz, fb = 1.1 kHz fIN on unselected channels up to 5 kHz −105 −113 −106 dB dB dB −3 dB, ±10 V range −3 dB, ±5 V/2.5 V range −0.1 dB ±10 V range ±5 V range ±2.5 V range ±10 V range ±10 V range ±5 V range ±2.5 V range 39 33 5.5 4.4 5 4.9 ±0.55 4.4 4.7 4.1 kHz kHz kHz µs µs µs ns/°C ns ns ns No missing codes 6 5 100 16 ±0.99 ±2 ±10 V range ±5 V range ±2.5 V range ±0.5 ±1 ±6 ±8 ±10 ±10 V range ±5 V range ±2.5 V range ±5 ±4 ±2 ±38 ±10 V range External reference Internal reference ±10 V range ±5 V range ±5 ±2 ±3 3 4 Bits LSB4 LSB4 LSB4 LSB4 LSB4 LSB4 LSB4 LSB4 Internal Reference 3 Drift Matching1 Rev. 0 | Page 3 of 46 ±5 ±10 11 LSB4 ppm/°C ppm/°C LSB4 LSB4 AD7616-P Parameter Bipolar Zero Code Error1 Drift3 Matching1 Negative Full-Scale (NFS) Error1, 6 3 Drift Matching1 ANALOG INPUT Input Voltage Ranges Analog Input Current Input Capacitance6 Input Impedance Input Impedance Drift3 REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance6 Reference Output Voltage Reference Temperature Coefficient3 LOGIC INPUTS Input Voltage High (VINH) Low (VINL) Input Current (IIN) Input Capacitance (CIN)6 LOGIC OUTPUTS Output Voltage High (VOH) Low (VOL) Floating State Leakage Current Floating State Output Capacitance6 Output Coding Data Sheet Test Conditions/Comments ±2.5 V range ±10 V range ±5 V range ±2.5 V range ±10 V range ±5 V range ±2.5 V range ±10 V range ±5 V range ±2.5 V range External reference ±10 V range ±5 V range ±2.5 V range Internal reference ±10 V range External reference Internal reference ±10 V range ±5 V range ±2.5 V range Min ±4 ±3 ±6 ±3 ±2 ±4 3 4 8 Software/hardware selectable Software/hardware selectable Software/hardware selectable ±10 V range, see Figure 33 ±5 V range, see Figure 33 ±2.5 V range, see Figure 33 See the Analog Input section Typ 8 ±0.8 ±1 ±3 ±1.3 ±0.9 ±0.5 ±2 ±3 ±3 Max ±8 ±10 ±15 ±20.4 ±10 ±38 ±5 ±10 11 ±10 ±5 ±2.5 0.85 ±10.5 ±6.5 ±4 10 1 25 See the ADC Transfer Function section 2.495 REFSEL = 1 REFINOUT 2.495 2.5 2.505 ±1 7.5 ±2 VDRIVE = 2.7 V to 3.6 V VDRIVE = 2.3 V to 2.7 V VDRIVE = 2.7 V to 3.6 V VDRIVE = 2.3 V to 2.7 V 2.505 ±15 2 1.7 0.8 0.7 ±1 5 ISOURCE = 100 µA ISINK = 100 µA VDRIVE − 0.2 ±0.005 5 Twos complement Rev. 0 | Page 4 of 46 0.4 ±1 Unit LSB4 LSB4 LSB4 LSB4 µV/°C µV/°C µV/°C LSB4 LSB4 LSB4 LSB4 LSB4 LSB4 LSB4 ppm/°C ppm/°C LSB4 LSB4 LSB4 V V V µA µA µA pF MΩ ppm/°C V µA pF V ppm/°C V V V V µA pF V V µA pF Data Sheet Parameter CONVERSION RATE Conversion Time Acquisition Time Throughput Rate POWER REQUIREMENTS VCC VDRIVE VCC Pin Current, IVCC Normal Mode Static Operational Shutdown Mode IDRIVE Normal Mode Static Operational Shutdown Mode Power Dissipation Normal Mode Static Operational Shutdown Mode AD7616-P Test Conditions/Comments Per channel pair Min Typ Max Unit 1 µs µs MSPS 5.25 3.6 V V 37 42 28 57 65 mA mA µA fSAMPLE = 1 MSPS 0.3 2.4 20 0.95 3.2 mA mA µA fSAMPLE = 1 MSPS 185 230 0.25 300 360 mW mW mW 0.5 0.5 4.75 2.3 fSAMPLE = 1 MSPS Digital inputs = 0 V or VDRIVE 1 See the Terminology section. The user can achieve 93 dB SNR by enabling oversampling. The values are valid for manual mode. In burst mode, values degrade by ~1 dB. Not production tested. Sample tested during initial release to ensure compliance. 4 LSB means least significant bit. With a ±2.5 V input range, 1 LSB = 76.293 µV. With a ±5 V input range, 1 LSB = 152.58 µV. With a ±10 V input range, 1 LSB = 305.175 µV. 5 Positive and negative full-scale error for the internal reference excludes reference errors. 6 Supported by simulation data. 2 3 Rev. 0 | Page 5 of 46 AD7616-P Data Sheet TIMING SPECIFICATIONS Note that throughout the timing specifications, multifunction pins, such as WR/ BURST, are referred to either by the entire pin name or by a single function of the pin, for example, WR, when only that function is relevant. Universal Timing Specifications VCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 3.6 V, VREF = 2.5 V external reference/internal reference, TA = −40°C to +125°C, unless otherwise noted. Interface timing tested using a load capacitance of 30 pF. Table 2. Parameter1 tCYCLE Min 1 tCONV_LOW tCONV_HIGH tBUSY_DELAY tCS_SETUP 50 50 tCH_SETUP tCH_HOLD tCONV tACQ tQUIET tRESET_LOW 50 20 Partial Reset Full Reset tDEVICE_SETUP Partial Reset Full Reset tWRITE Partial Reset Full Reset tRESET_WAIT Typ Max ns ns ns ns 34 20 475 530 470 50 40 1.2 Unit µs 500 ns ns ns ns ns Channel select setup time in hardware mode for CHSELx Channel select hold time in hardware mode for CHSELx Conversion time for the selected channel pair Acquisition time for the selected channel pair CS rising edge to next CONVST rising edge See Figure 3 ns µs Partial RESET low pulse width Full RESET low pulse width See Figure 3 Time between partial RESET high and CONVST rising edge Time between full RESET high and CONVST rising edge See Figure 3 Time between partial RESET high and CS for write operation Time between full RESET high and CS for write operation Time between stable VCC/VDRIVE and release of RESET (see Figure 3) 120 15 ns ms 50 240 1 ns µs ms 10 0.05 ns ms Time prior to release of RESET that queried hardware inputs must be stable for (see Figure 3) tRESET_SETUP Partial Reset Full Reset Time after release of RESET that latched hardware inputs must be stable for (see Figure 3) tRESET_HOLD Partial Reset Full Reset 10 0.24 ns ms Not production tested. Sample tested during initial release to ensure compliance. tCYCLE tCONV_LOW tCONV_HIGH tQUIET tBUSY_DELAY CONVST BUSY tCONV tACQ tCS_SETUP CS tCH_SETUP HARDWARE MODE ONLY CHSEL0 TO CHSEL2 tCH_HOLD CHX CHY Figure 2. Universal Timing Diagram Across All Interfaces Rev. 0 | Page 6 of 46 15695-002 1 Description Minimum time between consecutive CONVST rising edges (excluding burst and oversampling modes) CONVST low pulse width CONVST high pulse width CONVST high to BUSY high (manual mode) BUSY falling edge to CS falling edge setup time Data Sheet AD7616-P tRESET_WAIT tDEVICE_SETUP VCC VDRIVE RESET tRESET_LOW CONVST BUSY tWRITE CS tRESET_SETUP tRESET_HOLD REFSEL ALL MODES HW_RNGSEL0, HW_RNGSEL1 MODE RANGE SETTING IN HW MODE BURST, SEQEN CHSEL0 TO CHSEL2 ADC ACTION CHX CHZ CHY ACQX CONVX Figure 3. Reset Timing Diagram Rev. 0 | Page 7 of 46 ACQY CONVY 15695-003 HARDWARE MODE ONLY AD7616-P Data Sheet Parallel Interface Timing Specifications Table 3. Parameter tCS_HIGH Min 20 tRD_SETUP 0 Typ Max Unit ns Description CS high pulse width ns CS falling edge to RD falling edge setup time tRD_HOLD 0 ns RD rising edge to CS rising edge hold time tRD_HIGH 20 ns RD high pulse width tRD_LOW 40 ns RD low pulse width Data access time after falling edge of RD CS rising edge to DBx high impedance CS to WR setup time tDOUT_SETUP tDOUT_3STATE tWR_SETUP 40 16 0 ns ns ns tWR_HIGH 20 ns WR high pulse width tWR_LOW 40 ns WR low pulse width tWR_HOLD 0 ns WR hold time tDIN_SETUP tDIN_HOLD tCONF_SETTLE 12 5 20 ns ns ns Configuration data to WR setup time Configuration data to WR hold time Configuration data settle time, WR rising edge to CONVST rising edge CONVST BUSY tRD_HIGH tRD_HOLD tCS_HIGH tDOUT_3STATE CS RD CONV A CONV B tRD_SETUP tRD_LOW tDOUT_SETUP 15695-004 DB0 TO DB15 Figure 4. Parallel Read Timing Diagram tWR_SETUP tCONF_SETTLE CONVST CS tWR_HIGH tWR_HOLD WR WRITE REG 1 DB0 TO DB15 tWR_LOW WRITE REG 2 tDIN_SETUP Figure 5. Parallel Write Timing Diagram Rev. 0 | Page 8 of 46 15695-005 tDIN_HOLD Data Sheet AD7616-P ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 4. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Parameter VCC to AGND VDRIVE to AGND Analog Input Voltage to AGND1 Digital Input Voltage to AGND Digital Output Voltage to AGND REFINOUT to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature Soldering Reflow Pb/Sn Temperature (10 sec to 30 sec) Pb-Free Temperature ESD All Pins Except Analog Inputs Analog Input Pins Only 1 Rating −0.3 V to +7 V −0.3 V to VCC + 0.3 V ±21 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VCC + 0.3 V ±10 mA −40°C to +125°C −65°C to +150°C 150°C θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 5. Thermal Resistance Package Type ST-80-21 1 θJC 7.5 Unit °C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD51. ESD CAUTION 240 (+0)°C 260 (+0)°C θJA 41 2 kV 8 kV Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch-up. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 9 of 46 AD7616-P Data Sheet WR/BURST RD CHSEL0 CS CHSEL1 CHSEL2 BUSY CONVST REGGND REGCAP AGND VCC V0B V0BGND V1B V1BGND V2B V2BGND V3B V3BGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 V4BGND 1 60 DB15 V4B 2 59 DB14 V5BGND 3 58 DB13 V5B 4 57 DB12 AGND 5 VCC 6 56 DB11 55 DB10 54 DB9 V6B 7 V6BGND 8 AD7616-P 53 DB8 V7B 9 TOP VIEW (Not to Scale) 52 REGCAPD V7BGND 10 51 REGGNDD 50 DGND V7AGND 11 49 VDRIVE V7A 12 V6AGND 13 48 DB7 V6A 14 VCC 15 47 DB6 AGND 16 45 DB4 V5A 17 44 DB3 V5AGND 18 43 DB2 V4A 19 42 DB1 V4AGND 20 41 DB0 46 DB5 DIGITAL INPUT DECOUPLING CAP PIN REFERENCE INPUT/OUTPUT POWER SUPPLY DIGITAL INPUT/OUTPUT GROUND PIN DIGITAL OUTPUT PAR 15695-006 ANALOG INPUT HW_RNGSEL0 HW_RNGSEL1 SEQEN RESET REFSEL REFINOUTGND REFINOUT REFCAP REFGND VCC AGND V0A V0AGND V1A V1AGND V2A V2AGND V3A V3AGND 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 6. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5, 16, 29, 72 6, 15, 30, 71 Type1 AI GND AI AI GND AI P P Mnemonic2 V4BGND V4B V5BGND V5B AGND VCC 7 8 9 10 11 12 13 14 17 18 19 20 AI AI GND AI AI GND AI GND AI AI GND AI AI AI GND AI AI GND V6B V6BGND V7B V7BGND V7AGND V7A V6AGND V6A V5A V5AGND V4A V4AGND Description Analog Input Ground for V4B. Analog Input Channel 4, ADC B. Analog Input Ground for V5B. Analog Input Channel 5, ADC B. Analog Supply Ground. Analog Supply Voltage, 4.7 V to 5.25 V. This supply voltage is applied to the internal front-end amplifiers and to the ADC core. Decouple these pins to AGND using 0.1 µF and 10 µF capacitors in parallel. Analog Input Channel 6, ADC B. Analog Input Ground for V6B. Analog Input Channel 7, ADC B. Analog Input Ground for V7B. Analog Input Ground for V7A. Analog Input Channel 7, ADC A. Analog Input Ground for V6A. Analog Input Channel 6, ADC A. Analog Input Channel 5, ADC A. Analog Input Ground for V5A. Analog Input V4A. Analog Input Ground for V4A. Rev. 0 | Page 10 of 46 Data Sheet AD7616-P Pin No. 21 22 23 24 25 26 27 28 31 Type1 AI GND AI AI GND AI AI GND AI AI GND AI CAP Mnemonic2 V3AGND V3A V2AGND V2A V1AGND V1A V0AGND V0A REFCAP 32 33 GND REF REFGND REFINOUT 34 35 GND DI REFINOUTGND REFSEL 36 DI RESET 37 DI SEQEN 38, 39 DI HW_RNGSEL1, HW_RNGSEL0 40 DI PAR 41 to 48 DO/DI DB0 to DB7 49 P VDRIVE 50 GND DGND 51 52 GND CAP REGGNDD REGCAPD Description Analog Input Ground for V3A. Analog Input Channel 3, ADC A. Analog Input Ground for V2A. Analog Input Channel 2, ADC A. Analog Input Ground for V1A. Analog Input Channel 1, ADC A. Analog Input Ground for V0A. Analog Input Channel 0, ADC A. Reference Buffer Output Force/Sense. Decouple this pin to REFGND using a low effective series resistance (ESR), 10 µF, X5R ceramic capacitor, as close to the REFCAP pin as possible. The voltage on this pin is typically 4.096 V. Reference Ground. Connect this pin to AGND. Reference Input/Reference Output. The on-chip voltage reference of 2.5 V is available on this pin for external use when the REFSEL pin is set to logic high. Alternatively, the internal reference can be disabled by setting the REFSEL pin to logic low, and an external reference of 2.5 V can be applied to this input. Decoupling is required on this pin for both the internal and external reference options. Connect a 100 nF, X7R capacitor between the REFINOUT and REFINOUTGND pins, as close to the REFINOUT pin as possible. If using an external reference, connect a 10 kΩ series resistor to this pin to band limit the reference signal. Reference Input, Reference Output Ground. Internal/External Reference Selection Input. REFSEL is a logic input. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFINOUT pin. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. Reset Input. Connect a 100 pF capacitor between RESET and ground. Full and partial reset options are available. The type of reset is determined by the length of the RESET pulse. Keeping RESET low places the device into shutdown mode. See the Reset Functionality section for further details. Channel Sequencer Enable Input (Hardware Mode Only). When SEQEN is tied low, the sequencer is disabled. When SEQEN is high, the sequencer is enabled (with restricted functionality in hardware mode). See the Sequencer section for further details. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. In software mode, this pin must be connected to DGND. Hardware/Software Mode Selection, Hardware Mode Range Select Inputs. Hardware/software mode selection is latched at full reset. Range selection in hardware mode is not latched. HW_RNGSELx = 00: software mode; the AD7616-P is configured via the software registers. HW_RNGSELx = 01: hardware mode; analog input range is ±2.5 V. HW_RNGSELx = 10: hardware mode; analog input range is ±5 V. HW_RNGSELx = 11: hardware mode; analog input range is ±10 V. Parallel Interface Selection Input. PAR is a logic input. This pin must be tied to a logic low state on power-up or before the release of a full reset. PAR = 0: parallel interface selected. PAR = 1: invalid. Parallel Output/Input Data Bit 0 to Data Bit 7. These pins are output/input parallel data bits, DB7 to DB0. Refer to the Parallel Interface section for further details. Logic Power Supply Input. The voltage supplied at this pin (2.3 V to 3.6 V) determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface. Decouple this pin with 0.1 µF and 10 µF capacitors in parallel. Digital Ground. This pin is the ground reference point for all digital circuitry on the AD7616-P. The DGND pin must connect to the DGND plane of a system. Ground for the Digital Low Dropout (LDO) Regulator Connected to REGCAPD (Pin 52). Decoupling Capacitor Pin for Voltage Output from the Internal Digital Regulator. Decouple this output pin separately to REGGNDD using a 10 μF capacitor. The voltage at this pin is 1.89 V typical. Rev. 0 | Page 11 of 46 AD7616-P Data Sheet Pin No. 53 to 60 Type1 DO/DI Mnemonic2 DB8 to DB15 61 DI WR/BURST 62 DI RD 63 DI CS 64 to 66 DI CHSEL0 to CHSEL2 67 DO BUSY 68 DI CONVST 69 70 GND CAP REGGND REGCAP 73 74 75 76 77 78 79 80 AI AI GND AI AI GND AI AI GND AI AI GND V0B V0BGND V1B V1BGND V2B V2BGND V3B V3BGND 1 2 Description Parallel Output/Input Data Bit 8 to Data Bit 15. These pins act as three-state parallel digital input/outputs. Refer to the Parallel Interface section for further details. Write/Burst Mode Enable. In software mode, this pin acts as WR for register write commands. In hardware mode, this pin enables burst mode. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. Refer to the Burst Sequencer section for further information. Parallel Data Read Control Input. When both CS and RD are logic low in parallel mode, the output bus is enabled. Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low, the DBx output bus is enabled and the conversion result is output on the parallel data bus lines. Channel Selection Input 0 to Input 2 (Hardware Mode Only). In hardware mode, these inputs select the input channels for the next conversion in ADC A and ADC B. For example, CHSELx = 0x000 selects V0A and V0B for the next conversion; CHSELx = 0x001 selects V1A and V1B for the next conversion. Busy Output. This pin transitions to a logic high after a CONVST rising edge and indicates that the conversion process started. The BUSY output remains high until the conversion process for the current selected channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and is available to read. Data must be read after BUSY returns to low. Rising edges on CONVST have no effect while the BUSY signal is high. Conversion Start Input for ADC A and ADC B. This logic input initiates conversions on the analog input channels. A conversion is initiated when CONVST transitions from low to high for the selected analog input pair. When burst mode and oversampling mode are disabled, every CONVST transition from low to high converts one channel pair. In sequencer mode, when burst mode or oversampling is enabled, a single CONVST transition from low to high is necessary to perform the required number of conversions. Internal Analog Regulator Ground. This pin must connect to the AGND plane of a system. Decoupling Capacitor Pin for Voltage Output from Internal Analog Regulator. Decouple this output pin separately to REGGND using a 10 μF capacitor. The voltage at this pin is 1.87 V typical. Analog Input Channel 0, ADC B. Analog Input Ground for V0B. Analog Input Channel 1, ADC B. Analog Input Ground for V1B. Analog Input Channel 2, ADC B. Analog Input Ground for V2B. Analog Input Channel 3, ADC B. Analog Input Ground for V3B. AI is analog input, GND is ground, P is power supply, CAP is decoupling capacitor pin, REF is reference input/output, DI is digital input, and DO is digital output. Note that throughout this data sheet, multifunction pins, such as WR/BURST, are referred to either by the entire pin name or by a single function of the pin, for example, WR, when only that function is relevant. Rev. 0 | Page 12 of 46 Data Sheet AD7616-P TYPICAL PERFORMANCE CHARACTERISTICS VREF = 2.5 V internal, VCC = 5 V, VDRIVE = 3.3 V, fSAMPLE = 1 MSPS, fIN = 1 kHz TA = 25°C, unless otherwise noted. 100 0 SNR = 90.44dB SINAD = 90.25dB THD = –103.41dB N SAMPLES = 65536 –20 ±10V RANGE ±5V RANGE ±2.5V RANGE 98 96 –40 SNR (dB) MAGNITUDE (dB) 94 –60 –80 –100 92 90 88 86 –120 84 –140 20 40 60 80 100 FREQUENCY (kHz) 80 –40 15695-007 0 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 7. Fast Fourier Transform (FFT), ±10 V Range 15695-010 82 –160 Figure 10. SNR vs. Temperature 0 100 SNR = 89.59dB SINAD = 89.39dB THD = –102.36dB N SAMPLES = 65536 –20 ±10V RANGE ±5V RANGE ±2.5V RANGE 98 96 –40 SINAD (dB) MAGNITUDE (dB) 94 –60 –80 –100 92 90 88 86 –120 84 –140 20 40 80 60 100 FREQUENCY (kHz) 80 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 8. FFT, ±5 V Range 15695-011 0 15695-008 –160 82 Figure 11. SINAD vs. Temperature 0 –60 ±10V RANGE ±5V RANGE ±2.5V RANGE SNR = 90.6dB SINAD = 90.65dB THD = –107.4dB N SAMPLES = 65536 –20 –70 –80 THD (dB) –60 –80 –90 –100 –100 –120 –110 –160 0 10 20 30 40 FREQUENCY (kHz) 50 Figure 9. FFT Burst Mode, ±10 V Range RSOURCE MATCHED ON Vxx AND VxxGND INPUTS –120 –40 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) Figure 12. THD vs. Temperature Rev. 0 | Page 13 of 46 110 125 15695-012 –140 15695-009 MAGNITUDE (dB) –40 Data Sheet 2.0 1.5 1.5 1.0 1.0 0.5 0 –0.5 0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 0 10000 20000 30000 40000 50000 60000 CODE –2.0 0 10000 40000 50000 60000 Figure 16. Typical DNL Error, ±5 V Range 2.0 35000 1.5 ±10V RANGE Vxx AND VxxGND SHORTED TOGETHER 65536 SAMPLES 32731 30000 26334 1.0 25000 NUMBER OF HITS 0.5 0 –0.5 20000 15000 10000 –1.0 4140 5000 –1.5 2297 0 10000 20000 30000 40000 50000 60000 CODE 0 15695-014 –2.0 29 32766 5 32767 32768 32769 32770 32771 CODE 15695-017 INL ERROR (LSB) 30000 CODE Figure 13. Typical INL Error, ±10 V Range Figure 17. DC Histogram of Codes at Code Center, ±10 V Range Figure 14. Typical INL Error, ±5 V Range 2.0 35000 1.5 30000 1.0 ±5V RANGE Vxx AND VxxGND SHORTED TOGETHER 65536 SAMPLES NUMBER OF HITS 0.5 0 –0.5 31138 24343 25000 20000 15000 10000 –1.0 6841 5000 –1.5 3021 36 –2.0 0 10000 20000 30000 40000 50000 CODE 60000 15695-015 DNL ERROR (LSB) 20000 Figure 15. Typical DNL Error, ±10 V Range 0 32764 157 32765 32766 32767 32768 32769 CODE Figure 18. DC Histogram of Codes at Code Center, ±5 V Range Rev. 0 | Page 14 of 46 15695-018 –2.0 15695-016 DNL ERROR (LSB) 2.0 15695-013 INL ERROR (LSB) AD7616-P Data Sheet AD7616-P 30000 0.009 ±2.5V RANGE Vxx and VxxGND SHORTED TOGETHER 65536 SAMPLES 27621 25000 0.008 PFS/NFS ERROR (%FS) 20000 18123 15000 13596 10000 0.006 0.005 0.004 NFS ±10V RANGE NFS ±5V RANGE NFS ±2.5V RANGE PFS ±10V RANGE PFS ±5V RANGE PFS ±2.5V RANGE 0.003 0.002 5000 3836 0.001 2022 249 85 2 1 32757 32758 32759 32760 32761 32762 32763 32764 32765 32768 CODE 0 15695-019 0 1 0 40 60 SOURCE RESISTANCE (kΩ) 80 100 Figure 22. PFS/NFS Error vs. Source Resistance Figure 19. DC Histogram of Codes at Code Center, ±2.5 V Range 10 30 ±10V RANGE ±5V RANGE ±2.5V RANGE NFS/PFS ERROR MATCHING (LSB) 9 20 NFS ERROR (LSB) 20 15695-022 NUMBER OF HITS 0.007 10 0 –10 –20 PFS ±10V RANGE NFS ±10V RANGE 8 7 6 5 4 3 2 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 –40 15695-020 –30 –40 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 23. NFS/PFS Error Matching vs. Temperature Figure 20. NFS Error vs. Temperature 10 30 ±10V RANGE ±5V RANGE ±2.5V RANGE BIPOLAR ZERO CODE ERROR (LSB) 8 20 10 0 –10 –20 ±10V RANGE ±5V RANGE ±2.5V RANGE 6 4 2 0 -2 -4 -6 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) 110 125 -10 –40 –25 –10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) Figure 24. Bipolar Zero Code Error vs. Temperature Figure 21. PFS Error vs. Temperature Rev. 0 | Page 15 of 46 125 15695-024 -8 –30 –40 15695-021 PFS ERROR (LSB) –25 15695-023 1 AD7616-P 98 DC INPUT ±10V RANGE 96 7 94 6 92 SNR (dB) 5 4 88 86 NO OS OSR × 2 OSR × 4 OSR × 8 OSR × 16 OSR × 32 84 ±10V RANGE ±5V RANGE ±2.5V RANGE 1 –25 –10 5 82 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 80 100 Figure 25. Bipolar Zero Error Matching vs. Temperature 100k 1k 10k INPUT FREQUENCY (Hz) 15695-028 2 0 –40 Figure 28. SNR vs. Input Frequency for Different Oversampling Rates, ±10 V Range –40 98 ±10V RANGE RSOURCE MATCHED ON Vxx AND VxxGND INPUTS –50 ±5V RANGE 96 0Ω 50Ω 100Ω 1.2kΩ 5.6kΩ 10kΩ 23.7kΩ 47.3kΩ 105kΩ –70 94 92 SNR (dB) –60 THD (dB) 90 3 15695-025 BIPOLAR ZERO ERROR MATCHING (LSB) 8 Data Sheet –80 90 88 86 –90 –100 82 1k 10k INPUT FREQUENCY (Hz) 100k 1k 10k INPUT FREQUENCY (Hz) 100k Figure 29. SNR vs. Input Frequency for Different Oversampling Rates, ±5 V Range Figure 26. THD vs. Input Frequency for Various Source Impedances, ±10 V Range –50 –50 CHANNEL TO CHANNEL ISOLATION (dB) ±5V RANGE RSOURCE MATCHED ON Vxx AND VxxGND INPUTS 0Ω 50Ω 100Ω 1.2kΩ 5.6kΩ 10kΩ 23.7kΩ 47.3kΩ 105kΩ –60 –70 –80 –90 –100 –120 1k 10k INPUT FREQUENCY (Hz) 100k 15695-027 –110 ±10V RANGE ±5V RANGE ±2.5V RANGE –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 0 5000 10000 15000 20000 25000 30000 INTERFERER FREQUENCY (Hz) Figure 30. Channel to Channel Isolation vs. Interferer Frequency Figure 27. THD vs. Input Frequency for Various Source Impedances, ±5 V Range Rev. 0 | Page 16 of 46 15695-030 –40 THD (dB) 80 100 15695-026 –110 15695-029 NO OS OSR × 2 OSR × 4 OSR × 8 OSR × 16 OSR × 32 84 Data Sheet AD7616-P 12 130 ±10V RANGE ±5V RANGE ±2.5V RANGE 120 10 8 PSRR (dB) 100 6 90 80 70 4 60 ±10V RANGE ±5V RANGE ±2.5V RANGE 0 –40 –25 –10 5 20 35 50 65 80 95 50 110 125 TEMPERATURE (°C) 100mV p-p SINE WAVE APPLIED TO VCC SUPPLY 40 0.1 1 1000 0 2.510 ±10V RANGE ±5V RANGE ±2.5V RANGE 4.75V 5V 5.25V –20 2.505 CMRR (dB) –40 2.500 –60 –80 2.495 2.490 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) –120 10 5 +5V INPUT +2.5V INPUT –2.5V INPUT –5V INPUT –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 15695-033 –10V INPUT Figure 33. Analog Input Current vs. Temperature for Various Supply Voltages Rev. 0 | Page 17 of 46 90 80 70 60 50 DYNAMIC 40 STATIC 30 20 10 0 –40 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 Figure 36. Static/Dynamic IVCC Current vs. Temperature 125 15695-036 STATIC/DYNAMIC IVCC CURRENT (mA) +10V INPUT –15 –40 10M 100 10 –10 1M 100k Figure 35. CMRR vs. Ripple Frequency 15 –5 10k RIPPLE FREQUENCY (Hz) Figure 32. Internal Reference Voltage vs. Temperature for Various Supply Voltages 0 1k 100 15695-035 –100 15695-032 INTERNAL REFERENCE VOLTAGE (V) 100 Figure 34. PSRR vs. Ripple Frequency Figure 31. Phase Delay vs. Temperature ANALOG INPUT CURRENT (µA) 10 RIPPLE FREQUENCY (kHz) 15695-034 2 15695-031 PHASE DELAY (µs) 110 Data Sheet 5.0 47 4.5 46 4.0 45 3.5 IVCC CURRENT (mA) 3.0 2.5 2.0 1.5 –10 5 20 35 50 65 80 95 110 125 15695-071 –25 TEMPERATURE (°C) Figure 37. Dynamic VDRIVE Current vs. Temperature 41 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 –10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) 125 15695-070 0.1 –25 38 100 200 300 400 500 600 700 800 900 SAMPLING FREQUENCY (kSPS) Figure 39. IVCC Current vs. Sampling Frequency 1.0 STATIC VDRIVE CURRENT (mA) 42 39 0.5 0 –40 43 40 1.0 0 –40 44 Figure 38. Static VDRIVE Current vs. Temperature Rev. 0 | Page 18 of 46 1000 15695-039 DYNAMIC VDRIVE CURRENT (mA) AD7616-P Data Sheet AD7616-P TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, at ½ LSB below the first code transition; and full scale, at ½ LSB above the last code transition. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. The ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. The theoretical SNR for an ideal N-bit converter with a sine wave input is given by SNR = (6.02N + 1.76) dB where N is the number of bits. Therefore, for a 16-bit converter, the SNR is 98 dB. Bipolar Zero Code Error Bipolar zero code error is the deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 V − ½ LSB. Bipolar Zero Code Error Matching Bipolar zero code error matching is the absolute difference in bipolar zero code error between any two input channels. Positive Full-Scale (PFS) Error PFS error is the deviation of the actual last code transition from the ideal last code transition (10 V − 1½ LSB (9.99954), 5 V − 1½ LSB (4.99977), and 2.5 V − 1½ LSB (2.49989)) after bipolar zero code error is adjusted out. The PFS error includes the contribution from the internal reference buffer. PFS Error Matching PFS error matching is the absolute difference in positive fullscale error between any two input channels. Negative Full-Scale (NFS) Error NFS error is the deviation of the first code transition from the ideal first code transition (−10 V + ½ LSB (−9.99985), −5 V + ½ LSB (−4.99992) and −2.5 V + ½ LSB (−2.49996)) after the bipolar zero code error is adjusted out. The NFS error includes the contribution from the internal reference buffer. NFS Error Matching NFS error matching is the absolute difference in negative fullscale error between any two input channels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the measured ratio of signal to noise and distortion at the output of the ADC. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), including harmonics, but excluding dc. Signal-to-Noise Ratio (SNR) SNR is the measured ratio of signal to noise at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels (dB). Peak Harmonic or Spurious Noise Peak harmonic or spurious noise the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the secondorder terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB). Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. The PSRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the VCC supply of the ADC of frequency, fS. PSRR (dB) = 10log(Pf/PfS) where: Pf is equal to the power at frequency, f, in the ADC output. PfS is equal to the power at frequency, fS, coupled onto the VCC supply. Rev. 0 | Page 19 of 46 AD7616-P Data Sheet AC Common-Mode Rejection Ratio (AC CMRR) AC CMRR is defined as the ratio of the power in the ADC output at frequency, f, to the power of a sine wave applied to the common-mode voltage of Vxx and VxxGND at frequency, fS. AC CMRR (dB) = 10log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between all input channels. It is measured by applying a full-scale sine wave signal, up to 160 kHz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied. Phase Delay Phase delay is a measure of the absolute time delay between when an analog input is sampled by the converter and when the result associated with that sample is available to be read back from the ADC, including delay induced by the analog front end of the device. Phase Delay Drift Phase delay drift is the change in phase delay per unit temperature across the entire operating temperature of the device. Phase Delay Matching Phase delay matching is the maximum phase delay seen between any simultaneously sampled pair. Rev. 0 | Page 20 of 46 Data Sheet AD7616-P THEORY OF OPERATION The AD7616-P can be operated in hardware or software mode by controlling the HW_RNGSELx pins. In hardware mode, the AD7616-P is configured by pin control. In software mode, the AD7616-P is configured by the control registers accessed via the parallel interface. ANALOG INPUT Analog Input Channel Selection The AD7616-P contains dual, simultaneous sampling, 16-bit ADCs. Each ADC has eight analog input channels for a total of 16 analog input channels. Additionally, the AD7616-P has on-chip diagnostic channels to monitor the VCC supply and an on-chip adjustable LDO regulator. Channels can be selected for conversion by using the CHSELx pins in hardware mode or via the channel register control in software mode. Software mode is required to sample the diagnostic channels. Channels can be selected dynamically or the AD7616-P has an on-chip sequencer to allow the channels for conversion to be preprogrammed. In hardware mode, simultaneous sampling is limited to the corresponding ADC A and ADC B analog input channels. For example, Channel V0A is always sampled with Channel V0B. In software mode, it is possible to select any ADC A channel with any ADC B channel for simultaneous sampling. Analog Input Ranges The AD7616-P can handle true bipolar, single-ended input voltages. The logic levels on the range select pins, HW_RNGSEL0 and HW_RNGSEL1, determine the analog input range of all analog input channels. If both range select pins are tied to a logic low, the analog input range is determined in software mode via the input range registers (see the Register Summary section for more details). In software mode, it is possible to configure an individual analog input range per channel. Table 7. Analog Input Range Selection Analog Input Range Configured via the Input Range Registers ±2.5 V ±5 V ±10 V Analog Input Impedance The analog input impedance of the AD7616-P is 1 MΩ, a fixed input impedance that does not vary with the AD7616-P sampling frequency. This high analog input impedance eliminates the need for a driver amplifier in front of the AD7616-P, allowing direct connection to the source or sensor. Analog Input Clamp Protection Figure 40 shows the analog input circuitry of the AD7616-P. Each analog input of the AD7616-P contains clamp protection circuitry. Despite single 5 V supply operation, this analog input clamp protection allows an input overvoltage of between −20 V and +20 V. RFB Vxx VxxGND CLAMP CLAMP 1MΩ 1MΩ FIRSTORDER LPF RFB Figure 40. Analog Input Circuitry Figure 41 shows the input clamp current vs. source voltage characteristic of the clamp circuit. For source voltages between −20 V and +20 V, no current flows in the clamp circuit. For input voltages that are greater than +20 V and less than −20 V, the AD7616-P clamp circuitry turns on. 0.25 0.20 POWERED OFF POWERED ON 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 –30 –20 –10 0 10 SOURCE VOLTAGE (V) HW_RNGSEL1 0 HW_RNGSEL0 0 0 1 1 1 0 1 15695-040 The AD7616-P contains input clamp protection, input signal scaling amplifiers, a first-order antialiasing filter, an on-chip reference, a reference buffer, a dual high speed ADC, a digital filter, a flexible sequencer, and a high speed parallel interface. In hardware mode, a logic change on these pins has an immediate effect on the analog input range; however, there is typically a settling time of approximately 120 µs in addition to the normal acquisition time requirement. The recommended practice is to hardwire the range select pins according to the desired input range for the system signals. 20 30 15695-041 The AD7616-P is a DAS that employs a high speed, low power, charge redistribution, SAR ADC, and allows dual simultaneous sampling of 16 analog input channels. The analog inputs on the AD7616-P can accept true bipolar input signals. Analog input range options include ±10 V, ±5 V, and ±2.5 V. The AD7616-P operates from a single 5 V supply. INPUT CLAMP CURRENT (mA) CONVERTER DETAILS Figure 41. Input Protection Clamp Profile, Input Clamp Current vs. Source Voltage Place a series resistor on the analog input channels to limit the current to ±10 mA for input voltages greater than +20 V and less than −20 V. In an application where there is a series resistance on an analog input, VxA or VxB, a corresponding resistance is required on the analog input ground channel, VxAGND or VxBGND (see Figure 42). If there is no corresponding resistor on Rev. 0 | Page 21 of 46 AD7616-P Data Sheet the VxAGND or VxBGND channel, an offset error occurs on that channel. Use the input overvoltage clamp protection circuitry to protect the AD7616-P against transient overvoltage events. It is not recommended to leave the AD7616-P in a condition where the clamp protection circuitry is active in normal or power-down conditions for extended periods. Vxx CLAMP R C VxxGND CLAMP RFB 1MΩ 1MΩ RFB 011...111 011...110 ADC CODE Figure 42. Input Resistance Matching on the Analog Input Analog Input Antialiasing Filter An analog antialiasing filter (first-order Butterworth) is also provided on the AD7616-P. Figure 43 and Figure 44 show the frequency and phase response, respectively, of the analog antialiasing filter. The typical corner frequency in the ±10 V range is 39 kHz, and 33 kHz in the ±5 V range. 5 000...001 000...000 111...111 LSB = +FS – (–FS) 2N* 100...010 100...001 100...000 –FS + 1/2LSB 0V – 1/2LSB +FS – 3/2LSB ANALOG INPUT +FS ±10V RANGE +10V ±5V RANGE +5V ±2.5V RANGE +2.5V ±10V RANGE ±5V RANGE ±2.5V RANGE 0 VIN 2.5V × 32,768 × REFINOUT 10V VIN 2.5V ±5V CODE = × 32,768 × REFINOUT 5V VIN 2.5V ±2.5V CODE = × 32,768 × REFINOUT 2.5V ±10V CODE = 15695-042 R The output coding of the AD7616-P is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is full-scale range ÷ 65,536 for the AD7616-P. The ideal transfer characteristics for the AD7616-P are shown in Figure 45. The LSB size is dependent on the analog input range selected. MIDSCALE 0V 0V 0V –FS –10V –5V –2.5V LSB 305µV 152µV 76µV ATTENUATION (dB) *WHERE N IS THE NUMBER OF BITS OF THE CONVERTER –5 Figure 45. Transfer Characteristics INTERNAL/EXTERNAL REFERENCE –10 –15 –20 –30 100 1k 10k 100k INPUT FREQUENCY (Hz) 15695-043 –25 Figure 43. Analog Antialiasing Filter Frequency Response ±10V RANGE ±5V RANGE ±2.5V RANGE 5 4 The internal reference buffer is always enabled. After a full reset, the AD7616-P operates in the reference mode selected by the REFSEL pin. Decoupling is required on the REFINOUT pin for both the internal and external reference options. A 100 nF, X8R ceramic capacitor is required on the REFINOUT pin to REFINOUTGND. 3 2 1 100 1k 10k 100k INPUT FREQUENCY (Hz) Figure 44. Analog Antialiasing Filter Phase Response 15695-044 PHASE (µs) The AD7616-P can operate with either an internal or external reference. The device contains an on-chip, 2.5 V band gap reference. The REFINOUT pin allows access to the 2.5 V reference that generates the on-chip 4.096 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7616-P. An externally applied reference of 2.5 V is also amplified to 4.096 V using the internal buffer. This 4.096 V buffered reference is the reference used by the SAR ADC. The REFSEL pin is a logic input pin that allows the user to select between the internal reference and an external reference. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFINOUT pin. 6 0 15695-045 AD7616-P ANALOG INPUT SIGNAL ADC TRANSFER FUNCTION The AD7616-P contains a reference buffer configured to amplify the reference voltage to ~4.096 V. A 10 μF, X5R ceramic capacitor is required between REFCAP and REFGND. The reference voltage available at the REFINOUT pin is 2.5 V. When the AD7616-P is configured in external reference mode, the REFINOUT pin is a high input impedance pin. Rev. 0 | Page 22 of 46 Data Sheet AD7616-P REFCAP BUF REFSEL REFINOUTGND REFINOUTGND 15695-046 10µF 2.5V REF 100nF Figure 46. Reference Circuitry SHUTDOWN MODE The AD7616-P enters shutdown mode by keeping the RESET pin low for greater than 1.2 µs. When the RESET pin is set from low to high, the device exits shutdown mode and enters normal mode. When the AD7616-P is placed in shutdown mode, the current consumption is typically 78 µA and the power-up time to perform a write to the device is approximately 240 µs. The power-up time to perform a conversion is 15 ms. In shutdown mode, all circuitry is powered down and all registers are cleared and reset to their default values. DIGITAL FILTER The AD7616-P contains an optional digital, first-order sinc filter for use in applications where slower throughput rates are in use or where higher SNR or dynamic range is desirable. If oversampling is enabled with the sequencer or in burst mode, the extra samples are gathered for a given channel before the sequencer moves on to the next channel. Table 8 shows the typical SNR performance of the device for each permissible OSR. The input tone used is a 100 Hz sine wave for the three input ranges of the device. A plot of SNR vs. OSR is shown in Figure 47. 97 96 95 94 93 92 91 90 The OSR of the digital filter is controlled in software via the OS bits in the configuration register. In software mode, oversampling is enabled for all channels after the OS bits are set in the configuration register. ±2.5V RANGE ±5V RANGE ±10V RANGE 89 88 fIN = 100Hz 87 0 20 40 60 80 100 120 OSR Table 8 provides the oversampling bit decoding to select the different oversample rates. In addition to the oversampling function, the output result is decimated to 16-bit resolution. Figure 47. Typical SNR vs. OSR for All Analog Input Ranges Table 8. Oversampling Bit Decoding OS Bits 000 001 010 011 100 101 110 111 OSR No oversampling 2 4 8 16 32 64 128 ±2.5 V Range 87.5 88.1 89 89.9 91 92.6 93.9 94.4 Typical SNR (dB) ±5 V Range 89.7 90.6 91.6 92.6 93.6 94.8 95.5 95.4 Rev. 0 | Page 23 of 46 ±10 V Range 90.8 91.8 92.9 93.9 94.9 95.8 96.2 95.9 −3 dB Bandwidth (kHz), All Ranges 37 36.5 35 30.5 22 13.2 7.2 3.6 15695-047 REFINOUT If the OS bits are set to select an OSR of eight, the next CONVST rising edge takes the first sample for the selected channel, and the remaining seven samples for that channel are taken with an internally generated sampling signal. These samples are then averaged to yield an improvement in SNR performance. As the OS ratio increases, the −3 dB frequency is reduced, and the allowed sampling frequency is also reduced. The conversion time extends as the oversampling rate is increased, and the BUSY signal scales with oversampling rates. Acquisition and conversion time increase linearly with the OSR. SNR (dB) If the internal reference is to be applied elsewhere within the system, it must first be buffered externally. AD7616-P Data Sheet APPLICATIONS INFORMATION FUNCTIONALITY OVERVIEW POWER SUPPLIES The AD7616-P has two main modes of operation: hardware mode and software mode. Depending on the mode of operation, certain functionality may not be available. Full functionality is available in software mode; restricted functionality is available in hardware mode. Table 9 shows the functionality available in the different modes of operation. The AD7616-P has two independent power supplies, VCC and VDRIVE, that supply the analog circuitry and digital interface, respectively. Decouple both the VCC supply and the VDRIVE supply with a 10 µF capacitor in parallel with a 100 nF capacitor. Additionally, these supplies are regulated by two internal LDO regulators. The analog LDO (ALDO) typically supplies 1.87 V. Decouple the ALDO with a 10 µF capacitor between the REGCAP and REGGND pins. The digital LDO (DLDO) typically supplies 1.89 V. Decouple the DLDO with a 10 µF capacitor between the REGCAPD and REGGNDD pins. Table 9. Available Functionality Functionality Internal/External Reference Selectable Analog Input Ranges Individual Channel Configuration Common Channel Configuration Sequential Sequencer Fully Configurable Sequencer Burst Mode On-Chip Oversampling Cyclic redundancy check (CRC) Diagnostic Channel Conversion Hardware Reset Register Access Yes No No Yes Yes Yes Yes No Yes Yes Yes Yes No No Yes No Yes Yes Yes No The AD7616-P is robust to power supply sequencing. The recommended sequence is to power up VDRIVE first, followed by VCC. Hold RESET low until both supplies are stabilized. TYPICAL CONNECTIONS Figure 48 shows the typical connections required for correct operation of the AD7616-P. Decouple the VCC and VDRIVE supplies as shown in Figure 48. Place the smaller, 0.1 µF capacitor as close to the supply pin as possible, with the larger, 10 µF bulk capacitor in parallel. Decouple the reference and LDO regulators as shown in Figure 48 and as described in Table 6. The analog input pins require a matched resistance, R, on both the VxA and VxAGND (similarly, VxB and VxBGND) inputs to avoid a gain error on the analog input channels caused by an impedance mismatch. Yes means available; no means not available. 5V 10µF 2.5V/3.3V 0.1µF 0.1µF VCC REGCAP ALDO 10µF 10µF VDRIVE REGCAPD DLDO 10µF AD7616-P REGGND REGGNDD VxA R C VxAGND PGA MUX ADC PGA MUX ADC R VxB R C VxBGND R REFINOUT REFCAP BUF 0.1µF X8R 10µF X5R 2.5V REF REFINOUTGND REFGND Figure 48. Typical External Connections Rev. 0 | Page 24 of 46 15695-048 1 Operation Mode1 Software Mode Hardware Mode (HW_RNGSELx = 00) (HW_RNGSELx ≠ 00) Yes Yes Data Sheet AD7616-P DEVICE CONFIGURATION OPERATIONAL MODE The mode of operation, hardware mode or software mode, is configured when the AD7616-P is released from full reset. The logic level of the HW_RNGSELx pins when the RESET pin transitions from low to high determines the operational mode. The HW_RNGSELx pins are dual function. If HW_RNGSELx = 0b00, the AD7616-P enters software mode. Any other combination of the HW_RNGSELx configures the AD7616-P to hardware mode and the analog input range is configured as per Table 7. After software mode is configured, the logic level of the HW_RNGSELx signals is ignored. After an operational mode is configured, a full reset via the RESET pin is required to exit the operational mode and to set up an alternative mode. If hardware mode is selected, all further device configuration is via pin control. Access to the on-chip registers is prohibited in hardware mode. In software mode, the interface and reference configuration must be configured via pin control, but all further device configuration is via register access only. INTERNAL/EXTERNAL REFERENCE The internal reference is enabled or disabled when the AD7616-P is released from a full reset. The logic level of the REFSEL signal when the RESET pin transitions from low to high configures the reference. After the reference is configured, changes to the logic level of the REFSEL signal are ignored. If the REFSEL signal is set to 1, the internal reference is enabled. If REFSEL is set to Logic 0, the internal reference is disabled and an external reference must be supplied to the REFINOUT pin for correct operation of the AD7616-P. A full reset via the RESET pin is required to exit the operational mode and set up an alternative mode. Connect a 100 nF capacitor between the REFINOUT and REFINOUTGND pins. If using an external reference, place a 10 kΩ band limiting resistor in series between the reference and the REFINOUT pin of the AD7616-P. HARDWARE MODE If hardware mode is selected, the available functionality is restricted and all functionality is configured via pin control. The logic level of the following signals is checked after a full reset to configure the functionality of the AD7616-P: CRC, BURST, and SEQEN. Table 10 provides a summary of the signals that are latched by the device on the release of a full reset, depending on the mode of operation chosen. After the device is configured, a full reset via the RESET pin is required to exit the configuration and set up an alternative configuration. The CHSELx pins are read at reset to determine the initial analog input channel pair to acquire for conversion or to configure the initial settings for the sequencer. The channel pair selected for conversion or the hardware sequencer can be reconfigured during normal operation by setting and maintaining the CHSELx signal level before the CONVST rising edge until the BUSY falling edge. The HW_RNGSELx signals control the analog input range for all 16 analog input channels. A logic change on these pins has an immediate effect on the analog input range; however, the typical settling time is approximately 120 µs, in addition to the normal acquisition time requirement, tACQ. The recommended practice is to hardwire the range select pins according to the desired input range for the system signals. Access to the on-chip registers is prohibited in hardware mode. Table 10. Summary of Latched Hardware Signals1 Latched at Full Reset Signal REFSEL SEQEN HW_RNGSELx (Range Change) HW_RNGSELx (Hardware (HW) or Software (SW) Mode) PAR BURST CHSELx 1 Read at Reset Read During Busy Edge Driven HW Mode SW Mode HW Mode Yes Yes N/A Yes Yes No N/A Yes N/A N/A Yes N/A N/A N/A Yes N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Yes N/A N/A N/A No N/A Yes Yes N/A Yes No N/A N/A N/A Yes N/A N/A No N/A N/A Yes N/A N/A No N/A N/A N/A N/A N/A N/A Blank cells in Table 10 mean not applicable. Rev. 0 | Page 25 of 46 SW Mode HW Mode SW Mode HW Mode SW Mode AD7616-P Data Sheet SOFTWARE MODE If software mode is selected and the reference is configured, all other configuration settings in the AD7616-P are controlled via the on-chip registers. All functionality of the AD7616-P is available when software mode is selected. Table 10 provides a summary of the signals that are latched by the device on the release of a full reset, depending on the mode of operation chosen. In hardware mode, the CHSELx and HW_RNGSELx pins are read upon release of a full or partial reset to perform the following actions: • RESET FUNCTIONALITY The AD7616-P has two reset modes: full or partial. The reset mode selected is dependent on the length of the reset low pulse. A partial reset requires the RESET pin to be held low between 40 ns and 500 ns. After 120 ns from the release of RESET, the device is fully functional and a conversion can be initiated. A full reset requires the RESET pin to be held low for a minimum of 1.2 µs. After 15 ms from the release of RESET, the device is completely reconfigured and a conversion can be initiated. A partial reset reinitializes the following modules: • • • signals are ignored. In hardware mode, the analog input range (HW_RNGSELx signals) can be configured during a full reset, a partial reset, or during normal operation, but hardware/software mode selection requires a full reset to reconfigure when latched. Sequencer Digital filter Both SAR ADCs • • Determine the initial analog input channel pair to acquire for conversion. Configure the initial settings for the sequencer. Select the analog input voltage range. The CHSELx and HW_RNGSELx signals are not latched. The channel pair selected for conversion, or the hardware sequencer, can be reconfigured during normal operation by setting and maintaining the CHSELx signal level before the CONVST rising edge, and ensuring the signal level remains constant until after BUSY transitions low again. See the Channel Selection section for further details. In software mode, all additional functionality is configured by controlling the on-chip registers. The current conversion result is discarded on completion of a partial reset. The partial reset does not affect the register values programmed in software mode or the latches that store the user configuration in both hardware and software modes. A dummy conversion is required in software mode after a partial reset. PIN FUNCTION OVERVIEW There are several dual-function pins on the AD7616-P. Their functionality is dependent on the mode of operation selected by the HW_RNGSELx pins. Table 11 outlines the pin functionality in the different modes of operation and interface modes. A full reset returns the device to its default power-on state. The following features are configured when the AD7616-P is released from full reset: Table 11. Pin Functionality Overview • • • Pins CHSELx Hardware mode or software mode Internal/external reference Interface type On power-up, the RESET signal can be released as soon as both the VCC and VDRIVE supplies are stable. The logic level of the HW_RNGSELx, REFSEL, and PAR pins when the RESET pin is released after a full reset determines the configuration. If hardware mode is selected, the functionality determined by the BURST and SEQEN signals is also latched when the RESET pin transitions from low to high in full reset mode, as shown in Figure 3. After the functionality is configured, changes to these Operation Mode RD WR/BURST DB15 to DB0 HW_RNGSELx SEQEN REFSEL Rev. 0 | Page 26 of 46 Software (HW_RNGSELx = 00) No function, connect to DGND RD WR DB15 to DB0 HW_RNGSELx, connect to DGND No function, connect to DGND REFSEL Hardware (HW_RNGSELx ≠ 00) CHSELx RD BURST DB15 to DB0 HW_RNGSELx, configure analog input range SEQEN REFSEL Data Sheet AD7616-P DIGITAL INTERFACE CHANNEL SELECTION Software Mode Hardware Mode In software mode, the channels for conversion are selected using the channel register. On power-up or after a reset, the default channels selected for conversion are Analog Input V0A and Analog Input V0B. The logic level of the CHSELx signals determines the channel pair for conversion; see Table 12 for signal decoding information. The CHSELx signals at the time that either full or partial reset is released determine the initial channel pair to sample. After a reset, the logic levels of the CHSELx signals are examined during the BUSY high period to set the channel pair for the next conversion. The CHSELx signal level must be set before CONVST goes from low to high and must be maintained until BUSY goes from high to low to indicate a conversion is complete. See Figure 49 for further details. Table 12. CHSELx Pin Decoding Channel Selection Input Pin CHSEL0 CHSEL1 CHSEL2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Analog Inputs for Conversion V0A, V0B V1A, V1B V2A, V2B V3A, V3B V4A, V4B V5A, V5B V6A, V6B V7A, V7B RESET CONVST BUSY CHX CHY CHZ CH... A/BX DATA BUS INITIAL SETUP CONFIGURE POINT A/BY CONFIGURE POINT A/BZ CONFIGURE POINT 15695-050 CHSEL2 TO CHSEL0 Figure 49. Hardware Mode Channel Conversion Setting RESET CONVST BUSY CS WR DB0 TO DB15 CHX A0 B0 CHY AX BX CHZ CHx CONVERSION START Figure 50. Software Mode Channel Conversion Setting Rev. 0 | Page 27 of 46 AY BY CH 15695-051 RD AD7616-P Data Sheet The parallel interface reads the conversion results and, in software mode, configures/reads back the on-chip registers. Data can be read from the AD7616-P via the parallel data bus with standard CS, RD, and WR signals. Reading Conversion Results The CONVST signal initiates the conversion process. A low to high transition on the CONVST signal initiates a conversion of the selected inputs. The BUSY signal goes high to indicate a conversion is in progress. When the BUSY signal transitions from high to low to indicate that a conversion is complete, it is possible to read back conversion results on the parallel interface. Data can be read from the AD7616-P via the parallel data bus with standard CS and RD signals. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines, DB15 to DB0, leave their high impedance state when both CS and RD are logic low. The rising edge of the CS input signal three-states the bus, and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines; it is the function that allows multiple AD7616-P devices to share the same parallel data bus. The number of required read operations depends on the device configuration. A minimum of two reads are required to read the conversion result for the simultaneously sampled ADC A and ADC B channels. If additional functions such as CRC, status, and burst mode are enabled, the number of required readbacks increases accordingly. The RD pin reads data from the output conversion results register. Applying a sequence of RD pulses to the RD pin of the AD7616-P clocks the conversion results out from each channel onto the parallel bus, DB15 to DB0. The first RD falling edge after BUSY goes low clocks out the conversion result from ADC A. The next RD falling edge updates the bus with the ADC B conversion result. Writing Register Data In software mode, all the read/write registers in the AD7616-P can be written to over the parallel interface. A register write command is performed by a single 16-bit parallel access via the parallel bus (DB15 to DB0), CS, and WR signals. Provide data written to the AD7616-P on the DB15 to DB0 inputs, with DB0 as the LSB of the data-word. The format for a write command is shown in Figure 51. Bit D15 must be set to 1 to select a write command. Bits[D14:D9] contain the register address, REGADDR[5:0]. The subsequent nine bits (Bits[D8:D0]) contain the data to be written to the selected register. See the Register Summary section for the complete list of register addresses. Data is latched into the device on the rising edge of WR. CS WR DB15 TO DB0 WRITE REG 1 WRITE REG 2 Figure 51. Parallel Interface Register Write Reading Register Data All the registers in the device can be read over the parallel interface. A register read is performed by first writing the address of the register to be read to the AD7616-P. The format for a register read command is shown in Figure 53. Bit D15 must be set to 0 to select a read command. Bits[D14:D9] contain the register address. The subsequent nine bits (Bits[D8:D0]) are ignored. The read command is latched into the AD7616-P on the rising edge of WR. This latch transfers the relevant register data to the output register. The register data can then be read on the DB15 to DB0 pins by using a standard read command. See Figure 53 for additional information. CONVST BUSY CS CONV A CONV B Figure 52. Parallel Interface Conversion Readback Rev. 0 | Page 28 of 46 15695-053 RD DB15 TO DB0 15695-052 PARALLEL INTERFACE Data Sheet AD7616-P CS WR DB15 TO DB0 READ REG 1 DATA REG 1 READ REG 2 DATA REG 2 15695-054 RD Figure 53. Parallel Interface Register Read Table 13. Write Command Message Configuration MSB D15 W/R 1 D14 D13 D12 D11 D10 REGADDR[5:0] Register address D9 D8 D7 D6 D5 D4 D3 Data[8:0] Data to write D2 D1 LSB D0 D8 D7 D6 D5 D4 D3 Data[8:0] Do not care D2 D1 LSB D0 Table 14. Read Command Message Configuration MSB D15 W/R 0 D14 D13 D12 D11 D10 REGADDR[5:0] Register address D9 Rev. 0 | Page 29 of 46 AD7616-P Data Sheet SEQUENCER The AD7616-P features a highly configurable on-chip sequencer. The functionality and configuration of the sequencer is dependent on the mode of operation of the AD7616-P. When the sequencer is enabled, the logic levels of the CHSELx pins determine the final channel pair of the sequence. The CHSELx pins at the time RESET is released determine the initial settings for the channels to convert in the sequence. To reconfigure the channels selected for conversion thereafter, set the CHSELx pins to the required setting for the duration of the final BUSY pulse before the current conversion sequence is complete. See Figure 54 for further details. In hardware mode, the sequencer is sequential only. The sequencer always starts converting at Analog Input V0A and Analog Input V0B and converts each subsequent channel up to the configured end channel. In software mode, the sequencer has additional functionality and configurability. The sequencer stack has 32 uniquely configurable sequence steps, allowing any channel order to be programmed. Additionally, any VxA analog input can be paired with any VxB analog input or diagnostic channel. Table 16. CHSELx Pin Decoding Sequencer The sequencer can be operated with or without the burst function enabled. With the burst function enabled, only one CONVST pulse is required to convert every channel in a sequence. With burst mode disabled, one CONVST pulse is required for every conversion step in the sequence. See the Burst Sequencer section for additional details on operating in burst mode. Channel Selection Input Pin CHSEL0 CHSEL1 CHSEL2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 HARDWARE MODE SEQUENCER SOFTWARE MODE SEQUENCER In hardware mode, the sequencer is controlled by the SEQEN pin and the CHSELx pins. The sequencer is enabled or disabled when the AD7616-P is released from full reset. The logic level of the SEQEN pin when the RESET pin is released determines whether the sequencer is enabled or disabled (see Table 15 for settings). After the RESET pin is released, the function is fixed and a full reset via the RESET pin is required to exit the function and set up an alternative configuration. In software mode, the AD7616-P contains a 32-layer fully configurable sequencer stack. Control of the sequencer is achieved by programming the configuration register and sequencer stack registers via the parallel interface. Each stack layer can be individually programmed to pair any input from Analog Input VxA to any input from Analog Input VxB, or any diagnostic channel can be selected for conversion. The sequencer depth can be set to any length from 1 to 32 layers. The sequencer depth is controlled via the SSRENx bit. Set the SSRENx bit in the sequencer stack register corresponding to the last step required. The channels to convert are selected by programming the ASELx and BSELx bits in each sequence stack register for the depth required. Table 15. Hardware Mode Sequencer Configuration SEQEN 0 1 Analog Inputs for Sequential Conversion V0x only V0x to V1x V0x to V2x V0x to V3x V0x to V4x V0x to V5x V0x to V6x V0x to V7x Interface Mode Sequencer disabled Sequencer enabled The sequencer is activated by setting the SEQEN bit in the configuration register to 1. RESET SEQEN CONVST BUSY CHX CHY A/B0 DATA INITIAL SETUP A/BX – 1 CHZ A/BX A/B0 A/BY – 1 CONFIGURE POINT Figure 54. Hardware Mode Sequencer Configuration Rev. 0 | Page 30 of 46 A/BY CONFIGURE POINT A/B0 15695-055 CHSEL0 TO CHSEL2 Data Sheet AD7616-P RESET CONVST BUSY REGISTER SETUP INITIAL SETUP S1 S0 Sn – 1 Sn S0 SEQUENCE START SEQUENCE START DUMMY CONVERSION 15695-056 A/B0 DATA Figure 55. Software Mode Sequencer Configuration To configure and enable the sequencer, it is recommended to complete the following procedure (see Figure 55): 1. 2. 3. 4. 5. 6. Configure the analog input range for the required analog input channels. Program the sequencer stack registers to select the channels for the sequence. Set the SSRENx bit in the last required sequence step. Set the SEQEN bit in the configuration register. Provide a dummy CONVST pulse. Cycle through CONVST pulses and conversion reads to step through each element of the sequencer stack. The sequence automatically restarts from the first element in the sequencer stack with the next CONVST pulse. Following a partial reset, the sequencer pointer is repositioned to the first layer of the stack, but the register programmed values remain unchanged. BURST SEQUENCER Burst mode avoids generating a CONVST pulse for each step in a sequence of conversions. One CONVST pulse converts every step in the sequence. The burst sequencer is an additional feature that works in conjunction with the sequencer. If the burst function is enabled, one CONVST pulse initiates a conversion of all the channels configured in the sequencer. The burst function avoids generating a CONVST pulse for each step in a sequence of conversions, as is the case when the burst function is disabled. Configuration of the burst function varies depending on the mode of operation: hardware or software mode. See the Hardware Mode Burst section and the Software Mode Burst section for specific details on configuring the burst function in each mode. When configured, the burst sequence is initiated at the rising edge of CONVST. The BUSY pin goes high to indicate that a conversion is in progress. The BUSY pin remain highs until all conversions in the sequence are complete. The conversion results are available for readback after the BUSY pin goes low. The number of data reads required to read all the data in the burst sequence is dependent on the length of the sequence configured. The conversion results are presented on the parallel data bus in the same order as the programmed sequence. The throughput rate of the AD7616-P is limited in burst mode and dependent on the length of the sequence. Each channel pair requires an acquisition, conversion, and readback time. The time taken to complete a sequence with number of channel pairs, N, is estimated by tBURST = (tCONV + 25 ns) + (N – 1)(tACQ + tCONV) + N(tRB) where: tCONV is the typical conversion time. tACQ is typical acquisition time. tRB is the time required to read back the conversion results. Hardware Mode Burst Burst mode is enabled in hardware mode by setting the WR/ BURST pin to 1. The SEQEN pin must also be set to 1 to enable the sequencer. In hardware mode, the burst sequencer is controlled by the BURST, SEQEN, and CHSELx pins. The burst sequencer is enabled or disabled when the AD7616-P is released from full reset. The logic level of the SEQEN pin and the BURST pin when the RESET pin is released determines whether the burst sequencer is enabled or disabled. After the RESET pin is released, the burst sequencer function is fixed and a full reset via the RESET pin is required to exit the function and set up an alternative configuration. When the burst sequencer is enabled, the logic levels of the CHSELx pins determine the channels selected for conversion in the burst sequence. The CHSELx pins at the time RESET is released determine the initial settings for the channels to convert in the burst sequence. To reconfigure the channels selected for conversion after a reset, set the CHSELx pins to the required setting for the duration of the next BUSY pulse (see Figure 56 for further details). Software Mode Burst In software mode, the burst function is enabled by setting the BURSTEN bit in the configuration register to 1. This action must be performed when setting the SEQEN bit in the configuration register as outlined in the steps described in the Software Mode Sequencer section to configure the sequencer (see Figure 57 for additional information). Rev. 0 | Page 31 of 46 AD7616-P Data Sheet RESET SEQEN BURST CONVST BUSY CHx CHy CHz A/B0 DATA INITIAL SETUP A/Bx–1 A/Bx CONFIGURE POINT CHz A/By–1 A/B0 CONFIGURE POINT CHz A/By A/B0 A/Bz–1 15695-057 CHSEL2 TO CHSEL0 A/Bz CONFIGURE POINT Figure 56. Burst Sequencer, Hardware Mode RESET CONVST BUSY DATA A/B0 S0 S1 Sn–1 Sn DUMMY CONVERSION Figure 57. Burst Sequencer, Software Mode Rev. 0 | Page 32 of 46 S0 S1 Sn–1 Sn 15695-058 REGISTER SETUP Data Sheet AD7616-P DIAGNOSTICS DIAGNOSTIC CHANNELS 29000 28000 EXPECTED OUTPUT (Codes) 24500 4.75 5.00 5.25 5.50 VCC (V) ((4 × VCC ) – VREF ) × 32,768 Figure 60. ALDO Diagnostic Transfer Function 5 × VREF INTERFACE SELF TEST It is possible to test the integrity of the digital interface by selecting the communication self test channel in the channel register (see the Channel Register section). 10 × VREF 750 Selecting the communication self test for conversion forces the conversion result register to a known fixed output. When the conversion code is read, Code 0xAAAA is output as the conversion code of ADC A, and Code 0x5555 is output as the conversion code of ADC B. 500 250 VCC ERROR 0 CRC ALDO ERROR –250 –500 –750 0 100 200 300 400 500 600 SAMPLING FREQUENCY (kSPS) 15695-059 DEVIATION FROM EXPECTED VALUE (Codes) 25000 22000 4.50 ((10 × VALDO ) – (7 × VREF )) × 32,768 LDO Code = 29000 28000 After being enabled, the CRC result is appended to the conversion result and consists of a 16-bit word, where the first eight bits contain the channel ID of the last channel pair converted and the last eight bits are the CRC result. The result is accessed via an extra read command, as shown in Figure 61. 27000 26000 25000 24500 4.75 5.00 5.25 VCC (V) Figure 59. VCC Diagnostic Transfer Function 5.50 15695-060 23000 22000 4.50 The AD7616-P has a CRC checksum mode to improve interface robustness by detecting errors in data. The CRC feature is available only in software mode. The CRC feature is not available in hardware mode. The CRC result is contained within the status register. Enabling the CRC feature enables the status register and vice versa. The CRC function is enabled by setting either the CRCEN bit or the STATUSEN bit in the configuration register to 1 (see the Configuration Register section). Figure 58. Deviation from Expected Value vs. Sampling Frequency EXPECTED OUTPUT (Codes) 26000 23000 The expected output for each channel is governed by the following transfer functions: VCC Code = 27000 15695-060 In addition to the 16 analog inputs, VxA and VxB, the AD7616-P can also convert the following diagnostic channels: VCC and the analog ALDO voltage. The diagnostic channels are selected for conversion by programming the channel register (see the Channel Register section) to the corresponding channel identifier. Diagnostic channels can also be added to the sequencer stack in software mode, but only provide an accurate reading at throughput rates <250 kSPS. See Figure 58 for a plot of the deviation from the expected value vs. sampling frequency that can be expected when using the diagnostic channels. If the CRC function is enabled, a CRC is calculated on the conversion results for Channel VxA and Channel VxB. The CRC is calculated and transferred on the parallel interface after the conversion results are transmitted, depending on the configuration of the device. The Hamming distance varies relative to the number of bits in the conversion result. For conversions with ≤119 bits, the Hamming distance is 4. For >119 bits, the Hamming distance is 1, that is, 1-bit errors are always detected. Rev. 0 | Page 33 of 46 AD7616-P Data Sheet The following is a pseudocode description of how the CRC is implemented in the AD7616-P: data[2] ^ crc[0] ^ crc[2] ^ crc[4] ^ crc[6] ^ crc[7]; crc = 8’b0; crc_out[5] = data[15] ^ data[13] ^ data[11] ^ data[9] ^ data[5] ^ data[4] ^ data[3] ^ crc[1] ^ crc[3] ^ crc[5] ^ crc[7]; i = 0; x = number of conversion channel pairs; crc_out[6] = data[14] ^ data[12] ^ data[10] ^ data[6] ^ data[5] ^ data[4] ^ crc[2] ^ crc[4] ^ crc[6]; for (i=0, i<x, i++) begin crc1 = crc_out(An,Crc); crc_out[7] = data[15] ^ data[13] ^ data[11] ^ data[7] ^ data[6] ^ data[5] ^ crc[3] ^ crc[5] ^ crc[7]; crc = crc_out(Bn,Crc1); i = i +1; The initial CRC word used by the AD7616-P is an 8-bit word equal to zero. The XOR operation described in the preceding code is executed to calculate each bit of the CRC word for the conversion result, AN. This CRC word (crc1) is then used as the starting point for calculating the CRC word (crc) for the conversion result, BN. The process repeats cyclically for each channel pair converted. end where the function crc_out(data, crc) is crc_out[0] = data[14] ^ data[12] ^ data[8] ^ data[7] ^ data[6] ^ data[0] ^ crc[0] ^ crc[4] ^ crc[6]; crc_out[1] = data[15] ^ data[14] ^ data[13] ^ data[12] ^ data[9] ^ data[6] ^ data[1] ^ data[0] ^ crc[1] ^ crc[4] ^ crc[5] ^ crc[6] ^ crc[7]; Depending on the mode of operation of the AD7616-P, the status register value is appended to the conversion data and read via an extra read command over the parallel interface. The user can then repeat the XOR calculation described in the preceding code for the received conversion results to check whether both CRC words match. See Figure 61 for a description of how the CRC word is appended to the data for each mode of operation. crc_out[2] = data[15] ^ data[13] ^ data[12] ^ data[10] ^ data[8] ^ data[6] ^ data[2] ^ data[1] ^ data[0] ^ crc[0] ^ crc[2] ^ crc[4] ^ crc[5] ^ crc[7]; crc_out[3] = data[14] ^ data[13] ^ data[11] ^ data[9] ^ data[7] ^ data[3] ^ data[2] ^ data[1] ^ crc[1] ^ crc[3] ^ crc[5] ^ crc[6]; crc_out[4] = data[15] ^ data[14] ^ data[12] ^ data[10] ^ data[8] ^ data[4] ^ data[3] ^ CONVST BUSY DATA BURST MODE DATA AX AX BX BX AZ CRCAB(x) BZ CRCAB(X:Z) Figure 61. CRC Readback for All Modes Rev. 0 | Page 34 of 46 15695-062 SEQUENCER/ MANUAL MODE Data Sheet AD7616-P REGISTER SUMMARY The AD7616-P has six read/write registers for configuring the device in software mode, an additional 32 sequencer stack registers for programming the flexible on-chip sequencer, and a read only status register. Table 17 shows an overview of the read/write registers available on the AD7616-P. The status register is an additional read only register that contains information on the channel pair previously converted and the CRC result. Table 17. Register Summary1 Reg. 0x02 Name Configuration register 0x03 Channel register 0x04 0x05 0x06 0x07 0x20 to 0x3F N/A 1 2 Input Range Register A1 Input Range Register A2 Input Range Register B1 Input Range Register B2 Sequencer Stack Registers[0:31] Status register Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 7 Bit 6 Bit 5 SDEF BURSTEN SEQEN Bit 4 Addressing Bit 3 Bit 2 OS Bit 1 STATUSEN Addressing CHB V7A V3B V7B Reset 0x0000 R/W R/W 0x0000 R/W Reserved 0x00FF R/W Reserved 0x00FF R/W Reserved 0x00FF R/W Reserved 0x00FF R/W SSRENx 0x00002 R/W N/A R CHA Addressing V2A Addressing V6A Addressing V2B Addressing V6B Addressing V3A Bit 0 Reserved CRCEN Reserved BSELx V1A V0A V5A V4A VB1 V0B VB5 V4B ASELx A[3:0] B[3:0] CRC[7:0] N/A means not applicable. After a full or partial rest is issued, the sequencer stack register is reinitialized to cycle through Channel V0A and Channel V0B to Channel V7A and Channel V7B. The remaining 24 layers of the stack are reinitialized to 0x0. Rev. 0 | Page 35 of 46 AD7616-P Data Sheet ADDRESSING REGISTERS The seven MSBs written to the device are decoded to determine the register that is addressed. The seven MSBs consist of the register address (REGADDR), Bits[5:0], and the read/write bit. The register address bits determine the on-chip register that is selected. The read/write bit determines whether the remaining nine bits of data on the DBx lines are loaded into the addressed register. If the read/write bit is 1, the bits load into the register addressed by the register select bits. If the read/write bit is 0, the command is seen as a read request. The addressed register data is available to be read during the next read operation. MSB D15 W/R LSB D14 REGADDR[5] D13 REGADDR[4] D12 REGADDR[3] D11 REGADDR[2] D10 REGADDR[1] D9 REGADDR[0] D8 to D0 Data[8:0] Table 18. Bit D15 Mnemonic W/R Description If a 1 is written to this bit, Bits[D8:D0] of this register are written to the register specified by REGADDR[5:0]. Alternatively, if a 0 is written, the next operation is a read from the designated register. D14 REGADDR[5] If a 1 is written to this bit, the contents of REGADDR[4:0] specifies the 32 sequencer stack registers. Alternatively, if a 0 is written to this bit, a register is selected as defined by REGADDR[4:0]. [D13:D9] REGADDR[4:0] When W/R =1, the contents of REGADDR[4:0] determine the register for selection, as follows: 00001: reserved. 00010: selects the configuration register. 00011: selects the channel register. 00100: selects Input Range Register A1. 00101: selects Input Range Register A2. 00110: selects Input Range Register B1. 00111: selects Input Range Register B2. 01000: selects the status register When W/R = 0 and REGADDR[4:0] contains 00000, the conversion codes are read. [D8:D0] Data[8:0] These bits are written into the corresponding register specified by REGADDR[5:0]. See the following sections for detailed descriptions of each register. Rev. 0 | Page 36 of 46 Data Sheet AD7616-P CONFIGURATION REGISTER The configuration register is used in software mode to configure many of the main functions of the ADC, including the sequencer, burst mode, oversampling, and CRC options. Address: 0x02, Reset: 0x0000, Name: Configuration Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:9] Addressing (R/W) [0] CRCEN (R/W) CRC Enable [8] RESERVED [1] STATUSEN (R/W) Status Register Output Enable [7] SDEF (R) Self-Detector Error flag [4:2] OS (R/W) OS ratio sam ples per channel 000: OS1. 001: OS2. 010: OS4. 011: OS8. 100: OS16. 101: OS32. 110: OS64. 111: OS128. [6] BURSTEN (R/W) Burst Mode enable [5] SEQEN (R/W) Channel Sequencer Enable Table 19. Bit Descriptions for the Configuration Register Bits [15:9] Bit Name Addressing 8 7 RESERVED SDEF Settings 0 0 1 6 BURSTEN 0 1 5 SEQEN 0 1 [4:2] OS 000 001 010 011 100 101 110 111 1 STATUSEN 0 1 0 1 CRCEN Description Bits[15:9] define the address of the relevant register. See the Addressing Registers section for further details. Reserved. Self detector error flag. Test passed. The AD7616-P configured itself after power-up. Test failed. An issue was detected during device configuration. A reset is required. Burst mode enable. Burst mode is disabled. Each channel pair to be converted requires a CONVST pulse. A single CONVST pulse converts every channel pair programmed in the 32-layer sequencer stack registers up to and including the layer defined by the SSRENx bit. See the Software Mode Sequencer section and the Software Mode Burst section for further details. Channel sequencer enable. The channel sequencer is disabled. The channel sequencer is enabled. Oversampling (OS) ratio, samples per channel. Oversampling disabled. Oversampling enabled, OSR = 2. Oversampling enabled, OSR = 4. Oversampling enabled, OSR = 8. Oversampling enabled, OSR = 16. Oversampling enabled, OSR = 32. Oversampling enabled, OSR = 64. Oversampling enabled, OSR = 128. Status register output enable. The status register is not read out when reading the conversion result. The status register is read out at the end of all the conversion words (including the self test channel if enabled in sequencer mode) if all the selected channels are read out. The CRC result is included in the last eight bits. CRC enable. The STATUSEN and CRCEN bits have identical functionality. N/A means not applicable. Rev. 0 | Page 37 of 46 Reset1 0x0 Access RW 0x0 N/A R/W R 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW AD7616-P Data Sheet CHANNEL REGISTER Address: 0x03, Reset: 0x0000, Name: Channel Register In software manual mode, the channel register selects the input channel or self test channel for the next conversion. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:9] Addressing (R/W) [3:0] CHA (R/W) Channel Selection bits for ADC A Channels 0: V0A. 1: V1A. 10: V2A. ... 1010: Reserved. 1011: 0XAAAA. 1100: Reserved. [8] RESERVED [7:4] CHB (R/W) Channel Selection bits for ADC B Channels 0: V0B. 1: V1B. 10: V2B. ... 1010: Reserved. 1011: 0x5555. 1100: Reserved. Table 20. Bit Descriptions for the Channel Register Bits [15:9] Bit Name Addressing 8 [7:4] RESERVED CHB Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 [3:0] CHA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Description Bits[15:9] define the address of the relevant register. See the Addressing Registers section for further details. Reserved. Channel selection bits for ADC B channels. V0B. V1B. V2B. V3B. V4B. V5B. V6B. V7B. VCC. ALDO. Reserved. 0x5555. Set the dedicated bits for digital interface communication self test function. When conversion codes are read, Code 0x5555 is output as the conversion code of Channel B. Reserved. Channel selection bits for ADC A Channels. Settings are the same as for ADC B. V0A. V1A. V2A. V3A. V4A. V5A. V6A. V7A. VCC. ALDO. Reserved. 0xAAAA. Set the dedicated bits for digital interface communication self test function. When conversion codes are read, Code 0xAAAA is read out as the conversion code of Channel A. Reserved. Rev. 0 | Page 38 of 46 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W Data Sheet AD7616-P INPUT RANGE REGISTERS Input Range Register A1 and Input Range Register A2 select from one of the three possible input ranges (±10 V, ±5 V, or ±2.5 V) for Analog Input V0A to Analog Input V7A. Input Range Register B1 and Input Range Register B2 select from one of the three possible input ranges (±10 V, ±5 V, or ±2.5 V) for Analog Input V0B to Analog Input V7B. Input Range Register A1 Address: 0x04, Reset: 0x00FF, Name: Input Range Register A1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 [1:0] V0A (R/W) V0A Voltage Range Selection [15:9] ADDRESSING (R/W) [8] RESERVED [3:2] V1A (R/W) V1A Voltage Range Selection [7:6] V3A (R/W) V3A Voltage Range Selection [5:4] V2A (R/W) V2A Voltage Range Selection Table 21. Bit Descriptions for Input Range Register A1 Bits Bit Name [15:9] Description Reset Access Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers section for further details. 0x0 R/W 8 RESERVED Reserved. 0x0 R/W [7:6] V3A V3A voltage range selection. 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W [5:4] [3:2] [1:0] Settings 00 V3A ± 10 V. 01 V3A ± 2.5 V. 10 V3A ± 5 V. 11 V3A ± 10 V. V2A V2A voltage range selection. 00 V2A ± 10 V. 01 V2A ± 2.5 V. 10 V2A ± 5 V. 11 V2A ± 10 V. V1A V1A voltage range selection. 00 V1A ± 10 V. 01 V1A ± 2.5 V. 10 V1A ± 5 V. 11 V1A ± 10 V. V0A V0A voltage range selection. 00 V0A ± 10 V. 01 V0A ± 2.5 V. 10 V0A ± 5 V. 11 V0A ± 10 V. Rev. 0 | Page 39 of 46 AD7616-P Data Sheet Input Range Register A2 Address: 0x05, Reset: 0x00FF, Name: Input Range Register A2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 [15:9] ADDRESSING (R/W) Reserved [1:0] V4A (R/W) V4A Voltage Range Selection [8] RESERVED [3:2] V5A (R/W) V5A Voltage Range Selection [7:6] V7A (R/W) V7A Voltage Range Selection [5:4] V6A (R/W) V6A Voltage Range Selection Table 22. Bit Descriptions for Input Range Register A2 Bits Bit Name [15:9] Description Reset Access Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers section for further details. 0x0 R/W 8 RESERVED Reserved. 0x0 R/W [7:6] V7A V7A voltage range selection. 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W [5:4] [3:2] [1:0] Settings 00 V7A ± 10 V. 01 V7A ± 2.5 V. 10 V7A ± 5 V. 11 V7A ± 10 V. 00 V6A ± 10 V. 01 V6A ± 2.5 V. 10 V6A ± 5 V. 11 V6A ± 10 V. 00 V5A ± 10 V. 01 V5A ± 2.5 V. 10 V5A ± 5 V. 11 V5A ± 10 V. 00 V4A ± 10 V. 01 V4A ± 2.5 V. 10 V4A ± 5 V. 11 V4A ± 10 V. V6A V6A voltage range selection. V5A V5A voltage range selection. V4A V4A voltage range selection. Rev. 0 | Page 40 of 46 Data Sheet AD7616-P Input Range Register B1 Address: 0x06, Reset: 0x00FF, Name: Input Range Register B1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 [15:9] ADDRESSING (R/W) [1:0] V0B (R/W) V0B Voltage Range Selection [8] RESERVED [3:2] V1B (R/W) V1B Voltage Range Selection [7:6] V3B (R/W) V3B Voltage Range Selection [5:4] V2B (R/W) V2B Voltage Range Selection Table 23. Bit Descriptions for Input Range Register B1 Bits Bit Name [15:9] Description Reset Access Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers section for further details. 0x0 R/W 8 RESERVED Reserved. 0x0 R/W [7:6] V3B V3B voltage range selection. 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W [5:4] [3:2] [1:0] Settings 00 V3B ± 10 V. 01 V3B ± 2.5 V. 10 V3B ± 5 V. 11 V3B ± 10 V. V2B V2B voltage range selection. 00 V2B ± 10 V. 01 V2B ± 2.5 V. 10 V2B ± 5 V. 11 V2B ± 10 V. V1B V1B voltage range selection. 00 V1B ± 10 V. 01 V1B ± 2.5 V. 10 V1B ± 5 V. 11 V1B ± 10 V. V0B V0B voltage range selection. 00 V0B ± 10 V. 01 V0B ± 2.5 V. 10 V0B ± 5 V. 11 V0B ± 10 V. Rev. 0 | Page 41 of 46 AD7616-P Data Sheet Input Range Register B2 Address: 0x07, Reset: 0x00FF, Name: Input Range Register B2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 [15:9] ADDRESSING (R/W) [1:0] V4B (R/W) V4B Voltage Range Selection [8] RESERVED [3:2] V5B (R/W) V5B Voltage Range Selection [7:6] V7B (R/W) V7B Voltage Range Selection [5:4] V6B (R/W) V6B Voltage Range Selection Table 24. Bit Descriptions for Input Range Register B2 Bits Bit Name [15:9] Description Reset Access Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers section for further details. 0x0 R/W 8 RESERVED Reserved. 0x0 R/W [7:6] V7B V7B voltage range selection. 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W [5:4] [3:2] [1:0] Settings 00 V7B ± 10 V. 01 V7B ± 2.5 V. 10 V7B ± 5 V. 11 V7B ± 10 V. V6B V6B voltage range selection. 00 V6B ± 10 V. 01 V6B ± 2.5 V. 10 V6B ± 5 V. 11 V6B ± 10 V. V5B V5B voltage range selection. 00 V5B ± 10 V. 01 V5B ± 2.5 V. 10 V5B ± 5 V. 11 V5B ± 10 V. V4B V4B voltage range selection. 00 V4B ± 10 V. 01 V4B ± 2.5 V. 10 V4B ± 5 V. 11 V4B ± 10 V. SEQUENCER STACK REGISTERS Although the channel register defines the next channel for conversion (be it a diagnostic channel or pair of analog input channels), to sample numerous analog input channels, the 32 sequencer stack registers offer a convenient solution. Within the communication register, when the REGADDR5 bit is set to Logic 1, the contents of REGADDR[4:0] specify 1 of the 32 sequencer stack registers. Within each sequencer stack register, the user can define a pair of analog inputs to sample simultaneously. The structure of the sequence forms a stack, in which each row represents two channels to convert simultaneously. The sequence begins with Sequencer Stack Register 1 and cycles through to Sequencer Stack Register 32. If Bit D8 (the enable bit, SSRENx) within a sequencer stack register is set to 1, the sequence ends with the pair of analog inputs defined by that register, then returns to the first sequencer stack register, and resumes the cycle again. Rev. 0 | Page 42 of 46 Data Sheet AD7616-P By default, the first eight layers of the sequencer stack registers are programmed to cycle through Analog Input V0A and Analog Input V0B to Analog Input V7A and Analog Input V7B. After a full or partial reset is issued, the sequencer stack register reinitializes to cycle through Analog Input V0A and Analog Input V0B to Analog Input V7A and Analog Input V7B. The remaining sequencer stack registers are reinitialized to 0x0000. Sequencer Stack Register 0 to Sequencer Stack Register 7 Address: 0x20 to 0x27, Reset: 0x0000, 0x0011, 0x0022, 0x0033, 0x0044, 0x0055, 0x0066, 0x0077, Name: Sequencer Stack Register 0 to Sequencer Stack Register 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:9] ADDRESSING (R/W) [3:0] ASELX (R/W) Channel selection bits for ADC A channels [8] SSRENX (R/W) Defines final layer of stack [7:4] BSELX (R/W) Channel selection bits for ADC B channels Table 25. Bit Descriptions for Sequencer Stack Register 0 to Sequencer Stack Register 7 Bits Bit Name [15:9] Description Reset Access Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers section for further details. 0x0 R/W 8 SSRENx Setting this bit to 0 instructs the ADC to move to the next layer of the sequencer stack after converting the present channel pair. Setting this bit to 1 defines that layer of the sequencer stack as the final layer in the sequence. Thereafter, the sequencer loops back to the first layer of the stack. 0x0 R/W [7:4] BSELx Channel selection bits for ADC B channels. 0x01 R/W 0x01 R/W [3:0] 1 ASELx Settings 0000 V0B. 0001 V1B. 0010 V2B. 0011 V3B. 0100 V4B. 0101 V5B. 0110 V6B. 0111 V7B. 1000 VCC. 1001 ALDO. 1010 Reserved. 1011 Set the dedicated bits for digital interface communication self test function. When the conversion codes is read, Code 0xAAAA is read out as the conversion code of Channel A, and Code 0x5555 is output as the conversion code of Channel B. 1100 Reserved. Channel selection bits for ADC A channels. Settings are the same as for ADC B. By default, the first eight layers of the sequencer stack registers are programmed to cycle through Analog Input V0A and Analog Input V0B to Analog Input V7A and Analog Input V7B. After a full or partial reset is issued, the sequencer stack register reinitializes to cycle through Analog Input V0A and Analog Input V0B to Analog Input V7A and Analog Input V7B. The remaining sequencer stack registers are reinitialized to 0x0000. Rev. 0 | Page 43 of 46 AD7616-P Data Sheet Sequencer Stack Register 8 to Sequencer Stack Register 31 Address: 0x28 to 0x3F, Reset: 0x00, Name: Sequencer Stack Register 8 to Sequencer Stack Register 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:9] ADDRESSING (R/W) [3:0] ASELX (R/W) Channel selection bits for ADC A channels [8] SSRENX (R/W) Defines final layer of stack [7:4] BSELX (R/W) Channel selection bits for ADC B channels Table 26. Bit Descriptions for Sequencer Stack Register 8 to Sequencer Stack Register 31 Bits Bit Name [15:9] Description Reset Access Addressing Bits[15:9] define the address of the relevant register. See the Addressing Registers section for further details. 0x0 R/W 8 SSRENx Setting this bit to 0 instructs the ADC to move to the next layer of the sequencer stack after converting the present channel pair. Setting this bit to 1 defines that layer of the sequencer stack as the final layer in the sequence. Thereafter, the sequencer loops back to the first layer of the stack. 0x0 R/W [7:4] BSELx Channel selection bits for ADC B channels. 0x0 R/W 0x01 R/W [3:0] ASELx Settings 0000 V0B. 0001 V1B. 0010 V2B. 0011 V3B. 0100 V4B. 0101 V5B. 0110 V6B. 0111 V7B. 1000 VCC. 1001 ALDO. 1010 Reserved. 1011 Set the dedicated bits for digital interface communication self test function. When the conversion codes is read, Code 0xAAAA is read out as the conversion code of Channel A, and Code 0x5555 is output as the conversion code of Channel B. 1100 Reserved. Channel selection bits for ADC A channels. Settings are the same as for ADC B. Rev. 0 | Page 44 of 46 Data Sheet AD7616-P STATUS REGISTER The status register is a 16-bit read only register. If the STATUSEN bit or the CRCEN bit is set to Logic 1 in the configuration register, the status register is read out at the end of all conversion words for the selected channels, including the self test channel if enabled in sequencer mode. See the CRC section and Figure 61 for more information. MSB D15 D14 D13 A[3:0] D12 D11 D10 D9 B[3:0] D8 D7 D6 D5 D4 D3 CRC[7:0] D2 D1 LSB D0 Reset1 N/A N/A N/A Access R R R Table 27. Bit Descriptions for Status Register Bits [D15:D12] [D11:D8] [D7:D0] 1 Bit Name A[3:0] B[3:0] CRC[7:0] Settings Description Channel index for previous conversion result on Channel A. Channel index for previous conversion result on Channel B. CRC calculation for the previous conversion result(s). Refer to the CRC section for further details. N/A means not applicable. Rev. 0 | Page 45 of 46 AD7616-P Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.60 MAX 61 80 60 1 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.10 COPLANARITY VIEW A 20 41 40 21 VIEW A 0.65 BSC LEAD PITCH ROTATED 90° CCW 0.38 0.32 0.22 COMPLIANT TO JEDEC STANDARDS MS-026-BEC 051706-A 1.45 1.40 1.35 Figure 62. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7616-PBSTZ AD7616-PBSTZ-RL EVAL-AD7616-PSDZ 1 Junction Temperature Range −40°C to +125°C −40°C to +125°C Package Description 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Z = RoHS Compliant Part. ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15695-0-6/17(0) Rev. 0 | Page 46 of 46 Package Option ST-80-2 ST-80-2