ON NCV7351D10R2G High speed can transceiver Datasheet

NCV7351
High Speed CAN
Transceiver
The NCV7351 CAN transceiver is the interface between a
controller area network (CAN) protocol controller and the physical
bus and may be used in both 12 V and 24 V systems. The transceiver
provides differential transmit capability to the bus and differential
receive capability to the CAN controller.
The NCV7351 is an addition to the CAN high−speed transceiver
family complementing NCV734x CAN stand−alone transceivers and
previous generations such as AMIS42665, AMIS3066x, etc. Due to
the wide common−mode voltage range of the receiver inputs and other
design features, the NCV7351 is able to reach outstanding levels of
electromagnetic susceptibility (EMS). Similarly, extremely low
electromagnetic emission (EME) is achieved by the excellent
matching of the output signals.
KEY FEATURES
General
• Compatible with the ISO 11898−2 Standard
• High Speed (up to 1 Mbps)
• VIO Pin on NCV7351D13 Version Allowing Direct Interfacing with
•
•
•
•
•
•
8
1
SOIC−8
CASE 751AZ
PIN ASSIGNMENT
1
8
2
7
TxD
S
GND
3
VCC
4
1
NCV7351D13R2G
(Top View)
8
TxD
S
2
GND
3
VCC
4
7
CANH
6
CANL
5
NC
RxD
1
NCV7351D10R2G
(Top View)
8
TxD
S
2
GND
VCC
• Automotive
• Industrial Networks
CANL
5
VIO
3
Typical Applications
CANH
6
RxD
4
NCV7351−E
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
1
NV7351− = Specific Device Code
y = 3, 0, or E
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
Quality
• NCV Prefix for Automotive and Other Applications Requiring
NV7351−y
ALYW
G
8
NCV7351−0
•
•
MARKING
DIAGRAM
NCV7351−3
•
3 V to 5 V Microcontrollers
EN Pin on NCV7351D1E Version Allowing Switching the
Transceiver to a Very Low Current OFF Mode
Excellent Electromagnetic Susceptibility (EMS) Level Over Full
Frequency Range. Very Low Electromagnetic Emissions (EME) Low
EME also Without Common Mode (CM) Choke
Bus Pins Protected Against >15 kV System ESD Pulses
Transmit Data (TxD) Dominant Time−out Function
Under all Supply Conditions the Chip Behaves Predictably. No
Disturbance of the Bus Lines with an Unpowered Node
Bus Pins Short Circuit Proof to Supply Voltage and Ground
Bus Pins Protected Against Transients in an Automotive
Environment
Thermal Protection
These are Pb−Free Devices
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CANH
6
CANL
5
EN
RxD
NCV7351D1ER2G
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
October, 2013 − Rev. 0
1
Publication Order Number:
NCV7351/D
NCV7351
Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES
Symbol
Min
Max
Unit
VCC
Power supply voltage
Parameter
Conditions
4.5
5.5
V
VUV
Undervoltage detection voltage
on pin VCC
3.5
4.5
V
VCANH
DC voltage at pin CANH
0 < VCC < 5.5 V; no time limit
−50
+50
V
VCANL
DC voltage at pin CANL
0 < VCC < 5.5 V; no time limit
−50
+50
V
DC voltage between CANH and
CANL pin
0 < VCC < 5.5 V
−50
+50
V
DC voltage at pin CANH and
CANL during load dump
condition
0 < VCC < 5.5 V, less than one second
−
+58
V
VESD
Electrostatic discharge voltage
IEC 61000−4−2 at pins CANH and
CANL
−15
15
kV
VO(dif)(bus_dom)
Differential bus output voltage
in dominant state
45 W < RLT < 65 W
1.5
3
V
CM−range
Input common−mode range for
comparator
Guaranteed differential receiver threshold and leakage current
−30
+35
V
ICC
Supply current
Dominant; VTxD = 0 V
Recessive; VTxD = VCC
−
2.5
72
7.5
mA
ICCS
Supply current in silent mode
1.4
3.5
mA
90
245
ns
−40
150
°C
VCANH,L
VCANH,Lmax
tpd
Propagation delay TxD to RxD
TJ
Junction temperature
See Figure 5
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2
NCV7351
BLOCK DIAGRAM
VIO/NC
VCC
3
5
NCV7351
VIO
1
TxD
7
CANH
6
CANL
Thermal
shutdown
Timer
8
S
Driver
control
Mode control
5
EN(1)
2
4
GND
COMP
RxD
RB20120107
(1) Only present in the NCV7351D1ER2G
(2) Connected to VCC on versions without VIO pin
Figure 1. Block Diagram of NCV7351
Table 2. NCV7351: PIN FUNCTION DESCRIPTION
Pin
Number
Pin
Name
Pin Type
1
TxD
digital input, internal pull−up
2
GND
ground
Ground
3
VCC
supply
Supply voltage
4
RxD
digital output
5
Pin Function
Transmit data input; low input Ù dominant driver
Receive data output; dominant bus Ù low output
NC
not connected
VIO
supply
Not connected, NCV7351−0 version only
EN
digital input, internal pull−down
6
CANL
high voltage input/output
Low−level CAN bus line (low in dominant mode)
7
CANH
high voltage input/output
High−level CAN bus line (high in dominant mode)
8
S
digital input, internal pull−down
Supply voltage for digital inputs/outputs, NCV7351−3 Version only
Enable control input, NCV7351−E version only
Silent mode control input
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NCV7351
APPLICATION INFORMATION
VBAT
5 V−reg
3 V−reg
VCC
VIO
3
5
RLT = 60 W
7
S
Micro
controller
RxD
TxD
.
CANH
8
CAN
BUS
NCV7351
4
6
1
CANL
RLT = 60 W
2
GND
RB20120808
GND
Figure 2. NCV7351−3 Application Diagram
VBAT
5 V−reg
VCC
EN
3
5
RLT = 60 W
7
S
.
CANH
8
Micro
RxD
controller
TxD
CAN
BUS
NCV7351
4
6
1
CANL
RLT = 60 W
2
GND
GND
Figure 3. NCV7351−E Application diagram
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RB20120808
NCV7351
FUNCTIONAL DESCRIPTION
NCV7351−0: Pin 5 is not connected. This version is full
replacement of the previous generation CAN transceiver
AMIS30660.
NCV7351−E: Pin 5 is digital enable pin which allows
transceiver to be switched off with very low supply current.
NCV7351 has three versions which differ from each other
only by function of pin 5. (See also Table 2)
NCV7351−3: Pin 5 is VIO pin, which is supply pin for
transceiver digital inputs/output (supplying pins TxD, RxD,
S, EN). The VIO pin should be connected to microcontroller
supply pin. By using VIO supply pin shared with
microcontroller the I/O levels between microcontroller and
transceiver are properly adjusted. This allows in
applications with microcontroller supply down to 3 V to
easy communicate with the transceiver. (See Figure 2)
OPERATING MODES
The NCV7351 modes of operation are provided as
illustrated in Table 3. These modes are selectable through
pin S and also EN in case of NCV7351−E.
Table 3. OPERATING MODES
Mode
Pin S
Pin EN (Note 1)
Pin TxD
CANH,L Pins
RxD
Normal
0
1
0
Dominant
0
0
1
1
Recessive
1
1
1
X
Recessive
1
1
1
X
Dominant (Note 3)
0
X
0
X
floating
floating
Silent
Off (Note 1)
1. Only applicable to NCV7351−E
2. ‘X’ = don’t care
3. CAN bus driven to dominant by another transceiver on the bus
Normal Mode
circuit is particularly needed in case of the bus line short
circuits.
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give low EME.
TxD Dominant Time−out Function
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value tdom, the transmitter is disabled, driving
the bus into a recessive state. The timer is reset by a positive
edge on pin TxD. This TxD dominant time−out time
(tdom(TxD)) defines the minimum possible bit rate to
12 kbps.
Silent Mode
In the silent mode, the transmitter is disabled. The bus pins
are in recessive state independent of TxD input. Transceiver
listens to the bus and provides data to controller, but
controller is prevented from sending any data to the bus.
Off Mode
In Off mode, complete transceiver is disabled and
consumes very low current. The CAN pins are floating not
loading the CAN bus.
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637;
Figure 4). Internally, pin TxD is pulled high, pin EN and S
low should the input become disconnected. Pins TxD, S, EN
and RxD will be floating, preventing reverse supply should
the VCC supply be removed.
Over−temperature Detection
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 180°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes high. The thermal protection
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NCV7351
Definitions: All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current
is flowing into the pin; sourcing current means the current is flowing out of the pin.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Vsup
Parameter
Conditions
Supply voltage VCC
Min
Max
Unit
−0.3
+6
V
VCANH
DC voltage at pin CANH
0 < VCC < 5.5 V; no time limit
−50
+50
V
VCANL
DC voltage at pin CANL
0 < VCC < 5.5 V; no time limit
−50
+50
V
VIOs
DC voltage at pin TxD, RxD, S, EN, VIO
Notes 4 and 5
−0.3
6
V
Vesd
Electrostatic discharge voltage at all pins
according to EIA−JESD22
Note 6
−6
6
kV
Electrostatic discharge voltage at
CANH,CANL, pins according to
EIA−JESD22
Note 6
−8
8
kV
Electrostatic discharge voltage at CANH,
CANL pins According to IEC 61000−4−2
Note 7
−15
15
kV
750
750
V
−150
100
V
150
mA
Standardized charged device model ESD
pulses according to ESD−STM5.3.1−1999
Vschaff
Latch−up
Transient voltage at CANH, CANL pins,
See Figure 4
Note 8
Static latch−up at all pins
Note 9
Tstg
Storage temperature
−55
+150
°C
TJ
Maximum junction temperature
−40
+170
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. EN pin Only available on NCV7351−E version
5. VIO pin Only available on NCV7351−3 version
6. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
7. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 W resistor
referenced to GND. Verified by external test house
8. Pulses 1, 2a,3a and 3b according to ISO 7637 part 3. Results were verified by external test house.
9. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.
Table 5. THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
Value
Unit
RqJA_1
Thermal Resistance Junction−to−Air, 1S0P PCB (Note 10)
Free air
125
K/W
RqJA_2
Thermal Resistance Junction−to−Air, 2S2P PCB (Note 11)
Free air
75
K/W
10. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
11. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.
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NCV7351
ELECTRICAL CHARACTERISTICS
VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V; TJ = −40°C to +150°C; RLT = 60 W unless specified otherwise.
On chip versions without VIO pin reference voltage for all digital inputs and outputs is VCC instead of VIO.
Table 6. CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−
2.5
50
4.6
72
7.5
mA
1.4
2.3
3.5
mA
−
7
18
mA
−
7
10
mA
3.5
4
4.5
V
2.8
−
5.5
V
100
50
240
125
500
265
mA
−
2
16
mA
2.1
2.4
2.7
V
SUPPLY (Pin VCC)
ICC
Supply current in normal mode
ICCS
Supply current in silent mode
ICCOFF
Supply current in OFF mode on
NCV7351−E version only
ICCOFF
Supply current in OFF mode
NCV7351−E version only
VUVDVCC
Dominant; VTxD = 0 V
Recessive; VTxD = VIO
TJ v 100°C,
Note 13
Undervoltage detection voltage on VCC
pin
SUPPLY (Pin VIO) on NCV7351−3 Version Only
Viorange
Supply voltage range on pin VIO
IIO
Supply current on pin VIO normal mode
Dominant; VTxD = 0 V
Recessive; VTxD = VIO
IIOS
Supply current on pin VIO silent mode
Bus is recessive;
VTxD = VIO
VUVDVIO
Undervoltage detection voltage on VIO
pin
TRANSMITTER DATA INPUT (Pin TxD)
VIH
High−level input voltage, on NCV7351−3
version only
Output recessive
0.7 x
VIO
−
VIO +
0.3
V
VIH
High−level input voltage, on NCV7351−1
and NCV7351−E versions only
Output recessive
2.7
−
VCC +
0.3
V
VIL
Low−level input voltage
Output dominant
−0.3
−
+0.3 x
VIO
V
22
30
50
kW
−
5
10
pF
0.7 x
VIO
−
VIO +
0.3
V
RTxD
Ci
TxD pin pull up
Note 13
Input capacitance
TRANSMITTER MODE SELECT (Pin S and EN)
VIH
High−level input voltage, on NCV7351−3
version only
Silent mode
VIH
High−level input voltage on NCV7351−1
and NCV7351−E versions only
Silent or enable mode
2.7
−
VCC +
0.3
V
VIL
Low−level input voltage
Normal mode
−0.3
−
0.3 x
VIO
V
RS,EN
S and EN pin pull down
Note 12
0.55
1.1
1.5
MW
Input capacitance
Note 13
−
5
10
pF
Ci
RECEIVER DATA OUTPUT (Pin RxD)
IOH
High−level output current
Normal mode
VRxD = VIO – 0.4 V
−1
−0.4
−0.1
mA
IOL
Low−level output current
VRxD = 0.4 V
1.5
6
11
mA
BUS LINES (Pins CANH and CANL)
12. EN pin Only available on NCV7351−E version
13. Not tested in production. Guaranteed by design and prototype evaluation.
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NCV7351
Table 6. CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BUS LINES (Pins CANH and CANL)
Recessive bus voltage on pins CANH
and CANL
VTxD = VIO; no load
normal mode
2.0
2.5
3.0
V
(norm)
Io(reces)
Recessive output current at pin CANH
−30 V < VCANH< +35 V;
0 V < VCC < 5.5 V
−2.5
−
+2.5
mA
Recessive output current at pin CANL
−30 V < VCANL < +35 V;
0 V < VCC < 5.5 V
−2.5
−
+2.5
mA
ILI(CANH)
Input leakage current to pin CANH
−10
0
10
mA
ILI(CANL)
Input leakage current to pin CANL
0 W < R(VCC to GND) < 1 MW
VCANL = VCANH = 5 V
−10
0
10
mA
Vo(dom)
Dominant output voltage at pin CANH
VTxD = 0 V;
VCC = 4.75 V to 5.25 V
3.0
3.6
4.25
V
Dominant output voltage at pin CANL
VTxD = 0 V;
VCC = 4.75 V to 5.25 V
0.5
1.4
1.75
V
Vo(dif)
(bus_dom)
Differential bus output voltage
(VCANH − VCANL)
VTxD = 0 V; dominant;
VCC = 4.75 V to 5.25 V
45 W < RLT < 65 W
1.5
2.25
3.0
V
Vo(dif) (bus_rec)
Differential bus output voltage
(VCANH − VCANL)
VTxD = VIO; recessive;
no load
−120
0
+50
mV
Vo(sym)
(bus_dom)
Bus output voltage symmetry
VCANH + VCANL
VTxD = 0 V
VCC = 4.75 V to 5.25 V
0.9
−
1.1
VCC
Io(sc) (CANH)
Short circuit output current at pin CANH
VCANH = 0 V; VTxD = 0 V
−90
−70
−40
mA
Io(sc) (CANL)
Short circuit output current at pin CANL
VCANL = 36 V; VTxD = 0 V
40
70
100
mA
Differential receiver threshold voltage
−12 V < VCANL < +12 V;
−12 V < VCANH < +12 V;
0.5
0.7
0.9
V
Vihcm(dif) (th)
Differential receiver threshold voltage for
high common−mode
−30 V < VCANL < +35 V;
−30 V < VCANH < +35 V;
0.40
0.7
1.0
V
Ri(cm) (CANH)
Common−mode input resistance at pin
CANH
15
26
37
kW
Ri(cm) (CANL)
Common−mode input resistance at pin
CANL
15
26
37
kW
Ri(cm) (m)
Matching between pin CANH and pin
CANL common mode input resistance
−0.8
0
+0.8
%
25
50
75
kW
Vo(reces)
(CANH)
Io(reces) (CANL)
(CANH)
Vo(dom) (CANL)
Vi(dif) (th)
Ri(dif)
VCANH = VCANL
Differential input resistance
Ci(CANH)
Input capacitance at pin CANH
VTxD = VIO; not tested
−
7.5
20
pF
Ci(CANL)
Input capacitance at pin CANL
VTxD = VIO; not tested
−
7.5
20
pF
Differential input capacitance
VTxD = VIO; not tested
−
3.75
10
pF
160
180
200
°C
Ci(dif)
THERMAL SHUTDOWN
TJ(sd)
Shutdown junction temperature
Junction temperature rising
TIMING CHARACTERISTICS (see Figures 5 and 6)
td(TxD−BUSon)
Delay TxD to bus active
Ci = 100 pF between CANH to
CANL
−
75
−
ns
td(TxD−BUSoff)
Delay TxD to bus inactive
Ci = 100 pF between CANH to
CANL
−
65
−
ns
td(BUSon−RxD)
Delay bus active to RxD
Crxd = 15 pF
−
70
−
ns
td(BUSoff−RxD)
Delay bus inactive to RxD
Crxd = 15 pF
−
70
−
ns
Propagation delay TxD to RxD (both
edges)
Ci = 100 pF between CANH to
CANL
90
140
245
ns
TxD dominant time for time−out
VTxD = 0 V
1.5
2.5
5
ms
tpd
tdom(TxD)
12. EN pin Only available on NCV7351−E version
13. Not tested in production. Guaranteed by design and prototype evaluation.
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NCV7351
MEASUREMENT SETUPS AND DEFINITIONS
+5 V
100 nF
VIO/EN
VCC
3
5
7
TxD
CANH
1 nF
NCV7351
1
Transient
Generator
RxD
4
1 nF
6
CANL
2
8
15 pF
S
RB20120808
GND
Figure 4. Test Circuit for Automotive Transients
+5V
100 nF
VIO/EN
47 uF
5
VCC
3
CANH
7
TxD
100 pF
NCV7351
1
RL
RxD
4
6
CANL
2
88
15 pF
RB20120808
GND
S
Figure 5. Test Circuit for Timing Characteristics
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NCV7351
recessive
TxD
dominant
recessive
50%
50%
CANH
CANL
0.9 V
0.5 V
Vi(dif) = VCANH − VCANL
0.7 x VCC(1)
0.3 x VCC(1)
RxD
td(TxDBUSoff)
td(BUSon−RxD)
td(TxDBUSon)
tpd
td(BUSoff−RxD)
tpd
(1) On NCV7351−3 VCC is replaced by VIO
RB20130429
Figure 6. Transceiver Timing Diagram
DEVICE ORDERING INFORMATION
Part Number
Temperature
Range
Description
NCV7351D13R2G
High Speed CAN Transceiver with
VIO pin
NCV7351D10R2G
High Speed CAN Transceiver with
pin 5 NC
NCV7351D1ER2G
High Speed CAN Transceiver with
EN pin
−40°C to
+125°C
Package
Shipping†
SOIC 150 8 GREEN (Matte
Sn, JEDEC MS−012)
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCV7351
PACKAGE DIMENSIONS
SOIC 8
CASE 751AZ
ISSUE O
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NCV7351
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