MC10EP56, MC100EP56 3.3V / 5V ECL Dual Differential 2:1 Multiplexer Description The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The device features both individual and common select inputs to address both data path and random logic applications. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAMS* 20 MC100EP56 AWLYYWWG SOIC−20 DW SUFFIX CASE 751D 1 Features • 360 ps Typical Propagation Delays • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V TSSOP−20 DT SUFFIX CASE 948R with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V • • • • • • XXXX EP56 ALYWG G with VEE = −3.0 V to −5.5 V Open Input Default State Safety Clamp on Inputs Separate and Common Select Q Output Will Default LOW with Inputs Open or at VEE VBB Outputs These Devices are Pb−Free and are RoHS Compliant 20 1 QFN−20 MN SUFFIX CASE 485E XXXX A WL, L YY, Y WW, W G, G XXXX EP56 ALYWG G = MC10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2014 April, 2014 − Rev. 17 1 Publication Order Number: MC10EP56/D MC10EP56, MC100EP56 Q0 Q0 SEL0 20 19 18 17 1 1 D0a 2 D0a COM_SEL VCC Table 1. PIN DESCRIPTION SEL1 VCC Q1 Q1 VEE 16 15 14 13 12 11 0 1 3 4 VBBO D0b 5 D0b 0 6 7 D1a D1a 8 VBB1 9 D1b 10 D1b PIN FUNCTION D0a* − D1a* ECL Input Data a D0a* − D1a* ECL Input Data a Invert D0b* − D1b* ECL Input Data b D0b* − D1b* ECL Input Data b Invert SEL0* − SEL1* ECL Indiv. Select Input COM_SEL* ECL Common Select Input VBB0, VBB1 Output Reference Voltage Q0 − Q1 ECL True Outputs Q0 − Q1 ECL Inverted Outputs VCC Positive Supply VEE Negative Supply EP Exposed Pad * Pins will default LOW when left open. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Table 2. TRUTH TABLE Figure 1. 20−Lead Package (Top View) and Logic Diagram SEL0 SEL1 COM_SEL Q0, Q0 Q1, Q1 X L L H H X L H H L H L L L L a b b a a a b a a b Exposed Pad D0a 20 19 18 Q0 Q0 17 16 VBB0 1 15 SEL0 D0b 2 14 COM_SEL D0b 3 D1a 4 12 VCC D1a 5 11 Q1 MC10/100EP56 6 NOTE: D0a VCC 7 8 9 13 SEL1 10 VBB1 D1b D1b VEE Q1 The Exposed Pad (EP) on package bottom must be attached to a heat−sinking conduit. The Exposed Pad may only be electrically connected to VEE. Figure 1. QFN−20 Pinout (Top View) http://onsemi.com 2 MC10EP56, MC100EP56 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor Value 75 kW Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC TSSOP QFN Flammability Rating Oxygen Index: 28 to 34 > 2 kV > 150 V > 2 kV Pb Pkg Pb−Free Pkg Level 1 Level 1 N/A Level 3 Level 3 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 140 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 20 TSSOP 20 TSSOP 140 100 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 20 TSSOP 23 to 41 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 20 SOIC 20 SOIC 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 20 SOIC 33 to 35 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−20 QFN−20 47 33 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board QFN−20 18 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free VI VCC VI VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. http://onsemi.com 3 MC10EP56, MC100EP56 Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 61 75 45 63 75 45 65 75 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 3) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV 1690 1460 1755 1490 1815 mV 1990 1855 2055 1915 2115 mV 3.3 2.0 3.3 2.0 3.3 V 150 mA VIL Input LOW Voltage (Single−Ended) 1365 VBB Output Voltage Reference 1790 VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) IIH Input HIGH Current IIL Input LOW Current 1890 2.0 1955 150 −150 2015 150 −150 mA −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 3. All loading with 50 W to VCC − 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 61 75 45 63 75 45 65 75 mA Output HIGH Voltage (Note 6) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 6) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV VBB Output Voltage Reference 3490 3690 3555 3755 3615 3815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current IEE Power Supply Current VOH 3590 2.0 150 −150 3655 150 −150 −150 3715 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 6. All loading with 50 W to VCC − 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC10EP56, MC100EP56 Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 8) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 61 75 45 63 75 45 65 75 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 9) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 9) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV VBB Output Voltage Reference −1510 −1310 −1445 −1245 −1385 −1185 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) 0.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current −1410 VEE+2.0 0.0 −1345 VEE+2.0 0.0 150 −150 −1285 VEE+2.0 150 −150 mA −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. 9. All loading with 50 W to VCC − 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 50 61 75 50 63 77 55 66 80 mA Output HIGH Voltage (Note 12) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 12) 1305 1480 1605 1305 1480 1605 1305 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1305 1675 1305 1675 1305 1675 mV VBB Output Voltage Reference 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 mA IIL Input LOW Current IEE Power Supply Current VOH 1875 2.0 150 −150 1875 150 −150 −150 1875 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 12. All loading with 50 W to VCC − 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 MC10EP56, MC100EP56 Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 50 61 75 50 63 77 55 66 80 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 15) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 15) 3005 3180 3305 3005 3180 3305 3005 3180 3305 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3005 3375 3005 3375 3005 3375 mV VBB Output Voltage Reference 3475 3675 3475 3675 3475 3675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 16) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current 3575 2.0 3575 150 3575 150 −150 −150 mA −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 15. All loading with 50 W to VCC − 2.0 V. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 17) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 50 61 75 50 63 77 55 66 80 mA Output HIGH Voltage (Note 18) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 18) −1995 −1820 −1695 −1995 −1820 −1695 −1995 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1995 −1625 −1995 −1625 −1995 −1625 mV VBB Output Voltage Reference −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) 0.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current IEE Power Supply Current VOH −1425 VEE+2.0 0.0 150 −150 −1425 VEE+2.0 0.0 150 −150 −1425 VEE+2.0 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 W to VCC − 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 6 MC10EP56, MC100EP56 Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20) −40°C Symbol Characteristic Min fmax Maximum Frequency (See Figure 2 Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential 25°C Typ Max Min >3 85°C Typ Max Min >3 Typ Max >3 Unit GHz ps D to Q, Q SEL to Q, Q COM_SEL to Q, Q 250 250 250 340 340 350 450 450 450 270 270 270 360 340 360 470 470 470 300 300 300 400 400 400 500 500 500 tSKEW Within−Device Skew (Note 21) Device to Device Skew 50 100 200 50 100 200 50 100 200 ps tJITTER Random Clock Jitter (See Figure 2 Fmax/JITTER) 0.2 <1 0.2 <1 0.2 <1 ps VPP Input Voltage Swing (Differential Configuration) 150 800 1200 150 800 1200 150 800 1200 mV tr tf Output Rise/Fall Times (20% − 80%) 70 120 170 80 130 180 100 150 230 ps Q, Q NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 21. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 10 9 5V 8 800 7 3.3 V 6 600 5 JITTEROUT ps (RMS) VOUTamplitude (mVpp) 1000 ÉÉ ÉÉ ÉÉ 4 3 400 2 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 1 (JITTER) 200 1.0 0 1.5 2.0 2.5 FREQUENCY (GHz) 3.0 Figure 2. Fmax/Jitter @ 255C Q Zo = 50 W D Receiver Device Driver Device Q Zo = 50 W D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 7 MC10EP56, MC100EP56 ORDERING INFORMATION Package Shipping† MC10EP56DTG TSSOP−20 (Pb−Free) 75 Units / Rail MC10EP56DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel MC10EP56MNG QFN−20 (Pb−Free) 92 Units / Rail MC10EP56MNTXG QFN−20 (Pb−Free) 3000 / Tape & Reel MC100EP56DWG SOIC−20 (Pb−Free) 38 Units / Rail MC100EP56DWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel MC100EP56DTG TSSOP−20 (Pb−Free) 75 Units / Rail MC100EP56DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel MC100EP56MNG QFN−20 (Pb−Free) 92 Units / Rail MC100EP56MNTXG QFN−20 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 8 MC10EP56, MC100EP56 PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE G q A 20 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 9 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC10EP56, MC100EP56 PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B −U− L PIN 1 IDENT SECTION N−N 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING DIM A B C D F G H J J1 K K1 L M PLANE SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC10EP56, MC100EP56 PACKAGE DIMENSIONS QFN20, 4x4, 0.5P CASE 485E ISSUE B A B D PIN ONE REFERENCE 2X 0.15 C ÉÉ ÉÉ ÉÉ ÇÇ ÉÉ EXPOSED Cu E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ÉÉ ÉÉ ÇÇ A3 MOLD CMPD A1 DETAIL B OPTIONAL CONSTRUCTIONS 2X 0.15 C L L TOP VIEW (A3) DETAIL B L1 A 0.10 C DETAIL A OPTIONAL CONSTRUCTIONS 0.08 C A1 SIDE VIEW C MILLIMETERS MIN MAX 0.80 1.00 --0.05 0.20 REF 0.20 0.30 4.00 BSC 2.60 2.90 4.00 BSC 2.60 2.90 0.50 BSC 0.20 REF 0.35 0.45 0.00 0.15 SEATING PLANE SOLDERING FOOTPRINT* 4.30 0.10 C A B 20X 0.58 D2 DETAIL A DIM A A1 A3 b D D2 E E2 e K L L1 20X L 6 2.88 0.10 C A B 11 1 E2 1 2.88 4.30 20 K 20X e b 0.10 C A B 0.05 C PKG OUTLINE NOTE 3 BOTTOM VIEW 20X 0.35 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). 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