M27C160 16 Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM ■ 5V ± 10% SUPPLY VOLTAGE in READ OPERATION ■ ACCESS TIME: 50ns ■ BYTE-WIDE or WORD-WIDE CONFIGURABLE 42 42 ■ 16 Mbit MASK ROM REPLACEMENT 1 ■ LOW POWER CONSUMPTION FDIP42W (F) 1 PDIP42 (B) – Active Current 70mA at 8MHz – Standby Current 100µA ■ PROGRAMMING VOLTAGE: 12.5V ± 0.25V ■ PROGRAMMING TIME: 50µs/word ■ ELECTRONIC SIGNATURE 42 1 – Manufacturer Code: 20h SDIP42 (S) – Device Code: B1h DESCRIPTION The M27C160 is a 16 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage and is organised as either 2 Mbit words of 8 bit or 1 Mbit words of 16 bit. The pin-out is compatible with a 16 Mbit Mask ROM. The FDIP42W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written rapidly to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C160 is offered in PDIP42, SDIP42, PLCC44 and SO44 packages. 44 1 PLCC44 (K) SO44 (M) Figure 1. Logic Diagram VCC 20 Q15A–1 A0-A19 15 Q0-Q14 E M27C160 G BYTEVPP VSS AI00739B January 2002 1/19 M27C160 Figure 2. DIP Connections A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC A5 A6 A7 A17 A18 VSS A19 A8 A9 A10 A11 1 42 2 41 3 40 4 39 5 38 6 37 7 36 35 8 9 34 10 33 M27C160 32 11 31 12 30 13 29 14 28 15 27 16 17 26 18 25 19 24 20 23 22 21 1 44 A4 A3 A2 A1 A0 E 12 M27C160 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A–1 Q7 Q14 Q6 34 VSS G Q0 Q8 Q1 23 Q9 Q2 Q10 Q3 Q11 NC VCC Q4 Q12 Q5 Q13 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 Figure 3. PLCC Connections AI03012 AI00740 Figure 4. SO Connections NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 Table 1. Signal Names 44 1 43 2 3 42 4 41 40 5 39 6 38 7 37 8 36 9 35 10 34 11 M27C160 33 12 32 13 31 14 30 15 29 16 17 28 18 27 19 26 20 25 21 24 22 23 AI01264 2/19 NC A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC A0-A19 Address Inputs Q0-Q7 Data Outputs Q8-Q14 Data Outputs Q15A–1 Data Output / Address Input E Chip Enable G Output Enable BYTEVPP Byte Mode / Program Supply VCC Supply Voltage VSS Ground NC Not Connected Internally M27C160 Table 2. Absolute Maximum Ratings (1) Symbol Value Unit Ambient Operating Temperature (3) –40 to 125 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V –2 to 13.5 V –2 to 14 V TA VCC VA9 (2) Parameter A9 Voltage VPP Program Supply Voltage Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes E G BYTEVPP A9 Q15A–1 Q8-Q14 Q7-Q0 Read Word-wide VIL VIL VIH X Data Out Data Out Data Out Read Byte-wide Upper VIL VIL VIL X VIH Hi-Z Data Out Read Byte-wide Lower VIL VIL VIL X VIL Hi-Z Data Out Output Disable VIL VIH X X Hi-Z Hi-Z Hi-Z VIL Pulse VIH VPP X Data In Data In Data In Verify VIH VIL VPP X Data Out Data Out Data Out Program Inhibit VIH VIH VPP X Hi-Z Hi-Z Hi-Z Standby VIH X X X Hi-Z Hi-Z Hi-Z Electronic Signature VIL VIL VIH VID Code Codes Codes Mode Program Note: X = VIH or VIL, VID = 12V ± 0.5V. Table 4. Electronic Signature Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h Device Code VIH 1 0 1 1 0 0 0 1 B1h Note: Outputs Q15-Q8 are set to '0'. 3/19 M27C160 Table 5. AC Measurement Conditions High Speed Standard Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V 1.5V 0.8V and 2V Input and Output Timing Ref. Voltages Figure 5. AC Testing Input Output Waveform Figure 6. AC Testing Load Circuit 1.3V High Speed 1N914 3V 1.5V 3.3kΩ 0V DEVICE UNDER TEST Standard 2.4V OUT CL 2.0V 0.8V 0.4V AI01822 CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance AI01823B Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol CIN COUT Parameter Test Condition Min Max Unit Input Capacitance (except BYTEVPP) VIN = 0V 10 pF Input Capacitance (BYTEVPP) VIN = 0V 120 pF VOUT = 0V 12 pF Output Capacitance Note: 1. Sampled only, not 100% tested. DEVICE OPERATION The operating modes of the M27C160 are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL compatible except for VPP and 12V on A9 for the Electronic Signature. Read Mode The M27C160 has two organisations, Word-wide and Byte-wide. The organisation is selected by the signal level on the BYTEVPP pin. When BYTEVPP is at VIH the Word-wide organisation is selected and the Q15A–1 pin is used for Q15 Data Output. When the BYTEVPP pin is at VIL the Byte-wide organisation is selected and the Q15A–1 pin is used for the Address Input A–1. When the memory is logically regarded as 16 bit wide, but read in the Byte-wide organisation, then with A–1 at VIL the 4/19 lower 8 bits of the 16 bit data are selected and with A–1 at VIH the upper 8 bits of the 16 bit data are selected. The M27C160 has two control functions, both of which must be logically active in order to obtain data at the outputs. In addition the Word-wide or Byte- wide organisation must be selected. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. M27C160 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC Test Condition Min Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±10 µA E = VIL, G = VIL, IOUT = 0mA, f = 8MHz 70 mA E = VIL, G = VIL, IOUT = 0mA, f = 5MHz 50 mA E = VIH 1 mA E > VCC – 0.2V 100 µA VPP = VCC 10 µA Supply Current ICC1 Supply Current (Standby) TTL ICC2 Supply Current (Standby) CMOS IPP Program Current VIL Input Low Voltage –0.3 0.8 V VIH (2) Input High Voltage 2 VCC + 1 V VOL Output Low Voltage 0.4 V VOH Output High Voltage TTL IOL = 2.1mA IOH = –400µA 2.4 V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V. Standby Mode The M27C160 has a standby mode which reduces the active current from 50mA to 100µA. The M27C160 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the supplies to the devices. The supply current ICC has three segments of importance to the system designer: the standby current, the active current and the transient peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device outputs. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor is used on every device between VCC and VSS. This should be a high frequency type of low inherent inductance and should be placed as close as possible to the device. In addition, a 4.7µF electrolytic capacitor should be used between VCC and VSS for every eight devices. This capacitor should be mounted near the power supply connection point. The purpose of this capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. 5/19 M27C160 Table 8. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) M27C160 Symbol Alt Parameter -50 (3) Test Condition Min -70 (3) Max Min Unit Max Address Valid to Output Valid E = VIL, G = VIL 50 70 ns tST BYTE High to Output Valid E = VIL, G = VIL 50 70 ns tELQV tCE Chip Enable Low to Output Valid G = VIL 50 70 ns tGLQV tOE Output Enable Low to Output Valid E = VIL 30 35 ns tBLQZ (2) tSTD BYTE Low to Output Hi-Z E = VIL, G = VIL 30 30 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 25 0 25 ns tGHQZ (2) tDF Output Enable High to OutputHi-Z E = VIL 0 25 0 25 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 5 5 ns tBLQX tOH BYTE Low to Output Transition E = VIL, G = VIL 5 5 ns tAVQV tACC tBHQV Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed AC measurement conditions. 6/19 M27C160 Table 9. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) M27C160 Symbol Alt Parameter Test Condition -90 Min -100 Max Min -120/-150 Max Min Unit Max Address Valid to Output Valid E = VIL, G = VIL 90 100 120 ns tST BYTE High to Output Valid E = VIL, G = VIL 90 100 120 ns tELQV tCE Chip Enable Low to Output Valid G = VIL 90 100 120 ns tGLQV tOE Output Enable Low to Output Valid E = VIL 45 50 60 ns tBLQZ (2) tSTD BYTE Low to Output Hi-Z E = VIL, G = VIL 30 40 50 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 30 0 40 0 50 ns tGHQZ (2) tDF Output Enable High to OutputHi-Z E = VIL 0 30 0 40 0 50 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 5 5 5 ns tBLQX tOH BYTE Low to Output Transition E = VIL, G = VIL 5 5 5 ns tAVQV tACC tBHQV Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed AC measurement conditions. Figure 7. Word-Wide Read Mode AC Waveforms A0-A19 VALID tAVQV VALID tAXQX E tGLQV tEHQZ G tELQV Q0-Q15 tGHQZ Hi-Z AI00741B Note: BYTEVPP = VIH. 7/19 M27C160 Figure 8. Byte-Wide Read Mode AC Waveforms VALID A–1,A0-A19 VALID tAVQV tAXQX E tEHQZ tGLQV G tGHQZ tELQV Hi-Z Q0-Q7 AI00742B Note: BYTEVPP = VIL. Figure 9. BYTE Transition AC Waveforms VALID A0-A19 VALID A–1 tAVQV tAXQX BYTEVPP tBHQV DATA OUT Q0-Q7 tBLQX Hi-Z Q8-Q15 DATA OUT tBLQZ AI00743C Note: Chip Enable (E) and Output Enable (G) = VIL. 8/19 M27C160 Table 10. Programming Mode DC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.5V ± 0.25V) Symbol Parameter Test Condition Min 0 ≤ VIN ≤ VCC Max Unit ±1 µA 50 mA 50 mA ILI Input Leakage Current ICC Supply Current IPP Program Current VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.4 VCC + 0.5 V VOL Output Low Voltage 0.4 V VOH Output High Voltage TTL VID A9 Voltage E = VIL IOL = 2.1mA IOH = –2.5mA 3.5 V 11.5 12.5 V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Table 11. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.5V ± 0.25V) Symbol Alt Parameter Test Condition Min Max tAVEL tAS Address Valid to Chip Enable Low 2 µs tQVEL tDS Input Valid to Chip Enable Low 2 µs tVPHAV tVPS VPP High to Address Valid 2 µs tVCHAV tVCS VCC High to Address Valid 2 µs tELEH tPW Chip Enable Program Pulse Width 45 tEHQX tDH Chip Enable High to Input Transition 2 µs tQXGL tOES Input Transition to Output Enable Low 2 µs tGLQV tOE Output Enable Low to Output Valid tGHQZ (2) tDFP Output Enable High to Output Hi-Z 0 tGHAX tAH Output Enable High to Address Transition 0 55 Unit µs 120 ns 130 ns ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. Programming When delivered (and after each erasure for UV EPROM), all bits of the M27C160 are in the '1' state. Data is introduced by selectively programming '0's into the desired bit locations. Although only '0's will be programmed, both '1's and '0's can be present in the data word. The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The M27C160 is in the programming mode when VPP input is at 12.5V, G is at VIH and E is pulsed to VIL. The data to be programmed is applied to 16 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V ± 0.25V. 9/19 M27C160 Figure 10. Programming and Verify Modes AC Waveforms A0-A19 VALID tAVEL DATA IN Q0-Q15 DATA OUT tQVEL tEHQX BYTEVPP tVPHAV tGLQV tGHQZ VCC tVCHAV tGHAX E tELEH tQXGL G PROGRAM VERIFY AI00744 Figure 11. Programming Flowchart VCC = 6.25V, VPP = 12.5V n=0 E = 50µs Pulse NO ++n = 25 YES FAIL NO VERIFY ++ Addr YES Last Addr NO YES CHECK ALL WORDS BYTEVPP =VIH 1st: VCC = 6V 2nd: VCC = 4.2V AI01044B 10/19 PRESTO III Programming Algorithm The PRESTO III Programming Algorithm allows the whole array to be programed with a guaranteed margin in a typical time of 52.5 seconds. Programming with PRESTO III consists of applying a sequence of 50µs program pulses to each word until a correct verify occurs (see Figure 11). During programing and verify operation a MARGIN MODE circuit is automatically activated to guarantee that each cell is programed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the necessary margin to each programmed cell. Program Inhibit Programming of multiple M27C160s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27C160 may be common. A TTL low level pulse applied to a M27C160's E input and VPP at 12.5V, will program that M27C160. A high level E input inhibits the other M27C160s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E at VIH and G at VIL, VPP at 12.5V and VCC at 6.25V. M27C160 Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27C160. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27C160, with VPP = VCC = 5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics M27C160, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0. ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27C160 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27C160 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C160 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C160 window to prevent unintentional erasure. The recommended erasure procedure for M27C160 is exposure to short wave ultraviolet light which has a wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 30 W-sec/cm2. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 12000 µW/cm2 power rating. The M27C160 should be placed within 2.5cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure. 11/19 M27C160 Table 12. Ordering Information Scheme Example: M27C160 -70 X M 1 TR Device Type M27 Supply Voltage C = 5V Device Function 160 = 16 Mbit (2mb x 8 or 1Mb x 16) Speed -50(1) = 50 ns -70(1) = 70 ns -90 = 90 ns -100 = 100 ns -120 = 120 ns -150 = 150 ns VCC Tolerance blank = ± 10% X = ± 5% Package F = FDIP42W B = PDIP42 S = SDIP42 K = PLCC44 M = SO44 Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Options TR = Tape & Reel Packing Note: 1. High Speed, see AC Characteristics section for further information. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 12/19 M27C160 Table 13. Revision History Date Version Revision Details January 1999 -01 First Issue 20-Sep-00 -02 AN620 Reference removed 19-Jul-01 -03 SDIP42 package added 17-Jan-02 -04 50ns speed class added, SO44 package mechanical data and drawing clarified 13/19 M27C160 Table 14. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data mm Symbol Typ inches Min Max A Typ Min 5.72 A1 0.51 1.40 0.020 0.055 A2 3.91 4.57 0.154 0.180 A3 3.89 4.50 0.153 0.177 0.41 0.56 0.016 0.022 – – – – 0.23 0.30 0.009 0.012 54.41 54.86 2.142 2.160 – – 2.000 – – – – 0.600 14.50 14.90 B B1 1.45 C D D2 50.80 E 15.24 E1 0.057 – – 0.571 0.587 e 2.54 – – 0.100 – – eA 14.99 – – 0.590 – – 16.18 18.03 0.637 0.710 2.49 0.060 eB L 3.18 S 1.52 0.125 0.098 K 9.40 – – 0.370 – – K1 11.43 – – 0.450 – – α 4° 11° 4° 11° N 42 42 Figure 12. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline A2 A3 A1 B1 B A L e1 α eA D2 C eB D S N K 1 E1 E K1 FDIPW-b Drawing is not to scale. 14/19 Max 0.225 M27C160 Table 15. PDIP42 - 42 pin Plastic Dual In Line, 600 mils width, Package Mechanical Data mm Symbol Typ inches Min Max Typ Min Max A – 5.08 – 0.200 A1 0.25 – 0.010 – A2 3.56 4.06 0.140 0.160 B 0.38 0.53 0.015 0.021 B1 1.27 1.65 0.050 0.065 C 0.20 0.36 0.008 0.014 D 52.20 52.71 2.055 2.075 D2 50.80 – – 2.000 – – E 15.24 – – 0.600 – – E1 13.59 13.84 0.535 0.545 e1 2.54 – – 0.100 – – eA 14.99 – – 0.590 – – 15.24 17.78 0.600 0.700 eB L 3.18 3.43 0.125 0.135 S 0.86 1.37 0.034 0.054 α 0° 10° 0° 10° N 42 42 Figure 13. PDIP42 - 42 pin Plastic Dual In Line, 600 mils width, Package Outline A2 A1 B1 B A L e1 α eA D2 C eB D S N E1 E 1 PDIP Drawing is not to scale. 15/19 M27C160 Table 16. SDIP42 - 42 pin Shrink Plastic DIP, 600 mils width, Package Mechanical Data millimeters inches Symbol Typ Min Max A Typ Min 5.08 A1 0.200 0.51 0.020 A2 3.81 3.05 4.57 0.150 0.120 0.180 b 0.46 0.38 0.56 0.018 0.015 0.022 b2 1.02 0.89 1.14 0.040 0.035 0.045 c 0.25 0.23 0.38 0.010 0.009 0.015 D 36.83 36.58 37.08 1.450 1.440 1.460 e 1.78 – – 0.070 – – 15.24 16.00 0.600 0.630 E E1 13.72 12.70 14.48 0.540 0.500 0.570 eA 15.24 – – 0.600 – – eB 18.54 L 3.30 S 0.64 2.54 0.730 3.56 0.130 0.100 0.025 N 42 42 Figure 14. SDIP42 - 42 pin Shrink Plastic DIP, 600 mils width, Package Outline A2 A1 b2 b A L e eA D2 c eB D S N E1 E 1 SDIP Drawing is not to scale. 16/19 Max 0.140 M27C160 Table 17. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data mm inches Symbol Typ Min Max A 4.20 A1 Min Max 4.70 0.165 0.185 2.29 3.04 0.090 0.120 A2 – 0.51 – 0.020 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 17.40 17.65 0.685 0.695 D1 16.51 16.66 0.650 0.656 D2 14.99 16.00 0.590 0.630 E 17.40 17.65 0.685 0.695 E1 16.51 16.66 0.650 0.656 E2 14.99 16.00 0.590 0.630 – – – – 0.00 0.25 0.000 0.010 – – – – e 1.27 F R 0.89 N Typ 0.050 0.035 44 44 CP 0.10 0.004 Figure 15. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline D D1 A1 A2 1 N B1 E1 E Ne e D2/E2 F B 0.51 (.020) 1.14 (.045) A Nd R CP PLCC Drawing is not to scale. 17/19 M27C160 Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data millimeters Symbol Typ Min inches Max A Typ Min Max 2.80 A1 0.1102 0.10 0.0039 A2 2.30 2.20 2.40 0.0906 0.0866 0.0945 b 0.40 0.35 0.50 0.0157 0.0138 0.0197 C 0.15 0.10 0.20 0.0059 0.0039 0.0079 CP 0.08 0.0030 D 28.20 28.00 28.40 1.1102 1.1024 1.1181 E 13.30 13.20 13.50 0.5236 0.5197 0.5315 e 1.27 – – 0.0500 – – HE 16.00 15.75 16.25 0.6299 0.6201 0.6398 L 0.80 N 0.0315 44 44 α 8° 8° Figure 16. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline A A2 C b e CP D N E 1 EH A1 α L SO-d Drawing is not to scale. 18/19 M27C160 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 19/19