ON MC74VHCT245ADTRG Octal bus transceiver Datasheet

MC74VHCT245A
Octal Bus Transceiver
The MC74VHCT245A is an advanced high speed CMOS octal bus
transceiver fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
It is intended for two−way asynchronous communication between
data buses. The direction of data transmission is determined by the
level of the DIR input. The output enable pin (OE) can be used to
disable the device, so that the buses are effectively isolated.
All inputs are equipped with protection circuits against static
discharge.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT245A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply
voltage−input/output voltage mismatch, battery backup, hot insertion,
etc.
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MARKING
DIAGRAMS
20
1
SOIC−20WB
SUFFIX DW
CASE 751D
•
•
High Speed: tPD = 4.9 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating Range
Low Noise: VOLP = 1.6 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 304 FETs or 76 Equivalent Gates
Pb−Free Packages are Available*
APPLICATION NOTES
• Do not force a signal on an I/O pin when it is an active output,
•
1
20
Features
•
•
•
•
•
•
•
•
•
•
VHCT245A
AWLYYWWG
damage may occur.
All floating (high impedance) input or I/O pins must be fixed by
means of pullup or pulldown resistors or bus terminator ICs.
1
VHCT
245A
ALYWG
G
TSSOP−20
SUFFIX DT
CASE 948E
1
20
1
SOEIAJ−20
SUFFIX M
CASE 967
74VHCT245
AWLYWWG
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 5
1
Publication Order Number:
MC74VHCT245A/D
MC74VHCT245A
A1
A2
A
DATA
PORT
A3
A4
A5
A6
A7
A8
DIR
OE
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
B1
B2
B3
B4
B5
B
DATA
PORT
B6
B7
B8
DIR
1
20
VCC
A1
2
19
OE
A2
3
18
B1
A3
4
17
B2
A4
5
16
B3
A5
6
15
B4
1
A6
7
14
B5
19
A7
8
13
B6
A8
9
12
B7
10
11
B8
Figure 1. Logic Diagram
GND
FUNCTION TABLE
Figure 2. Pin Assignment
Control Inputs
OE
DIR
Operation
L
L
H
L
H
X
Data Tx from Bus B to Bus A
Data Tx from Bus A to Bus B
Buses Isolated (High−Z State)
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MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
VI/O
DC Output Voltage
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
V
Outputs in 3−State
High or Low State
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current (VOUT < GND; VOUT > VCC)
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage
Vin
DC Input Voltage
VI/O
DC Output Voltage
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
Outputs in 3−State
High or Low State
VCC =5.0V ±0.5V
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2
Min
Max
Unit
4.5
5.5
V
0
5.5
V
0
0
5.5
VCC
V
− 40
+ 85
_C
0
20
ns/V
MC74VHCT245A
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DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA = 25°C
VCC
V
Min
2.0
Typ
TA = − 40 to 85°C
Max
Min
Max
VIH
Minimum High−Level Input
Voltage
4.5 to 5.5
VIL
Maximum Low−Level Input
Voltage
4.5 to 5.5
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
IOH = − 50mA
4.5
4.4
IOH = − 8mA
4.5
3.94
Maximum Low−Level Output
Voltage
Vin = VIH or VIL
IOL = 50mA
4.5
0.1
0.1
IOL = 8mA
4.5
0.36
0.44
Iin
Maximum Input Leakage Current
Vin = 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
mA
IOZ
Maximum 3−State Leakage
Current
Vin = VIL or VIH
Vout = VCC or GND
5.5
±
0.25
± 2.5
mA
ICC
Maximum Quiescent Supply
Current
Vin = VCC or GND
5.5
4.0
40.0
mA
ICCT
Quiescent Supply Current
Per Input: VIN = 3.4V
Other Input: VCC or GND
5.5
1.35
1.50
mA
IOPD
Output Leakage Current
VOUT = 5.5V
0
0.5
5.0
mA
VOL
2.0
Unit
V
0.8
0.8
4.5
4.4
V
V
3.80
0.0
V
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
Test Conditions
Min
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
tPLH,
tPHL
Maximum Propagation Delay
A to B or B to A
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.9
5.4
7.7
8.7
1.0
1.0
8.5
9.5
ns
tPZL,
tPZH
Output Enable Time
OE to A or B
VCC = 5.0 ± 0.5V
RL = 1kW
CL = 15pF
CL = 50pF
9.4
9.9
13.8
14.8
1.0
1.0
15.0
16.0
ns
tPLZ,
tPHZ
Output Disable Time
OE to A or B
VCC = 5.0 ± 0.5V
RL = 1kW
CL = 50pF
10.1
15.4
1.0
16.5
ns
Output to Output Skew
VCC = 5.0 ± 0.5V
(Note 1)
CL = 50pF
1.0
1.0
ns
10
10
pF
tOSLH,
tOSHL
Cin
Maximum Input Capacitance
4
Cout
Maximum 3−State Output
Capacitance (Output in
High−Impedance State)
13
pF
Typical @ 25°C, VCC = 5.0V
CPD
16
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no−load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol
Parameter
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
1.2
1.6
V
VOLV
Quiet Output Minimum Dynamic VOL
−1.2
−1.6
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
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3
MC74VHCT245A
ORDERING INFORMATION
Package
Shipping †
MC74VHCT245ADW
SOIC−20WB
38 Units / Rail
MC74VHCT245ADWG
SOIC−20WB
(Pb−Free)
38 Units / Rail
MC74VHCT245ADWR2
SOIC−20WB
1000 / Tape & Reel
MC74VHCT245ADWRG
SOIC−20WB
(Pb−Free)
1000 / Tape & Reel
MC74VHCT245ADT
TSSOP−20*
75 Units / Rail
MC74VHCT245ADTG
TSSOP−20*
75 Units / Rail
MC74VHCT245ADTR2
TSSOP−20*
2500 / Tape & Reel
MC74VHCT245ADTRG
TSSOP−20*
2500 / Tape & Reel
MC74VHCT245AMEL
SOEIAJ−20
2000 / Tape & Reel
MC74VHCT245AMELG
SOEIAJ−20
(Pb−Free)
2000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
3V
DIR
A or B
tPLH
tPHL
B or A
OE
GND
A or B
VOL
1.5V
Figure 3. Switching Waveform
GND
tPLZ
HIGH
IMPEDANCE
1.5V
tPZH
A or B
VOL +0.3V
tPHZ
VOH −0.3V
1.5V
HIGH
IMPEDANCE
Figure 4. Switching Waveform
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
1.5V
tPZL
VOH
1.5V
GND
3V
3V
1.5V
1.5V
OUTPUT
DEVICE
UNDER
TEST
C L*
1 kW
C L*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
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4
MC74VHCT245A
A1
2
18
A2
3
17
A3
OE
B7
9
11
DIR
B6
8
12
A8
B5
7
13
A7
B4
6
14
A6
B3
5
15
A5
B2
4
16
A4
B1
1
19
Figure 7. Expanded Logic Diagram
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5
B8
MC74VHCT245A
PACKAGE DIMENSIONS
SOIC−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 _
h
1
10
20X
DIM
A
A1
B
C
D
E
e
H
h
L
q
B
B
0.25
M
T A
B
S
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
e
18X
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
SEATING
PLANE
A1
C
T
TSSOP−20
D5 SUFFIX
CASE 948E−02
ISSUE B
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
S
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
D
G
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74VHCT245A
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE A
20
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
VIEW P
e
A
c
0.13 (0.005)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.032
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MC74VHCT245A/D
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