IRF IRS2334SPBF 3 phase gate driver hvic Datasheet

27 January 2011
IRS2334SPbF/IRS2334MPbF
3 PHASE GATE DRIVER HVIC
Product Summary
Features
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Floating channel designed for bootstrap operation
Fully operational to 600 V
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 V to 20 V
Integrated dead time protection
Shoot-through (cross-conduction) prevention logic
Under-Voltage lockout for both channels
Independent 3 half-bridge drivers
3.3 V input logic compatible
Advanced input filter
Matched propagation delay for both channels
Lower di/dt gate driver for better noise immunity
Outputs in phase with inputs
RoHS compliant
Topology
3 phase
VOFFSET
≤ 600 V
VOUT
Io+ & I o- (typical)
200 mA & 350 mA
tON & tOFF (typical)
530 ns
Package Options
Typical Applications
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10 V – 20 V
20 leads wide body SOIC
Motor Control
Low Power Fans
General Purpose Inverters
Micro/Mini Inverter Drivers
28 leads MLPQ 5x5 (32 leads without 4)
Typical Connection Diagram
Up to 600V
Vcc
Vcc
HIN1,2,3
HIN1,2,3
LIN1,2,3
LIN1,2,3
VB1,2,3
HO1,2,3
VS 1,2,3
TO
LOAD
LO1,2,3
COM
IRS2334
GND
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1
© 2010 International Rectifier
IRS2334SPbF/MPbF
Table of Contents
Page
Description
3
Simplified Block Diagram
3
Typical Application Diagram
4
Qualification Information
5
Absolute Maximum Ratings
6
Recommended Operating Conditions
6
Static Electrical Characteristics
7
Dynamic Electrical Characteristics
7
Functional Block Diagram
8
Input/Output Pin Equivalent Circuit Diagram
9
Lead Definitions
10
Lead Assignments
11
Application Information and Additional Details
12
Parameter Temperature Trends
21
Package Details
25
Tape and Reel Details
27
Part Marking Information
29
Ordering Information
30
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IRS2334SPbF/MPbF
Description
The IRS2334 is a high voltage, high speed power MOSFET and IGBT driver with three independent high side
and low side referenced output channels for 3-phase applications. Proprietary HVIC and latch immune CMOS
technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL
outputs, down to 3.3 V. The output drivers feature a high pulse current buffer stage designed for minimum
driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The
floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration up
to 600 V.
Simplified Block Diagram
HV floating well
Schmitt trigger, minimum dead time
and shoot-through protection
to high side
power switches
(x3)
HV Level
Shifters
Delay
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to low side
power switches
(x3)
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IRS2334SPbF/MPbF
Typical Application Diagram
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IRS2334SPbF/MPbF
Qualification Information†
Industrial††
Comments: This IC has passed JEDEC industrial
qualification. IR consumer qualification level is granted by
extension of the higher Industrial level.
Qualification Level
MSL2 , 260C
(per IPC/JEDEC J-STD-020)
Moisture Sensitivity Level
Class 1C
(per JEDEC standard JESD22-A114)
Class B
(per EIA/JEDEC standard EIA/JESD22-A115)
Class I, Level A
(per JESD78)
Human Body Model
ESD
Machine Model
IC Latch-Up Test
Yes
RoHS Compliant
†
††
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
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IRS2334SPbF/MPbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM unless otherwise specified. The thermal resistance and
power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB
VS
Definition
VHO1,2,3
VCC
VLO1,2,3
VIN
PWHIN
dVS/dt
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic and analog input voltages
High-side input pulse width
Allowable offset supply voltage slew rate
PD
Package power dissipation @ TA ≤ 25°C
RthJA
TJ
TS
TL
†
Thermal resistance, junction to ambient
20 lead SOIC
28 lead MLPQ
20 lead SOIC
28 lead MLPQ
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
Min.
Max.
-0.3
†
VB1,2,3 - 25
VS1,2,3 - 0.3
-0.3
-0.3
-0.3
500
—
—
—
—
—
—
-55
—
625
VB1,2,3 + 0.3
VB1,2,3 + 0.3
†
25
VCC + 0.3
VCC + 0.3
—
50
1.14
3.363
65.8
22.3
150
150
300
Units
V
ns
V/ns
W
°C/W
°C
All supplies are fully tested at 25 V. An internal 25 V clamp exists for each supply.
Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters are
absolute voltages referenced to COM unless otherwise specified. The VS1,2,3 offset ratings are tested with all
supplies biased at 15 V.
Symbol
VB1,2,3
VS1,2,3
VS1,2,3(t)
VHO1,2,3
VCC
VLO1,2,3
VIN
TA
†
††
Definition
Min.
High side floating supply voltage
†
Static high side floating supply offset voltage
Transient high side floating supply offset voltage††
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage
Ambient temperature
VS1,2,3 +10
-8
-50
VS1,2,3
10
0
0
-40
Max.
VS1,2,3 + 20
600
600
VB1,2,3
20
VCC
VCC
125
Units
V
°C
Logic operation for VS of –8 V to 600 V. Logic state held for VS of –8 V to –VBS.
Operational for transient negative VS of -50 V with a 50 ns pulse width. Guaranteed by design. Refer to the
Application Information section of this datasheet for more details.
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IRS2334SPbF/MPbF
Static Electrical Characteristics
(VCC-COM) = (VB1,2,3-VS1,2,3) = 15 V and TA = 25 oC unless otherwise specified. The VIN and IIN parameters are
referenced to COM. The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the output
leads LO1,2,3 and HO1,2,3 respectively. The VCCUV and VBSUV parameters are referenced to COM and VS
respectively.
Symbol
VIH
VIL
VIN,TH+
VIN,THVOH
VOL
VCCUV+
VBSUV+
VCCUVVBSUVVCCUVH
VBSUVH
ILK
IQBS
IQCC
IIN+
IINIo+
Io-
Definition
Min.
Typ.
Max.
Units
2.5
—
—
—
—
—
—
—
1.9
1
0.9
0.4
—
0.8
—
—
1.4
0.6
V
10.4
11.1
11.6
10.2
10.9
11.4
VCC and VBS supply under-voltage hysteresis
0.1
0.2
—
Offset supply leakage current
Quiescent VBS supply current
Quiescent VCC supply current
Logic “1” input bias current
Logic “0” input bias current
Output high short circuit pulsed current
Output low short circuit pulsed current
—
—
—
—
—
120
250
1
40
300
150
50
120
700
250
1
—
—
Logic “1” input voltage
Logic “0” input voltage
Input positive going threshold
Input negative going threshold
High level output voltage
Low level output voltage
VCC and VBS supply under-voltage positive
going threshold
VCC and VBS supply under-voltage negative
going threshold
200
350
µA
µA
Test Conditions
IO = 20 mA
VB =VS = 600 V
VIN = 0 V
µA
VIN = 5 V
VIN = 0 V
mA
VO = 0 V or 15 V
PW ≤ 10 µs
Dynamic Electrical Characteristics
VCC = VB1,2,3 = 15 V, VS1,2,3 = COM, TA = 25 oC and CL = 1000 pF unless otherwise specified.
Symbol
ton
toff
tr
tf
tFILIN
DT
MDT
MT
PM
†
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
Input filter time
Dead time
Dead time matching
ton, toff propagation delay matching time
†
PW pulse width distortion
Min.
Typ.
Max.
400
400
—
—
200
190
—
—
—
530
530
125
50
350
290
—
—
—
750
750
190
75
510
420
60
50
75
Units
Test Conditions
VIN = 0V and 5V
ns
VIN = 0V & 5V
External dead time
0s
PW input =10µs
PM is defined as PWIN - PWOUT.
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IRS2334SPbF/MPbF
Functional Block Diagram
HIN1
Input
Noise
Filter
LIN1
Input
Noise
Filter
HIN2
Input
Noise
Filter
LIN2
Input
Noise
Filter
HIN3
Input
Noise
Filter
LIN3
Input
Noise
Filter
VB1
SD
SD
SD
HV
Level
Shifter
Deadtime &
Shoot-Through
Prevention
Deadtime &
Shoot-Through
Prevention
HV
Level
Shifter
Deadtime &
Shoot-Through
Prevention
HV
Level
Shifter
SET
Latch
RESET
UV
Detect
Driver
HO1
VS1
VB2
SET
Latch
RESET
UV
Detect
SET
Latch
RESET
UV
Detect
Driver
HO2
VS2
VB3
Driver
HO3
VS3
VCC
UV
Detect
Delay
Driver
LO1
Delay
Driver
LO2
Delay
Driver
LO3
COM
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IRS2334SPbF/MPbF
Input/Output Pin Equivalent Circuit Diagrams
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IRS2334SPbF/MPbF
Lead Definitions
Symbol
VCC
VB1
VB2
VB3
VS1
VS2
VS3
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
HO1
HO2
HO3
LO1
LO2
LO3
COM
Description
Low side and logic power supply
High side floating power supply (phase 1)
High side floating power supply (phase 2)
High side floating power supply (phase 3)
High side floating supply return (phase 1)
High side floating supply return (phase 2)
High side floating supply return (phase 3)
Logic input for high side gate driver output HO1, input is in-phase with output
Logic input for high side gate driver output HO2, input is in-phase with output
Logic input for high side gate driver output HO3, input is in-phase with output
Logic input for low side gate driver output LO1, input is in-phase with output
Logic input for low side gate driver output LO2, input is in-phase with output
Logic input for low side gate driver output LO3, input is in-phase with output
High side gate driver output (phase 1)
High side gate driver output (phase 2)
High side gate driver output (phase 3)
Low side gate driver output (phase 1)
Low side gate driver output (phase 2)
Low side gate driver output (phase 3)
Low side supply return
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IRS2334SPbF/MPbF
Lead Assignments
VB2
HO2
VS2
VB3
HO3
HS3
31
30
27
26
25
32 leads MLPQ 5x5 without 4 leads
32
20 leads wide body SOIC
VS1
1
24
HO1
2
23
VB1
3
22
21
20
VCC
LO3
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COM
16
17
15
8
14
HIN3
13
LO2
12
18
11
7
LIN3
HIN2
10
LO1
LIN2
19
9
6
LIN1
HIN1
© 2010 International Rectifier
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IRS2334SPbF/MPbF
Application Information and Additional Details
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IGBT/MOSFET Gate Drive
Switching and Timing Relationships
Deadtime
Matched Propagation Delays
Input Logic Compatibility
Shoot-Through Protection
Under-Voltage Lockout Protection
Truth Table: Under-Voltage lockout
Advanced Input Filter
Short-Pulse and Noise Rejection
Tolerant to Negative VS Transients
PCB Layout Tips
Additional Documentation
IGBT/MOSFET Gate Drive
The IRS2334 HVIC is designed to drive high side and low side MOSFET or IGBT power devices. Figures 1 and 2
show the definition of some of the relevant parameters associated with the gate driver output functionality. The
output current that drives the gate of the external power switches is defined as IO. The output voltage that drives
the gate of the external power switches is defined as VHO for the high side and VLO for the low side; this
parameter is sometimes generically called VOUT and in this case the high side and low side output voltages are
not differentiated.
VB
(or VCC)
VB
(or VCC)
IO+
H
(or LO)
H
(or LO)
+
VH (or VL )
(or
VS
)
(or
Figure 1: HVIC sourcing current
VS
IO -
)
Figure 2: HVIC sinking current
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IRS2334SPbF/MPbF
Switching and Timing Relationships
The relationship between the input and output signals of the IRS2334 HVIC is shown in Figure 3. The definitions
of some of the relevant parameters associated with the gate driver input to output transmission are given.
LIN
or HIN
50%
50%
PWIN
t ON
LO
or HO
tR
PWOUT
90%
10%
tOFF
tF
90%
10%
Figure 3: Switching time waveforms
During interval A of Figure 4 the HVIC receives the command to turn on both the high and low side switches at
the same time; correspondingly, the shoot-through protection prevents the high and low side signals HO and LO
turn on by keeping them low.
Figure 4: Input/output timing diagram
Deadtime
The IRS2334 HVIC provides an integrated deadtime protection circuitry. The deadtime interval for this HVIC is
fixed; while other ICs within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The
deadtime feature inserts a time interval in which both the gate driver outputs LO and HO are held off; to ensure
that the power switch being turned off has fully turned off before the second power switch is turned on. This
minimum deadtime is automatically inserted whenever the external deadtime commanded by the host
microcontroller is shorter than DT, while external deadtimes larger than DT are not modified by the gate driver.
Figure 7 illustrates the deadtime interval definition and the relationship between the output gate signals.
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IRS2334SPbF/MPbF
The deadtime interval introduced is matched with respect to the commutation from HIN turning off to LIN turning
on, and viceversa. Figure 5 defines the two deadtime parameters DT1 and DT2. The deadtime matching
parameter MDT is defined as the maximum difference between DT1 and DT2.
LIN
HIN
50%
LO
HO
50%
DT1
DT2
50%
50%
Figure 5: Deadtime definition
Matched Propagation Delays
The IRS2334 HVIC is designed for propagation delay matching. With this feature, the input to output propagation
delays tON, tOFF are the same for the low side and the high side channels; the maximum difference being specified
by the delay matching parameter MT as defined in Figure 6.
Figure 6: Delay Matching Waveform Definition
Input Logic Compatibility
The IRS2334 HVIC is designed with inputs compatible with standard CMOS and TTL outputs with 3.3 V and 5 V
logic level signals. Figure 7 shows how an input signal is logically interpreted.
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IRS2334SPbF/MPbF
Figure 7: HIN & LIN input thresholds
Shoot-Through Protection
The IRS2334 is equipped with a shoot-through protection circuitry which prevents cross-conduction of the power
switches. Table 1 shows the input to output relationship in the form of a truth table. Note that the HVIC has noninverting inputs (the output is in-phase with the respective input).
HIN
LIN
HO
LO
0
0
0
0
0
1
0
1
1
0
1
0
1
1
0
0
Table 1: Input/output truth table
Under-Voltage Lockout Protection
The IRS2334 HVIC provides under-voltage lockout protection on both the VCC low side and logic fixed power
supply and the VBS high side floating power supply. Figure 8 illustrates this concept by considering the VCC (or
VBS) plotted over time: as the waveform crosses the UVLO threshold, the under-voltage protection is entered or
exited.
Upon power up, should the VCC voltage fail to reach the VCCUV+ threshold, the gate driver outputs LO and HO will
remain disabled. Additionally, if the VCC voltage decreases below the VCCUV- threshold during normal operation,
the under-voltage lockout circuitry will shutdown the gate driver outputs LO and HO.
Upon power up, should the VBS voltage fail to reach the VBSUV threshold, the gate driver output HO will remain
disabled. Additionally, if the VBS voltage decreases below the VBSUV threshold during normal operation, the undervoltage lockout circuitry will shutdown the high side gate driver output HO.
The UVLO protection ensures that the HVIC drives external power devices only with a gate supply voltage
sufficient to fully enhance them. Without this protection, the gates of the external power switches could be driven
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IRS2334SPbF/MPbF
with a low voltage, which would result in power switches conducting current while with a high channel impedance,
which would produce very high conduction losses possibly leading to power device failure.
VCC
(or B )
V CCU +
(or BSU + )
VCCU (or BSU - )
Time
UVLO Protection
(Gate Driver Outputs Disabled
)
Norma
Operation
Norma
Operation
Figure 8: UVLO protection
Truth Table: Under-Voltage lockout
Table 2 provides the truth table for the IRS2334 HVIC.
The 1st line shows that for VCC below the UVLO threshold both the gate driver outputs LO and HO are disabled.
After VCC returns above VCCUV, the gate driver outputs return functional.
The 2nd line shows that for VBS below the UVLO threshold, the gate driver output HO is disabled. After VBS returns
above VBSUV, HO remains low until a new rising transition of HIN is received.
The last line shows the normal operation of the HVIC.
UVLO VCC
UVLO VBS
Normal operation
VCC
VBS
<VCCUV
15 V
15 V
<VBSUV
15 V
outputs
LO
0
LIN
LIN
HO
0
0
HIN
Table 2: UVLO truth table
Advanced Input Filter
The IRS2334 HVIC provides an advanced input filter that improves the input/output pulse symmetry of the signals
processed by the HVIC. This input filter is inserted at the HIN and LIN input pins. The working principle of the
filter is shown in Figures 9 and 10.
Figure 9 shows a typical input filter and the asymmetry it produces on its output signal. The upper waveforms of
Example 1 show an input signal with a pulse duration mush longer than the filtering time tFILIN; the resulting output
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IRS2334SPbF/MPbF
signal has a duration given approximately by the difference between the input signal and tFILIN. The lower
waveforms of Example 2 show an input signal with a pulse duration slightly longer than the filtering time tFILIN; the
resulting output signal has a duration given approximately by the difference between the input signal and tFILIN,
much shorter than it should be.
Figure 10 shows the advanced input filter and the symmetry it produces on its output signal. The upper
waveforms of Example 1 show an input signal with a pulse duration much longer than the filtering time tFILIN; the
resulting output signal has approximately the same duration as the input signal. The lower waveforms of Example
2 show an input signal with a pulse duration slightly longer than the filtering time tFILIN; the resulting output signal
has approximately the same duration as the input signal.
Figure 9: Typical input filter
Figure 10: Advanced input filter
Short-Pulse and Noise Rejection
The advanced input filter that improves the input/output pulse symmetry of the signals processed by the HVIC
also helps the rejection of noise spikes and of short pulses on the input signals.
Example 2
Example 1
Input signals with a pulse duration less than the filtering time tFILIN will be filtered out. In Figure 11 Example 1
shows an input signal in the low state with superimposed positive noise spikes of duration less than tFILIN; the
advanced input filter filters out the noise spikes and the output signal remains in the low state. Example 2 shows
an input signal in the high state with superimposed negative noise spikes of duration less than tFILIN; the
advanced input filter filters out the noise spikes and the output signal remains in the high state.
Figure 11: Noise rejection of the advanced input filter
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IRS2334SPbF/MPbF
Time (ns)
The measured characteristic of the advanced input filter is shown in Figure 12. On the left side the characteristic
for narrow ON pulses is shown (short positive pulse) while on the left side the characteristic for narrow OFF
pulses is shown (short negative pulse). The x-axis represents the input pulse duration PWIN, while the y-axis the
resulting output pulse duration PWOUT. For pulses with input pulse duration PWIN less than the filtering time tFILIN
the resulting output pulse duration PWOUT is zero because the filter rejects the input signal. For pulses with input
pulse duration PWIN greater than the filtering time tFILIN the resulting output pulse duration PWOUT tracks the input
pulse durations well, the higher the duration the better the symmetry.
Figure 12: Measured advanced input filter characteristic
The difference between the output pulse duration PWOUT and the input pulse duration PWIN of both the narrow
ON and narrow OFF cases is shown in Figure 13. The x-axis represents the input pulse duration PWIN, while the
y-axis the resulting difference PWOUT–PWIN.
Figure 13: Difference between the input pulse duration and the output pulse duration
Tolerant to Negative VS Transients
A common problem in today’s high-power switching converters is the transient response of the switch node’s
voltage as the power devices switch on and off quickly while carrying a large current. A typical 3-phase inverter
circuit is shown in Figure 14; where we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figures 15 and 16) switches off, while the U phase current is flowing
to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with
the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive
DC bus voltage to the negative DC bus voltage.
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IRS2334SPbF/MPbF
Figure 14: Three phase inverter
DC+ BUS
Q1
ON
IU
VS1
Q2
OFF
D2
DC- BUS
Figure 15: Q1 conducting
Figure 16: D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figures 17 and 18), and Q4
IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2,
swings from the positive DC bus voltage to the negative DC bus voltage.
DC+ BUS
Q3
OFF
D3
IV
VS2
Q4
OFF
D4
DC- BUS
Figure 17: D3 conducting
Figure 18: Q4 conducting
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it
swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”.
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IRS2334SPbF/MPbF
The circuit shown in Figure 19 depicts one leg of the three phase inverter; Figures 20 and 21 show a simplified
illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit
from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side
switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the
parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in
the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these
figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a
negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential
than the VS pin).
Figure 19: Parasitic Elements
Figure 20: VS positive
Figure 21: VS negative
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS
transient voltage can exceed this range during some events such as short circuit and over-current shutdown,
when di/dt is greater than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding
applications. An indication of the IRS2334’s robustness can be seen in Figure 22, where there is represented the
IRS2334 Safe Operating Area at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage
falling in the grey area (outside SOA) may lead to IC permanent damage; vice versa unwanted functional
anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside SOA.
At VBS=15V in case of -VS transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will
hold by design the high-side outputs in the off state for 4.5 μs.
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IRS2334SPbF/MPbF
Figure 22: Negative VS transient SOA @ VBS=15V
Even though the IRS2334 has been shown able to handle these large negative VS transient conditions, it is
highly recommended that the circuit designer always limit the negative VS transients as much as possible by
careful PCB layout and component use.
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IRS2334SPbF/MPbF
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied to
the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the Case
Outline information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high
voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure
23). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive
loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the
IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to
developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.
VB
(or CC )
H
(or
IGC
CGC
RG
)
Gate Drive
Loo
VS
(or
VGE
)
Figure 23: Antenna Loops
Supply Capacitor: It is recommended to place a bypass capacitor between the VCC and COM pins. This
connection is shown in Figure 24. A ceramic 1 μF ceramic capacitor is suitable for most applications. This
component should be placed as close as possible to the pins in order to reduce parasitic elements.
Up to 600V
Vcc
Vcc
HIN1,2,3
HIN1,2,3
LIN1,2,3
LIN1,2,3
VB1,2,3
HO1,2,3
VS 1,2,3
TO
LOAD
LO1,2,3
COM
GND
Figure 24: Supply capacitor
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© 2010 International Rectifier
22
IRS2334SPbF/MPbF
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients
at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such
conditions, it is recommended to 1) minimize the high-side source to low-side collector distance, and 2) minimize
the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive,
further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin
and the switch node (see Figure 25), and in some cases using a clamping diode between COM and VS (see
Figure 26). See DT04-4 at www.irf.com for more detailed information.
DC+ BU
DC+ BU
VB
VB
C BS
C BS
HO
HO
VS
R VS
VS
T
Load
L
RVS
T
Load
D VS
L
CO
CO
DC- BU
DC- BU
Figure 25: VS resistor
Figure 26: VS clamping diode
Additional Documentation
Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search
function and the document number to quickly locate them. Below is a short list of some of these documents.
DT97-3: Managing Transients in Control IC Driven Power Stages
AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
DT04-4: Using Monolithic High Voltage Gate Drivers
AN-978: HV Floating MOS-Gate Driver ICs
Parameter Temperature Trends
Figures 27-44 provide information on the experimental performance of the IRS2334 HVIC. The line plotted in
each figure is generated from actual experimental data. A small number of individual samples were tested at
three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental curve. The line labeled
Exp. consist of three data points (one data point at each of the tested temperatures) that have been
connected together to illustrate the understood temperature trend. The individual data points on the curve
were determined by calculating the averaged experimental value of the parameter (for a given temperature).
www.irf.com
© 2010 International Rectifier
23
IRS2334SPbF/MPbF
800
1000
700
800
Exp.
500
tOFF (ns)
tON (ns)
600
Exp.
400
300
200
600
400
200
100
0
0
-50
-25
0
25
50
75
100
-50
125
-25
0
o
75
100
125
Temperature ( C)
Fig. 27. Turn-on Propagation Delay vs. Temperature
Fig. 28. Turn-off Propagation Delay vs. Temperature
100
90
400
TF (ns)
300
TR (ns)
50
o
Temperature ( C)
200
Exp.
80
70
60
Exp.
50
40
30
20
10
100
0
0
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
o
Temperature ( C)
o
Temperature ( C)
Fig. 29. Turn-on Rise Time vs. Temperature
Fig.30. Turn-off Fall Time vs. Temperature
500
4
400
VOL (mV)
3
VIN _th- (V)
25
2
300
Exp.
200
Exp.
1
100
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (o C)
o
Temperature ( C)
Fig. 31. Input Negative Going Threshold vs. Temperature
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Fig. 32. Low Level Output Voltage vs. Temperature
© 2010 International Rectifier
24
20
4
15
3
IQCC1 (mA)
lleak1_Vccmax (uA)
IRS2334SPbF/MPbF
10
2
Exp.
5
1
Exp.
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
o
Temperature (o C)
Temperature ( C)
Fig. 33. Offset Supply Leakage Current vs. Temperature
Fig. 34. Quiescent VCC Supply Current vs. Temperature
100
4
80
IQBS10 (uA)
IQCC0 (mA)
3
2
60
Exp.
40
Exp.
1
20
0
0
-50
-25
0
25
50
75
100
-50
125
-25
0
o
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Fig. 35. Quiescent VCC Supply Current vs. Temperature
Fig. 36. Quiescent VBS Supply Current vs. Temperature
100
15
80
12
VCCUVTH- (V)
IQBS11 (uA)
25
60
Exp.
40
20
Exp.
9
6
3
0
0
-50
-25
0
25
50
75
100
125
o
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Fig. 37. Quiescent VBS Supply Current vs. Temperature
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Fig. 38. VCC Supply Under-voltage Negative Going
Threshold vs. Temperature
© 2010 International Rectifier
25
15
15
12
12
VbsUVTH- (V)
VCCUVTH+ (V)
IRS2334SPbF/MPbF
Exp.
9
6
Exp.
9
6
3
3
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
o
75
100
125
Temperature ( C)
Fig. 39. VCC Supply Under-voltage Positive Going
Threshold vs. Temperature
Fig. 40. VBS Supply Under-voltage Negative Going
Threshold vs. Temperature
15
500
12
400
Exp.
Io+ (mA)
VbsUVTH+ (V)
50
o
Temperature ( C)
9
6
3
300
Exp.
200
100
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
o
25
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Fig. 41. VBS Supply Under-voltage Positive Going
Threshold vs. Temperature
Fig. 42. Output High Short Circuit Pulsed Current vs.
Temperature
500
-50
-25
0
25
50
75
100
125
0
VS1_RS_domin (V)
400
Io- (mA)
25
300
Exp.
200
100
0
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Fig. 43. Output Low Short Circuit Pulsed Current vs.
Temperature
www.irf.com
-5
Exp.
-10
-15
-20
Temperature (o C)
Fig. 44. Max –Vs vs. Temperature
© 2010 International Rectifier
26
IRS2334SPbF/MPbF
Package Details
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© 2010 International Rectifier
27
IRS2334SPbF/MPbF
Package Details
28 (32 – 4) lead MLPQ 5x5mm
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© 2010 International Rectifier
28
IRS2334SPbF/MPbF
Tape and Reel Details
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 20SOICW
Metri
Imperial
Cod
Mi
Ma
Mi
Ma
11.9
12.1
0.46
0.47
A
B
3.9
4.1
0.15
0.16
23.7
24.3
0.93
0.95
C
11.4
11.6
0.44
0.45
D
10.8
11.0
0.42
0.43
E
F
13.2
13.4
0.52
0.52
1.5
n/
0.05
n/
G
1.5
1.6
0.05
0.06
H
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 20SOICW
Metri
Imperial
Cod
Mi
Ma
Mi
Ma
A
329.6
330.2
12.97
13.00
20.9
21.4
0.82
0.84
B
12.8
13.2
0.50
0.51
C
D
1.9
2.4
0.76
0.09
98.0
102.0
3.85
4.01
E
n/
30.4
n/
1.19
F
26.5
29.1
1.0
1.14
G
24.4
26.4
0.9
1.03
H
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© 2010 International Rectifier
29
IRS2334SPbF/MPbF
Tape and Reel Details:
28 (32 – 4) lead MLPQ 5x5mm
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© 2010 International Rectifier
30
IRS2334SPbF/MPbF
Part Marking Information
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© 2010 International Rectifier
31
IRS2334SPbF/MPbF
Ordering Information
Standard Pack
Base Part Number
Package Type
SOIC20W
Complete Part Number
Form
Quantity
Tube/Bulk
XXX
IRS2334 SPBF
Tape and Reel
XXX
IRS2334 STRPBF
Tube/Bulk
XXX
IRS2334 MPBF
Tape and Reel
XXX
IRS2334 MTRPBF
IRS2334
28L MLPQ 5x5mm
(32 leads without 4)
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the
consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties
which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International
Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information
previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
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© 2010 International Rectifier
32
IRS2334SPbF/MPbF
Revision History
Revision Date
5.0
24 Jun 2009
5.1
30 Jun 2009
5.2
5.3
3 July 2009
Aug 2009
5.4
12 Nov
2009
5.5
5.6
5.7
5.8
5.9
5.10
9 Dec 2009
12 Mar 2010
02 Apr 2010
26 Jan 2011
31 Jan 2011
Change comments
Ramanan updated lead assignment, MLPQ 5x5 package information and Absolute Max
Ratings to reflect 25V capability
Updated: format, lead assignment, functional block diagram,
Added: simplified block diagram, typical application diagram, qualification information,
application details, parameters temperature trend, tape and reel detail, order
information, revision history
Removed: inputs internally clamped at 5.2V in static electrical characteristic
Lead definition corrected, delay matching waveform definition figure added
Package and tape & reel details for MLPQ 32-4 leads 5x5 added, package thermal
parameters added
Advanced input filter section added
TBD values in Static Electrical Characteristics updated
Changed MM ESD rating from Class C to Class B
Parameter limits updated: IQCC, IQBS, IIN+
Io+, Io- values corrected
Update temperature dependence tables, UVcc hyst corrected
Include the IRS2334MPbF in the datasheet title
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© 2010 International Rectifier
33
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