ON FAN2360AMPX 10 a synchronous buck regulator Datasheet

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FAN2360AMPX
10 A Synchronous Buck Regulator
Features
Description
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The FAN2360A is a highly efficient synchronous buck
regulator. The regulator is capable of operating with an
input range from 4.5 V to 24 V and supporting up to
10 A continuous load currents.
VIN Range: 4.5 V to 24 V
High Efficiency: Over 96% Peak
Continuous Output Current: 10 A
PFM Mode for Light-Load Efficiency
Excellent Line and Load Transient Response
Precision Reference: ±1% Over-Temperature
Output Voltage Range: 0.6 to 5.5 V
Programmable Frequency: 200 kHz to 1.5 MHz
Programmable Soft-Start
Low Shutdown Current
Adjustable Sourcing Current Limit
Internal Boot Diode
Thermal Shutdown
Halogen and Lead Free, RoHS Compliant
The FAN2360A utilizes Fairchild’s constant on-time
control architecture to provide excellent transient
response and to maintain a relatively constant switching
frequency. This device utilizes Pulse Frequency
Modulation (PFM) mode to maximize light-load
efficiency by reducing switching frequency when the
inductor is operating in discontinuous conduction mode
at light loads, while clamping the minimum frequency
above the audible range with ultrasonic mode.
Switching frequency and over-current protection can
be programmed to provide a flexible solution for
various applications. Output over-voltage, undervoltage, over-current, and thermal shutdown protections
help prevent damage to the device during fault
conditions. After thermal shutdown is activated, a
hysteresis feature restarts the device when normal
operating temperature is reached.
Applications
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Mainstream Notebooks
Servers and Desktop Computers
Game Consoles
Telecommunications
Storage
Base Stations
Ordering Information
Part Number
Configuration
Operating
Temperature Range
Output
Current (A)
FAN2360AMPX
PFM with Ultrasonic Mode
-40 to 125°C
10
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
Package
34-Lead, PQFN,
5.5 mm x 5.0 mm
www.fairchildsemi.com
FAN2360AMPX — 6 A Synchronous Buck Regulator
September 2015
VBIAS = 5V
R11
10Ω
C9
0.1µF
C10
2.2µF
PVCC
VCC
Ext
EN
VIN = 12V
CIN
0.1µF
VIN
CIN
2x10µF
PVIN
C3
0.1µF
EN
VOUT = 1.2V
IOUT=0-6A
BOOT
L1
1.2µH
FAN2360A
SW
PGOOD
ILIM
SOFT START
R2
1.5kΩ
R5 1.5kΩ
C7
15nF
C4
0.1µF
R3
10kΩ
C5
100pF
FREQ
FB
R9
54.9kΩ
AGND
R6
4.99kΩ
PGND
R4
10kΩ
Figure 1. Typical Application
Functional Block Diagram
VIN
BOOT
PVIN
COUT
4x47µF
FAN2360AMPX — 10 A Synchronous Buck Regulator
Typical Application Diagram
PVCC
PVCC
VCC
VCC
VCC UVLO
0.8V/
2.0V
PVCC
EN
ENABLE
VCC
VCC
10µA
Modulator
HS Gate
Driver
SS
FB
FB
Comparator
VREF
SW
FREQ
Control
Logic
x1.2
2nd Level Over-Voltage
Comparator
x1.1
1st Level Over-Voltage
Comparator
PFM
Comparator
PVCC
x0.9
LS Gate
Driver
Under-Voltage
Comparator
VCC
PGOOD
Thermal
Shutdown
10µA
Current Limit
Comparator
AGND
ILIM
PGND
Figure 2. Block Diagram
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
www.fairchildsemi.com
2
VIN
SW
BOOT
AGND
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
AGND
BOOT
SW
VIN
1
2
3
4
5
6
7
8
9
9
8
7
6
5
4
3
2
1
10
PVIN
PVIN 10
34
NC
11
PVIN
PVIN 11
33
NC
12
SW
SW
12
32
FREQ
13
SW
SW 13
31
SS
14
SW
SW
30 PGOOD
29
15
SW
SW 15
29
EN
28
16
SW
SW 16
28
NC
SW
SW 17
27
FB
SW
(P3)
PGOOD 30
EN
NC
27
24
23
22
21
20
ILIM
AGND
SW
PGND
PGND
19
18
PGND
25
PGND
26
PVCC
17
VCC
FB
14
Figure 3. Pin Assignments(Bottom View)
18
19
20
21
22
23
24
25
26
VCC
AGND
(P1)
PVCC
31
ILIM
SS
AGND
32
SW
FREQ
PGND
33
PGND
NC
PVIN
(P2)
PGND
34
PGND
NC
Figure 4. Pin Assignments(Top View)
Pin Definitions
Name
Pad / Pin
PVIN
P2, 5-11
Description
Power input for the power stage.
VIN
1
Input to the modulator for input voltage feed-forward.
PVCC
25
Power input for the low-side gate driver and boot diode.
VCC
26
Power supply input for the controller.
PGND
18-21
AGND
SW
P1, 4, 23
Power ground for the low-side power MOSFET and for the low-side gate driver.
Analog ground for the analog portions of the IC and substrate.
P3, 2, 12-17, 22 Switching node; junction between high-and low-side MOSFETs.
BOOT
3
Supply for high-side MOSFET gate driver. A capacitor from BOOT to SW supplies the
charge to turn on the N-channel high-side MOSFET. During the freewheeling interval
(low-side MOSFET on), the high-side capacitor is recharged by an internal diode
connected to PVCC.
ILIM
24
Current limit. A resistor between ILIM and SW sets the current limit threshold.
FB
27
Output voltage feedback to the modulator.
EN
29
Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable.
SS
31
Soft-start input to the modulator.
FREQ
32
On-time and frequency programming pin. Connect a resistor between FREQ and
AGND to program on-time and switching frequency.
PGOOD
30
Power good; open-drain output indicating VOUT is within set limits.
NC
28, 33-34
Leave pin open or connect to AGND.
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
www.fairchildsemi.com
3
FAN2360AMPX — 10 A Synchronous Buck Regulator
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VPVIN
VIN
VBOOT
VSW
Parameter
Conditions
Min. Max. Unit
Power Input
Referenced to PGND
-0.3
30.0
V
Modulator Input
Referenced to AGND
-0.3
30.0
V
Referenced to PVCC
-0.3
30.0
V
Referenced to PVCC, <20 ns
-0.3
33.0
V
Referenced to PGND, AGND
-1
30
V
Boot Voltage
SW Voltage to GND
-5
30
V
Boot to SW Voltage
Referenced to SW
-0.3
6.0
V
Boot to PGND
Referenced to PGND
-0.3
30
V
VPVCC
Gate Drive Supply Input
Referenced to PGND, AGND
-0.3
6.0
V
VVCC
Controller Supply Input
Referenced to PGND, AGND
-0.3
6.0
V
VILIM
Current Limit Input
Referenced to AGND
-0.3
6.0
V
VFB
Output Voltage Feedback
Referenced to AGND
-0.3
6.0
V
VEN
Enable Input
Referenced to AGND
-0.3
6.0
V
VSS
Soft Start Input
Referenced to AGND
-0.3
6.0
V
VFREQ
Frequency Input
Referenced to AGND
-0.3
6.0
V
Power Good Output
Referenced to AGND
-0.3
VBOOT
VPGOOD
ESD
Electrostatic Discharge
TJ
Junction Temperature
TSTG
Storage Temperature
Referenced to PGND, AGND < 20 ns
6.0
V
Human Body Model, JESD22-A114
1000
V
Charged Device Model, JESD22-C101
2500
V
+150
°C
+150
°C
-55
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VPVIN
Parameter
Min.
Typ. Max.
Unit
Power Input
Referenced to PGND
4.5
24.0
V
VIN
Modulator Input
Referenced to AGND
4.5
24,0
V
TJ
Junction Temperature
-40
+125
°C
15
A
5.5
V
ILOAD
Load Current
TA=25°C, No Airflow
VPVCC
Gate Drive Supply Input
Referenced to PGND, AGND
4.5
Thermal Characteristics
The thermal characteristics were evaluated on a 4-layer pcb structure (1 oz/1 oz/1 oz/1 oz) measuring 7 cm x 7 cm).
Symbol
Parameter
Typ.
Unit
JA
Thermal Resistance, Junction-to-Ambient
35
°C/W
ψJC
Thermal Characterization Parameter, Junction-to-Top of Case
2.7
°C/W
Thermal Characterization Parameter, Junction-to-PCB
2.3
°C/W
ψJPCB
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
www.fairchildsemi.com
4
FAN2360AMPX — 10 A Synchronous Buck Regulator
Absolute Maximum Ratings
Unless otherwise noted; VIN=12 V, VOUT=1.2 V, and TA=TJ = -40 to +125°C.
Symbol
Parameter
(1)
Condition
Min.
Typ.
Max.
Unit
10
µA
1.8
mA
Supply Current
IVCC,SD
Shutdown Current
EN=0 V
IVCC,Q
Quiescent Current
EN=5 V, Not Switching
IVCC,GateCharge Gate Charge Current
EN=5 V, fSW=500 kHz
14
mA
Reference, Feedback Comparator
VFB
FB Voltage Trip Point
590
596
602
mV
IFB
FB Pin Bias Current
-100
0
100
nA
20
%
Modulator
tON
On-Time Accuracy
RFREQ=56.2 k, VIN=10 V,
tON=250 ns, No Load
-20
tON,PFM
PFM On-Time Multiplier
150
tOFF,MIN
Minimum SW Off-Time
320
tON,MIN
Minimum SW On-Time
DMIN
Minimum Duty Cycle
fMINF
Minimum Frequency Clamp
FB=1 V
%
374
ns
45
ns
0
%
18.2
25.4
32.7
kHz
10
13
µA
100
%
Soft-Start
ISS
tON,SSMOD
Soft-Start Current
SS=0.5 V
7
SS On-Time Modulation
SS<0.6 V
25
VSSCLAMP,NOM Nominal Soft-Start Voltage Clamp
VSSCLAMP,OVL
Soft-Start Voltage Clamp in Overload
Condition
VFB=0.6 V
400
mV
VFB=0.3 V, OC Condition
40
mV
PFM Zero-Crossing Detection Comparator
VOFF
ZCD Offset Voltage
TA=TJ=25°C
-6
0
mV
TA=TJ=25°C,
IVALLEY=12 A
-10
10
%
-3
3
mV
Current Limit
ILIM
VILIM,OFFSET
Valley Current Limit Accuracy
Comparator Offset
KILIM
ILIM Set-Point Scale Factor
149
ILIMTC
Temperature Coefficient
4000
ppm/°C
Continued on the following page…
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
www.fairchildsemi.com
5
FAN2360AMPX — 10 A Synchronous Buck Regulator
Electrical Characteristics
Unless otherwise noted; VIN=12 V, VOUT=1.2 V, and TA=TJ = -40 to +125°C.
Symbol
Parameter
(1)
Condition
Min.
Typ.
Max.
Unit
2.0
V
Enable
VTH+
Rising Threshold
VTH-
Falling Threshold
IENLK
Enable Pin Leakage
EN=1.2 V
0.8
100
nA
V
IENLK
Enable Pin Leakage
EN=5 V
76
µA
UVLO
VON
VCC Good Threshold Rising
VHYS
Hysteresis Voltage
4.4
160
V
mV
Fault Protection
VUVP
PGOOD UV Trip Point
On FB Falling
86
89
92
%
VVOP1
PGOOD OV Trip Point
On FB Rising
108
111
115
%
VOVP2
Second OV Trip Point
On FB Rising; LS=On
118
122
125
%
PGOOD Pull-Down Resistance
IPGOOD=2 mA
125
Ω
2.03
ms
1
µA
RPGOOD
tPG,SSDELAY
PGOOD Soft-Start Delay
IPG,LEAK
PGOOD Leakage Current
0.82
1.42
Thermal Shutdown
TOFF
THYS
Thermal Shutdown Trip Point
Hysteresis
(2)
(2)
155
°C
15
°C
Internal Bootstrap Diode
VFBOOT
Forward Voltage
IF=10 mA
0.6
V
IR
Reverse Leakage
VR=24 V
1000
µA
Notes:
1. Device is 100% production tested at TA=25°C. Limits over that temperature are guaranteed by design.
2. Guaranteed by design; not production tested.
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
www.fairchildsemi.com
6
FAN2360AMPX — 10 A Synchronous Buck Regulator
Electrical Characteristics (Continued)
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Tested using evaluation board circuit shown in Figure 1 with VIN=19 V, VOUT=1.2 V, fSW=500 kHz, TA=25°C, and
no airflow; unless otherwise specified.
60
50
40
19VIN_1.05VOUT_500KHZ_0.72UH
30
19VIN_1.2VOUT_500KHZ_0.72UH
19VIN_3.3VOUT_500KHZ_1.8UH
20
40
12VIN_1.05VOUT_500KHZ_0.72UH
30
12VIN_1.2VOUT_500KHZ_0.72UH
12VIN_3.3VOUT_500KHZ_1.8UH
12VIN_5VOUT_500KHZ_1.8UH
10
0.01
0.1
1
Load Current (A)
10
0.01
Figure 5. Efficiency vs. Load Current with VIN=19 V
and fSW=500 kHz
100
100
90
90
80
80
70
70
60
50
19VIN_1.2VOUT_300KHZ_1.2UH
40
19VIN_1.2VOUT_500KHZ_0.72UH
30
19VIN_1.2VOUT_1MHZ_0.4UH
20
0.1
1
Load Current (A)
10
Figure 6. Efficiency vs. Load Current with VIN=12 V
and fSW=500kHz
Efficiency (%)
Efficiency (%)
50
20
19VIN_5VOUT_500KHZ_1.8UH
10
60
50
40
12VIN_1.2VOUT_300KHZ_1.2UH
30
12VIN_1.2VOUT_500KHZ_0.72UH
12VIN_1.2VOUT_1MHZ_0.4UH
20
19VIN_1.2VOUT_1.5MHZ_0.3UH
10
12VIN_1.2VOUT_1.5MHZ_0.3UH
10
0.01
0.1
1
Load Current (A)
10
0.01
Figure 7. Efficiency vs. Load Current with VIN=19 V
and VOUT=1.2 V
90
10
90
12VIN_1.2VOUT_1.5MHz_0.3uH
12VIN_1.2VOUT_1MHz_0.4uH
12VIN_1.2VOUT_500kHz_0.72uH
80
Case Temperature Rise (⁰C)
70
0.1
1
Load Current (A)
Figure 8. Efficiency vs. Load Current with VIN=12 V
and VOUT=1.2 V
19VIN_1.2VOUT_1.5MHz_0.3uH
19VIN_1.2VOUT_1MHz_0.4uH
19VIN_1.2VOUT_500kHz_0.72uH
80
Case Temperature Rise (⁰C)
60
60
50
40
30
20
10
70
60
50
40
30
20
10
0
0
0
5
10
Load Current (A)
0
15
Figure 9. Case Temperature Rise vs. Load Current
on 4 Layer PCB, 1 oz Copper, 7 cm x 7 cm
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
5
10
Load Current (A)
15
Figure 10. Case Temperature Rise vs. Load Current
on 4 Layer PCB, 1 oz Copper, 7 cm x 7 cm
www.fairchildsemi.com
7
FAN2360AMPX — 10 A Synchronous Buck Regulator
Typical Performance Characteristics
1.212
1.212
1.208
1.208
Output Voltage (V)
Output Voltage (V)
Tested using evaluation board circuit shown in Figure 1 with VIN=19 V, VOUT=1.2 V, fSW=500 kHz, TA=25°C, and
no airflow; unless otherwise specified.
1.204
1.2
1.196
12VIN_1.2Vout
19VIN_1.2Vout
1.192
1.204
1.2
1.196
0A_1.2VOUT[V]
10A_1.2VOUT[V]
1.192
1.188
1.188
0
2
4
6
8
7
10
9
11 13 15 17 19 21 23 25
Input Voltage (V)
Load Current (A)
Figure 12. Line Regulation
Figure 11. Load Regulation
EN (5V/div)
VIN=19V
IOUT=0A
EN (5V/div)
VIN=19V
IOUT=10A
Soft Start (0.5V/div)
Soft Start (0.5V/div)
VOUT (0.5V/div)
VOUT (0.5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
Time (500µs/div)
Time (500µs/div)
Figure 13. Startup Waveforms with 0 A Load Current Figure 14. Startup Waveforms with 10 A Load Current
EN (5V/div)
EN (5V/div)
VIN=19V
IOUT=0A
Soft Start (0.5V/div)
Soft Start (0.5V/div)
VOUT (0.5V/div)
VIN=19V
IOUT=10A
Vout Prebias
VOUT (0.5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
Time (500µs/div)
Time (200µs/div)
Figure 15. Shutdown Waveforms with 10 A Load
Current
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
Figure 16. Startup Waveforms with Prebias Voltage on
Output
www.fairchildsemi.com
8
FAN2360AMPX — 10 A Synchronous Buck Regulator
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=19 V, VOUT=1.2 V, fSW=500 kHz, TA=25°C, and
no airflow; unless otherwise specified.
VOUT (20mV/div)
VOUT (20mV/div)
VIN=19V
IOUT=0A
VIN=19V
IOUT=10A
VSW (10V/div)
VSW (10V/div)
Time (10µs/div)
Figure 17.
Time (10µs/div)
Static Load Ripple at Light Load
Figure 18.
VOUT (20mV/div)
Static Load Ripple at Full Load
VOUT (20mV/div)
VIN=19V
VOUT=1.2V
VIN=19V
VOUT=1.2V
IOUT (1A/div)
IOUT (1A/div)
Time (50µs/div)
Time (50µs/div)
Figure 19. Operation as Load Changes from 0 A to 2 A Figure 20. Operation as Load Changes from 2 A to 0 A
VOUT (20mV/div)
VOUT (20mV/div)
VIN=19V, VOUT=1.2V
IOUT from 5A to 10A, 2.5A/µs
VIN=19V, VOUT=1.2V
IOUT from 0A to 5A, 2.5A/µs
IOUT (5A/div)
IOUT (5A/div)
Time (100µs/div)
Time (100µs/div)
Figure 21. Load Transient from 0% to 50% Load
Current
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
Figure 22. Load Transient from 50% to 100% Load
Current
www.fairchildsemi.com
9
FAN2360AMPX — 10 A Synchronous Buck Regulator
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=19 V, VOUT=1.2 V, fSW=500 kHz, TA=25°C, and
no airflow; unless otherwise specified.
PGOOD (5V/div)
PGOOD indicates UVP
With VOUT falling in OCP
Level 2
Pull Vout to 3.8V
through 3Ω resistor
Vfb (0.5V/div) Level 1
VOUT (1V/div)
Vout (1V/div)
Soft Start (1V/div)
PGOOD (5V/div)
IL (10A/div)
IOUT=0A then short output
Vsw (10V/div)
Time (20µs/div)
Figure 23. Over-Current Protection with Heavy Load Figure 24. Over-Voltage Protection Level 1 and Level 2
Applied
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
www.fairchildsemi.com
10
FAN2360AMPX — 10 A Synchronous Buck Regulator
Typical Performance Characteristics
The FAN2360A uses a constant on-time modulation
architecture with a VIN feed-forward input to
accommodate a wide VIN range. This method provides
fixed switching frequency (fSW ) operation when the
inductor operates in Continuous Conduction Mode
(CCM) and variable frequency when operating in Pulse
Frequency Mode (PFM) at light loads. Additional
benefits include excellent line and load transient
response, cycle-by-cycle current limiting, and no loop
compensation is required.
At the beginning of each cycle, FAN2360A turns on the
high-side MOSFET (HS) for a fixed duration (tON). At the
end of tON, HS turns off for a duration (tOFF) determined
by the operating conditions. Once the FB voltage (VFB)
falls below the reference voltage (VREF), a new switching
cycle begins.
The modulator provides a minimum off-time (tOFF-MIN) of
320 ns to provide a guaranteed interval for low-side
MOSFET (LS) current sensing and PFM operation. tOFFMIN is also used to provide stability against multiple
pulsing and limits maximum switching frequency during
transient events.
where RFREQ is the frequency-setting resistor
described in the Setting Switching Frequency section;
CtON is the internal 2.2 pF capacitor; and ItON is the VIN
feed-forward current that generates the on-time.
The FAN2360A implements open-circuit detection on
the FREQ pin to protect the output from an infinitely long
on-time. In the event the FREQ pin is left floating,
switching of the regulator is disabled. The FAN2360A is
designed for VIN input range 4.5 to 24 V, fSW 200 kHz to
1.5 MHz, resulting in an ItON ratio exceeding 1 to 25.
As the ratio of VOUT to VIN increases, tOFF,min introduces a
limit on the maximum switching frequency as calculated
in the following equation, where the factor 1.2 is
included in the denominator to add some headroom for
transient operation:
Enable
Soft-Start (SS)
The enable pin is TTL compatible, which supports lowshutdown-current applications, such as notebooks. VCC
should be applied after VIN / PVIN is applied to the
circuit.
The EN pin can be directly driven by logic voltages of
5 V, 3.3 V, 2.5 V, etc. If the EN pin is driven by 5V logic,
a small current flows into the pin when the EN pin
voltage exceeds the internal clamp voltage of 4.3 V. To
eliminate clamp current flowing into the EN pin use a
voltage divider to limit the EN pin voltage to < 4 V.
A conventional soft-start ramp is implemented to provide
a controlled startup sequence of the output voltage. A
current is generated on the SS pin to charge an external
capacitor. The lesser of the voltage on the SS pin and
the reference voltage is used for output regulation.
To reduce VOUT ripple and achieve a smoother ramp of
the output voltage, tON is modulated during soft-start. tON
starts at 50% of the steady-state on-time (PWM Mode)
and ramps up to 100% gradually.
During normal operation, the SS voltage is clamped to
400 mV above the FB voltage. The clamp voltage drops
to 40 mV during an overload condition to allow the
converter to recover using the soft-start ramp once the
overload condition is removed. On-time modulation
during SS is disabled when an overload condition exists.
To maintain a monotonic soft-start ramp, the regulator is
forced into PFM Mode during soft-start. The minimum
frequency clamp is disabled during soft-start.
The nominal startup time is programmable through an
internal current source charging the external soft-start
capacitor CSS:
(3)
(4)
Constant On-time Modulation
The FAN2360A uses a constant on-time modulation
technique, in which the HS MOSFET is turned on for a
fixed time, set by the modulator, in response to the input
voltage and the frequency setting resistor. This on-time
is proportional to the desired output voltage, divided by
the input voltage. With this proportionality, the frequency
is essentially constant over the load range where
inductor current is continuous.
For buck converter in Continuous-Conduction Mode
(CCM), the switching frequency fSW is expressed as:
(5)
(1)
The on-time generator sets the on-time (tON) for the
high-side MOSFET, which results in the switching
frequency of the regulator during steady-state operation.
To maintain a relatively constant switching frequency
over a wide range of input conditions, the input voltage
information is fed into the on-time generator.
tON is determined by:
where:
CSS = External soft-start programming capacitor;
ISS = Internal soft-start charging current source,
10 A;
tSS = Soft-start time; and
VREF = 600 mV
For example; for 1 ms startup time, CSS=15 nF.
(2)
The soft-start option can be used for ratiometric tracking.
where ItON is:
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
When EN is LOW, the soft-start capacitor is discharged.
www.fairchildsemi.com
11
FAN2360AMPX — 10 A Synchronous Buck Regulator
Circuit Operation
FAN2360A allows the regulator to start on a pre-bias
output, VOUT, and ensures VOUT is not discharged during
the soft-start operation.
To guarantee no glitches on VOUT at the beginning of the
soft-start ramp, the LS is disabled until the first positivegoing edge of the PWM signal. The regulator is also
forced into PFM Mode during soft-start to ensure the
inductor current remains positive, reducing the
possibility of discharging the output voltage.
PVCC
The FAN2360A requires an external source connected
to PVCC to supply power to the internal gate drivers.
The PVCC pin should be bypassed with a 2.2 µF
ceramic capacitor.
VCC Bias Supply and UVLO
The VCC rail supplies power to the controller. It is
generally connected to the PVCC rail through a lowpass filter of a 10  resistor and 0.1 F capacitor to
minimize any noise sources from the driver supply.
An Under-Voltage Lockout (UVLO) circuit monitors the
VCC voltage to ensure proper operation. Once the VCC
voltage is above the UVLO threshold, the part begins
operation after an initialization routine of 50 µs. There is
no UVLO circuitry on either the PVCC or VIN rails.
Pulse Frequency Modulation (PFM)
One of the key benefits of using a constant on-time
modulation scheme is the seamless transitions in and
out of Pulse Frequency Modulation (PFM) Mode. The
PWM signal is not slave to a fixed oscillator and,
therefore, can operate at any frequency below the target
steady-state frequency. By reducing the frequency
during light-load conditions, the efficiency can be
significantly improved.
The FAN2360A provides a Zero-Crossing Detector
(ZCD) circuit to identify when the current in the inductor
reverses direction. To improve efficiency at light load,
the LS MOSFET is turned off around the zero crossing
to eliminate negative current in the inductor. For
predictable operation entering PFM mode the controller
waits for nine consecutive zero crossings before
allowing the LS MOSFET to turn off.
In PFM Mode, fSW varies or modulates proportionally to
the load; as load decreases, fSW also decreases. The
switching frequency, while the regulator is operating in
PFM, can be expressed as:
a minimum value of 18 kHz. The LS MOSFET is turned
on to discharge the output and trigger a new PWM cycle.
Protection Features
The converter output is monitored and protected against
over-current, over-voltage, under-voltage, and hightemperature conditions.
Over-Current Protection (OCP)
The FAN2360A uses current information through the LS
to implement valley-current limiting. While an OC event
is detected, the HS is prevented from turning on and the
LS is kept on until the current falls below the userdefined set point. Once the current is below the set
point, the HS is allowed to turn on.
During an OC event, the output voltage may droop if the
load current is greater than the current the converter is
providing. If the output voltage drops below the UV
threshold, an overload condition is triggered. During an
overload condition, the SS clamp voltage is reduced to
40 mV and the on-time is fixed at the steady-state
duration. By nature of the control method; as VOUT drops,
the switching frequency is lower due to the reduced rate
of inductor current decay during the off-time.
The ILIM pin has an open-detection circuit to provide
protection against operation without a current limit.
Under-Voltage Protection (UVP)
If VFB is below the under-voltage threshold of -11% VREF
(534 mV), the part enters UVP and PGOOD pulls LOW.
Over-Voltage Protection (OVP)
There are two levels of OV protection: +11% and +22%.
During an over-voltage event, PGOOD pulls LOW.
When VFB is > +11% of VREF (666 mV), both HS and LS
turn off. By turning off the LS during an OV event, V OUT
overshoot can be reduced when there is positive
inductor current by increasing the rate of discharge.
Once the VFB voltage falls below VREF, the latched OV
signal is cleared and operation returns to normal.
A second over-voltage detection is implemented to
protect the load from more serious failure. When VFB
rises +22% above the VREF (732 mV), the HS latches off
until a power cycle on VCC while the LS is forced on
until 530 mV of VFB.
Over-Temperature Protection (OTP)
FAN2360A incorporates an over-temperature protection
circuit that disables the converter when the die
temperature reaches 155°C. The IC restarts when the
die temperature falls below 140°C.
Power Good (PGOOD)
(6)
where L is inductance and IOUT is output load current.
Minimum Frequency Clamp
To maintain a switching frequency above the audible
range, the FAN2360A clamps the switching frequency to
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
The PGOOD pin serves as an indication to the system
that the output voltage of the regulator is stable and
within regulation. Whenever VOUT is outside the
regulation window or the regulator is at overtemperature (UV, OV, and OT), the PGOOD pin is
pulled LOW.
PGOOD is an open-drain output that asserts LOW when
VOUT is out of regulation or when OT is detected.
12
www.fairchildsemi.com
FAN2360AMPX -— 10 A Synchronous Buck Regulator
Startup on Pre-Bias
Stability
Setting the Output Voltage (VOUT)
Constant on-time stability consists of two parameters:
stability criterion and sufficient signal at VFB.
The output voltage VOUT is regulated by initiating a highside MOSFET on-time interval when the valley of the
divided output voltage appearing at the FB pin reaches
VREF. Since this method regulates at the valley of the
output ripple voltage, the actual DC output voltage on
VOUT is offset from the programmed output voltage by the
average value of the output ripple voltage. The initial VOUT
setting of the regulator can be programmed from 0.6 V to
5.5 V by an external resistor divider (R3 and R4):
Stability criterion is given by:
(7)
Sufficient signal requirement is given by:
(8)
where IIND is the inductor current ripple and VFB is
the ripple voltage on VFB, which should be ≥12 mV.
In certain applications, especially designs utilizing only
ceramic output capacitors, there may not be sufficient
ripple magnitude available on the feedback pin for
stable operation. In this case, an external circuit
consisting of 2 resistors (R2 and R6) and 2 capacitors
(C4 and C5) can be added to inject ripple voltage into
the FB pin (See Figure 1).
There are some specific considerations when selecting
the RCC ripple injector circuit. For typical applications,
use 4.99 kΩ for R6; the value of C4 can be selected as
0.1 µF and approximate values for R2 and C5 can be
determined using the following equations.
R2 must be small enough to develop 12 mV of ripple:
(13)
where VREF is 600 mV.
For example; for 1.2 V VOUT and 10 k R3, then R4 is
10 k. For 600 mV VOUT, R4 is left open. The final
output voltage, including the effect of the output ripple
voltage, can be approximated by the equation:
(14)
Setting the Switching Frequency (fSW)
fSW is programmed through external RFREQ as follows:
(15)
(9)
R2 must be selected such that the R2C4 time constant
enables stable operation:
(10)
The minimum value of C5 can be selected to minimize
the capacitive component of ripple appearing on the
feedback pin:
(11)
Using the minimum value of C5 generally offers the best
transient response, and 100 pF is a good initial value in
many applications. However, under some operating
conditions excessive pulse jitter may be observed. To
reduce jitter and improve stability, the value of C5 can
be increased:
where CtON=2.2 pF internal capacitor that generates
tON. For example; for fSW=500 kHz and VOUT=1.2 V,
select a standard value for RFREQ=54.9 k.
Inductor Selection
The inductor is typically selected based on the ripple
current (IL), which is approximately 25% to 45% of the
maximum DC load. The inductor current rating should
be selected such that the saturation and heating current
ratings exceed the intended currents encountered in the
application over the expected temperature range of
operation. Regulators that require fast transient
response use smaller inductance and higher current
ripple; while regulators that require higher efficiency
keep ripple current on the low side.
The inductor value is given by:
(16)
(12)
5V PVCC
The PVCC is supplied from an external source to provide
power to the drivers and VCC. It is crucial to keep this pin
decoupled to PGND with a ≥1 µF X5R or X7R ceramic
capacitor. Because VCC powers internal analog circuit, it
is filtered from PVCC with a 10 Ω resistor and 0.1 µF X7R
decoupling ceramic capacitor to AGND.
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
For example: for 19 V VIN, 1.2 V VOUT, 10 A load, 30%
IL, and 500 kHz fSW; L is 720 nH.
Input Capacitor Selection
Input capacitor CIN is selected based on voltage rating,
RMS current ICIN(RMS) rating, and capacitance. For
capacitors having DC voltage bias derating, such as
ceramic capacitors, higher rating is strongly
recommended. RMS current rating is given by:
13
www.fairchildsemi.com
FAN2360AMPX -— 10 A Synchronous Buck Regulator
Application Information
Current limit is implemented by sensing the inductor
valley current across the LS MOSFET VDS during the LS
on-time. The current limit comparator prevents a new
on-time from being started until the valley current is less
than the current limit.
where ILOAD-MAX is the maximum load current and D is
the duty cycle VOUT/VIN. The maximum ICIN(RMS) occurs at
50% duty cycle.
The capacitance is given by:
The set point is configured by connecting a resistor from
the ILIM pin to the SW pin. A trimmed current is output
onto the ILIM pin, which creates a voltage across the
resistor. When the voltage on ILIM goes negative, an
over-current condition is detected.
(18)
where VIN is the input voltage ripple, normally 1% of
VIN.
RILIM is calculated by:
For example; for VIN=19 V, VIN=120 mV, VOUT=1.2 V,
10 A load, and fSW=500 kHz; CIN is 9.8 µF and ICIN(RMS) is
2.4 ARMS. Select a minimum of two 10 µF25 V-rated
ceramic capacitors with X7R or similar dielectric,
recognizing that the capacitor DC bias characteristic
indicates that the capacitance value falls approximately
60% at VIN=19 V. Also, each 10 µF can carry over
3 ARMS in the frequency range from 100 kHz to 1 MHz,
exceeding the input capacitor current rating
requirements. An additional 0.1 µF capacitor may be
needed to suppress noise generated by high frequency
switching transitions.
(20)
where KILIM is the current source scale factor, and
IVALLEY is the inductor valley current when the current
limit threshold is reached. The factor 1.04 accounts
for the temperature offset of the LS MOSFET
compared to the control circuit.
With the constant on-time architecture, HS is always
turned on for a fixed on-time; this determines the peakto-peak inductor current.
Current ripple I is given by:
Output Capacitor Selection
(21)
Output capacitor COUT is also selected based on voltage
rating, RMS current ICOUT(RMS) rating, and capacitance.
For capacitors having DC voltage bias derating, such as
ceramic
capacitors,
higher
rating
is
highly
recommended.
From the equation above, the worst-case ripple occurs
during an output short circuit (where VOUT is 0 V). This
should be taken into account when selecting the current
limit set point.
When calculating COUT, usually the dominant
requirement is the current load step transient. If the
unloading transient requirement (IOUT transitioning from
HIGH to LOW), is satisfied, then the load transient (IOUT
transitioning LOW to HIGH), is also usually satisfied.
The unloading COUT calculation, assuming COUT has
negligible parasitic resistance and inductance in the
circuit path, is given by:
The FAN2360A uses valley-current sensing, the current
limit (IILIM) set point is the valley (IVALLEY).
The valley current level for calculating RILIM is given by:
(22)
where ILOAD (CL) is the DC load current when the
current limit threshold is reached.
(19)
For example: In a converter designed for 10 A steadystate operation and 3 A current ripple, the current-limit
threshold could be selected at 120% of ILOAD,(MAX) to
accommodate transient operation and inductor value
decrease under loading. As a result, ILOAD,(MAX) is 12 A,
IVALLEY=10.5 A, and RILIM is selected as a standard value
of 1.62 k
where IMAX and IMIN are maximum and minimum load
steps, respectively and VOUT is the voltage
overshoot, usually specified at 3to 5%.
For example: for VI=12 V, VOUT=1.2 V, 6 A IMAX, 2 A IMIN,
fSW=500 kHz, LOUT=720 nH, and 3% VOUT ripple of
36 mV; the COUT value is calculated to be 263 µF. This
capacitor requirement can be satisfied using six 47 µF,
6.3 V-rated X5R ceramic capacitors. This calculation
applies for load current slew rates that are faster than
the inductor current slew rate, which can be defined as
VOUT/L during the load current removal. For reducedload-current slew rates and/or reduced transient
requirements, the output capacitor value may be
reduced and comprised of low-cost 22 µF capacitors.
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
www.fairchildsemi.com
14
FAN2360AMPX — 10 A Synchronous Buck Regulator
Setting the Current Limit
(17)
In some applications, especially with higher input
voltage, the VSW ring voltage may exceed derating
guidelines of 80% to 90% of absolute rating for V SW. In
this situation a resistor can be connected in series with
boot capacitor (C3 in Figure 1) to reduce the turn-on
speed of the high side MOSFET to reduce the amplitude
of the VSW ring voltage. If necessary, a resistor and
capacitor snubber can be added from VSW to PGND to
reduce the magnitude of the ringing voltage. Please
contact Fairchild Customer Support for assistance
selecting a boot resistor or snubber circuit in
applications that operate above a 21 V typical input
voltage.
Power circuit loops that carry high currents should be
arranged to minimize the loop area. Primary focus
should be directed to minimize the loop for current flow
from the input capacitor to PVIN, through the internal
MOSFETs, and returning to the input capacitor. The
input capacitor should be placed as close to the PVIN
terminals as possible.
The current return path from PGND at the low-side
MOSFET source to the negative terminal of the input
capacitor can be routed under the inductor and also
through vias that connect the input capacitor and lowside MOSFET source to the PGND region under the
power portion of the IC.
Printed Circuit Board (PCB) Layout
Guidelines
The following points should be considered before
beginning a PCB layout using the FAN2360A. A sample
PCB layout from the evaluation board is shown in Figure
25-Figure 28 following the layout guidelines.
The SW node trace which connects the source of the
high-side MOSFET and the drain of the low-side
MOSFET to the inductor should be short and wide.
Power components consisting of the input capacitors,
output capacitors, inductor, and device should be placed
on a common side of the pcb in close proximity to each
other and connected using surface copper.
To control the voltage across the output capacitor, the
output voltage divider should be located close to the FB
pin, with the upper FB voltage divider resistor connected
to the positive side of the output capacitor, and the
bottom resistor should be connected to the AGND
portion of the device.
Sensitive analog components including SS, FB, ILIM,
FREQ, and EN should be placed away from the highvoltage switching circuits such as SW and BOOT, and
connected to their respective pins with short traces.
When using ceramic capacitor solutions with external
ramp injection circuitry (R2, C4, C5 in Figure 1), R2 and
C4 should be connected near the inductor, and coupling
capacitor C5 should be placed near FB pin to minimize
FB pin trace length.
The inner PCB layer closest to the device should have
Power Ground (PGND) under the power processing
portion of the device (PVIN, SW, and PGND). This inner
PCB layer should have a separate Analog Ground
(AGND) under the P1 pad and the associated analog
components. AGND and PGND should be connected
together near the IC between PGND pins 18-21 and
AGND pin 23 which connects to P1 thermal pad.
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
Decoupling capacitors for PVCC and VCC should be
located close to their respective device pins.
SW node connections to BOOT, ILIM, and ripple injection
resistor R2 should be made through separate traces.
www.fairchildsemi.com
15
FAN2360AMPX — 10 A Synchronous Buck Regulator
The AGND thermal pad (P1) should be connected to
AGND plane on inner layer using four 0.25 mm vias
spread under the pad. No vias are included under PVIN
(P2) and SW (P3) to maintain the PGND plane under
the power circuitry intact.
Boot Resistor
FAN2360AMPX — 10 A Synchronous Buck Regulator
Figure 25. Evaluation Board Top Layer Copper
Figure 26. Evaluation Board Inner Layer 1 Copper
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
www.fairchildsemi.com
16
FAN2360AMPX — 10 A Synchronous Buck Regulator
Figure 27.
Evaluation Board Inner Layer 2 Copper
Figure 28. Evaluation Board Bottom Layer Copper
© 2015 Fairchild Semiconductor Corporation
FAN2360AMPX • Rev. 1.0
www.fairchildsemi.com
17
5.50±0.10
26
18
1.05±0.10
17
27
0.25±0.05 (30X)
5.00±0.10
34
0.25±0.05
0.025±0.025
10
1
9
SEATING
PLANE
PIN#1
INDICATOR
SEE
DETAIL 'A'
1.58±0.01
(0.35)
SCALE: 2:1
2.18±0.01
(0.43)
0.50±0.01
9
1
(0.25)
0.40±0.01 (30X)
(0.35) 34
10
0.68±0.01
(0.35)
3.50±0.01
2.58±0.01
(1.75)
17
(0.75)
(0.33)
(0.35)
27
0.43±0.01
18
26
(0.35)
NOTES: UNLESS OTHERWISE SPECIFIED
A) NO INDUSTRY REGISTRATION APPLIES.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) DRAWING FILE NAME: MKT-PQFN34AREV2
F) FAIRCHILD SEMICONDUCTOR
(0.25)
(0.28) (3X)
(0.24)
1.75±0.01
5.70
2.18
1.58
0.55 (30X)
2.10
(0.35)
1.80
26
18
0.55
17
27
(1.75)
2.58
4.10
3.50
3.60
(1.85)
0.68
34
10
0.75
1
(0.30)
9
(0.35)
0.50±0.05
0.43
(0.08)
4.10
LAND PATTERN
RECOMMENDATION
0.20
0.30 (30X)
5.20
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