ATMEL AT49F2048-70TC 2-megabit 128k x 16 5-volt only cmos flash memory Datasheet

Features
• Single Voltage Operation
•
•
•
•
•
•
•
•
•
– 5V Read
– 5V Reprogramming
Fast Read Access Time - 70 ns
Internal Erase/Program Control
Sector Architecture
– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 8K Words (16K bytes) Parameter Blocks
– One 104K Words (208K bytes) Main Memory Array Block
Fast Sector Erase Time - 10 seconds
Word-By-Word Programming - 50 µs/Word
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 50 mA Active Current
– 300 µA CMOS Standby Current
Typical 10,000 Write Cycles
2-Megabit
(128K x 16)
5-volt Only
CMOS Flash
Memory
Description
The AT49F2048 is a 5-volt-only, 2 megabit Flash Memory organized as 128K words
of 16 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology,
the device offers access times to 70 ns with power dissipation of just 275 mW. When
deselected, the CMOS standby current is less than 300 µA.
To allow for simple in-system reprogrammability, the AT49F2048 does not require
high input voltages for programming. Five-volt-only commands determine the read
and programming operation of the device. Reading data out of the device is similar to
AT49F2048
(continued)
Pin Configurations
Pin Name
Function
A0 - A16
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
I/O0 - I/O15
Data
Inputs/Outputs
NC
No Connect
SOIC (SOP)
TSOP Top View
Type 1
0568D-A–9/97
1
reading from an EPROM; it has standard CE, OE, and WE
inputs to avoid bus connection. The AT49F2048 is a 5-voltonly, 2 megabit Flash Memory organized as 128K words
contention. Reprogramming the AT49F2048 is performed
by first erasing a block of data and then programming on a
word-by-word basis.
The device is erased by executing the erase command
sequence; the device internally controls the erase operation. The memory is divided into three blocks for erase
operations. There are two 8K word parameter block sections and one sector consisting of the boot block and the
main memory array block. The AT49F2048 is programmed
on a word-by-word basis.
The device has the capability to protect the data in the boot
block; this feature is enabled by a command sequence.
Once the boot block programming lockout feature is
enabled, the data in the boot block cannot be changed
when input levels of 5.5 volts or less are used. The typical
number of program and erase cycles is in excess of 10,000
cycles.
The optional 8K word boot block section includes a reprogramming lock out feature to provide data integrity. The
boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is protected
from being reprogrammed.
Block Diagram
Device Operation
READ: The AT49F2048 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don't care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca2
AT49F2048
tions used in the command sequences are not affected by
entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the Read or Standby mode, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin the boot block array can be reprogrammed even if the boot block program lockout feature
has been enabled (see Boot Block Programming Lockout
Override section).
ERASURE: Before a word can be reprogrammed, it must
be erased. The erased state of the memory bits is a logical
“1”. The entire device can be erased at one time by using a
6-byte software code.
AT49F2048
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC.
CHIP ERASE: If the boot block lockout has been enabled,
the Chip Erase function is disabled; sector erases for the
parameter blocks and main memory block will still operate.
After the full chip erase the device will return back to read
mode. Any command during chip erase will be ignored.
SECTOR ERASE: As an alternative to a full chip erase,
the device is organized into three sectors that can be individually erased. There are two 8K word parameter block
sections and one sector consisting of the boot block and
the main memory array block. The Sector Erase command
is a six bus cycle operation. The sector address is latched
on the falling WE edge of the sixth cycle while the 30H data
input command is latched at the rising edge of WE. The
sector erase starts after the rising edge of WE of the sixth
cycle. The erase operation is internally controlled; it will
automatically time to completion. When the boot block programming lockout feature is not enabled, the boot block
and the main memory block will erase together (from the
same sector erase command). Once the boot region has
been protected, only the main memory array sector will
erase when its sector erase command is issued.
WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical “0”) on a word-byword basis. Programming is accomplished via the internal
device command register and is a 4 bus cycle operation.
The device will automatically generate the required internal
program pulses.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The DATA polling feature may
also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 01FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the software product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lockout feature has been enabled and the block cannot be programmed. The software product identification exit code
should be used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming
lockout by taking the RESET pin to 12 volts. By doing this
protected boot block data can be altered through a chip
erase, sector erase or word programming. When the
RESET pin is brought back to TTL levels the boot block
programming lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F2048 features DATA polling
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all
outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give
a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT49F2048
provides another method for determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F2048 in
the following ways: (a) V CC sense: if V CC is below 3.8V
3
(typical), the program function is inhibited. (b) VCC power
on delay: once VCC has reached the VCC sense level, the
device will automatically time out 10 ms (typical) before
programming. (c) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Noise
filter: pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
Command Definition (in Hex)(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
Sector Erase
6
Word Program
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
SA(4)(5)
30
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Boot Block
Lockout(2)
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
40
Product ID
Entry
3
5555
AA
2AAA
55
5555
90
Product ID
Exit(3)
3
5555
AA
2AAA
55
5555
F0
Product ID
Exit(3)
1
xxxx
F0
Notes:
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex)
2. The 8K word boot sector has the address range 00000H to 01FFFH.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses:
SA = 03XXX for PARAMETER BLOCK 1
SA = 05XXX for PARAMETER BLOCK 2
SA = 1FXXX for MAIN MEMORY ARRAY
5. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase
together (from the same sector erase command). Once the boot region has been protected, only the main memory array
sector will erase when its sector erase command is issued.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground ............................ -0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
4
AT49F2048
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
AT49F2048
DC and AC Operating Range
AT49F2048-70
AT49F2048-90
AT49F2048-12
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
5V ± 10%
5V ± 10%
5V ± 10%
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply
Operating Modes
Mode
CE
OE
WE
RESET
Ai
I/O
VIL
VIL
VIH
VIH
Ai
DOUT
VIL
VIH
VIL
VIH
Ai
DIN
X
VIH
X
High Z
Read
Program/Erase
(2)
Standby/Write Inhibit
VIH
X
(1)
Program Inhibit
X
X
VIH
VIH
Program Inhibit
X
VIL
X
VIH
Output Disable
X
VIH
X
VIH
Reset
X
X
X
VIL
High Z
X
High Z
Product Identification
Hardware
VIL
VIL
VIH
Software(5)
Notes:
VIH
A1 - A16 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
A1 - A16 = VIL, A9 = VH,(3)
A0 = VIH
Device Code(4)
VIH
A0 = VIL, A1 - A16 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A16 = VIL
Device Code(4)
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 82H
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
300
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ICC(1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
VOH2
Note:
Min
2.0
V
.45
V
1. In the erase mode, ICC is 90 mA.
5
AC Read Characteristics
AT49F2048-70
Min
Max
AT49F2048-90
Symbol
Parameter
Min
Max
tACC
Address to Output Delay
70
tCE(1)
CE to Output Delay
70
tOE(2)
OE to Output Delay
35
0
40
tDF(3)(4)
CE or OE to Output Float
0
25
0
25
tOH
Output Hold from OE, CE
or Address, whichever occurred first
0
0
AT49F2048-12
Min
Max
Units
90
120
ns
90
120
ns
0
50
ns
0
30
ns
0
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
HIGH Z
OUTPUT
Notes:
OUTPUT
VALID
1.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2.
OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address
change without impact on tACC.
3.
tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4.
This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
(f = 1 MHz, T = 25°C)(1)
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
6
1. This parameter is characterized and is not 100% tested.
AT49F2048
ns
AT49F2048
AC Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Set-up Time
10
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
100
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
10
ns
tWPH
Write Pulse Width High
100
ns
AC Word Load Waveforms
WE Controlled
OE
tOES
tOEH
ADDRESS
tAS
tAH
tCH
CE
tCS
WE
tWP
tDS
tWPH
tDH
DATA IN
CE Controlled
OE
tOES
tOEH
ADDRESS
tAS
tAH
tCH
WE
tCS
CE
tWP
tDS
tWPH
tDH
DATA IN
7
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
tBP
Word Programming Time
50
µs
tAS
Address Set-up Time
10
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
10
ns
tWP
Write Pulse Width
100
ns
tWPH
Write Pulse Width High
100
ns
tEC
Erase Cycle Time
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP
tWPH
tBP
WE
tAS
tAH
A0-A16
5555
tDH
2AAA
5555
ADDRESS
5555
tDS
AA
DATA
55
INPUT
DATA
A0
AA
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
tWP
tWPH
WE
tAS
A0-A16
tAH
5555
tDH
2AAA
5555
5555
2AAA
Note 2
tDS
DATA
Notes:
8
tEC
AA
55
80
AA
55
Note 3
WORD 0
WORD 1
WORD 2
WORD 3
WORD 4
WORD 5
1.
OE must be high only when WE and CE are both low.
2.
For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See
note 4 under command definitions.)
3.
For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
AT49F2048
AT49F2048
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tWR
Write Recovery Time
Notes:
Min
Typ
Max
Units
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
tWR
HIGH Z
I/O7
A0-A16
An
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Delay(2)
tOE
OE to Output
tOEHP
OE High Pulse
tWR
Notes:
Typ
Max
Units
ns
Write Recovery Time
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
tOEH
tOEHP
OE
tDH
I/O6
Notes:
tOE
tWR
HIGH Z
1.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2.
Beginning and ending state of I/O6 will vary.
3.
Any address location may be used but the address should not vary.
9
Software Product
Identification Entry(1)
Boot Block Lockout
Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
Software Product
Identification Exit(1)(6)
LOAD DATA AA
TO
ADDRESS 5555
OR
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA F0
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
10
1.
Data Format: I/O15 - I/O8 (Don’t Care);
I/O7 - I/O0 (Hex)
Address Format: A14 - A0 (Hex).
2.
A1 - A16 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3.
The device does not remain in identification mode if
powered down.
4.
The device returns to standard operation mode.
5.
Manufacturer Code: 1FH
Device Code: 82H
6.
Either one of the Product ID Exit commands can be
used.
AT49F2048
PAUSE 1 second
Notes:
1.
Data Format: I/O15 - I/O8 (Don’t Care);
I/O7 - I/O0 (Hex)
Address Format: A14 - A0 (Hex).
2.
Boot block lockout feature enabled.
AT49F2048
Ordering Information(1)
tACC
ICC (mA)
(ns)
Active
Standby
70
50
90
120
Note:
Ordering Code
Package
Operation Range
0.3
AT49F2048-70RC
AT49F2048-70TC
44R
48T
Commercial
(0° to 70°C)
50
0.3
AT49F2048-70RI
AT49F2048-70TI
44R
48T
Industrial
(-40° to 85°C)
50
0.3
AT49F2048-90RC
AT49F2048-90TC
44R
48T
Commercial
(0° to 70°C)
50
0.3
AT49F2048-90RI
AT49F2048-90TI
44R
48T
Industrial
(-40° to 85°C)
50
0.3
AT49F2048-12RC
AT49F2048-12TC
44R
48T
Commercial
(0° to 70°C)
50
0.3
AT49F2048-12RI
AT49F2048-12TI
44R
48T
Industrial
(-40° to 85°C)
1. The AT49F2048 has as optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher
address range should contact Atmel.
Package Type
44R
44-Lead, 0.525" Wide, Plastic Gull-Wing Small Outline Package (SOIC/SOP)
48T
48-Lead, Thin Small Outline Package (TSOP)
11
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