a FEATURES Charge Balancing ADC 24 Bits No Missing Codes ⴞ0.0015% Nonlinearity Two-Channel Programmable Gain Front End Gains from 1 to 128 Differential Inputs Low-Pass Filter with Programmable Filter Cutoffs Ability to Read/Write Calibration Coefficients Bidirectional Microcontroller Serial Interface Internal/External Reference Option Single or Dual Supply Operation Low Power (25 mW typ) with Power-Down Mode (7 mW typ) Signal Conditioning ADC AD7710* FUNCTIONAL BLOCK DIAGRAM AVDD DVDD REF REF IN (–) IN (+) REF OUT 2.5V REFERENCE 4.5mA CHARGE-BALANCING A/D CONVERTER AIN1(+) AIN1(–) M U X AIN2(+) AUTO-ZEROED PGA MODULATOR DIGITAL FILTER SYNC A = 1 – 128 AIN2(–) AVDD CLOCK GENERATION 20mA APPLICATIONS Weigh Scales Thermocouples Process Control Smart Transmitters Chromatography VBIAS AVDD MCLK IN MCLK OUT SERIAL INTERFACE CONTROL REGISTER IOUT OUTPUT REGISTER AD7710 AGND DGND VSS RFS TFS MODE SDATA SCLK DRDY A0 GENERAL DESCRIPTION The AD7710 is a complete analog front end for low frequency measurement applications. The device accepts low level signals directly from a strain gage or transducer and outputs a serial digital word. It employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. The input signal is applied to a proprietary programmable gain front end based around an analog modulator. The modulator output is processed by an on-chip digital filter. The first notch of this digital filter can be programmed via the on-chip control register allowing adjustment of the filter cutoff and settling time. The part features two differential analog inputs and a differential reference input. Normally, one of the channels will be used as the main channel with the second channel used as an auxiliary input to periodically measure a second voltage. It can be operated from a single supply (by tying the VSS pin to AGND) provided that the input signals on the analog inputs are more positive than –30 mV. By taking the VSS pin negative, the part can convert signals down to –VREF on its inputs. The AD7710 thus performs all signal conditioning and conversion for a single or dual channel system. The AD7710 is ideal for use in smart, microcontroller based systems. Input channel selection, gain settings and signal polarity can be configured in software using the bidirectional serial port. The AD7710 contains self-calibration, system calibration and background calibration options and also allows the user to read and write the on-chip calibration registers. CMOS construction ensures low power dissipation and a software programmable power down mode reduces the standby power consumption to only 7 mW typical. The part is available in a 24-lead, 0.3 inch-wide, plastic and hermetic dual-in-line package (DIP) as well as a 24-lead small outline (SOIC) package. PRODUCT HIGHLIGHTS 1. The programmable gain front end allows the AD7710 to accept input signals directly from a strain gage or transducer, removing a considerable amount of signal conditioning. 2. The AD7710 is ideal for microcontroller or DSP processor applications with an on-chip control register which allows control over filter cutoff, input gain, channel selection, signal polarity and calibration modes. 3. The AD7710 allows the user to read and write the on-chip calibration registers. This means that the microcontroller has much greater control over the calibration procedure. 4. No missing codes ensures true, usable, 23-bit dynamic range coupled with excellent ± 0.0015% accuracy. The effects of temperature drift are eliminated by on-chip self-calibration, which removes zero-scale and full-scale errors. *Protected by U.S. Patent No. 5,134,401. REV. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 (AV = +5␣ V ⴞ 5%; DV = +5␣ V ⴞ 5%; V = 0␣ V or –5 V ⴞ 5%; REF IN(+) = +2.5␣ V; AD7710–SPECIFICATIONS REF␣ IN(–) = AGND; MCLK IN = 10␣ MHz unless otherwise noted. All specifications T to T unless otherwise noted.) DD DD SS MIN Parameter STATIC PERFORMANCE No Missing Codes A, S Versions1 Units 24 22 18 15 12 Output Noise Tables I and II Integral Nonlinearity @ +25°C ± 0.0015 ± 0.003 TMIN to TMAX See Note 4 Positive Full-Scale Error2, 3 1 Full-Scale Drift 5 0.3 See Note 4 Unipolar Offset Error2 Unipolar Offset Drift 5 0.5 0.25 See Note 4 Bipolar Zero Error2 0.5 Bipolar Zero Drift5 0.25 Gain Drift 2 Bipolar Negative Full-Scale Error 2 @ +25°C ± 0.003 ± 0.006 TMIN to TMAX 1 Bipolar Negative Full-Scale Drift5 0.3 ANALOG INPUTS/REFERENCE INPUTS Input Common-Mode Rejection (CMR) Common-Mode Voltage Range6 Normal-Mode 50 Hz Rejection 7 Normal-Mode 60 Hz Rejection 7 Common-Mode 50 Hz Rejection 7 Common-Mode 60 Hz Rejection 7 DC Input Leakage Current7 @ +25°C TMIN to TMAX Sampling Capacitance7 Analog Inputs8 Input Voltage Range 9 Input Sampling Rate, fS Reference Inputs REF IN(+) – REF IN(–) Voltage 11 Input Sampling Rate, fS MAX Conditions/Comments µV/°C typ µV/°C typ Guaranteed by Design. For Filter Notches ≤ 60 Hz For Filter Notch = 100 Hz For Filter Notch = 250 Hz For Filter Notch = 500 Hz For Filter Notch = 1 kHz Depends on Filter Cutoffs and Selected Gain Filter Notches ≤ 60 Hz Typically ± 0.0003% Excluding Reference Excluding Reference. For Gains of 1, 2 Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 µV/°C typ µV/°C typ For Gains of 1, 2 For Gains of 4, 8, 16, 32, 64, 128 µV/°C typ µV/°C typ ppm/°C typ % of FSR max % of FSR max µV/°C typ µV/°C typ For Gains of 1, 2 For Gains of 4, 8, 16, 32, 64, 128 Bits min Bits min Bits min Bits min Bits min % of FSR max % of FSR max Excluding Reference Typically ± 0.0006% Excluding Reference. For Gains of 1, 2 Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 At DC and AV DD = 5 V At DC and AV DD = 10 V 100 90 VSS to AVDD 100 100 150 150 10 1 20 dB min dB min V min to V max dB min dB min dB min dB min pA max nA max pF max 0 to +VREF10 ± VREF See Table III nom nom +2.5 to +5 V min to V max For Specified Performance. Part Is Functional with Lower VREF Voltages For Filter Notches of 10, 25, 50 Hz, ± 0.02 × fNOTCH For Filter Notches of 10, 30, 60 Hz, ± 0.02 × fNOTCH For Filter Notches of 10, 25, 50 Hz, ± 0.02 × fNOTCH For Filter Notches of 10, 30, 60 Hz, ± 0.02 × fNOTCH For Normal Operation. Depends on Gain Selected Unipolar Input Range (B/U Bit of Control Register = 1) Bipolar Input Range (B/U Bit of Control Register = 0) fCLK IN/256 NOTES 1 Temperature ranges are as follows: A Version, –40°C to +85°C; S Version, –55°C to +125°C. See also Note 16. 2 Applies after calibration at the temperature of interest. 3 Positive full-scale error applies to both unipolar and bipolar input ranges. 4 These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration or background calibration. 5 Recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6 This common-mode voltage range is allowed provided that the input voltage on AIN(+) and AIN(–) does not exceed AV DD + 30 mV and VSS – 30 mV. 7 These numbers are guaranteed by design and/or characterization. 8 The analog inputs present a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended source resistance depends on the selected gain (see Tables IV and V). 9 The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The absolute voltage on the analog inputs should not go more positive than AV DD + 30 mV or go more negative than V SS – 30 mV. 10 VREF = REF IN(+) – REF IN(–). 11 The reference input voltage range may be restricted by the input voltage range requirement on the V BIAS input. –2– REV. F AD7710 Parameter REFERENCE OUTPUT Output Voltage Initial Tolerance @ +25°C Drift Output Noise Line Regulation (AVDD) Load Regulation External Current VBIAS INPUT12 Input Voltage Range A, S Versions1 Units 2.5 ±1 20 30 1 1.5 1 V nom % max ppm/°C typ µV typ pk-pk Noise 0.1 Hz to 10 Hz Bandwidth mV/V max mV/mA max Maximum Load Current 1 mA mA max AVDD – 0.85 × VREF or AV DD – 3.5 V max or AV DD – 2.1 VSS + 0.85 × VREF or VSS + 3 V min or VSS + 2.1 65 to 85 V min dB typ ± 10 µΑ max 0.8 2.0 V max V min 0.8 3.5 V max V min LOGIC OUTPUTS VOL, Output Low Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance 13 0.4 DVDD – 1 ± 10 9 V max V min µA max pF typ TRANSDUCER BURNOUT Current Initial Tolerance @ +25°C Drift 4.5 ± 10 0.1 µA nom % typ %/°C typ COMPENSATION CURRENT Output Current Initial Tolerance @ +25°C Drift Line Regulation (AVDD) Load Regulation Output Compliance 20 ±4 35 20 20 AVDD – 2 µA nom µA max ppm/°C typ nA/V max nA/V max V max (1.05 × VREF)/GAIN –(1.05 × VREF)/GAIN –(1.05 × VREF)/GAIN 0.8 × VREF/GAIN (2.1 × VREF )/GAIN V max V max V max V min V max VBIAS Rejection LOGIC INPUTS Input Current All Inputs Except MCLK IN VINL, Input Low Voltage VINH, Input High Voltage MCLK IN Only VINL, Input Low Voltage VINH, Input High Voltage SYSTEM CALIBRATION Positive Full-Scale Calibration Limitl4 Negative Full-Scale Calibration Limit l4 Offset Calibration Limits 15 Input Span 15 V max Conditions/Comments See VBIAS Input Section Whichever Is Smaller: +5 V/–5 V or +10 V/0 V Nominal AV DD/VSS Whichever Is Smaller; +5 V/0 V Nominal AVDD/VSS See VBIAS Input Section Whichever Is Greater; +5 V/–5 V or +10 V/0 V Nominal AV DD/VSS Whichever Is Greater; +5 V/0 V Nominal AV DD/VSS Increasing with Gain ISINK = 1.6 mA ISOURCE = 100 µA AVDD = +5 V GAIN Is the Selected PGA Gain (Between 1 and 128) GAIN Is the Selected PGA Gain (Between 1 and 128) GAIN Is the Selected PGA Gain (Between 1 and 128) GAIN Is the Selected PGA Gain (Between 1 and 128) GAIN Is the Selected PGA Gain (Between 1 and 128) NOTES 12 The AD7710 is tested with the following V BIAS voltages. With AVDD = +5 V and V SS = 0 V, VBIAS = +2.5 V; with AV DD = +10 V and VSS = 0 V, VBIAS = +5 V and with AVDD = +5 V and V SS = –5 V, VBIAS = 0 V. 13 Guaranteed by design, not production tested. 14 After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale then the device will output all 0s. 15 These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV DD + 30 mV or go more negative than V SS – 30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. REV. F –3– AD7710–SPECIFICATIONS Parameter POWER REQUIREMENTS Power Supply Voltages AVDD Voltage16 DVDD Voltage17 AVDD-VSS Voltage Power Supply Currents AVDD Current DVDD Current VSS Current Power Supply Rejection18 Positive Supply (AVDD & DV DD) Negative Supply (VSS ) Power Dissipation Normal Mode Standby (Power-Down) Mode A, S Versionsl Units Conditions/Comments +5 to +10 +5 +10.5 V nom V nom V max ± 5% for Specified Performance ± 5% for Specified Performance For Specified Performance 4 4.5 1.5 mA max mA max mA max See Note 19 90 dB typ dB typ 45 52.5 15 mW max mW max mW max VSS = –5 V Rejection w.r.t. AGND; Assumes V BIAS Is Fixed AVDD = DVDD = +5 V, V SS = 0 V; Typically 25 mW AVDD = DVDD = +5 V, V SS = –5 V; Typically 30 mW AVDD = DVDD = +5 V, V SS = 0 V or –5 V; Typically 7 mW NOTES 16The AD7710 is specified with a 10 MHz clock for AV DD voltages of +5 V ±5%. It is specified with an 8 MHz clock for AV DD voltages greater than 5.25 V and less than 10.5 V. 17The ±5% tolerance on the DV DD input is allowed provided that DV DD does not exceed AV DD by more than 0.3 V. 18Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 10 Hz, 30 Hz or 60 Hz. 19PSRR depends on gain: Gain of 1: 70 dB typ; Gain of 2: 75 dB typ; Gain of 4: 80 dB typ; Gains of 8 to 128: 85 dB typ. These numbers can be improved ( to 95 dB typ) by deriving the VBIAS voltage (via Zener diode or reference) from the AV DD supply. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* (TA = +25°C, unless otherwise noted) AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +12 V AVDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +12 V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +12 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +12 V DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –6 V VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –6 V Analog Input Voltage to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to AVDD + 0.3 V Reference Input Voltage to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to AVDD + 0.3 V REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD Digital Input Voltage to DGND . . . . . –0.3 V to AVDD + 0.3 V Digital Output Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V Operating Temperature Range Commercial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW Derates Above +75°C . . . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7710 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model1 Temperature Range Package Options2 AD7710AN AD7710AR AD7710AQ AD7710SQ EVAL-AD7710EB –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C Evaluation Board N-24 R-24 Q-24 Q-24 NOTES 1 To order MIL-STD-883B, Class B processed parts, add /883B to par number. Contact our local sales office for military data sheet and availability. 2 N = Plastic DIP; Q = Cerdip; R = SOIC. –4– REV. F AD7710 3 1, 2 (DVDD = +5␣ V ⴞ 5%; AVDD = +5␣ V or +10 V ⴞ 5%; VSS = 0 V or –5 V ⴞ 10%; AGND = DGND = TIMING CHARACTERISTICS Parameter 0 V; fCLK IN =10␣ MHz; Input Logic 0 = 0 V, Logic 1 = DV DD, unless otherwise noted) Limit at TMIN, T MAX (A, S Versions) Units Conditions/Comments 400 10 8 0.4 × tCLK IN 0.4 × tCLK IN 50 50 1000 kHz min MHz max MHz max ns min ns min ns max ns max ns min Master Clock Frequency: Crystal Oscillator or Externally Supplied for Specified Performance AVDD = +5 V ± 5% AVDD = +5.25 V to +10.5 V Master Clock Input Low Time. tCLK IN = 1/fCLK IN Master Clock Input High Time Digital Output Rise Time. Typically 20 ns Digital Output Fall Time. Typically 20 ns SYNC Pulsewidth 0 0 2 × tCLK IN 0 4 × tCLK IN + 20 4 × tCLK IN + 20 tCLK IN/2 tCLK IN/2 + 30 tCLK IN/2 3 × tCLK IN/2 50 0 4 × tCLK IN + 20 4 × tCLK IN 0 10 ns min ns min ns min ns min ns max ns max ns min ns max ns nom ns nom ns min ns min ns max ns min ns min ns min fCLK IN4, 5 tCLK IN LO tCLK IN HI tr 6 tf 6 t1 Self-Clocking Mode t2 t3 t4 t5 t6 t77 t87 t9 t10 t14 t15 t16 t17 t18 t19 REV. F DRDY to RFS Setup Time DRDY to RFS Hold Time A0 to RFS Setup Time A0 to RFS Hold Time RFS Low to SCLK Falling Edge Data Access Time (RFS Low to Data Valid) SCLK Falling Edge to Data Valid Delay SCLK High Pulsewidth SCLK Low Pulsewidth A0 to TFS Setup Time A0 to TFS Hold Time TFS to SCLK Falling Edge Delay Time TFS to SCLK Falling Edge Hold Time Data Valid to SCLK Setup Time Data Valid to SCLK Hold Time –5– AD7710 Parameter External Clocking Mode fSCLK t20 t21 t22 t23 t247 t257 t26 t27 t28 t298 t30 t318 t32 t33 t34 t35 t36 Limit at TMIN, T MAX (A, S Versions) Units Conditions/Comments fCLK IN/5 0 0 2 × tCLK IN 0 4 × tCLK IN 10 2 × tCLK IN + 20 2 × tCLK IN 2 × tCLK IN tCLK IN + 10 10 tCLK IN + 10 10 5 × tCLK IN/2 + 50 0 0 4 × tCLK IN 2 × tCLK IN – SCLK High 30 MHz max ns min ns min ns min ns min ns max ns min ns max ns min ns min ns max ns min ns max ns min ns max ns min ns min ns min ns min ns min Serial Clock Input Frequency DRDY to RFS Setup Time DRDY to RFS Hold Time A0 to RFS Setup Time A0 to RFS Hold Time Data Access Time (RFS Low to Data Valid) SCLK Falling Edge to Data Valid Delay SCLK High Pulsewidth SCLK Low Pulsewidth SCLK Falling Edge to DRDY High SCLK to Data Valid Hold Time RFS/TFS to SCLK Falling Edge Hold Time RFS to Data Valid Hold Time A0 to TFS Setup Time A0 to TFS Hold Time SCLK Falling Edge to TFS Hold Time Data Valid to SCLK Setup Time Data Valid to SCLK Hold Time NOTES 1 Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figures 10 to 13. 3 The AD7710 is specified with a 10 MHz clock for AV DD voltages of +5 V ± 5%. It is specified with an 8 MHz clock for AV DD voltages greater than 5.25 V and less than 10.5 V. 4 CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7710 is not in STANDBY mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 5 The AD7710 is production tested with f CLK IN at 10 MHz (8 MHz for AV DD > +5.25 V). It is guaranteed by characterization to operate at 400 kHz. 6 Specified using 10% and 90% points on waveform of interest. 7 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 8 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. Specifications subject to change without notice. PIN CONFIGURATION DIP AND SOIC 1.6mA TO OUTPUT PIN +2.1V 100pF SCLK 1 24 DGND MCLK IN 2 23 DVDD MCLK OUT 3 22 SDATA A0 4 21 DRDY SYNC 5 MODE 6 AIN1(+) 7 AIN1(–) 8 17 IOUT AIN2(+) 9 16 REF OUT AIN2(–) 10 15 REF IN(+) 200mA Figure 1. Load Circuit for Access Time and Bus Relinquish Time VSS 11 AVDD 12 –6– AD7710 20 RFS 19 TFS TOP VIEW (Not to Scale) 18 AGND 14 REF IN(–) 13 VBIAS REV. F AD7710 PIN FUNCTION DESCRIPTIONS Pin Mnemonic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Function SCLK Serial Clock. Logic Input/Output depending on the status of the MODE pin. When MODE is high, the device is in its self-clocking mode and the SCLK pin provides a serial clock output. This SCLK becomes active when RFS or TFS goes low and it goes high impedance when either RFS or TFS returns high or when the device has completed transmission of an output word. When MODE is low, the device is in its external clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7710 in smaller batches of data. MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal or external clock. A crystal can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz. MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT. A0 Address Input. With this input low, reading and writing to the device is to the control register. With this input high, access is to either the data register or the calibration registers. SYNC Logic Input which allows for synchronization of the digital filters when using a number of AD7710s. It resets the nodes of the digital filter. MODE Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its external clocking mode. AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input is connected to an output current source which can be used to check that an external transducer has burned out or gone open circuit. This output current source can be turned on/off via the control register. AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input. AIN2(+) Analog Input Channel 2. Positive input of the programmable gain differential analog input. AIN2(–) Analog Input Channel 2. Negative input of the programmable gain differential analog input. Analog Negative Supply, 0 V to –5 V. Tied to AGND for single supply operation. The input voltage on VSS AIN1 or AIN2 should not go > 30 mV negative w.r.t. VSS for correct operation of the device. Analog Positive Supply Voltage, +5 V to +10 V. AVDD Input Bias Voltage. This input voltage should be set such that VBIAS + 0.85 × VREF < AVDD and VBIAS – VBIAS 0.85 × VREF > VSS where VREF is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AVDD , and VSS. Thus with AVDD = +5 V and VSS = 0 V, it can be tied to REF OUT; with AVDD = +5 V and VSS = –5 V, it can be tied to AGND while with AVDD = +10 V, it can be tied to +5 V. REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AVDD and VSS provided REF IN(+) is greater than REF IN(–). REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–). REF IN(+) can lie anywhere between AVDD and VSS. REF OUT Reference Output. The internal +2.5 V reference is provided at this pin. This is a single ended output which is referred to AGND. It is a buffered output which is capable of providing 1 mA to an external load. Compensation Current Output. A 20 µA constant current is provided at this pin. This current can be used in IOUT association with an external thermistor to provide cold junction compensation in thermocouple applications. This current can be turned on or off via the control register. AGND Ground reference point for analog circuitry. REV. F –7– AD7710 Pin Mnemonic Function 19 TFS 20 RFS 21 DRDY 22 SDATA 23 24 DVDD DGND Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data word is written to the part. Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the external clocking mode, the SDATA line becomes active after RFS goes low. Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin will return high upon completion of transmission of a full output word. DRDY is also used to indicate when the AD7710 has completed its on-chip calibration sequence. Serial Data. Input/Output with serial data being written to either the control register or the calibration registers and serial data being accessed from the control register, calibration registers or the data register. During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low). During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs. Digital Supply Voltage, +5 V. DVDD should not exceed AV DD by more than 0.3 V in normal operation. Ground reference point for digital circuitry. TERMINOLOGY POSITIVE FULL-SCALE OVERRANGE INTEGRAL NONLINEARITY Positive Full-Scale Overrange is the amount of overhead available to handle input voltages on AIN(+) input greater than AIN(–) +VREF/GAIN (for example, noise peaks or excess voltages due to system gain errors in system calibration routines) without introducing errors due to overloading the analog modulator or to overflowing the digital filter. This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 LSB below the first code transition (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB above the last code transition (111 . . . 110 to 111 . . . 111). The error is expressed as a percentage of full scale. NEGATIVE FULL-SCALE OVERRANGE Positive Full-Scale Error is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage (AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar and bipolar analog input ranges. This is the amount of overhead available to handle voltages on AIN(+) below AIN(–) –VREF/GAIN without overloading the analog modulator or overflowing the digital filter. Note that the analog input will accept negative voltage peaks even in the unipolar mode provided that AIN(+) is greater than AIN(–) and greater than VSS – 30 mV. UNIPOLAR OFFSET ERROR OFFSET CALIBRATION RANGE Unipolar Offset Error is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when operating in the unipolar mode. In the system calibration modes, the AD7710 calibrates its offset with respect to the analog input. The Offset Calibration Range specification defines the range of voltages that the AD7710 can accept and still calibrate offset accurately. POSITIVE FULL-SCALE ERROR BIPOLAR ZERO ERROR This is the deviation of the midscale transition (0111 . . . 111 to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB) when operating in the bipolar mode. FULL-SCALE CALIBRATION RANGE BIPOLAR NEGATIVE FULL-SCALE ERROR INPUT SPAN This is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5 LSB) when operating in the bipolar mode. In system calibration schemes, two voltages applied in sequence to the AD7710’s analog input define the analog input range. The input span specification defines the minimum and maximum input voltages from zero to full scale that the AD7710 can accept and still calibrate gain accurately. This is the range of voltages that the AD7710 can accept in the system calibration mode and still calibrate full scale correctly. –8– REV. F AD7710 CONTROL REGISTER (24 BITS) A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the contents of the control register. The control register is 24 bits wide and when writing to the register 24 bits of data must be written otherwise the data will not be loaded to the control register. In other words, it is not possible to write just the first 12 bits of data into the control register. If more than 24 clock pulses are provided before TFS returns high, then all clock pulses after the 24th clock pulse are ignored. Similarly, a read operation from the control register should access 24 bits of data. MSB MD2 MD1 MD0 G2 G1 G0 CH PD WL IO BO FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 B/U FS0 LSB Operating Mode MD2 MD1 MD0 Operating Mode 0 0 0 Normal Mode. This is the normal mode of operation of the device whereby a read to the device with A0 high accesses data from the data register. This is the default condition of these bits after the internal power on reset. 0 0 1 Activate Self-Calibration. This activates self-calibration on the channel selected by CH. This is a one-step calibration sequence, and when complete, the part returns to normal mode (with MD2, MD1, MD0 of the control register returning to 0, 0, 0). The DRDY output indicates when this self-calibration is complete. For this calibration type, the zero-scale calibration is done internally on shorted (zeroed) inputs and the full-scale calibration is done internally on VREF. 0 1 0 Activate System Calibration. This activates system calibration on the channel selected by CH. This is a two-step calibration sequence, with the zero-scale calibration done first on the selected input channel and DRDY indicating when this zero-scale calibration is complete. The part returns to normal mode at the end of this first step in the two-step sequence. 0 1 1 Activate System Calibration. This is the second step of the system calibration sequence with full-scale calibration being performed on the selected input channel. Once again, DRDY indicates when the fullscale calibration is complete. When this calibration is complete, the part returns to normal mode. 1 0 0 Activate System Offset Calibration. This activates system offset calibration on the channel selected by CH. This is a one-step calibration sequence and, when complete, the part returns to normal mode with DRDY indicating when this system offset calibration is complete. For this calibration type, the zero-scale calibration is done on the selected input channel and the full-scale calibration is done internally on VREF. 1 0 1 Activate Background Calibration. This activates background calibration on the channel selected by CH. If the background calibration mode is on, then the AD7710 provides continuous self-calibration of the reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of six. Its major advantage is that the user does not have to worry about recalibrating the device when there is a change in the ambient temperature. In this mode, the shorted (zeroed) inputs and VREF, as well as the analog input voltage, are continuously monitored and the calibration registers of the device are automatically updated. 1 1 0 Read/Write Zero-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of the zero-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high writes data to the zero-scale calibration coefficients of the channel selected by CH. The word length for reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control register. Therefore, when writing to the calibration register 24 bits of data must be written, otherwise the new data will not be transferred to the calibration register. 1 1 1 Read/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of the full-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high writes data to the full-scale calibration coefficients of the channel selected by CH. The word length for reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control register. Therefore, when writing to the calibration register 24 bits of data must be written, otherwise the new data will not be transferred to the calibration register. REV. F –9– AD7710 PGA GAIN G2 G1 G0 Gain 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 16 32 64 128 (Default Condition After the Internal Power-On Reset) Channel Selection CH 0 1 Channel AIN1 AIN2 (Default Condition After the Internal Power-On Reset) Power-Down PD 0 1 Normal Operation Power-Down (Default Condition After the Internal Power-On Reset) Word Length WL Output Word Length 0 1 16-Bit 24-Bit (Default Condition After Internal Power-On Reset) Output Compensation Current IO 0 1 Off On (Default Condition After Internal Power-On Reset) Burn-Out Current BO 0 1 Off On (Default Condition After Internal Power-On Reset) Bipolar/Unipolar Selection (Both Inputs) B/U 0 1 Bipolar Unipolar (Default Condition After Internal Power-On Reset) Filter Selection (FS11–FS0) The on-chip digital filter provides a Sinc3 (or (Sinx/x)3) filter response. The 12 bits of data programmed into these bits determine the filter cutoff frequency, the position of the first notch of the filter and the data rate for the part. In association with the gain selection, it also determines the output noise (and hence the effective resolution) of the device. The first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (fCLK IN/512)/code where code is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 2,000. With the nominal fCLK IN of 10 MHz, this results in a first notch frequency range from 9.76 Hz to 1.028 kHz. To ensure correct operation of the AD7710, the value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I and II and Figure 2 show the effect of the filter notch frequency and gain on the effective resolution of the AD7710. The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz, then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 1 kHz, a new word is available every 1 ms. The settling time of the filter to a full-scale step input change is worst case 4 × 1/(output data rate). This settling time is to 100% of the final value. For example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is 80 ms max. If the first notch is at 1 kHz, the settling time of the filter to a full-scale input step is 4 ms max. This settling time can be reduced to 3 × l/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with SYNC low, the settling time will be 3 × l/(output data rate). If a change of channels takes place, the settling time is 3 × l/(output data rate) regardless of the SYNC input. The –3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter –3 dB frequency = 0.262 × first notch frequency. –10– REV. F AD7710 Tables I and II show the output rms noise for some typical notch and –3 dB frequencies. The numbers given are for the bipolar input ranges with a VREF of +2.5 V. These numbers are typical and are generated with an analog input voltage of 0 V. The output noise from the part comes from two sources. First, there is the electrical noise in the semiconductor devices used in the implementation of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quantization noise is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter notch settings (below 60 Hz approximately) tend to be device noise dominated while higher notch settings are dominated by quantization noise. Changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic improvement in noise performance than it does in the device noise dominated region as shown in Table I. Furthermore, quantization noise is added after the PGA, so effective resolution is independent of gain for the higher filter notch frequencies. Meanwhile, device noise is added in the PGA and, therefore, effective resolution suffers a little at high gains for lower notch frequencies. At the lower filter notch settings (below 60 Hz), the no missing codes performance of the device is at the 24-bit level. At the higher settings, more codes will be missed until at 1 kHz notch setting, no missing codes performance is only guaranteed to the 12-bit level. However, since the effective resolution of the part is 10.5 bits for this filter notch setting, this no missing codes performance should be more than adequate for all applications. The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale. This does not remain constant with increasing gain or with increasing bandwidth. Table II shows the same table as Table I except that the output is now expressed in terms of effective resolution (the magnitude of the rms noise with respect to 2 × VREF/GAIN, i.e., the input full scale). It is possible to do post filtering on the device to improve the output data rate for a given –3 dB frequency and also to further reduce the output noise (see Digital Filtering section). Table I. Output Noise vs. Gain and First Notch Frequency First Notch of Filter & O/P Data Rate 1 –3␣ dB Frequency Gain of 1 Gain of 2 Typical Output RMS Noise (V) Gain of Gain of Gain of 4 8 16 Gain of 32 Gain of 64 Gain of 128 10␣ Hz2 25␣ Hz2 30␣ Hz2 50␣ Hz2 60␣ Hz2 100␣ Hz3 250␣ Hz3 500␣ Hz3 1␣ kHz3 2.62␣ Hz 6.55␣ Hz 7.86␣ Hz 13.1 Hz 15.72 Hz 26.2 Hz 65.5 Hz 131 Hz 262 Hz 1.0 1.8 2.5 4.33 5.28 13 130 0.6 × 103 3.1 × 103 0.78 1.1 1.31 2.06 2.36 6.4 75 0.26 × 10 3 1.6 × 103 0.48 0.63 0.84 1.2 1.33 3.7 25 140 0.7 × 10 3 0.25 0.41 0.43 0.46 0.62 0.9 4 25 120 0.25 0.38 0.4 0.46 0.6 0.65 2.7 15 70 0.25 0.38 0.4 0.46 0.56 0.65 1.7 8 40 0.33 0.5 0.57 0.64 0.87 1.8 12 70 0.29 × 10 3 0.25 0.44 0.46 0.54 0.63 1.1 7.5 35 180 NOTES 1 The default condition (after the internal power-on reset) for the first notch of filter is 60 Hz. 2 For these filter notch frequencies, the output rms noise is primarily dominated by device noise and as a result is independent of the value of the reference voltage. Therefore, increasing the reference voltage will give an increase in the effective resolution of the device (i.e., the ratio of the rms noise to the input full scale is increased since the output rms noise remains constant as the input full scale increases). 3 For these filter notch frequencies, the output rms noise is dominated by quantization noise and as a result is proportional to the value of the reference voltage. Table II. Effective Resolution vs. Gain and First Notch Frequency First Notch of Filter & O/P Data Rate –3␣ dB Frequency Gain of 1 10␣ Hz 25␣ Hz 30␣ Hz 50␣ Hz 60␣ Hz 100␣ Hz 250␣ Hz 500␣ Hz 1␣ kHz 2.62␣ Hz 6.55␣ Hz 7.86␣ Hz 13.1␣ Hz 15.72␣ Hz 26.2␣ Hz 65.5␣ Hz 131␣ Hz 262␣ Hz 22.5 21.5 21 20 20 18.5 15 13 10.5 Gain of 2 Effective Resolution 1 (Bits) Gain of Gain of Gain of 4 8 16 Gain of 32 Gain of 64 Gain of 128 21.5 21 21 20 20 18.5 15 13 10.5 21.5 21 20.5 20 20 18.5 15.5 13 11 19.5 18.5 18.5 18.5 18 17.5 15.5 12.5 10.5 18.5 17.5 17.5 17.5 17 17 15 12.5 10 17.5 16.5 16.5 16.5 16 16 14.5 12.5 10 21 20 20 19.5 19.5 18.5 15.5 13 11 20.5 19.5 19.5 19 19 18 15.5 13 11 NOTE 1Effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 × V REF /GAIN). The above table applies for a V REF of +2.5 V and resolution numbers are rounded to the nearest 0.5 LSB. REV. F –11– AD7710 Figure 2 gives similar information to that outlined in Table I. In this plot, the output rms noise is shown for the full range of available cutoffs frequencies rather than for some typical cutoff frequencies as in Tables I and II. The numbers given in these plots are typical values at 25°C. 1k 10k GAIN OF 1 GAIN OF 2 GAIN OF 16 GAIN OF 4 100 GAIN OF 8 OUTPUT NOISE – mV OUTPUT NOISE – mV 1k 100 10 GAIN OF 64 GAIN OF 128 10 1 1 0.1 10 GAIN OF 32 100 1k 0.1 10 10k 1k 100 NOTCH FREQUENCY – Hz NOTCH FREQUENCY – Hz 10k Figure 2b. Plot of Output Noise vs. Gain and Notch Frequency (Gains of 16 to 128) Figure 2a. Plot of Output Noise vs. Gain and Notch Frequency (Gains of 1 to 8) CIRCUIT DESCRIPTION The AD7710 is a sigma-delta A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in weigh scale, industrial control or process control applications. It contains a sigma-delta (or charge balancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter and a bidirectional serial communications port. The basic connection diagram for the part is shown in Figure 3. This shows the AD7710 in the external clocking mode with both the AVDD and DVDD pins of the AD7710 being driven from the analog +5 V supply. Some applications will have separate supplies for both AVDD and DVDD, and in some of these cases, the analog supply will exceed the +5 V digital supply (see Power Supplies and Grounding section). The part contains two programmable gain differential analog input channels. The gain range is from 1 to 128 allowing the part to accept unipolar signals of between 0 mV to +20 mV and 0 V to +2.5 V or bipolar signals in the range from ± 20 mV to ± 2.5 V when the reference input voltage equals +2.5 V. The input signal to the selected analog input channel is continuously sampled at a rate determined by the frequency of the master clock, MCLK IN, and the selected gain (see Table III). A charge-balancing A/D converter (Sigma-Delta Modulator) converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. The programmable gain function on the analog input is also incorporated in this sigmadelta modulator with the input sampling frequency being modified to give the higher gains. A sinc3 digital low-pass filter processes the output of the sigma-delta modulator and updates the output register at a rate determined by the first notch frequency of this filter. The output data can be read from the serial port randomly or periodically at any rate up to the output register update rate. The first notch of this digital filter (and hence its –3 dB frequency) can be programmed via an on-chip control register. The programmable range for this first notch frequency is from 9.76 Hz to 1.028 kHz, giving a programmable range for the –3 dB frequency of 2.58 Hz to 269 Hz. –12– ANALOG +5V SUPPLY 10mF 0.1mF 0.1mF AVDD DVDD DATA READY DRDY DIFFERENTIAL ANALOG INPUT AIN1(+) DIFFERENTIAL ANALOG INPUT AIN2(+) AIN1(–) AIN2(–) AD7710 IOUT ANALOG GROUND AGND DIGITAL GROUND DGND VSS REF OUT REF IN(+) TFS TRANSMIT (WRITE) RFS RECEIVE (READ) SDATA SERIAL DATA SCLK SERIAL CLOCK ADDRESS INPUT A0 MODE SYNC +5V MCLK OUT VBIAS REF IN(–) MCLK IN Figure 3. Basic Connection Diagram REV. F AD7710 The AD7710 provides a number of calibration options which can be programmed via the on-chip control register. A calibration cycle may be initiated at any time by writing to this control register. The part can perform self-calibration using the on-chip calibration microcontroller and SRAM to store calibration parameters. Other system components may also be included in the calibration loop to remove offset and gain errors in the input channel using the system calibration mode. Another option is a background calibration mode where the part continuously performs self-calibration and updates the calibration coefficients. Once the part is in this mode, the user does not have to worry about issuing periodic calibration commands to the device or asking the device to recalibrate when there is a change in the ambient temperature or power supply voltage. The AD7710 gives the user access to the on-chip calibration registers allowing the microprocessor to read the device’s calibration coefficients and also to write its own calibration coefficients to the part from prestored values in E2PROM. This gives the microprocessor much greater control over the AD7710’s calibration procedure. It also means that the user can verify that the device has performed its calibration correctly by comparing the coefficients after calibration with prestored values in E2PROM. The AD7710 samples the input signal at a frequency of 39 kHz or greater (see Table III). As a result, the quantization noise is spread over a much wider frequency than that of the band of interest. The noise in the band of interest is reduced still further by analog filtering in the modulator loop, which shapes the quantization noise spectrum to move most of the noise energy to frequencies outside the bandwidth of interest. The noise performance is thus improved from this 1-bit level to the performance outlined in Tables I and II and in Figure 2. The output of the comparator provides the digital input for the 1-bit DAC, so that the system functions as a negative feedback loop that tries to minimize the difference signal. The digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the comparator. It can be retrieved as a parallel binary data word using a digital filter. Sigma-delta ADCs are generally described by the order of the analog low-pass filter. A simple example of a first order sigmadelta ADC is shown in Figure 5. This contains only a first order low-pass filter or integrator. It also illustrates the derivation of the alternative name for these devices: Charge Balancing ADCs. DIFFERENTIAL AMPLIFIER The AD7710 can be operated in single supply systems provided that the analog input voltage does not go more negative than –30 mV. For larger bipolar signals, a VSS of –5 V is required by the part. For battery operation, the AD7710 also offers a software-programmable standby mode that reduces idle power consumption to typically 7 mW. INTEGRATOR COMPARATOR VI N +FS DAC THEORY OF OPERATION –FS The general block diagram of a sigma-delta ADC is shown in Figure 4. It contains the following elements: Figure 5. Basic Charge-Balancing ADC 1. A sample-hold amplifier. 2. A differential amplifier or subtracter. 3. An analog low-pass filter. 4. A 1-bit A/D converter (comparator). 5. A 1-bit DAC. 6. A digital low-pass filter. COMPARATOR S/H AMP ANALOG LOW-PASS FILTER DIGITAL FILTER DAC DIGITAL DATA Figure 4. General Sigma-Delta ADC In operation, the analog signal sample is fed to the subtracter, along with the output of the 1-bit DAC. The filtered difference signal is fed to the comparator, whose output samples the difference signal at a frequency many times that of the analog signal sampling frequency (oversampling). It consists of a differential amplifier (whose output is the difference between the analog input and the output of a 1-bit DAC), an integrator and a comparator. The term, charge-balancing, comes from the fact that this system is a negative feedback loop that tries to keep the net charge on the integrator capacitor at zero, by balancing charge injected by the input voltage with charge injected by the 1-bit DAC. When the analog input is zero, the only contribution to the integrator output comes from the 1-bit DAC. For the net charge on the integrator capacitor to be zero, the DAC output must spend half its time at +FS and half its time at –FS. Assuming ideal components, the duty cycle of the comparator will be 50%. When a positive analog input is applied, the output of the 1-bit DAC must spend a larger proportion of the time at +FS, so the duty cycle of the comparator increases. When a negative input voltage is applied, the duty cycle decreases. The AD7710 uses a second order sigma-delta modulator and a digital filter that provides a rolling average of the sampled output. After power-up, or if there is a step change in the input voltage, there is a settling time that must elapse before valid data is obtained. Oversampling is fundamental to the operation of sigma-delta ADCs. Using the quantization noise formula for an ADC: SNR = (6.02 × number of bits + 1.76) dB, a 1-bit ADC or comparator yields an SNR of 7.78 dB. REV. F –13– AD7710 0 Input Sample Rate The modulator sample frequency for the device remains at fCLK IN/512 (19.5 kHz @ fCLK IN = 10 MHz) regardless of the selected gain. However, gains greater than ×1 are achieved by a combination of multiple input samples per modulator cycle and a scaling of the ratio of reference capacitor to input capacitor. As a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see Table III). The effective input impedance is 1/C × fS where C is the input sampling capacitance and fS is the input sample rate. –20 –40 –60 GAIN – dB –80 –100 –120 –140 –160 –180 –200 Table III. Input Sampling Frequency vs. Gain –220 –240 Gain Input Sampling Frequency (fS) 1 2 4 8 16 32 64 128 fCLK IN/256 (39 kHz @ fCLK IN = 10 MHz) 2 × fCLK IN /256 (78 kHz @ fCLK IN = 10 MHz) 4 × fCLK IN /256 (156 kHz @ fCLK IN = 10 MHz) 8 × fCLK IN /256 (312 kHz @ fCLK IN = 10 MHz) 8 × fCLK IN /256 (312 kHz @ fCLK IN = 10 MHz) 8 × fCLK IN /256 (312 kHz @ fCLK IN = 10 MHz) 8 × fCLK IN /256 (312 kHz @ fCLK IN = 10 MHz) 8 × fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz) DIGITAL FILTERING The AD7710’s digital filter behaves like a similar analog filter, with a few minor differences. On the other hand, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7710 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 5% above the analog input range. If noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. This will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). The cutoff frequency of the digital filter is determined by the value loaded to bits FS0 to FS11 in the control register. At the maximum clock frequency of 10 MHz, the minimum cutoff frequency of the filter is 2.58 Hz while the maximum programmable cutoff frequency is 269 Hz. Figure 6 shows the filter frequency response for a cutoff frequency of 2.62 Hz which corresponds to a first filter notch frequency of 10 Hz. This is a (sinx/x)3 response (also called sinc3) that provides >100 dB of 50 Hz and 60 Hz rejection. Programming a different cutoff frequency via FS0–FS11 does not alter the profile of the filter response, it changes the frequency of the notches as outlined in the Control Register section. 10 20 30 40 50 FREQUENCY – Hz 60 70 Figure 6. Frequency Response of AD7710 Filter Since the AD7710 contains this on-chip, low-pass filtering, there is a settling time associated with step function inputs, and data on the output will be invalid after a step change until the settling time has elapsed. The settling time depends upon the notch frequency chosen for the filter. The output data rate equates to this filter notch frequency and the settling time of the filter to a full-scale step input is four times the output data period. In applications using both input channels, the settling time of the filter must be allowed to elapse before data from the second channel is accessed. Post Filtering First, since digital filtering occurs after the A-to-D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Filter Characteristics 0 The on-chip modulator provides samples at a 19.5 kHz output rate. The on-chip digital filter decimates these samples to provide data at an output rate which corresponds to the programmed first notch frequency of the filter. Since the output data rate exceeds the Nyquist criterion, the output rate for a given bandwidth will satisfy most application requirements. However, there may be some applications which require a higher data rate for a given bandwidth and noise performance. Applications which need this higher data rate will require some post filtering following the digital filter of the AD7710. For example, if the required bandwidth is 7.86 Hz but the required update rate is 100 Hz, the data can be taken from the AD7710 at the 100 Hz rate giving a –3 dB bandwidth of 26.2 Hz. Post filtering can be applied to this to reduce the bandwidth and output noise, to the 7.86 Hz bandwidth level, while maintaining an output rate of 100 Hz. Post filtering can also be used to reduce the output noise from the device for bandwidths below 2.62 Hz. At a gain of 128, the output rms noise is 250 nV. This is essentially device noise or white noise, and since the input is chopped, the noise has a flat frequency response. By reducing the bandwidth below 2.62 Hz, the noise in the resultant passband can be reduced. A reduction in bandwidth by a factor of two results in a √2 reduction in the output rms noise. This additional filtering will result in a longer settling time. –14– REV. F AD7710 Antialias Considerations The digital filter does not provide any rejection at integer multiples of the modulator sample frequency (n × 19.5 kHz, where n = 1, 2, 3 . . . ). This means that there are frequency bands, ± f3 dB wide (f3 dB is cutoff frequency selected by FS0 to FS11) where noise passes unattenuated to the output. However, due to the AD7710’s high oversampling ratio, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. In any case, because of the high oversampling ratio a simple, RC, single pole filter is generally sufficient to attenuate the signals in these bands on the analog input and thus provide adequate antialiasing filtering. If passive components are placed in front of the AD7710, care must be taken to ensure that the source impedance is low enough so as not to introduce gain errors in the system. The dc input impedance for the AD7710 is over 1 GΩ. The input appears as a dynamic load which varies with the clock frequency and with the selected gain (see Figure 7). The input sample rate, as shown in Table III, determines the time allowed for the analog input capacitor, CIN, to be charged. External impedances result in a longer charge time for this capacitor and this may result in gain errors being introduced on the analog inputs. Table IV shows the allowable external resistance/capacitance values such that no gain error to the 16-bit level is introduced while Table V shows the allowable external resistance/capacitance values such that no gain error to the 20-bit level is introduced. Both inputs of the differential input channels look into similar input circuitry. AD7710 RINT 7kV TYP HIGH IMPEDANCE >1GV AIN CINT ANALOG INPUT FUNCTIONS Analog Input Ranges Both analog inputs are differential, programmable gain, input channels which can handle either unipolar or bipolar input signals. The common-mode range of these inputs is from VSS to AVDD , provided that the absolute value of the analog input voltage lies between VSS –30 mV and AVDD +30 mV. The dc input leakage current is 10 pA maximum at 25°C (± 1 nA over temperature). This results in a dc offset voltage developed across the source impedance. However, this dc offset effect can be compensated for by a combination of the differential input capability of the part and its system calibration mode. Burnout Current The AIN1(+) input of the AD7710 contains a 4.5 µA current source which can be turned on/off via the control register. This current source can be used in checking that a transducer has not burned out or gone open circuit before attempting to take measurements on that channel. If the current is turned on and allowed flow into the transducer and a measurement of the input voltage on the AIN1 input is taken, it can indicate that the transducer has burned out or gone open circuit. For normal operation, this burnout current is turned off by writing a 0 to the BO bit in the control register. Output Compensation Current The AD7710 also contains a feature which can enable the user to implement cold junction compensation in thermocouple applications. This can be achieved using the output compensation current from the IOUT pin of the device. Once again, this current can be turned on/off via the control register. Writing a 1 to the IO bit of the control register enables this compensation current. 11.5pF TYP VBIAS SWITCHING FREQ DEPENDS ON fCLKIN AND SELECTED GAIN Figure 7. Analog Input Impedance Table IV. Typical External Series Resistance That Will Not Introduce 16-Bit Gain Error External Capacitance (pF) Gain 0 50 100 500 1000 5000 1 2 4 8–128 184 kΩ 88.6 kΩ 41.4 kΩ 17.6 kΩ 45.3 kΩ 22.1 kΩ 10.6 kΩ 4.8 kΩ 27.1 kΩ 13.2 kΩ 6.3 kΩ 2.9 kΩ 7.3 kΩ 3.6 kΩ 1.7 kΩ 790 Ω 4.1 kΩ 2.0 kΩ 970 Ω 440 Ω 1.1 kΩ 560 Ω 270 Ω 120 Ω Table V. Typical External Series Resistance That Will Not Introduce 20-Bit Gain Error External Capacitance (pF) Gain 0 50 100 500 1000 5000 1 2 4 8–128 145 kΩ 70.5 kΩ 31.8 kΩ 13.4 kΩ 34.5 kΩ 16.9 kΩ 8.0 kΩ 3.6 kΩ 20.4 kΩ 10 kΩ 4.8 kΩ 2.2 kΩ 5.2 kΩ 2.5 kΩ 1.2 kΩ 550 Ω 2.8 kΩ 1.4 kΩ 670 Ω 300 Ω 700 Ω 350 Ω 170 Ω 80 Ω REV. F The numbers in the above tables assume a full-scale change on the analog input. In any case, the error introduced due to longer charging times is a gain error which can be removed using the system calibration capabilities of the AD7710 provided that the resultant span is within the span limits of the system calibration techniques for the AD7710. The compensation current provides a 20 µA constant current source which can be used in association with a thermistor or a diode to provide cold junction compensation. A common method of generating cold junction compensation is to use a temperature dependent current flowing through a fixed resistor to provide a voltage that is equal to the voltage developed across the cold junction at any temperature in the expected ambient range. In this case, the temperature coefficient of the compensation current is so low compared with the temperature coefficient of the thermistor that it can be considered constant with temperature. The temperature variation is then provided by the variation of the thermistor’s resistance with temperature. Normally, the cold junction compensation will be implemented by applying the compensation voltage to the second input channel of the AD7710. Periodic conversion of this channel gives the user a voltage which corresponds to the cold junction compensation voltage. This can be used to implement cold junction compensation in software with the result from the thermocouple input being adjusted according to the result in the compensation channel. Alternatively, the voltage can be subtracted from the input voltage in an analog fashion, thereby using only one channel of the AD7710. –15– AD7710 Bipolar/Unipolar Inputs The two analog inputs on the AD7710 can accept either unipolar or bipolar input voltage ranges. Bipolar or unipolar options are chosen by programming the B/U bit of the control register. This programs both channels for either unipolar or bipolar operation. Programming the part for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding. The data coding is binary for unipolar inputs and offset binary for bipolar inputs. The input channels are differential and, as a result, the voltage to which the unipolar and bipolar signals are referenced is the voltage on the AIN(–) input. For example, if AIN(–) is +1.25 V and the AD7710 is configured for unipolar operation with a gain of 1 and a VREF of +2.5 V, the input voltage range on the AIN(+) input is +1.25 V to +3.75 V. If AIN(–) is +1.25 V and the AD7710 is configured for bipolar mode with a gain of 1 and a VREF of +2.5 V, the analog input range on the AIN(+) input is –1.25 V to +3.75 V. the reference noise in the bandwidth of interest is excessive, it can degrade the performance of the AD7710. Using the on-chip reference as the reference source for the part (i.e., connecting REF OUT to REF IN) results in somewhat degraded output noise performance from the AD7710 for portions of the noise table that are dominated by the device noise. The on-chip reference noise effect is eliminated in ratiometric applications where the reference is used to provide the excitation voltage for the analog front end. The connection scheme, shown in Figure 8, is recommended when using the on-chip reference. Recommended reference voltage sources for the AD7710 include the AD580 and AD680 2.5 V references. REF OUT AD7710 REF IN (+) REF IN (–) REFERENCE INPUT/OUTPUT The AD7710 contains a temperature compensated +2.5 V reference which has an initial tolerance of ± 1%. This reference voltage is provided at the REF OUT pin and it can be used as the reference voltage for the part by connecting the REF OUT pin to the REF IN(+) pin. This REF OUT pin is a single-ended output, referenced to AGND, which is capable of providing up to 1 mA to an external load. In applications where REF OUT is connected to REF IN(+), REF IN(–) should be tied to AGND to provide the nominal +2.5 V reference for the AD7710. The reference inputs of the AD7710 REF IN(+) and REF IN(–), provide a differential reference input capability. The commonmode range for these differential inputs is from VSS to AVDD. The nominal differential voltage, VREF (REF IN(+)–REF IN(–)), is +2.5 V for specified operation, but the reference voltage can go to +5 V with no degradation in performance provided that the absolute value of REF IN(+) and REF IN(–) does not exceed its AVDD and VSS limits and the VBIAS input voltage range limits are obeyed. The part is also functional with VREF voltage down to 1 V but with degraded performance as the output noise will, in terms of LSB size, be larger. REF IN(+) must always be greater than REF IN(–) for correct operation of the AD7710. Both reference inputs provide a high impedance, dynamic load similar to the analog inputs. The maximum dc input leakage current is 10 pA (± 1 nA over temperature) and source resistance may result in gain errors on the part. The reference inputs look like the analog input (see Figure 7). In this case, RINT is 5 kΩ typ and CINT varies with gain. The input sample rate is fCLK IN/256 and does not vary with gain. For gains of 1 to 8 CINT is 20 pF; for a gain of 16 it is 10 pF; for a gain of 32 it is 5 pF; for a gain of 64 it is 2.5 pF; and for a gain of 128 it is 1.25 pF. The digital filter of the AD7710 removes noise from the reference input just as it does with the analog input, and the same limitations apply regarding lack of noise rejection at integer multiples of the sampling frequency. The output noise performance outlined in Tables I and II assumes a clean reference. If Figure 8. REF OUT/REF IN Connection VBIAS Input The VBIAS input determine at what voltage the internal analog circuitry is biased. It essentially provides the return path for analog currents flowing in the modulator and, as such, it should be driven from a low impedance point to minimize errors. For maximum internal headroom, the VBIAS voltage should be set halfway between AVDD and VSS. The difference between AVDD and (VBIAS + 0.85 × VREF) determines the amount of headroom the circuit has at the upper end, while the difference between VSS and (VBIAS – 0.85 × VREF) determines the amount of headroom the circuit has at the lower end. Care should be taken in choosing a VBIAS voltage to ensure that it stays within prescribed limits. For single +5 V operation, the selected VBIAS voltage must ensure that VBIAS ± 0.85 × VREF does not exceed AVDD or VSS or that the VBIAS voltage itself is greater than VSS + 2.1 V and less than AVDD – 2.1 V. For single +10 V operation or dual ± 5 V operation, the selected VBIAS voltage must ensure that VBIAS ± 0.85 × VREF does not exceed AVDD or VSS or that the VBIAS voltage itself is greater than VSS + 3 V or less than AVDD –3 V. For example, with AVDD = +4.75 V, VSS = 0 V and VREF = +2.5 V, the allowable range for the VBIAS voltage is +2.125 V to +2.625 V. With AVDD = +9.5 V, VSS = 0 V and VREF = +5 V, the range for VBIAS is +4.25 V to +5.25 V. With AVDD = +4.75 V, VSS = –4.75 V and VREF = +2.5 V, the VBIAS range is –2.625 V to +2.625 V. The VBIAS voltage does have an effect on the AVDD power supply rejection performance of the AD7710. If the VBIAS voltage tracks the AVDD supply, it improves the power supply rejection from the AVDD supply line from 80 dB to 95 dB. Using an external Zener diode, connected between the AVDD line and VBIAS, as the source for the VBIAS voltage gives the improvement in AVDD power supply rejection performance. –16– REV. F AD7710 USING THE AD7710 ACCURACY SYSTEM DESIGN CONSIDERATIONS Sigma-delta ADCs, like VFCs and other integrating ADCs, do not contain any source of nonmonotonicity and inherently offer no missing codes performance. The AD7710 achieves excellent linearity by the use of high quality, on-chip silicon dioxide capacitors, which have a very low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper stabilized techniques in its input stage. To ensure excellent performance over time and temperature, the AD7710 uses digital calibration techniques which minimize offset and gain error. The AD7710 operates differently from successive approximation ADCs or integrating ADCs. Since it samples the signal continuously, like a tracking ADC, there is no need for a start convert command. The output register is updated at a rate determined by the first notch of the filter and the output can be read at any time, either synchronously or asynchronously. Clocking The AD7710 requires a master clock input, which may be an external TTL/CMOS compatible clock signal applied to the MCLK IN pin with the MCLK OUT pin left unconnected. Alternatively, a crystal of the correct frequency can be connected between MCLK IN and MCLK OUT, in which case the clock circuit will function as a crystal controlled oscillator. For lower clock frequencies, a ceramic resonator may be used instead of the crystal. For these lower frequency oscillators, external capacitors may be required on either the ceramic resonator or on the crystal. The input sampling frequency, the modulator sampling frequency, the –3 dB frequency, output update rate and calibration time are all directly related to the master clock frequency, fCLK IN. Reducing the master clock frequency by a factor of two will halve the above frequencies and update rate and will double the calibration time. The current drawn from the DVDD power supply is also directly related to fCLK IN. Reducing fCLK IN by a factor of two will halve the DVDD current but will not affect the current drawn from the AVDD power supply. System Synchronization If multiple AD7710s are operated from a common master clock, they can be synchronized to update their output registers simultaneously. A falling edge on the SYNC input resets the filter and places the AD7710 into a consistent, known state. A common signal to the AD7710s’ SYNC inputs will synchronize their operation. This would normally be done after each AD7710 has performed its own calibration or has had calibration coefficients loaded to it. The SYNC input can also be used to reset the digital filter in systems where the turn-on time of the digital power supply (DVDD ) is very long. In such cases, the AD7710 will start operating internally before the DVDD line has reached its minimum operating level, +4.75 V. With a low DVDD voltage, the AD7710’s internal digital filter logic does not operate correctly. Thus, the AD7710 may have clocked itself into an incorrect operating condition by the time that DVDD has reached its correct level. The digital filter will be reset upon issue of a calibration command (whether it is self-calibration, system calibration or background calibration) to the AD7710. This ensures correct operation of the AD7710. In systems where the power-on default conditions of the AD7710 are acceptable, and no calibration is performed after power-on, issuing a SYNC pulse to the AD7710 will reset the AD7710’s digital filter logic. An R, C on the SYNC line, with R, C time constant longer than the DVDD power-on time, will perform the SYNC function. REV. F AUTOCALIBRATION Autocalibration on the AD7710 removes offset and gain errors from the device. A calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch or bipolar/unipolar input range. However, if the AD7710 is in its background calibration mode, the above changes are all automatically taken care of (after the settling time of the filter has been allowed for). The AD7710 offers self-calibration, system calibration and background calibration facilities. For calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. These are “zero-scale” and “full-scale” points. With these readings, the microcontroller can calculate the gain slope for the input to output transfer function of the converter. Internally, the part works with a resolution of 33 bits to determine its conversion result of either 16 bits or 24 bits. The AD7710 also provides the facility to write to the on-chip calibration registers and in this manner the span and offset for the part can be adjusted by the user. The offset calibration register contains a value which is subtracted from all conversion results, while the full-scale calibration register contains a value which is multiplied by all conversion results. The offset calibration coefficient is subtracted from the result prior to the multiplication by the full-scale coefficient. In the first three modes outlined here, the DRDY line indicates that calibration is complete by going low. If DRDY is low before (or goes low during) the calibration command, it may take up to one modulator cycle before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the control register. Self-Calibration In the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with both inputs shorted (i.e., AIN(+) = AIN(–) = VBIAS) and the full-scale point is VREF. The zero-scale coefficient is determined by converting an internal shorted inputs node. The fullscale coefficient is determined from the span between this shorted inputs conversion and a conversion on an internal VREF node. The self-calibration mode is invoked by writing the appropriate values (0, 0, 1) to the MD2, MD1 and MD0 bits of the control register. In this calibration mode, the shorted inputs node is switched in to the modulator first and a conversion is –17– AD7710 performed; the VREF node is then switched in and another conversion is performed. When the calibration sequence is complete, the calibration coefficients updated and the filter resettled to the analog input voltage, the DRDY output goes low. The self-calibration procedure takes into account the selected gain on the PGA. System calibration can also be used to remove any errors from an antialiasing filter on the analog input. A simple R, C antialiasing filter on the front end may introduce a gain error on the analog input voltage but the system calibration can be used to remove this error. For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. In this case, the two points which the AD7710 calibrates are midscale (bipolar zero) and positive full scale. System offset calibration is a variation of both the system calibration and self-calibration. In this case, the zero-scale point for the system is presented to the AIN input of the converter. System-offset calibration is initiated by writing 1, 0, 0 to MD2, MD1, MD0. The system zero-scale coefficient is determined by converting the voltage applied to the AIN input, while the fullscale coefficient is determined from the span between this AIN conversion and a conversion on VREF. The zero-scale point should be applied to the AIN input for the duration of the calibration sequence. This is a one-step calibration sequence with DRDY going low when the sequence is completed. In the unipolar mode, the system offset calibration is performed between the two end points of the transfer function; in the bipolar mode, it is performed between midscale and positive full scale. System Calibration System calibration allows the AD7710 to compensate for system gain and offset errors as well as its own internal errors. System calibration performs the same slope factor calculations as self-calibration but uses voltage values presented by the system to the AIN inputs for the zero and full-scale points. System calibration is a two-step process. The zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. System calibration is initiated by writing the appropriate values (0, 1, 0) to the MD2, MD1 and MD0 bits of the control register. The DRDY output from the device will signal when the step is complete by going low. After the zero-scale point is calibrated, the full-scale point is applied and the second step of the calibration process is initiated by again writing the appropriate values (0, 1, 1) to MD2, MD1 and MD0. Again the full-scale voltage must be set up before the calibration is initiated and it must remain stable throughout the calibration step. DRDY goes low at the end of this second step to indicate that the system calibration is complete. In the unipolar mode, the system calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale and positive full scale. This two-step system calibration mode offers another feature. After the sequence has been completed, additional offset or gain calibrations can be performed by themselves to adjust the zero reference point or the system gain. This is achieved by performing the first step of the system calibration sequence (by writing 0, 1, 0 to MD2, MD1, MD0). This will adjust the zero-scale or offset point but will not change the slope factor from what was set during a full system calibration sequence. System Offset Calibration Background Calibration The AD7710 also offers a background calibration mode where the part interleaves its calibration procedure with its normal conversion sequence. In the background calibration mode, the same voltages are used as the calibration points as are used in the self-calibration mode, i.e., shorted inputs and VREF. The background calibration mode is invoked by writing 1, 0, 1 to MD2, MD1, MD0 of the control register. When invoked, the background calibration mode reduces the output data rate of the AD7710 by a factor of six while the –3 dB bandwidth remains unchanged. Its advantage is that the part is continually performing calibration and automatically updating its calibration coefficients. As a result, the effects of temperature drift, supply sensitivity and time drift on zero- and full-scale errors are automatically removed. When the background calibration mode is turned on, the part will remain in this mode until bits MD2, MD1 and MD0 of the control register are changed. With background calibration mode on, the first result from the AD7710 will be incorrect as the full-scale calibration will not have been performed. For a step change on the input, the second output update will have settled to 100% of the final value. Table VI summarizes the calibration modes and the calibration points associated with them. It also gives the duration from when the calibration is invoked to when valid data is available to the user. Table VI. Calibration Truth Table Cal Type MD2, MD1, MD0 Zero-Scale Cal Full-Scale Cal Sequence Duration Self-Cal System Cal System Cal System Offset Cal Background Cal 0, 0, 1 0, 1, 0 0, 1, 1 1, 0, 0 1, 0, 1 Shorted Inputs AIN – AIN Shorted Inputs VREF – AIN VREF VREF One Step Two Step Two Step One Step One Step 9 × 1/Output Rate 4 × 1/Output Rate 4 × 1/Output Rate 9 × 1/Output Rate 6 × 1/Output Rate –18– REV. F AD7710 The analog and digital supplies to the AD7710 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital supply (DVDD ) must not exceed the analog positive supply (AVDD ) by more than 0.3 V in normal operation. If separate analog and digital supplies are used, the recommended decoupling scheme is shown in Figure 9. In systems where AVDD = +5 V and DVDD = +5 V, it is recommended that AVDD and DVDD are driven from the same +5 V supply, although each supply should be decoupled separately as shown in Figure 9. It is preferable that the common supply is the system’s analog +5 V supply. Span and Offset Limits Whenever a system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 × VREF/GAIN and a maximum value of 2.1 × VREF/GAIN. The amount of offset which can be accommodated depends on whether the unipolar or bipolar mode is being used. This offset range is limited by the requirement that the positive full-scale calibration limit is ≤ 1.05 × VREF/GAIN. Therefore, the offset range plus the span range cannot exceed 1.05 × VREF/GAIN. If the span is at its minimum (0.8 × VREF/GAIN) the maximum the offset can be is (0.25 × VREF/GAIN). In the bipolar mode, the system offset calibration range is again restricted by the span range. The span range of the converter in bipolar mode is equidistant around the voltage used for the zero-scale point thus the offset range plus half the span range cannot exceed (1.05 × VREF/GAIN). If the span is set to 2 × V REF/ GAIN, the offset span cannot move more than ± (0.05 × VREF/ GAIN) before the endpoints of the transfer function exceed the input overrange limits ± (1.05 × VREF/GAIN). If the span range is set to the minimum ± (0.4 × VREF/GAIN) the maximum allowable offset range is ±(0.65 × VREF/GAIN). It is also important that power is applied to the AD7710 before signals at REF IN, AIN or the logic input pins in order to avoid excessive current. If separate supplies are used for the AD7710 and the system digital circuitry, then the AD7710 should be powered up first. If it is not possible to guarantee this, then current limiting resistors should be placed in series with the logic inputs. DIGITAL +5V SUPPLY ANALOG SUPPLY 10mF POWER-UP AND CALIBRATION 0.1mF On power-up, the AD7710 performs an internal reset which sets the contents of the control register to a known state. However, to ensure correct calibration for the device a calibration routine should be performed after power-up. The power dissipation and temperature drift of the AD7710 are low and no warm up time is required before the initial calibration is performed. However, if an external reference is being used, this reference must have stabilized before calibration is initiated. AVDD DVDD AD7710 Figure 9. Recommended Decoupling Scheme DIGITAL INTERFACE Drift Considerations The AD7710 uses chopper stabilization techniques to minimize input offset drift. Charge injection in the analog switches and dc leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. The dc input leakage current is essentially independent of the selected gain. Gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. It is not affected by leakage currents. Measurement errors due to offset drift or gain drift can be eliminated at any time by recalibrating the converter or by operating the part in the background calibration mode. Using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. Integral and differential linearity errors are not significantly affected by temperature changes. POWER SUPPLIES AND GROUNDING Since the analog inputs and reference input are differential, most of the voltages in the analog modulator are common-mode voltages. VBIAS provides the return path for most of the analog currents flowing in the analog modulator. As a result, the VBIAS input should be driven from a low impedance to minimize errors due to charging/discharging impedances on this line. When the internal reference is used as the reference source for the part, AGND is the ground return for this reference voltage. REV. F 0.1mF The AD7710’s serial communications port provides a flexible arrangement to allow easy interfacing to industry-standard microprocessors, microcontrollers and digital signal processors. A serial read to the AD7710 can access data from the output register, the control register or from the calibration registers. A serial write to the AD7710 can write data to the control register or the calibration registers. Two different modes of operation are available, optimized for different types of interface where the AD7710 can act either as master in the system (it provides the serial clock) or as slave (an external serial clock can be provided to the AD7710). These two modes, labelled self-clocking mode and external clocking mode, are discussed in detail in the following sections. Self-Clocking Mode The AD7710 is configured for its self-clocking mode by tying the MODE pin high. In this mode, the AD7710 provides the serial clock signal used for the transfer of data to and from the AD7710. This self-clocking mode can be used with processors that allow an external device to clock their serial port including most digital signal processors and microcontrollers such as the 68HC11 and 68HC05. It also allows easy interfacing to serialparallel conversion circuits in systems with parallel data communication, allowing interfacing to 74XX299 Universal Shift registers without any additional decoding. In the case of shift registers, the serial clock line should have a pull-down resistor instead of the pull-up resistor shown in Figure 10 and Figure 11. –19– AD7710 Read Operation Data can be read from either the output register, the control register or the calibration registers. A0 determines whether the data read accesses data from the control register or from the output/calibration registers. This A0 signal must remain valid for the duration of the serial read operation. With A0 high, data is accessed from either the output register or from the calibration registers. With A0 low, data is accessed from the control register. The function of the DRDY line is dependent only on the output update rate of the device and the reading of the output data register. DRDY goes low when a new data word is available in the output data register. It is reset high when the last bit of data (either 16th bit or 24th bit) is read from the output register. If data is not read from the output register, the DRDY line will remain low. The output register will continue to be updated at the output update rate but DRDY will not indicate this. A read from the device in this circumstance will access the most recent word in the output register. If a new data word becomes available to the output register while data is being read from the output register, DRDY will not indicate this and the new data word will be lost to the user. DRDY is not affected by reading from the control register or the calibration registers. Figure 10 shows a timing diagram for reading from the AD7710 in the self-clocking mode. This read operation shows a read from the AD7710’s output data register. A read from the control register or calibration registers is similar but in these cases the DRDY line is not related to the read function. Depending on the output update rate, it can go low at any stage in the control/calibration register read cycle without affecting the read and its status should be ignored. A read operation from either the control or calibration registers must always read 24 bits of data from the respective register. Figure 10 shows a read operation from the AD7710. For the timing diagram shown, it is assumed that there is a pull-up resistor on the SCLK output. With DRDY low, the RFS input is brought low. RFS going low enables the serial clock of the AD7710 and also places the MSB of the word on the serial data line. All subsequent data bits are clocked out on a high to low transition of the serial clock and are valid prior to the following rising edge of this clock. The final active falling edge of SCLK clocks out the LSB and this LSB is valid prior to the final active rising edge of SCLK. Coincident with the next falling edge of SCLK, DRDY is reset high. DRDY going high turns off the SCLK and the SDATA outputs. This means that the data hold time for the LSB is slightly shorter than for all other bits. Data can only be accessed from the output data register when DRDY is low. If RFS goes low with DRDY high, no data transfer will take place. DRDY does not have any effect on reading data from the control register or from the calibration registers. DRDY (O) t3 t2 A0 (I) t5 t4 RFS (I) t6 t9 SCLK (O) t7 t8 t 10 THREE-STATE SDATA (O) MSB LSB Figure 10. Self-Clocking Mode, Output Data Read Operation –20– REV. F AD7710 Write Operation Read Operation Data can be written to either the control register or calibration registers. In either case, the write operation is not affected by the DRDY line and the write operation does not have any effect on the status of DRDY. A write operation to the control register or the calibration register must always write 24 bits to the respective register. As with the self-clocking mode, data can be read from either the output register, the control register or the calibration registers. A0 determines whether the data read accesses data from the control register or from the output/calibration registers. This A0 signal must remain valid for the duration of the serial read operation. With A0 high, data is accessed from either the output register or from the calibration registers. With A0 low, data is accessed from the control register. Figure 11 shows a write operation to the AD7710. A0 determines whether a write operation transfers data to the control register or to the calibration registers. This A0 signal must remain valid for the duration of the serial write operation. The falling edge of TFS enables the internally generated SCLK output. The serial data to be loaded to the AD7710 must be valid on the rising edge of this SCLK signal. Data is clocked into the AD7710 on the rising edge of the SCLK signal with the MSB transferred first. On the last active high time of SCLK, the LSB is loaded to the AD7710. Subsequent to the next falling edge of SCLK, the SCLK output is turned off. (The timing diagram of Figure 11 assumes a pull-up resistor on the SCLK line.) External Clocking Mode The AD7710 is configured for its external clocking mode by tying the MODE pin low. In this mode, SCLK of the AD7710 is configured as an input and an external serial clock must be provided to this SCLK pin. This external clocking mode is designed for direct interface to systems which provide a serial clock output that is synchronized to the serial data output, including microcontrollers such as the 80C51, 87C51, 68HC11 and 68HC05 and most digital signal processors. The function of the DRDY line is dependent only on the output update rate of the device and the reading of the output data register. DRDY goes low when a new data word is available in the output data register. It is reset high when the last bit of data (either 16th bit or 24th bit) is read from the output register. If data is not read from the output register, the DRDY line will remain low. The output register will continue to be updated at the output update rate but DRDY will not indicate this. A read from the device in this circumstance will access the most recent word in the output register. If a new data word becomes available to the output register while data is being read from the output register, DRDY will not indicate this and the new data word will be lost to the user. DRDY is not affected by reading from the control register or the calibration register. Data can only be accessed from the output data register when DRDY is low. If RFS goes low while DRDY is high, no data transfer will take place. DRDY does not have any effect on reading data from the control register or from the calibration registers. A0 (I) t 15 t 14 TFS (I) t 17 t 16 t9 SCLK (O) t18 t 10 t19 SDATA (I) MSB LSB Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation REV. F –21– AD7710 edge of SCLK clocks out the LSB and the final falling edge resets the DRDY line high. This rising edge of DRDY turns off the serial data output. Figures 12a and 12b show timing diagrams for reading from the AD7710 in the external clocking mode. Figure 12a shows a situation where all the data is read from the AD7710 in one read operation. Figure 12b shows a situation where the data is read from the AD7710 over a number of read operations. Both read operations show a read from the AD7710’s output data register. A read from the control register or calibration registers is similar but in these cases the DRDY line is not related to the read function. Depending on the output update rate, it can go low at any stage in the control/calibration register read cycle without affecting the read and its status should be ignored. A read operation from either the control or calibration registers must always read 24 bits of data from the respective register. Figure 12b shows a timing diagram for a read operation where RFS returns high during the transmission of the word and returns low again to access the rest of the data word. Timing parameters and functions are very similar to that outlined for Figure 12a but Figure 12b has a number of additional times to show timing relationships when RFS returns high in the middle of transferring a word. RFS should return high during a low time of SCLK. On the rising edge of RFS, the SDATA output is turned off. DRDY remains low and will remain low until all bits of the data word are read from the AD7710, regardless of the number of times RFS changes state during the read operation. Depending on the time between the falling edge of SCLK and the rising edge of RFS, the next bit (BIT N+1) may appear on the databus before RFS goes high. When RFS returns low again, it activates the SDATA output. When the entire word is transmitted, the DRDY line will go high turning off the SDATA output as per Figure 12a. Figure 12a shows a read operation from the AD7710 where RFS remains low for the duration of the data word transmission. With DRDY low, the RFS input is brought low. The input SCLK signal should be low between read and write operations. RFS going low places the MSB of the word to be read on the serial data line. All subsequent data bits are clocked out on a high to low transition of the serial clock and are valid prior to the following rising edge of this clock. The penultimate falling DRDY (O) t 21 t 20 A0 (I) t 23 t 22 RFS (I) t 26 t 28 SCLK (I) SDATA (O) t 27 t 25 t 24 t 29 MSB LSB THREE-STATE Figure 12a. External-Clocking Mode, Output Data Read Operation DRDY (O) t20 A0 (I) t 22 RFS (I) t 26 t 30 SCLK (I) t 27 t 24 t 31 t 25 SDATA (O) t 24 t 25 THREE-STATE MSB BIT N BIT N+1 Figure 12b. External-Clocking Mode, Output Data Read Operation ( RFS Returns High During Read Operation) –22– REV. F AD7710 SCLK signal with the MSB transferred first. On the last active high time of SCLK, the LSB is loaded to the AD7710. Write Operation Data can be written to either the control register or calibration registers. In either case, the write operation is not affected by the DRDY line and the write operation does not have any effect on the status of DRDY. A write operation to the control register or the calibration register must always write 24 bits to the respective register. Figure 13b shows a timing diagram for a write operation to the AD7710 with TFS returning high during the write operation and returning low again to write the rest of the data word. Timing parameters and functions are very similar to that outlined for Figure 13a, but Figure 13b has a number of additional times to show timing relationships when TFS returns high in the middle of transferring a word. Figure 13a shows a write operation to the AD7710 with TFS remaining low for the duration of the write operation. A0 determines whether a write operation transfers data to the control register or to the calibration registers. This A0 signal must remain valid for the duration of the serial write operation. As before, the serial clock line should be low between read and write operations. The serial data to be loaded to the AD7710 must be valid on the high level of the externally applied SCLK signal. Data is clocked into the AD7710 on the high level of this Data to be loaded to the AD7710 must be valid prior to the rising edge of the SCLK signal. TFS should return high during the low time of SCLK. After TFS returns low again, the next bit of the data word to be loaded to the AD7710 is clocked in on next high level of the SCLK input. On the last active high time of the SCLK input, the LSB is loaded to the AD7710. A0 (I) t 33 t 32 TFS (I) t 26 t 34 SCLK (I) t 36 t 35 SDATA (I) t 27 MSB LSB Figure 13a. External-Clocking Mode, Control/Calibration Register Write Operation A0 (I) t 32 TFS (I) t 26 t 30 SCLK (I) t 35 SDATA (I) t 27 t 35 t 36 t 36 MSB BIT N BIT N+1 Figure 13b. External-Clocking Mode, Control/Calibration Register Write Operation (TFS Returns High During Write Operation) REV. F –23– AD7710 SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE In many applications, the user may not require the facility of writing to the on-chip calibration registers. In this case, the serial interface to the AD7710 in external clocking mode can be simplified by connecting the TFS line to the A0 input of the AD7710 (see Figure 14). This means that any write to the device will load data to the control register (since A0 is low while TFS is low) and any read to the device will access data from the output data register or from the calibration registers (since A0 is high while RFS is low). It should be noted that in this arrangement the user does not have the capability of reading from the control register. being transferred from data memory to the accumulator before being written to the serial buffer. Some microprocessor systems will allow data to be written directly to the serial buffer from data memory. The writing of data to the serial buffer from the accumulator will generally consist of either two or three write operations, depending on the size of the serial buffer. START CONFIGURE & INITIALIZE mC/mP SERIAL PORT BRING RFS, TFS HIGH RFS FOUR INTERFACE LINES SDATA SCLK AD7710 TFS POLL DRDY A0 Figure 14. Simplified Interface with TFS Connected to A0 DRDY LOW? Another method of simplifying the interface is to generate the TFS signal from an inverted RFS signal. However, generating the signals the opposite way around (RFS from an inverted TFS) will cause writing errors. NO YES BRING RFS LOW MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7710’s flexible serial interface allows for easy interface to most microcomputers and microprocessors. Figure 15 shows a flowchart diagram for a typical programming sequence for reading data from the AD7710 to a microcomputer while Figure 16 shows a flowchart diagram for writing data to the AD7710. Figures 17, 18 and 19 show some typical interface circuits. The flowchart of Figure 15 is for continuous read operations from the AD7710 output register. In the example shown, the DRDY line is continuously polled. Depending on the microprocessor configuration, the DRDY line may come to an interrupt input in which case the DRDY will automatically generate an interrupt without being polled. The reading of the serial buffer could be anything from one read operation up to three read operations (where 24 bits of data are read into an 8-bit serial register). A read operation to the control/calibration registers is similar but in this case the status of DRDY can be ignored. The A0 line is brought low when the RFS line is brought low when reading from the control register. The flowchart also shows the bits being reversed after they have been read in from the serial port. This depends on whether the microprocessor expects the MSB of the word first or the LSB of the word first. The AD7710 outputs the MSB first. The flowchart for Figure 16 is for a single 24-bit write operation to the AD7710 control or calibration registers. This shows data x3 READ SERIAL BUFFER BRING RFS HIGH REVERSE ORDER OF BITS Figure 15. Flowchart for Continuous Read Operations to the AD7710 The flowchart also shows the option of the bits being reversed before being written to the serial buffer. This depends on whether the first bit transmitted by the microprocessor is the MSB or the LSB. The AD7710 expects the MSB as the first bit in the data stream. In cases where the data is being read or being written in bytes and the data has to be reversed, the bits will have to be reversed for every byte. –24– REV. F AD7710 Table VII shows some typical 8XC51 code used for a single 24bit read from the output register of the AD7710. Table VIII shows some typical code for a single write operation to the control register of the AD7710. The 8XC51 outputs the LSB first in a write operation while the AD7710 expects the MSB first so the data to be transmitted has to be rearranged before being written to the output serial register. Similarly, the AD7710 outputs the MSB first during a read operation while the 8XC51 expects the LSB first. Therefore, the data which is read into the serial buffer needs to be rearranged before the correct data word from the AD7710 is available in the accumulator. START CONFIGURE & INITIALIZE mC/mP SERIAL PORT BRING RFS, TFS & A0 HIGH LOAD DATA FROM ADDRESS TO ACCUMULATOR Table VII. 8XC51 Code for Reading from the AD7710 REVERSE ORDER OF BITS BRING TFS & A0 LOW x3 WRITE DATA FROM ACCUMULATOR TO SERIAL BUFFER BRING TFS & A0 HIGH END Figure 16. Flowchart for Single Write Operation to the AD7710 AD7710 to 8XC51 Interface Figure 17 shows an interface between the AD7710 and the 8XC51 microcontroller. The AD7710 is configured for its external clocking mode while the 8XC51 is configured in its Mode 0 serial interface mode. The DRDY line from the AD7710 is connected to the Port P1.2 input of the 8XC51 so the DRDY line is polled by the 8XC51. The DRDY line can be connected to the INT1 input of the 8XC51 if an interrupt driven system is preferred. DVDD SYNC P1.0 8XC51 RFS P1.1 TFS P1.2 DRDY P1.3 A0 P3.0 SDATA P3.1 SCLK AD7710 MOV SCON,#00010001B; Configure 8051 for MODE 0 Operation MOV IE,#00010000B; Disable All Interrupts SETB 90H; Set P1.0, Used as RFS SETB 91H; Set P1.1, Used as TFS SETB 93H; Set P1.3, Used as A0 MOV R1,#003H; Sets Number of Bytes to Be Read in A Read Operation MOV R0,#030H; Start Address for Where Bytes Will Be Loaded MOV R6,#004H; Use P1.2 as DRDY WAIT: NOP; MOV A,P1; Read Port 1 ANL A,R6; Mask Out All Bits Except DRDY JZ READ; If Zero Read SJMP WAIT; Otherwise Keep Polling READ: CLR 90H; Bring RFS Low CLR 98H; Clear Receive Flag POLL: JB 98H, READ1 Tests Receive Interrupt Flag SJMP POLL READ 1: MOV A,SBUF; Read Buffer RLC A; Rearrange Data MOV B.0,C; Reverse Order of Bits RLC A; MOV B.1,C; RLC A; MOV B.2,C; RLC A; MOV B.3,C; RLC A; MOV B.4,C; RLC A; MOV B.5,C; RLC A; MOV B.6,C; RLC A; MOV B.7,C; MOV A,B; MOV @R0,A; Write Data to Memory INC R0; Increment Memory Location DEC R1 Decrement Byte Counter MOV A,R1 JZ END Jump if Zero JMP WAIT Fetch Next Byte END: SETB 90H Bring RFS High FIN: SJMP FIN MODE Figure 17. AD7710 to 8XC51 Interface REV. F –25– AD7710 Table VIII. 8XC51 Code for Writing to the AD7710 MOV SCON,#00000000B; MOV IE,#10010000B; MOV IP,#00010000B; SETB 91H; SETB 90H; MOV R1,#003H; MOV R0,#030H; MOV A,#00H; MOV SBUF,A; WAIT: JMP WAIT; INT ROUTINE: NOP; MOV A,R1; JZ FIN; DEC R1; MOV A,@R; INC R0; RLC A; DVDD DVDD SYNC SS Configure 8051 for MODE 0 Operation & Enable Serial Reception Enable Transmit Interrupt Prioritize the Transmit Interrupt Bring TFS High Bring TFS High Sets Number of Bytes to Be Written in a Write Operation Start Address in RAM for Bytes Clear Accumulator Initialize the Serial Port PC0 68HC11 RFS PC1 TFS PC2 DRDY PC3 A0 SCK SCLK MISO SDATA MOSI MODE AD7710 Figure 18. AD7710 to 68HC11 Interface Wait for Interrupt AD7710 to ADSP-2105 Interface An interface circuit between the AD7710 and the ADSP-2105 microprocessor is shown in Figure 19. In this interface, the AD7710 is configured for its self-clocking mode while the RFS and TFS pins of the ADSP-2105 are configured as inputs and the ADSP-2105 serial clock line is also configured as an input. Interrupt Subroutine Load R1 to Accumulator If Zero Jump to FIN Decrement R1 Byte Counter Move Byte into the Accumulator Increment Address Rearrange Data—From LSB First to MSB First MOV B.0,C; RLC A; MOV B.1,C; RLC A; MOV B.2,C; RLC A; MOV B.3,C; RLC A; MOV B.4,C; RLC A; MOV B.5,C; RLC A; MOV B.6,C; RLC A: MOV B.7,C; MOV A,B; CLR 93H; Bring A0 Low CLR 91H; Bring TFS Low MOV SBUF,A; Write to Serial Port RETI; Return from Subroutine FIN: SETB 91H; Set TFS High SETB 93H; Set A0 High RETI; Return from Interrupt Subroutine When the ADSP-2105’s serial clock is configured as an input it needs a couple of clock pulses to initialize itself correctly before accepting data. Therefore, the first read from the AD7710 may not read correct data. In the interface shown, a read operation to the AD7710 accesses either the output register or the calibration registers. Data cannot be read from the control register. A write operation always writes to the control or calibration registers. DRDY is used as the frame synchronization pulse for read operations from the output register and it is decoded with A0 to drive the RFS inputs of both the AD7710 and the ADSP-2105. The latched A0 line drives the TFS inputs of both the AD7710 and the ADSP-2105 as well as the AD7710 A0 input. DVDD AD7710 to 68HC11 Interface MODE Figure 18 shows an interface between the AD7710 and the 68HC11 microcontroller. The AD7710 is configured for its external clocking mode while the SPI port is used on the 68HC11 which is in its single chip mode. The DRDY line from the AD7710 is connected to the Port PC0 input of the 68HC11 so the DRDY line is polled by the 68HC11. The DRDY line can be connected to the IRQ input of the 68HC11 if an interrupt driven system is preferred. The 68HC11 MOSI and MISO lines should be configured for wired-or operation. Depending on the interface configuration, it may be necessary to provide bidirectional buffers between the 68HC11’s MOSI and MISO lines. RFS RFS DRDY TFS ADSP-2105 AD7710 A0 D Q 74HC74 DMWR Q DR DT SCLK A0 TFS SDATA SCLK Figure 19. AD7710 to ADSP-2105 Interface The 68HC11 is configured in the master mode with its CPOL bit set to a logic zero and its CPHA bit set to a logic one. With a 10 MHz master clock on the AD7710, the interface will operate with all four serial clock rates of the 68HC11. –26– REV. F AD7710 reference voltage for the AD7710 generated across a resistor which is placed in series with the bridge network. In this case, the value of the reference resistor is determined by the required reference voltage divided by the value of the excitation current. APPLICATIONS Figure 20 shows a strain gage interfaced directly to one of the analog input channels of the AD7710. The differential inputs to the AD7710 are connected directly to the bridge network of the strain gage. In the diagram shown, the on-chip reference of the AD7710 provides the voltage for the bridge network and also provides the reference voltage for the AD7710. An alternative scheme, outlined in Figure 21, shows the analog positive supply voltage powering the bridge network and the AD7710 with the The on-chip PGA allows the AD7710 to handle an analog input voltage range as low as 20 mV full scale. The differential inputs of the part allow this analog input range to have an absolute value anywhere between VSS and AVDD. ANALOG +5V SUPPLY REF OUT ACTIVE GAGE REF IN (–) REF IN (+) AVDD DVDD 2.5V REFERENCE R CHARGE-BALANCING A/D CONVERTER AIN1(+) DUMMY GAGE VBIAS AUTO-ZEROED PGA R AIN1(–) AIN2(+) SYNC DIGITAL FILTER MODULATOR M U X A = 1 – 128 MCLK IN CLOCK GENERATION AIN2(–) MCLK OUT SERIAL INTERFACE CONTROL REGISTER OUTPUT REGISTER AD7710 AGND DGND VSS RFS TFS MODE SDATA SCLK DRDY A0 Figure 20. Strain-Gage Application with the AD7710 DIGITAL +5V SUPPLY ANALOG SUPPLY EXCITATION CURRENT R= VREF AVDD DVDD REF OUT VBIAS REF IN(+) IEXCITATION ACTIVE GAGE 2.5V REFERENCE REF IN(–) CHARGE-BALANCING A/D CONVERTER R AIN1(+) AUTO-ZEROED DUMMY GAGE R PGA M U X AIN1(–) MODULATOR DIGITAL FILTER SYNC A = 1 – 128 AIN2(+) CLOCK GENERATION AIN2(–) MCLK IN MCLK OUT SERIAL INTERFACE CONTROL REGISTER AD7710 AGND DGND VSS OUTPUT REGISTER RFS TFS MODE SDATA SCLK DRDY A0 Figure 21. Alternate Scheme for Generating AD7710 Reference Voltage REV. F –27– AD7710 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-24) 24 13 1 12 PIN 1 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) C1654e–0–10/99 1.275 (32.30) 1.125 (28.60) 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.022 (0.558) 0.014 (0.356) 0.015 (0.381) 0.008 (0.204) 0.070 (1.77) SEATING 0.045 (1.15) PLANE Cerdip (Q-24) 0.005 (0.13) MIN 0.098 (2.49) MAX 24 13 1 12 0.310 (7.87) 0.220 (5.59) 0.320 (8.13) 0.290 (7.37) PIN 1 0.060 (1.52) 0.015 (0.38) 1.280 (32.51) MAX 0.200 (5.08) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) SEATING 0.030 (0.76) PLANE 15° 0° 0.015 (0.38) 0.008 (0.20) SOIC (R-24) 1 12 PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 8° 0.0192 (0.49) 0° SEATING 0.0138 (0.35) PLANE 0.0125 (0.32) 0.0091 (0.23) –28– 0.0291 (0.74) x 45° 0.0098 (0.25) PRINTED IN U.S.A. 13 0.4193 (10.65) 0.3937 (10.00) 24 0.2992 (7.60) 0.2914 (7.40) 0.6141 (15.60) 0.5985 (15.20) 0.0500 (1.27) 0.0157 (0.40) REV. F